Memory system resource partitioning and monitoring (MPAM) configuration using secure processor

Abstract

Various embodiments include systems and methods for allocating memory resources in a computing system that includes memory system resource partitioning and monitoring (MPAM) features. The computing system may transition from an MPAM configuration controlled using a CPU to using an MPAM configuration managed by an external entity, such as a CPU co-processor (CPCP). The computing system may centralize MPAM operations, introduce various control modes, and / or notify the autonomous decision process in conjunction with the use of system sensors and parameters.

Description

[0001] Related applications

[0002] This application claims priority to Indian Provisional Patent Application No. 202321051620, filed on August 1, 2023, entitled “Memory-System Resource Partitioning and Monitoring (MPAM) Configuration Using Secure Processor,” the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] Memory System Resource Partitioning and Monitoring (MPAM) and System Control and Management Interface (SCMI) are advanced features used in modern computing systems to allow for more efficient and controlled system performance.

[0004] MPAM can be a component included in the memory management unit (MMU) of a computing system and configured to partition and monitor system resources (e.g., cache, memory bandwidth, etc.) across different workloads. The computing system can systematically and strategically allocate typically limited memory resources. For example, the computing system can intelligently assign specific resources to specific tasks to prevent resource contention and improve overall system performance. In multiprocessor systems, the computing system can prevent processes from monopolizing shared resources, thereby allowing for a more equitable distribution of memory access. For these and other reasons, MPAM systems are increasingly used to efficiently manage shared system resources, especially in cloud computing environments and in systems with multiple cores and / or threads, where multiple applications may execute concurrently and compete for the same memory resources.

[0005] SCMI (System Resource Management) is a standardized interface that facilitates the control and management of system resources in a computing system or device. SCMI allows operating system (OS) power management software to communicate with the underlying hardware to manage system resources, including power status, performance levels, thermal limits, etc. SCMI can include a set of predefined protocols and messages that software can use to instruct the hardware on how to adjust its settings. SCMI can be particularly beneficial in systems with complex power and performance requirements, where efficient resource management can lead to significant power savings and improved performance.

[0006] The popularity and use of MPAM and SCMI technologies are growing. Although in slightly different contexts, they both allow for the management and control of resources. MPAM can be used for resource partitioning and monitoring, while SCMI can be used as an interface for managing and controlling system-wide resources. Summary of the Invention

[0007] Various aspects may include methods for allocating memory resources in a computing system. In some aspects, the method may include: centralized memory system resource partitioning and monitoring (MPAM) operations; operating the computing system in one of several control modes (e.g., KERNEL_FULL_CONTROL, HYBRID, SECURE_SW_FULL_CONTROL, etc.); and / or allocating memory segments to software applications operating on the computing system or computing device, represented by different partition identifiers (PARTIDs).

[0008] Some aspects may also include dividing the MPAM operation between a request component included in the kernel portion of the computing system and a configuration component included in the security software portion of the computing system. Some aspects may also include using the computing system control and management interface (SCMI) framework or other inter-processor communication (IPC) mechanisms or protocols to securely communicate information between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system.

[0009] Some aspects may also include using the SCMI framework or IPC protocol to communicate information between the central processing unit (CPU) core in the computing system and the CPU coprocessor (CPUCP) in the computing system.

[0010] Some aspects may also include using the SCMI framework or other IPC organization or protocol to transmit MPAM configuration request messages to the configuration component included in the security software portion and operating on the CPUCP.

[0011] Some aspects may also include partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application within the software application, for use by multiple software applications operating on the computing system. In some aspects, partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application within the software application for use by multiple software applications operating on the computing system may include partitioning the cache memory by the CPUCP based on MPAM configuration and / or Quality of Service (QoS) parameters to reduce cache conflicts, cache pollution, or cache thrashing. In some aspects, the QoS parameters may be associated with components that can be configured to support MPAM operation, such as L4 cache, DDR, other processing, and dedicated cores.

[0012] In some respects, partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software application for use by multiple software applications operating on the computing system may include partitioning the cache memory by the CPUCP such that a portion of the cache memory can be reserved for secure applications and the remaining portion of the cache memory is reserved for non-secure applications.

[0013] In some respects, the kernel assumes complete control over the MPAM configuration for each memory segment or software application, and when the computing system operates in KERNEL_FULL_CONTROL mode, the CPUCP implements kernel commands without modification. The kernel operates as a pass-through component by forwarding received information to the CPUCP. When the computing system operates in SECURE_SW_FULL_CONTROL mode, the CPUCP assumes complete control over the MPAM configuration for each memory segment or software application. When the computing system operates in HYBRID mode, the kernel and the CPUCP share control over the MPAM configuration for each memory segment or software application.

[0014] In some respects, the computing system operates in the HYBRID mode, and the kernel issues commands proposing specific performance configurations, such as CPU performance configuration (CPU_PERF_CONFIG) or system performance configuration (SYSTEM_PERF_CONFIG), and the CPUCP dynamically adjusts the commands to adjust the MPAM configuration based on workload data, real-time system parameters, or additional system information, such as data on current resource utilization on the computing system, network traffic, current operations (e.g., data read, write, processing tasks, etc.) or hardware-specific data (e.g., thermal sensor readings, current state of CPU cores, etc.).

[0015] In some respects, the operation of allocating memory segments to software applications represented by different partition identifiers (PARTIDs) operating on the computing system can be performed in a virtual machine (VM) configured to allow autonomous or hybrid mode configurations of MPAM.

[0016] Some aspects may include a method for allocating memory resources in a computing system, the method comprising: receiving, by a CPU coprocessor (CPUCP) of the computing system, a kernel request for memory system resource partitioning and monitoring (MPAM) configuration in a security software portion of the computing system; and by the CPUCP configuring one or more MPAM registers in the computing system based on the received kernel request.

[0017] In some respects, configuring one or more MPAM registers in the computing system based on received kernel requests may include coordinating the MPAM configuration by the CPUCP across multiple security states or between secure and non-secure operations.

[0018] Some aspects may also include selecting one of a plurality of operating modes, which may include KERNEL_FULL_CONTROL mode, SECURE_SW_FULL_CONTROL mode, and HYBRID_MODE.

[0019] In some respects, configuring one or more MPAM registers in the computing system based on received kernel requests may include allocating caches via MPAM and configuring additional Quality of Service (QOS) parameters using various system parameters including thermal parameters, core count parameters, effective frequency parameters, and DDR parameters.

[0020] In some respects, configuring one or more MPAM registers in the computing system based on received kernel requests may include configuring one or more MPAM registers using a virtual machine (VM) and an autonomous or hybrid mode of the security software.

[0021] Another aspect may include a computing system or computing device having a processor configured with processor-executable instructions for performing various operations corresponding to the methods outlined above.

[0022] Another aspect may include a non-transitory processor-readable storage medium on which processor-executable instructions are stored, the processor-executable instructions being configured to cause the processor to perform various operations corresponding to the method operations outlined above.

[0023] Another aspect may include a computing system or computing device having various components for performing functions corresponding to the method operations outlined above. Attached Figure Description

[0024] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate exemplary embodiments of the claims and, together with the general description and detailed description given, serve to explain the features of this document.

[0025] Figures 1 to 5 This is a component block diagram illustrating example components in a computing system that can be configured to implement some implementation schemes.

[0026] Figures 6A to 6D This is a flowchart illustrating a method for allocating memory resources in a computing system according to some implementation schemes.

[0027] Figure 7 This is a flowchart illustrating a method for allocating memory resources in a computing system including virtual machines (VMs) according to some implementation schemes.

[0028] Figures 8A to 8D This is a flowchart illustrating a method for allocating memory resources in a computing system using centralized memory system resource partitioning and monitoring (MPAM) operations, according to some implementation schemes.

[0029] Figure 9 This is a component block diagram illustrating an example computing device applicable to various implementation schemes.

[0030] Figure 10 This is a component block diagram illustrating an example wireless communication device applicable to various implementation schemes. Detailed Implementation

[0031] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the claims.

[0032] Various implementations include systems and methods for allocating memory resources in computing systems that include Memory System Resource Partitioning and Monitoring (MPAM) features. Various implementations may include a shift from MPAM configurations controlled by a central processing unit (CPU) to MPAM configurations managed by an external entity, such as a CPU coprocessor (CPUCP).

[0033] The terms “computing system” and “computing device” may be used herein to refer to any or all of the following: quantum computing devices, edge devices, internet access gateways, modems, routers, network switches, residential gateways, access points, integrated access devices (IADs), mobile convergence products, networking adapters, multiplexers, personal computers, laptop computers, tablet computers, user equipment (UE), smartphones, personal or mobile multimedia players, personal data assistants (PDAs), handheld computers, wireless email receivers, cellular phones supporting multimedia internet, and gaming systems (e.g., PlayStation). ™ Xbox ™ Nintendo Switch ™ Wearable devices (e.g., smartwatches, head-mounted displays, fitness trackers, etc.), media players (e.g., DVD players, ROKU...), etc. ™ Apple TV ™Digital video recorders (DVRs), automotive displays, portable projectors, 3D holographic displays, and other similar devices including displays and programmable processors that can be configured to provide functionality for various implementation schemes.

[0034] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources or independent processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose or specialized processors (e.g., network processors, digital signal processors, modem processors, video processors, etc.), blocks of memory (e.g., ROM, RAM, flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). For example, an SoC may include application processors that operate as the SoC's main processor, central processing unit (CPU), microprocessor unit (MPU), arithmetic logic unit (ALU), etc. An SoC may also include software for controlling the integrated resources and processors, as well as software for controlling peripheral devices.

[0035] The term "System-in-Package" (SIP) may be used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC chips, substrates, or SoCs. For example, a SIP may include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a single substrate. A SIP may also include multiple independent SoCs coupled together and packaged adjacently (e.g., on a single motherboard, in a single UE, or in a single CPU device) via high-speed communication circuitry. The proximity of SoCs facilitates high-speed communication and the sharing of memory and resources.

[0036] The term "Quality of Service (QoS) parameters" is used herein to refer to parameters that a computing system may use to determine how system resources (e.g., cache memory, memory bandwidth, etc.) will be allocated to different tasks or processes. Some implementations include computing systems configured to use QoS parameters to manage Level 3 (L3) cache allocations or other system resources (which may or may not be directly supported by MPAM). For example, in some implementations, a computing system may be configured to use QoS parameters to manage other cache levels (e.g., L4), main memory (e.g., Double Data Rate (DDR) memory, etc.), or any of a variety of system processing cores.

[0037] Modern computing systems or chipsets (e.g., ARM-based chipsets) may include, implement, or use a System Control and Management Interface (SCMI) for managing various system functions, such as performance, power, and clock management. SCMIs can standardize various functions across different hardware platforms to allow operating systems (OS) or other components to control system functions in a platform-agnostic manner. Specifically, the SCMI specification outlines a set of standardized, scalable interfaces for managing system performance, power, and overall operation. These interfaces provide access to functions typically embedded within the processor's firmware. As examples, SCMIs may include platform interface discovery and self-describing interfaces, agent-specific resource isolation interfaces for dynamically modifying SCMI-compliant agent access to devices and protocols, power domain management interfaces for managing the power-saving state of devices, reset management interfaces for restarting peripheral devices or domains, clock management interfaces for handling platform-managed clock rates, sensor management interfaces for monitoring sensor data and being notified of changes, and performance management interfaces for controlling the performance of devices, which may include application processors (APs), graphics processing units (GPUs), coprocessors, or accelerators.

[0038] Many modern computing systems and chipsets include multi-level caches. A cache can be a small, high-speed memory layer located closer to the CPU than main memory (RAM). In systems that include multi-level caches, the caches can be organized in a hierarchical manner. Typically, the cache closest to the CPU is the Level 1 (L1) cache, followed by the Level 2 (L2) cache, then the Level 3 (L3) cache, and so on. The L1 cache can be the smallest and fastest cache, and it is usually located inside the CPU (each CPU core typically has its own L1 cache). The L2 cache can be larger and slightly slower than the L1 cache, and each CPU core can have its own L2 cache, or multiple cores can share an L2 cache. The L3 cache can be larger and slower than both the L1 and L2 caches, but it is still much faster than main memory. In many modern processors, all CPU cores share the L3 cache.

[0039] Modern computing systems or chipsets may include memory subsystems, which comprise various components such as a memory management unit (MMU), cache controller, and memory controller. The MMU is responsible for translating virtual memory addresses used by software applications operating on the CPU into physical memory addresses. The MMU manages the page tables used for these translations, handles page faults, manages memory protection and access permissions, ensures that each process in the system has its own isolated security space in memory, and / or manages the memory hierarchy. The cache controller can be configured to manage data entering and leaving the cache memory. For example, an L3 cache controller manages the operation of the L3 cache.

[0040] When the CPU core needs to access data, it checks the L1 cache first, then the L2 cache, and finally the L3 cache before accessing main memory. The L3 cache controller is responsible for determining whether the requested data is in the L3 cache (cache hit) or not (cache miss). If it's a cache hit, the cache controller can quickly deliver the data to the CPU. If it's a cache miss, the cache controller can forward the request to the memory controller. The memory controller may interface with physical memory (e.g., RAM). When the memory controller receives a request forwarded from the cache controller (after a cache miss) or (depending on the architecture) directly from the CPU, it can translate the request into appropriate signals for RAM, read the requested data, and then send the data back to the CPU. If the MMU requests a data block that is not currently in the cache, the memory controller can retrieve the data from RAM and send it to the cache controller, which can update the cache and then send the data to the CPU.

[0041] In some implementations, the MMU may be equipped with the MPAM feature / component. MPAM, introduced by Arm Limited, allows software applications to dynamically manage and allocate memory resources to different applications. Therefore, MPAM can improve system performance based on the specific needs and priority levels of software applications. If a software application is more memory-intensive or requires a larger portion of cache memory to operate efficiently, MPAM can allow for a larger cache allocation for that application, thereby improving its performance. Conversely, if another software application is less memory-intensive or has a lower priority, MPAM can limit its cache usage, reserving memory resources that can be better utilized by higher-priority or memory-intensive applications. These operations prevent lower-priority or less memory-intensive tasks from hindering the performance and efficiency of more important tasks. For these and other reasons, MPAM can improve the system performance and power consumption characteristics of computing systems, especially in multi-core and multi-threaded environments where multiple applications may execute concurrently and thus potentially compete for the same memory resources.

[0042] In a typical MPAM solution, the CPU is responsible for controlling and managing MPAM operations, which may include assigning partition identifiers (PARTIDs), configuring cache segments, executing memory transactions, and evaluating the cache controller. Each memory transaction initiated by the CPU can be assigned a unique PARTID, which corresponds to a specific application scheduled to run on the CPU. PARTIDs can be associated with specific cache configurations that identify segments of cache memory that can be used by the corresponding software application. For example, an application with PARTID 123 might include a configuration specifying that the application can only use the first 10% of available cache memory. Another application with PARTID 456 might be configured to use the next 20% of cache memory. Therefore, these configurations help guide the MMU to direct memory transactions to the appropriate cache segments.

[0043] The computing system can schedule software applications to run / operate / execute on the CPU and encode corresponding PARTIDs, ensuring that all memory transactions associated with the software application include the PARTID. Memory transactions ultimately reach the L3 cache controller. In a typical MPAM solution, the L3 cache controller is an MPAM-compliant controller configured to provide the system with the ability to partition the L3 cache differently for various applications or PARTIDs. For example, the L3 cache controller may include PARTID-specific settings or configurations. The cache controller can use the configuration to determine the segments of cache memory used for transferring transactions. These and other operations allow the MMU to control and manage cache memory usage with a high level of precision and assign these different applications to different segments of the cache based on their specific needs and priority levels.

[0044] The conventional MPAM solution described above may include several technical challenges and limitations, such as the inability to allow distributed entities to influence MPAM configuration, the inability to guarantee system-level Quality of Service (QoS) solely using MPAM configuration, and insufficient support for coordination between different security states. For example, in a conventional MPAM solution, MPAM configuration is handled exclusively by the CPU. The memory-mapped registers used for MPAM configuration are only accessible by the CPU core. Therefore, a conventional MPAM solution may limit the ability of entities (e.g., coprocessors, etc.) to adjust settings or configurations. In other words, in a conventional MPAM solution, there is no separate system entity to manage and coordinate how different partition IDs (representing applications) affect the system. For these and other reasons, a conventional MPAM solution may not be able to efficiently balance system resources among applications.

[0045] Furthermore, conventional MPAM solutions cannot leverage MPAM configuration to guarantee system-level Quality of Service (QoS). Typically, QoS identifies performance levels and / or can be used to ensure that specific tasks and applications are allocated appropriate system resources. MPAM systems can improve the QoS of certain applications by controlling how caches are allocated and used based on each application's requirements and priorities. However, this QoS improvement can be limited in conventional MPAM solutions because they typically only work with hardware components specifically designed to support both the ARM and MPAM specifications. This can be a significant limitation, as many computing systems include other types of cache memory besides L3 (e.g., L4 cache, DDR memory, etc.) and / or may include QoS parameters and / or other components that can be used to enhance QoS.

[0046] Furthermore, conventional MPAM solutions are insufficient to support coordination between different security states (e.g., between secure and insecure states). Some MPAM solutions support different MPAM configurations for secure and insecure applications. However, conventional MPAM solutions typically lack coordination components suitable for ensuring efficient cache usage between secure and insecure states. This lack of coordination can lead to secure and insecure applications unintentionally using the same cache portions, potentially causing cache thrashing or contamination, or otherwise negatively impacting the efficiency of the computing system.

[0047] Various implementations include components configured to overcome the limitations described above in conventional MPAM solutions to improve the performance and functionality of computing systems. Implementations may allow a shift from CPU-controlled MPAM configurations to MPAM configurations managed by external entities such as CPUCP. Implementations may centralize MPAM operation, provide multiple control modes, and / or incorporate the use of system sensors and parameters to inform autonomous decision-making processes.

[0048] Some implementations can divide MPAM operations across two components: a request component and a configuration component. The request component can be included in or executed by software applications, the kernel, or the OS. The configuration component can be included in or executed by security software. The computing system can use the SCMI framework or other IPC mechanisms or protocols to ensure secure and efficient communication between the request component in the kernel / OS and the configuration component in the security software.

[0049] In some implementations, the computing system can be configured to use the SCMI framework or other IPC mechanisms or protocols to facilitate communication between the CPU core and external entities (e.g., CPUCP). For example, the CPU core can transmit configuration for PARTID to a coprocessor performing configuration operations via the SCMI interface (or other IPC mechanisms or protocols). The coprocessor can partition the cache memory for different applications and / or otherwise configure MPAM and QoS parameters to improve cache utilization and / or reduce cache conflicts, cache pollution, cache thrashing, etc.

[0050] Typically, software applications operate in either a secure or insecure state. In a secure state, the application has access to all system resources and / or can perform any operation. In an insecure state, the application's operations and access to system resources may be restricted or controlled. In some implementations, the computing system can be configured to allow external entities (e.g., CPUCP, etc.) to manage the secure and insecure states. For example, the computing system can be configured to allow external entities to coordinate between secure and insecure states. External entities can also manage cache portions, such that one portion is reserved for secure applications and the remainder is used for insecure applications. These and other operations prevent cache pollution caused by inefficient simultaneous use of the cache by secure and insecure applications.

[0051] In some implementations, the computing system can be configured to extend the use of QoS parameters beyond components that support both the ARM and MPAM specifications. As discussed above, a typical MPAM solution may only work with components that support both the ARM and MPAM specifications. In some implementations, the computing system can be configured to allow external entities to utilize QoS parameters exposed by other components not currently supported by ARM or MPAM. These implementations allow for the integration of more components into resource management operations, which enables better resource distribution and improves the performance of the computing system.

[0052] In some implementations, the computing system can be configured to provide access to the MPAM configuration. Unlike conventional MPAM solutions where only the CPU core accesses the MPAM configuration, implementations may allow external entities within the SoC (e.g., CPUCP, etc.) to access the MPAM configuration. For example, implementations may allow external entities to coordinate and manage partitions of cache resources for different applications represented by different PARTIDs. External entities can also manage other QoS parameters that exist in the system but are not compatible with MPAM, such as parameters for other caches in the system (e.g., L4, DDR, etc.) or other types of cores. Therefore, the external entity can operate as a coordinating entity that not only manages partitions of cache memory for different applications but also handles other system parameters that further enhance the efficiency of the entire transaction path from CPU to memory. Thus, the external entity can improve the efficiency of the entire transaction path, not just at the L3 cache level.

[0053] In some implementations, the computing system may include multiple operating modes for MPAM configuration, such as KERNEL_FULL_CONTROL, HYBRID, and SECURE_SW_FULL_CONTROL. These operating modes can provide various levels of control to software applications or the kernel, ranging from complete control by the application / kernel to complete control by the security software. Hybrid modes can balance control between the application / kernel and the security software. These modes can intelligently adjust and control the MPAM configuration using various sensors and system parameters, such as thermal parameters, core count, effective frequency, DDR frequency, etc.

[0054] When operating in KERNEL_FULL_CONTROL mode, the kernel assumes complete control over the MPAM configuration for each segment or application. External entities can be configured to implement kernel commands without any intervention. For example, a request for a specific configuration can be passed directly from the kernel to an external entity (e.g., a coprocessor or CPUCP), which can precisely program the MPAM registers according to the kernel's instructions without any modification. The external entity can transfer kernel configuration data to the MPAM registers and log the information.

[0055] When operating in SECURE_SW_FULL_CONTROL mode, the external entity assumes complete control over MPAM configuration. The kernel can perform pass-through operations by forwarding received information to the external entity to configure MPAM. In this mode, the external entity can override or ignore kernel commands.

[0056] HYBRID mode allows both external entities and the kernel to participate in control configuration, balancing control between the kernel and the coprocessor. In HYBRID mode, the kernel can provide some of the commands or instructions to the coprocessor (e.g., via configuration requests). The coprocessor can modify, adjust, or ignore commands based on local information and local determinations before programming the MPAM. Examples of local information usable by external entities include application performance requirements, QoS hints / tunable parameters (system or application-level parameters that can be configured to meet specific performance, reliability, or other QoS goals), current workload information, and cache usage information.

[0057] The HYBRID model allows computing systems to benefit from both kernel application control and external entity oversight. For example, the kernel can request specific performance configurations from external entities, such as CPU performance configuration (CPU_PERF_CONFIG) or system performance configuration (SYSTEM_PERF_CONFIG). External entities can use these configurations and metrics to make informed decisions about resource allocation. For instance, external entities can monitor various characteristics, conditions, and real-time system parameters on the device, such as workload demands, operating frequency, and cache usage. Depending on the selected configuration, external entities can adjust MPAM settings based on real-time system parameters, ensuring smarter and more dynamic resource management compared to simply fulfilling kernel requests without modification. Therefore, external entities can dynamically adjust MPAM configurations to adapt to changing workloads and conditions, which in turn improves the overall performance of the computing system.

[0058] In some implementations, external entities can dynamically adjust MPAM configurations based on workload data. Workload data can include information related to current tasks and processes operating within the system, such as whether a task requires high CPU or memory usage. External entities can use workload data to fine-tune MPAM settings to more effectively support tasks. For example, an external entity might allocate increased cache space for tasks requiring significant CPU usage or modify memory partitions for memory-intensive tasks.

[0059] In some implementations, external entities may dynamically adjust the MPAM configuration based on real-time parameters. Real-time parameters may include dynamic elements such as data about the current resource utilization of the system (e.g., CPU and memory), network traffic, or operations (e.g., data reads, writes, processing tasks, etc.).

[0060] In some implementations, an external entity can dynamically adjust the MPAM configuration based on hardware-specific data, such as thermal sensor readings and the current state of the CPU cores (how many are active, idle, etc.). For example, if a thermal sensor indicates that the system is overheating, the external entity can adjust the MPAM settings to lower energy usage and heat generation. If multiple CPU cores are idle, the external entity can reallocate resources to improve efficiency.

[0061] In some implementations, an external entity may dynamically adjust the MPAM configuration based on thermal considerations. For example, an external entity may increase the cache allocation used to run tasks or processes in response to determining that the system is operating at high temperatures and at very high frequencies. Increasing cache allocation allows the system to access data faster, reduces the time spent completing tasks, and thus allows the system to cool down more quickly.

[0062] In some implementations, external entities can dynamically adjust MPAM configurations based on multi-core cache management information. For example, an external entity can dynamically adjust cache allocation based on the workload of cores in a multi-core system. That is, all cores in a multi-core system can share a common cache (L3), with heavy threads (e.g., threads requiring significant computational resources to execute) running on larger, high-performance cores (“big cores”), and lighter or smaller threads (e.g., threads performing less computationally intensive tasks compared to heavy threads) running on smaller, more energy-efficient cores (“small cores”). In game scenarios where many concurrent heavy and light threads operate in a computing system, an external entity can allocate more of the shared common cache (L3) to the big cores handling more demanding processes, rather than to the small cores handling less computationally intensive tasks. These cache management operations prevent less important tasks from polluting the cache (cache pollution) and reduce the cache space available for heavier or more important tasks. This, in turn, allows all tasks to complete faster and / or may otherwise improve the overall performance of the computing system.

[0063] In some implementations, external entities may dynamically adjust MPAM configurations based on the operating frequency of tasks performed in a multi-core system, cache allocation, and / or workload. In some implementations, external entities may determine the load on the system based on the real-time operating frequency (effective frequency) of one or more cores.

[0064] In other words, the scheduler typically manages the load by distributing tasks among cores, and Dynamic Voltage and Frequency Scaling (DVFS) adjusts the core frequency based on this load. Therefore, external entities can use the effective frequency to adjust cache allocation, increasing cache allocation when the load is heavy and decreasing it when the load is light. In other words, an external entity can increase cache allocation in response to determining that the effective frequency is above or greater than a threshold (which may indicate higher compute demand or load, etc.). An external entity can decrease cache allocation in response to determining that the effective frequency is below or less than a threshold, thereby allowing for more efficient use of cache memory. This dynamic adjustment allows for more efficient use of cache memory and can be particularly beneficial during periods of high compute demand.

[0065] In some implementations, external entities can dynamically adjust parameters of other components (e.g., CPU, L1 cache, L2 cache, L3 cache, last-level cache, and DDR controller, etc.) in the memory transaction path beyond the cache controller, regardless of whether these components support MPAM. As an example, a DDR controller that does not directly support MPAM can expose parameters that can be adjusted to optimize bandwidth. External entities can adjust the exposed parameters each time they adjust the L3 cache space allocated to an application or process running on the computing system. Therefore, external entities can dynamically manage MPAM configuration, operating frequency, and cache allocation to match the changing workload of tasks performed in a multi-core system.

[0066] In some implementations, MPAM operations can be integrated with virtual machines (VMs) that allow for autonomous or hybrid configuration of MPAM. These implementations may be particularly beneficial in systems where VMs are not Linux-based or where each VM operates and makes decisions independently of the activities of other VMs.

[0067] In some implementations, the computing system may include a host OS and multiple virtual machines (VMs), including a primary VM (PVM), any or all of which may include various different operating systems. Furthermore, each VM may run different applications with different memory requirements. For example, one VM may run a security camera application, while the PVM may host multiple applications, including Android-based applications. In this example, the primary VM may not have full visibility into the overall system configuration, but it can pass its memory requirements to a secondary VM whose task is to manage MPAM configuration via an external entity. The secondary VM can receive MPAM configuration requests from all VMs in the system, compile or aggregate these MPAM configuration requests, and pass the aggregated requests to the external entity. The external entity can then adjust the MPAM settings based on the aggregated MPAM configuration requests from all VMs in the system.

[0068] In some implementations, a computing system can be configured to request a specific performance bandwidth mode for a particular VM by adjusting system resources (e.g., cache memory allocation, etc.) to increase the data processing power allocated to that VM in the system. Performance bandwidth can be a parameter that identifies the data processing power or throughput of a system or subsystem. For example, in a multi-core processor, each core may include a specific performance bandwidth in terms of how many instructions it can process per second. The total performance bandwidth of the system can be determined by adding the individual bandwidths of each core in the system. For virtual machines, performance bandwidth can identify the processing power allocated to each VM. For example, a VM with higher performance bandwidth may be able to process data faster than a VM with lower performance bandwidth.

[0069] Various implementation schemes can be implemented on multiple single-processor and multi-processor computer systems, including system-on-a-chip (SOC) or system-in-package (SIP) systems. Figure 1 Example computing systems or SIP 100 architectures that can be used in mobile computing devices implementing various implementation schemes are illustrated.

[0070] refer to Figure 1 The illustrated example SIP 100 includes two SOCs 102 and 104, a clock 106, a voltage regulator 108, and a wireless transceiver 166. The first SOC 102 and the second SOC 104 can communicate via an interconnect bus 150. Various processors 110, 112, 114, 116, 118, 121, and 122 can be interconnected with each other and to one or more memory elements 120, system components and resources 124, and a thermal management unit 132 via an interconnect bus 126, which may include advanced interconnects such as high-performance network-on-chip (NOC). Similarly, processor 152 can be interconnected to a power management unit 154, a millimeter-wave transceiver 156, memory 158, and various additional processors 160 via an interconnect bus 164. These interconnect buses 126, 150, and 164 may include arrays of reconfigurable logic gates and / or implement bus architectures (e.g., CoreConnect, AMBA, etc.). Communication can be provided by advanced interconnect components such as NOC.

[0071] In various implementation schemes, any or all of the processors 110, 112, 114, 116, 121, and 122 in the system can operate as the main processor, central processing unit (CPU), microprocessor unit (MPU), arithmetic logic unit (ALU), etc. of the SoC. One or more of the coprocessors 118 can operate as CPUCP.

[0072] In some implementations, the first SOC 102 may operate as a central processing unit (CPU) of a mobile computing device, which executes instructions by performing arithmetic, logic, control, and input / output (I / O) operations specified by instructions from software applications. In some implementations, the second SOC 104 may operate as a dedicated processing unit. For example, the second SOC 104 may operate as a dedicated 5G processing unit responsible for managing high-capacity, high-speed (e.g., 5Gbps) and / or ultra-high frequency short-wavelength (e.g., 28GHz millimeter-wave spectrum) communications.

[0073] The first SOC 102 may include a digital signal processor (DSP) 110, a modem processor 112, a graphics processor 114, an application processor 116, one or more coprocessors 118 (e.g., vector coprocessors, CPUCP, etc.) connected to one or more of these processors, memory 120, a deep processing unit (DPU) 121, an artificial intelligence processor 122, system components and resources 124, an interconnect bus 126, one or more temperature sensors 130, a thermal management unit 132, and a thermal power envelope (TPE) component 134. The second SOC 104 may include a 5G modem processor 152, a power management unit 154, an interconnect bus 164, multiple millimeter-wave transceivers 156, memory 158, and various additional processors 160, such as application processors, packet processors, etc.

[0074] Each processor 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may include one or more cores, and each processor / core may perform operations independently of other processors / cores. For example, the first SOC 102 may include a processor running a first type of operating system (e.g., FreeBSD, LINUX, OS X, etc.) and a processor running a second type of operating system (e.g., MICROSOFT WINDOWS 11). Additionally, any or all of processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be included as part of a processor cluster architecture (e.g., synchronous processor cluster architecture, asynchronous or heterogeneous processor cluster architecture, etc.).

[0075] Processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, and 160, or any or all of them, can operate as the CPU of a mobile computing device. Additionally, processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, and 160, or any or all of them, can be included as one or more nodes in one or more CPU clusters. A CPU cluster can be a group of interconnected nodes (e.g., processing cores, processors, SOCs, SIPs, computing devices, etc.) configured to work in a coordinated manner to perform computational tasks. Each node can run its own operating system and contains its own CPU, memory, and storage devices. Tasks assigned to the CPU cluster can be divided into smaller tasks, which are distributed across the nodes for processing. Nodes can work together to complete a task, with each node handling a portion of the computation. The results of the computations from each node can be combined to produce a final result. CPU clusters are particularly useful for tasks that can be parallelized and executed concurrently. This allows CPU clusters to complete tasks much faster than a single high-performance computer. Furthermore, because CPU clusters consist of multiple nodes, they are generally more reliable and less prone to failure than a single high-performance component.

[0076] The first SOC 102 and the second SOC 104 may include various system components, resources, and custom circuitry for managing sensor data, analog-to-digital conversion, wireless data transmission, and performing other specialized operations such as decoding data packets and processing encoded audio and video signals for presentation in a web browser. For example, the system components and resources 124 of the first SOC 102 may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients running on mobile computing devices. The system components and resources 124 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0077] The first SOC 102 and / or the second SOC 104 may also include input / output modules (not illustrated) for communicating with external resources such as clock 106, voltage regulator 108, and wireless transceiver 166 (e.g., cellular wireless transceiver, Bluetooth transceiver, etc.). External resources (e.g., clock 106, voltage regulator 108, wireless transceiver 166) may be shared by two or more internal SOC processors / cores.

[0078] In addition to the example SIP 100 discussed above, various implementations can be implemented in a wide variety of computing systems, including single processors, multiple processors, multi-core processors, or any combination thereof.

[0079] Figure 2 Example components that may be included in a computing system configured to allocate memory resources, according to an implementation scheme, are illustrated. References Figure 1 and Figure 2 The computing system 200 (e.g., SIP 100, SOC 102, 104, etc.) may include an MPAM requester 202 component, an MPAM data 204 component, and a memory system component 206. The MPAM data 204 component may include a PARTID space 208 component, a PARTID 210 component, and a performance monitoring group 212 component. The PARTID space 208 may indicate whether the MPAM is in a secure space (MPAM_S) or an insecure space (MPAM_NS).

[0080] Various components 202-212 can interact to manage and allocate memory resources in a computing system. The MPAM requester 202 component can be configured to generate or manage MPAM requests, which may include determining how memory resources should be allocated or deallocated based on factors such as workload requirements or system performance.

[0081] The MPAM data 204 component can be configured to store data related to memory partitioning and monitoring operations. The PARTID space 208 component indicates whether an MPAM operation is performed in the secure space (MPAM_S) or the insecure space (MPAM_NS). Each memory transaction within the system is assigned a unique PARTID 210. This identifier can be linked to a specific software application running on the system and / or associated with a cache configuration that defines the cache memory segments available to the corresponding software application. The Performance Management Group (PMG) 212 component can be configured to monitor and track system performance. For example, PMG 212 can provide insights into the efficiency of memory allocation and / or help inform decisions about how to adjust cache memory allocation to improve performance.

[0082] Memory system component 206 can be configured to manage physical memory resources. Memory system component 206 can receive memory transactions with a specific PARTID, determine the appropriate segment of the L3 cache memory based on the PARTID, and deliver the transaction to the appropriate segment of the L3 cache memory. Memory system component 206 may include an L3 cache controller configured to partition the L3 cache differently for each PARTID and allocate memory resources according to the specific needs of each application running on the system.

[0083] Figure 3 Examples of additional components that may be included in a computing system configured to allocate memory resources, according to an implementation scheme, are illustrated. Reference Figures 1 to 3 The computing system 300 (e.g., SIP 100, SOC 102, 104, computing system 200, etc.) may include an OS 330 component, an external entity 340 component, a CPU information 320 component, and a QOS parameter 322 component. The OS 330 component includes a kernel driver 302 component, an MPAM driver 304 component, a packer 306 component, and an SCMI framework 308 component. The external entity 340 component may include an SCMI framework 310 component, an MPAM driver 312 component, and a configuration MPAM register 314 component.

[0084] As mentioned above, some implementations may divide MPAM operations across two components: a request component and a configuration component. In some implementations, the kernel driver 302 component may be a request component included in or executed by a software application, kernel, or OS 330. In some implementations, configuring the MPAM register 314 may be a configuration component included in or executed by security software.

[0085] The OS 330 component operates on the system's main CPU. The OS 330 component can be configured to manage applications running on the system and interact with hardware. The kernel driver 302 generates MPAM configuration requests for the allocation or reallocation of memory resources. The MPAM driver 304 may include an application programming interface (API) that allows software applications to interact with the MPAM system. The packer 306 prepares data and packages it into an appropriate SCMI format. The SCMI framework 308 facilitates secure and efficient communication between the kernel driver 302 in the kernel / OS and the configuration component 314 in the security software.

[0086] External entity 340 may include security software operating on a CPUCP (e.g., coprocessor 118, etc.). In some embodiments, the external entity may be a CPUCP or coprocessor 118. The external entity may be configured to manage CPU resources and assist in configuring MPAM. The external entity may manage the partitioning of cache memory among different applications represented by different PARTIDs to improve resource utilization and reduce cache conflicts, cache pollution, and cache thrashing. The external entity may manage transitions between secure and insecure states, as well as simultaneous use of cache resources by software applications operating in secure and / or insecure states. The external entity may reduce cache pollution caused by inefficient simultaneous use by secure and insecure applications.

[0087] The SCMI framework 310 can be mirrored in OS 330 to ensure secure communication between the CPU and CPUCP. The MPAM driver 312 can be configured to allow CPUCP to control the MPAM from security software. The MPAM register configuration component 314 can be configured to directly modify MPAM settings based on requests from kernel driver 302.

[0088] The CPU Information 320 component can store data related to the CPU's status and performance, such as the current usage of CPU resources and performance metrics.

[0089] The QoS parameter 322 component stores QoS parameters that can be used to determine resource allocation and ensure that all processes meet their performance requirements. External entities can use QoS parameters for components that support both ARM and MPAM specifications, as well as for components that do not support either ARM or MPAM specifications.

[0090] Computing system 300 can provide external entities with access to MPAM configurations that would otherwise be accessible only to the CPU core. Computing system 300 can provide external entities with the authority to manage partitions of cache resources for different applications represented by different PARTIDs and to process other system parameters, thereby enhancing the efficiency of the entire transaction path from CPU to memory. Computing system 300 enhances the efficiency of the entire transaction path (not just at the L3 cache level).

[0091] Figure 4 This illustrates example transaction paths that can be traversed by a computing system configured according to various implementation schemes when operating in KERNEL_FULL_CONTROL mode. Reference Figures 1 to 4The computing system 400 (e.g., SIP 100, SOC 102, 104, computing system 200, 300, etc.) may include application component 402, OS component 330, external entity component 340 and MPAM register 404.

[0092] In KERNEL_FULL_CONTROL mode, the kernel in the OS 330 component controls the MPAM configuration, and the external entity 340 component implements these MPAM configurations by programming the MPAM register 404 according to the kernel's instructions without any changes.

[0093] Application 402 components may include software applications running on a computing system. Examples of software applications include user interface applications (e.g., web browsers, text editors, etc.) and background applications (e.g., servers, system monitors, etc.).

[0094] The OS 330 components may include a kernel that, during KERNEL_FULL_CONTROL mode, has complete control over the MPAM configuration for each segment or application. The kernel can make all decisions regarding how to allocate the system's memory resources among different software applications running on the system.

[0095] External Entity 340 (CPUCP) can be configured to implement kernel commands without any intervention. External Entity 340 can receive requests for specific configurations from the kernel or applications and program the MPAM registers precisely according to kernel instructions (without any modification).

[0096] MPAM register 404 can store MPAM configuration for how memory resources are allocated among software applications. External entity 340 can receive configuration data from the kernel and store that data in MPAM register 404.

[0097] Figure 5 Example components of a computing system that can be configured according to various implementation schemes are illustrated. References Figures 1 to 5 The computing system 500 (e.g., SIP 100, SOC 102, 104, computing system 200, 300, 400, etc.) may include an activity monitoring unit (AMU) 502, other monitors 504, a performance monitoring unit (PMU) 506, external entity 340, and MPAM register 404.

[0098] In SECURE_SW_FULL_CONTROL mode, decision power is provided to an external entity 340 (e.g., CPUCP), which can determine the MPAM configuration based on inputs from AMU 502, PMU 506, and other monitors 504. Therefore, the computing system 500 can dynamically adapt to changes in workload, temperature, power usage, and other factors to improve the performance and efficiency of the computing system.

[0099] The AMU 502 monitors CPU activity, allowing software applications to make more informed power management decisions. The AMU 502 measures and reports the utilization of computing resources, such as pipeline depth or renamed register utilization, which can be used to determine or characterize CPU behavior and identify performance bottlenecks.

[0100] Other monitors 504 may include any of a variety of monitoring systems or components within the computer system, such as a thermal monitor (which monitors CPU and system temperature), a power monitor (which monitors power consumption), and a system event monitor (which monitors system events such as interrupts, faults, or other important events).

[0101] The PMU 506 can be a component of the CPU configured to provide metrics and data related to processor performance. These metrics and data may include clock cycle measurements, cache hits and misses, instruction counts, and other low-level data, any or all of which can be used to determine or characterize processor behavior and identify performance bottlenecks.

[0102] In SECURE_SW_FULL_CONTROL mode, external entity 340 may assume complete control over MPAM configuration. External entity 340 may make decisions regarding MPAM configuration based on data received from AMU 502, PMU 506, and other monitors 504. The kernel in this mode may act as a pass-through operation, forwarding received information to external entity 340, which may override or ignore commands from the kernel while operating in this mode.

[0103] MPAM register 404 can store MPAM configurations for how memory resources are allocated among software applications. External entity 340 can make MPAM configuration decisions and store them in MPAM register 404. MPAM can then use the configurations stored in these registers to control how different parts of the cache are allocated or used.

[0104] Figures 6A to 6D and Figure 7 These are flowcharts illustrating methods 600, 620, 640, 660, and 700 for allocating memory resources in a computing system according to some implementation schemes. Figures 6A to 6D and Figure 7 The operations can be performed in a computing system by any or all of the processing units (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, etc.), components, or subsystems discussed herein. Used for execution Figures 6A to 6D and Figure 7 The functional components of the operation may include any or all of the processing units (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, etc.), components, or subsystems discussed in this application.

[0105] refer to Figures 1 to 6A In block 602 of method 600, the processing system may determine the current operating mode for MPAM configuration. The computing system may include multiple operating modes for MPAM configuration, such as KERNEL_FULL_CONTROL, HYBRID, and SECURE_SW_FULL_CONTROL. These operating modes can provide various levels of control to software applications or the kernel, ranging from complete control by the application / kernel to complete control by the security software. Hybrid modes can balance control between the application / kernel and the security software. These modes can intelligently adjust and control the MPAM configuration using various sensors and system parameters, such as thermal parameters, core count, effective frequency, DDR frequency, etc.

[0106] In some implementations, the determined operating mode (e.g., as determined in box 602 above) can influence how the kernel and / or CPUCP interact with the MPAM configuration. In other words, in some implementations, the choice of operating mode can directly affect resource allocation across different PARTIDs. Each operating mode allows processing units in the computing system to apply different strategies for resource allocation, focusing on prioritizing different balances between performance, security, and efficiency. For example, in KERNEL_FULL_CONTROL mode, the kernel can be responsible for allocating memory segments to software applications, and processing units can do so based on performance (e.g., by prioritizing high-demand applications or applications requiring immediate resource access). In SECURE_SW_FULL_CONTROL mode, an external entity (e.g., security software, etc.) can be responsible for allocating memory segments to software applications, and processing units can do so based on security (e.g., by prioritizing secure applications, trusted applications, or low-risk applications, etc.). In HYBRID mode, multiple control entities (e.g., the kernel and security software) can allocate memory segments to software applications. For example, in HYBRID mode, the kernel can enable processing units to allocate memory based on performance requirements, while allowing external entities or security software to adjust memory allocation to comply with security policies.

[0107] In box 604, the processing system can collect local information such as application execution requirements, QoS hints / tunable parameters, current workload information, and cache usage information. For example, in HYBRID mode, the coprocessor can modify, adjust, or ignore commands based on local information and local determinations before programming the MPAM. Examples of local information include application performance requirements, QoS hints / tunable parameters (system or application-level parameters that can be configured to meet specific performance, reliability, or other QoS objectives), current workload information, and cache usage information.

[0108] In box 606, the processing system may adjust MPAM settings based on system parameters, workload data, real-time parameters, hardware-specific data, thermal considerations, multi-core cache management information, etc. In some embodiments, the processing system may adjust MPAM settings based on collected local information. In some embodiments, the processing system may dynamically adjust the MPAM configuration based on workload data. Workload data may include information related to current tasks and processes operating within the system. In some embodiments, the processing system may dynamically adjust the MPAM configuration based on real-time parameters. Real-time parameters may include dynamic elements such as data on the current resource utilization of the system, network traffic, or operations. In some embodiments, the processing system may dynamically adjust the MPAM configuration based on hardware-specific data such as thermal sensor readings and the current state of CPU cores. In some embodiments, the processing system may dynamically adjust the MPAM configuration based on thermal considerations. In some embodiments, the processing system may dynamically adjust the MPAM configuration based on multi-core cache management information.

[0109] In block 608, the processing system can determine the system load. For example, in some implementations, an external entity can determine the load on the system based on the real-time operating frequency (effective frequency) of one or more cores. That is, a scheduler typically manages the load by distributing tasks among cores, and Dynamic Voltage and Frequency Scaling (DVFS) can adjust the core frequencies based on this load. Therefore, the external entity can use the effective frequency to adjust cache allocation, increasing cache allocation when the load is heavy and decreasing cache allocation when the load is light. In other words, the external entity can increase cache allocation in response to determining that the effective frequency is above or greater than a threshold (which may indicate higher computational demand or load, etc.). The external entity can decrease cache allocation in response to determining that the effective frequency is below or less than a threshold, thereby allowing for more efficient use of cache memory. This dynamic adjustment allows for more efficient use of cache memory and can be particularly beneficial during periods of high computational demand.

[0110] In box 610, the processing system can adjust cache allocation. For example, the processing system can use an effective frequency to adjust cache allocation, increasing cache allocation when the load is heavy and decreasing cache allocation when the load is light. For example, if a software application is more memory-intensive or requires a larger portion of cache memory to operate efficiently, the processing system can allow a larger cache allocation for that application, thereby improving the application's performance. On the other hand, if another software application is less memory-intensive or has a lower priority, the processing system can limit the cache usage of that software application, thereby reserving memory resources that can be better utilized by higher-priority or memory-intensive applications.

[0111] In box 612, the processing system can adjust other components. For example, the processing system can dynamically adjust parameters of other components (e.g., CPU, L1 cache, L2 cache, L3 cache, last-level cache, and DDR controller, etc.) in the memory transaction path beyond the cache controller, regardless of whether these components support MPAM. As an example, a DDR controller that does not directly support MPAM can expose parameters that can be adjusted to optimize bandwidth. External entities can adjust the exposed parameters each time they adjust the L3 cache space allocated to an application or process running on the computing system. Thus, external entities can dynamically manage MPAM configuration, operating frequency, and cache allocation to match the changing workload of tasks performed in a multi-core system.

[0112] refer to Figures 1 to 6B In block 622 of method 620, the processing system can determine that the current operating mode used for MPAM configuration is KERNEL_FULL_CONTROL.

[0113] In box 624, the processing system allows the kernel to assume complete control over the MPAM configuration for each segment or application. That is, when operating in KERNEL_FULL_CONTROL mode, the kernel assumes complete control over the MPAM configuration for each segment or application. External entities can be configured to implement kernel commands without intervention. For example, a request for a specific configuration can be sent directly from the kernel to an external entity (e.g., a coprocessor or CPUCP) that can precisely program the MPAM registers according to the kernel's instructions without any modification. The external entity can transfer the kernel's configuration data to the MPAM registers and log the information. Therefore, in box 626, the processing system can process requests for specific configurations from the kernel. In box 628, the processing system can program the MPAM registers according to the kernel's instructions without any modification.

[0114] refer to Figures 1 to 6CIn block 642 of method 640, the processing system may determine that the current operating mode for MPAM configuration is SECURE_SW_FULL_CONTROL. In block 644, the processing system may delegate full control of MPAM configuration to an external entity (coprocessor 118 or CPUCP). That is, when operating in SECURE_SW_FULL_CONTROL mode, the external entity may assume full control of MPAM configuration. The kernel may act as a transparent operation by forwarding received information to the external entity to configure MPAM. In this mode, the external entity may override or ignore kernel commands. Therefore, in block 646, the processing system may act as a transparent operation by forwarding received information to the external entity. In block 648, the processing system may allow the external entity to override or ignore kernel commands.

[0115] refer to Figures 1 to 6D In block 662 of method 660, the processing system may determine that the current operating mode for MPAM configuration is HYBRID mode. In block 664, the processing system may allow both the kernel and external entities to participate in the control configuration (achieving a balance between them). That is, HYBRID mode allows both external entities and the kernel to participate in the control configuration to balance control between the kernel and the coprocessor. In HYBRID mode, the kernel may (e.g., via a configuration request) provide some of the commands or instructions to the coprocessor. Before programming the MPAM, the coprocessor may modify, adjust, or ignore commands based on local information and local determinations. Examples of local information that may be used by external entities include application performance requirement information, QoS hints / tunable parameters (system or application-level parameters that can be configured to meet specific performance, reliability, or other QoS goals), current workload information, and cache usage information.

[0116] In box 666, the processing system can transmit commands from the kernel to external entities.

[0117] In box 668, the processing system allows external entities to modify, adjust, or ignore these commands based on local information and local determinations before programming the MPAM.

[0118] refer to Figures 1 to 7 In block 702 of method 700, the processing system may integrate MPAM operations with virtual machines (VMs) to allow for autonomous or hybrid mode configuration of MPAM. In some implementations, the VMs may operate independently of each other.

[0119] In block 704, the processing system can configure the system such that a primary virtual machine (PVM) transfers its memory requirements to a secondary virtual machine managing the MPAM configuration via an external entity. In some embodiments, the system may include a host OS and multiple virtual machines (including the primary virtual machine (PVM)), each running different applications with different memory requirements.

[0120] In box 706, the processing system can aggregate MPAM configuration requests from all VMs in the system.

[0121] In box 708, the processing system can transmit the aggregated requests to external entities.

[0122] In box 710, the processing system can adjust MPAM settings based on the aggregated requests.

[0123] In box 712, the processing system may request specific performance bandwidth. For example, the system may configure the computing system to request a specific performance bandwidth mode for a particular VM by adjusting system resources to increase the data processing power allocated to that VM in the system. As discussed above, performance bandwidth can be a parameter that identifies the data processing power or throughput of a system or subsystem. For example, in a multi-core processor, each core may include a specific performance bandwidth in terms of how many instructions it can process per second. The total performance bandwidth of the system can be determined by adding the individual bandwidths of each core in the system. For virtual machines, performance bandwidth can identify the processing power allocated to each VM. For example, a VM with higher performance bandwidth may be able to process data faster than a VM with lower performance bandwidth.

[0124] Figures 8A to 8D These are flowcharts illustrating methods 800, 810, 820, and 830 for allocating memory resources in a computing system according to some implementation schemes. Figures 8A to 8D The operations can be performed in a computing system by any or all of the processing units (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, etc.), components, or subsystems discussed herein. Used for execution Figures 8A to 8D The functional components of the operation may include any or all of the processing units (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, etc.), components, or subsystems discussed in this application.

[0125] For clarity and ease of presentation, methods 600, 620, 640, 660, 700, 800, 810, 820, and 830 are presented as individual embodiments. While each method is depicted for illustrative purposes, it will be apparent to those skilled in the art that various combinations or omissions of these methods, blocks, operations, etc., can be used to achieve desired or specific results. It should also be understood that the description herein does not preclude the integration or adaptation of different embodiments of methods, blocks, operations, etc., to produce modified or alternative results or solutions. Unless expressly stated in the claims, the presentation of the various methods, blocks, operations, etc., should not be construed as mutually exclusive, limiting, or required.

[0126] refer to Figures 1 to 8A In method 800 ( Figure 8A In block 602 and methods 810, 820, 830, the processing system may perform operations as described in blocks similarly numbered in method 600. For example, the processing system may proactively determine the current operating mode for MPAM configuration, which in turn may set the underlying strategy for how resources will be managed and allocated across the system. In some embodiments, determining the operating mode may include analyzing current system conditions, workload requirements, and security requirements. In some embodiments, determining the operating mode may also include analyzing any of a variety of sensor and system parameters, such as thermal conditions, core count, effective frequency, and DDR frequency, to make an informed decision about the most suitable operating mode. In some embodiments, the processing system may use the analysis results to select between KERNEL_FULL_CONTROL mode, SECURE_SW_FULL_CONTROL mode, and HYBRID mode. In some embodiments, the selection or determination of the operating mode in block 602 may directly affect the overall approach to subsequent actions and resource allocation on the computing system.

[0127] In box 804, the processing system can allocate memory segments, represented by different PARTIDs, to software applications operating on the computing system based on a determined operating mode. For example, in KERNEL_FULL_CONTROL mode, the processing system can allocate memory segments to software applications to prioritize applications requiring high bandwidth or processing speed. The processing system can also dynamically adjust resource distribution based on real-time performance metrics. As another example, in SECURE_SW_FULL_CONTROL mode, the processing system can allocate memory segments to software applications to prioritize applications that use secure memory segments to process sensitive data. In HYBRID mode, the processing system can allocate memory segments to software applications by merging performance and security policies and / or enabling or allowing both the kernel and security software to collaboratively determine resource allocation.

[0128] refer to Figures 1 to 8B In method 810 ( Figure 8B In box 602, the processing system can perform operations of similarly numbered boxes as described in methods 600 and 800.

[0129] In block 812, the processing system can partition MPAM operations between the request component in the kernel and the configuration component in the security software. In some embodiments, in block 812, the processing system can perform operations of any of blocks 622, 624, 642, 644, 646, 648, 662, 664, 666, and 668 of methods 620, 640, and 660 as described.

[0130] In block 814, the processing system may use the SCMI framework or other inter-processor or inter-processor communication mechanisms or protocols to securely communicate information between a requesting component included in the kernel portion of the computing system and a configuration component included in the security software portion of the computing system. In some embodiments, in block 814, the processing system may perform any of the operations described in blocks 646, 648, 666, and 668.

[0131] In box 804, the processing system may perform the operations of similarly numbered boxes as described in method 800.

[0132] refer to Figures 1 to 8C In method 820 ( Figure 8C In box 602, the processing system can perform operations of similarly numbered boxes as described in methods 600, 800 and 810.

[0133] In box 812, the processing system can perform the operations of similarly numbered boxes as described in method 810.

[0134] In box 824, the processing system can use the SCMI framework to transmit MPAM configuration request messages to a configuration component included in the security software and operating on the CPUCP. For example, the processing system can generate commands based on current and predicted future workload requirements or resource availability, and encode the generated commands in a format compatible with the SCMI framework. The configuration component within the security software can receive and analyze the commands to make real-time adjustments to cache allocations or other memory management parameters. In some implementations, the configuration component can use the dedicated processing capabilities of the CPUCP for these adjustments.

[0135] In block 826, the processing system may partition the cache memory for use by multiple software applications operating on the computing system based on the specific requirements or priority levels of each software application within the software application (e.g., via CPUCP). In some embodiments, the processing system may partition the cache memory based on MPAM configuration or QoS parameters associated with components not configured to support MPAM operation to reduce cache conflicts, cache pollution, or cache thrashing. In some embodiments, the processing system may partition the cache memory such that a portion of the cache memory is reserved for secure applications, and the remaining portion of the cache memory is reserved for non-secure applications.

[0136] In box 804, the processing system may perform the operations of similarly numbered boxes as described in method 800.

[0137] refer to Figures 1 to 8D In method 830 ( Figure 8D In box 602, the processing system can perform operations of boxes with similar numbers as described in methods 600, 800, 810, 820.

[0138] In box 804, the processing system can perform operations similarly numbered to those in method 800 as described. Figure 8D In the illustrated example, the operations of box 804 include operations of boxes 622, 642, and 662 as described in methods 620, 640, and 660. The operations of box 804 may include any or all of the operations discussed with reference to boxes 832-846.

[0139] In response to determining in box 622 that the operating mode is KERNEL_FULL_CONTROL mode, in box 832, the processing system may enable or allow the kernel to assume control over the MPAM configuration for each memory segment or software application. As discussed, this control may allow the kernel to directly manage memory resources. The kernel may, for example, dynamically adjust memory segments and / or prioritize memory allocations for high-demand applications based on application performance metrics or system conditions.

[0140] In box 834, the processing system enables or allows CPUCP to implement kernel commands without modification. As discussed, these operations allow the kernel to retain master control and use CPUCP to efficiently execute configuration or allocation policies.

[0141] In response to determining in block 642 that the operating mode is SECURE_SW_FULL_CONTROL mode, in block 836, the processing system may enable or allow the kernel to operate as a pass-through component that forwards received information to the CPUCP. As discussed, in some implementations, these operations may include synchronizing operations between the kernel and the CPUCP to improve or maintain security, performance, efficiency, etc.

[0142] In block 838, the processing system may enable or allow the CPUCP to assume complete control over the MPAM configuration for each memory segment or software application. As discussed, the processing system may grant the CPUCP autonomy to manage critical memory resources and perform additional operations to maintain system integrity, prevent resource conflicts, etc.

[0143] In response to determining in block 662 that the operating mode is HYBRID mode, in block 840, the processing system may enable or allow the kernel and CPUCP to share control over the MPAM configuration for each memory segment or software application. As discussed, this shared control can improve the performance and functionality of the computing system.

[0144] In box 842, the processing system can enable or allow the kernel to issue commands proposing specific performance configurations, such as CPU performance configurations or system performance configurations. These operations allow the kernel to dynamically adapt to changing conditions.

[0145] In box 844, the processing system may enable or allow the CPUCP to dynamically adjust commands based on workload data, real-time system parameters, or additional system information (e.g., data on current resource utilization on the computing system, network traffic, current operations, hardware-specific data, etc.). For example, as discussed, these operations may allow the computing system to implement dynamic resource management strategies to improve computational efficiency and system responsiveness.

[0146] In box 846, the processing system can allocate memory segments to software applications represented by different PARTIDs. For example, the processing system can distribute memory resources among applications based on current or predicted future resource requirements.

[0147] Various implementation plans (including but not limited to the above references) Figures 1 to 9 The described implementation scheme can be implemented in a wide variety of computing systems, including a laptop computer 900, an example of which is... Figure 9 Example in. refer to Figures 1 to 9The laptop computer 900 may include a processor 902 coupled to volatile memory 904 and a disk drive 906 containing mass non-volatile memory (such as flash memory). The laptop computer 900 may include a touchpad touch surface 908 serving as a pointing device for the computer and thus capable of receiving drag, scroll, and tap gestures. Additionally, the laptop computer 900 may have one or more antennas 910 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular transceiver 912 coupled to the processor 902. The laptop computer 900 may also include a BT transceiver 914 coupled to the processor 902, a compact disc (CD) drive 916, a keyboard 918, and a display 920. Other configurations of the computing system may include a computer mouse or trackball, as is well known, coupled to the processor (e.g., via a Universal Serial Bus (USB) input), which may also be used in various implementations.

[0148] Figure 10 This is another example of a component block diagram suitable for use with various implementation schemes. Reference Figures 1 to 10 Various implementation schemes can be implemented on a variety of computing systems, examples of which are shown in Figure 10 The example is illustrated as a smartphone 1000. The smartphone 1000 may include a first SoC 102 coupled to a second SoC 104. The first SoC 102 and the second SoC 104 may be coupled to internal memory 1016, a display 1012, and a speaker 1014. The first SoC 102 and the second SoC 104 may also be coupled to at least one subscriber identity module (SIM) 1040 and / or a SIM interface, which may store information supporting a first 5G NR subscription and a second 5G NR subscription, supporting services on a 5G non-autonomous (NSA) network.

[0149] The smartphone 1000 may include an antenna 1004 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless transceiver 166 coupled to one or more processors in a first SOC 102 and / or a second SOC 104. The smartphone 1000 may also include menu selection buttons or a joystick switch 1020 for receiving user input.

[0150] The smartphone 1000 also includes a voice encoding / decoding (CODEC) circuit 1010, which digitizes sound received from the microphone into data packets suitable for wireless transmission and decodes the received voice data packets to generate an analog signal provided to the speaker to produce sound. Furthermore, one or more of the processor in the first circuit 102 and the second circuit 104, the wireless transceiver 166, and the CODEC 1010 may include a digital signal processor (DSP) circuit (not shown separately).

[0151] The processor or processing unit discussed in this application can be any programmable microprocessor, microcomputer, or one or more multiprocessor chips that can be configured via software instructions (applications) to perform a variety of functions, including those described in the various embodiments. In some computing systems, multiple processors may be provided, such as one processor within a first circuit dedicated to wireless communication functions and another processor within a second circuit dedicated to running other applications. Software applications may be stored in memory and then accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0152] The following paragraphs describe specific implementation examples. While some of the specific implementation examples below are described as example methods, further example implementations may include: example methods discussed in the following paragraphs that can be implemented by a computing system including a processor configured (e.g., configured with processor-executable instructions) to perform the operations of the methods of the following specific implementation examples; example methods discussed in the following paragraphs that are implemented by a computing system including components that have functionality for performing the methods of the following specific implementation examples; and example methods discussed in the following paragraphs that can be implemented as a non-transitory processor-readable storage medium storing processor-executable instructions configured to cause a processor of a computing system to perform the operations of the methods of the following specific implementation examples.

[0153] Example 1. A method for allocating memory resources in a computing system through centralized MPAM operations, the method comprising: determining the operating mode of the computing system; and, based on the determined operating mode, allocating memory segments to software applications operating on the computing system, represented by different PARTIDs.

[0154] Example 2. According to the method of Example 1, the method further includes: dividing the MPAM operation between a request component included in the kernel portion of the computing system and a configuration component included in the security software portion of the computing system; and using the SCMI framework of the computing system or other IPC mechanism or protocol to securely communicate information between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system.

[0155] Example 3. The method according to any one of Examples 1 or 2, wherein using the SCMI framework of the computation to securely communicate information between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system comprises: using the SCMI framework to communicate information between the central processing unit (CPU) core of the computing system and the CPUCP of the computing system.

[0156] Example 4. The method according to any one of Examples 1 to 3, wherein communicating information between the CPU core in the computing system and the CPUCP in the computing system using the SCMI framework includes: transmitting an MPAM configuration request message to the configuration component included in the security software portion and operating on the CPUCP using the SCMI framework.

[0157] Example 5. The method according to any one of Examples 1 to 4, the method further comprising partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software application for use by multiple software applications operating on the computing system.

[0158] Example 6. The method according to any one of Examples 1 to 5, wherein partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software application for use by multiple software applications operating on the computing system includes: partitioning the cache memory by the CPUCP based on MPAM configuration and / or QoS parameters to reduce cache conflicts, cache pollution, or cache thrashing.

[0159] Example 7. The method according to any one of Examples 1 to 6, wherein the QoS parameter is associated with a component that is not configured to support MPAM operation.

[0160] Example 8. The method according to any one of Examples 1 to 5, wherein partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software application for use by multiple software applications operating on the computing system comprises: partitioning the cache memory by the CPUCP such that a portion of the cache memory is reserved for secure applications and the remaining portion of the cache memory is reserved for non-secure applications.

[0161] Example 9. The method according to any one of Examples 1 to 8, wherein: the kernel assumes complete control over the MPAM configuration for each memory segment or software application, and when the computing system operates in KERNEL_FULL_CONTROL mode, the CPUCP implements the kernel's commands without modification; the kernel operates as a pass-through component by forwarding received information to the CPUCP, and when the computing system operates in SECURE_SW_FULL_CONTROL mode, the CPUCP assumes complete control over the MPAM configuration for each memory segment or software application; and when the computing system operates in HYBRID mode, the kernel and the CPUCP share control over the MPAM configuration for each memory segment or software application.

[0162] Example 10. The method according to any one of Examples 1 to 9, wherein: the computing system operates in the HYBRID mode; the kernel issues a command proposing a specific performance configuration, such as CPU performance configuration (CPU_PERF_CONFIG) or system performance configuration (SYSTEM_PERF_CONFIG); and the CPUCP dynamically adjusts the command to adjust the MPAM configuration based on workload data, real-time system parameters, or additional system information, such as data on current resource utilization on the computing system, network traffic, current operations (e.g., data read, write, processing tasks, etc.) or hardware-specific data (e.g., thermal sensor readings, current state of CPU cores, etc.).

[0163] Example 11. The method according to any one of Examples 1 to 10, wherein the operation of allocating memory segments to software applications represented by different PARTIDs operating on the computing system is performed in a virtual machine (VM) configured to allow autonomous or hybrid mode configuration of MPAM.

[0164] Example 12. A method for allocating memory resources in a computing system, the method comprising: receiving a kernel request for MPAM configuration in a security software portion of the computing system by a CPUCP of the computing system; and configuring one or more MPAM registers in the computing system based on the received kernel request by the CPUCP.

[0165] Example 13. The method according to Example 12, wherein configuring the one or more MPAM registers in the computing system based on a received kernel request includes the CPUCP coordinating the MPAM configuration across multiple security states or between secure and insecure operations.

[0166] Example 14. The method according to any one of Examples 12 or 13, the method further includes selecting one of a plurality of operating modes, the plurality of operating modes including: KERNEL_FULL_CONTROL mode; SECURE / CPUCP_SW_FULL_CONTROL mode; or HYBRID_MODE.

[0167] Example 15. The method according to any one of Examples 12 to 14, wherein configuring the one or more MPAM registers in the computing system based on the received kernel request includes allocating cache via MPAM and configuring additional Quality of Service (QOS) parameters using various system parameters including thermal parameters, core count parameters, effective frequency parameters and DDR parameters.

[0168] Example 16. The method according to any one of Examples 12 to 15, wherein configuring the one or more MPAM registers in the computing system based on a received kernel request includes configuring the one or more MPAM registers using an autonomous or hybrid mode of a virtual machine (VM) and the security software.

[0169] As used herein, the terms “component,” “module,” “system,” etc., are intended to include computer-related entities such as, but not limited to, hardware, firmware, combinations of hardware and software, software, or software being executed, configured to perform specific operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of example, both an application running on a computing system and a computing system or computing device can be referred to as a component. One or more components may reside within a process and / or a thread of execution, and components may reside on a processor or core and / or be distributed across two or more processors or cores. Furthermore, these components may execute on various non-transitory computer-readable media on which various instructions and / or data structures are stored. Components may communicate via local and / or remote processes, function or procedure calls, electronic signals, data packets, memory read / write, and other known network, computer, processor, and / or process-related communication methods.

[0170] A variety of different memory types and memory technologies are available or conceivable in the future, and any or all of these different memory types and memory technologies can be included and used in systems and computing systems to implement various implementation schemes. Such memory technologies / types may include non-volatile random access memory (NVRAM), such as magnetoresistive RAM (M-RAM), resistive random access memory (ReRAM or RRAM), phase-change random access memory (PC-RAM, PRAM, or PCM), ferroelectric RAM (F-RAM), spin-transfer torque magnetoresistive random access memory (STT-MRAM), and 3D-XPOINT memory. Such memory technologies / types may also include non-volatile or read-only memory (ROM) technologies, such as programmable read-only memory (PROM), field-programmable read-only memory (FPROM), and one-time programmable non-volatile memory (OTP NVM). Such memory technologies / types may also include volatile random access memory (RAM) technologies, such as dynamic random access memory (DRAM), double data rate (DDR) synchronous dynamic random access memory (DDR SDRAM), static random access memory (SRAM), and pseudo static random access memory (PSRAM). Computing systems and devices implementing various embodiments may also include or use electronic (solid-state) non-volatile computer storage media, such as flash memory. Each of the memory technologies mentioned above includes, for example, elements suitable for storing instructions, programs, control signals, and / or data for use in or for use in: advanced driver assistance systems (ADAS), state-of-the-art (SOC), or other electronic components of a vehicle. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless expressly stated in the language of the claims.

[0171] The various embodiments illustrated and described are provided merely as examples illustrating the various features of the claims. However, the features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and may be used or combined with other embodiments shown and described. Furthermore, the claims are not intended to be limited to any one of the exemplary embodiments. For example, one or more operations of the method may substitute for or combine with one or more operations of the method.

[0172] The foregoing method descriptions and process flowcharts are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the given order. As those skilled in the art will appreciate, the operations in the foregoing embodiments can be performed in any order. Words such as “afterward,” “then,” “next,” etc., are not intended to restrict the order of operations; these words are only used to guide the reader through the description of the method. Furthermore, any reference to singular claim elements (e.g., references using the articles “a,” “an,” or “described”) should not be construed as limiting that element to the singular.

[0173] The various exemplary logic blocks, modules, circuits, and algorithmic operations described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. While those skilled in the art may implement the described functionality in different ways for each specific application, such implementation decisions should not be construed as departing from the scope of the claims.

[0174] Hardware for implementing the various exemplary logic components, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of programmable devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0175] In one or more embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operation of the methods or algorithms disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to store object program code in the form of instructions or data structures and is accessible by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while optical discs utilize lasers to optically copy data. Combinations of the above may also be included within the scope of non-transitory computer-readable and processor-readable media. In addition, the operation of a method or algorithm may reside as a single piece of code and / or instruction, or any combination or set of code and / or instructions, on a non-transitory processor-readable medium and / or computer-readable medium that may be incorporated into a computer program product.

[0176] The above description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the scope of the claims. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but should be granted the broadest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A method for allocating memory resources in a computing system through centralized memory system resource partitioning and monitoring (MPAM) operations, the method comprising: Determine the operating mode of the computing system; as well as Based on the determined operating mode, memory segments are allocated to software applications operating on the computing system, each represented by a different partition identifier (PARTID).

2. The method according to claim 1, further comprising: The MPAM operation is divided between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system; as well as Using the System Control and Management Interface (SCMI) framework of the computing system or other inter-processor communication mechanisms or protocols, information is securely communicated between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system.

3. The method according to claim 1, further comprising: The MPAM operation is divided between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system; as well as The System Control and Management Interface (SCMI) framework is used to transmit MPAM configuration request messages to the configuration component, which is included in the security software portion and operates on the central processing unit (CPU) coprocessor (CPUCP) of the computing system.

4. The method according to claim 3, further comprising: The CPUCP partitions the cache memory based on the specific requirements or priority level of each software application in the software application so that it can be used by multiple software applications operating on the computing system.

5. The method of claim 4, wherein partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software application for use by multiple software applications operating on the computing system comprises: The CPUCP partitions the cache memory based on MPAM configuration or Quality of Service (QoS) parameters associated with components not configured to support MPAM operations to reduce cache conflicts, cache pollution, or cache thrashing.

6. The method of claim 4, wherein partitioning the cache memory by the CPUCP based on the specific requirements or priority level of each software application in the software applications for use by multiple software applications operating on the computing system comprises: The CPUCP partitions the cache memory such that one portion of the cache memory is reserved for security applications, and the remaining portion of the cache memory is reserved for non-security applications.

7. The method according to claim 1, wherein: The kernel portion of the computing system assumes complete control over the MPAM configuration for each memory segment or software application, and when the computing system operates in KERNEL_FULL_CONTROL mode, the CPU coprocessor (CPUCP) of the computing system implements the kernel's commands without modification. The kernel operates as a pass-through component by forwarding received information to the CPUCP, and when the computing system operates in SECURE_SW_FULL_CONTROL mode, the CPUCP assumes complete control over the MPAM configuration for each memory segment or software application; and When the computing system operates in HYBRID mode, the kernel and the CPUCP share control over the MPAM configuration for each memory segment or software application.

8. The method according to claim 7, wherein: The computing system operates in the HYBRID mode; The kernel issues a command proposing a specific performance configuration, such as a CPU performance configuration or a system performance configuration; and The CPUCP dynamically adjusts the commands to adjust the MPAM configuration based on workload data, real-time system parameters, or additional system information, including data on current resource utilization on the computing system, network services, current operations, or hardware-specific data.

9. The method of claim 1, wherein the operation of allocating a memory segment to a software application represented by a PARTID operating on the computing system is performed in a virtual machine configured to allow autonomous or hybrid mode operation of MPAM.

10. A computing system, the computing system comprising: Memory; and A central processing unit (CPU) coprocessor (CPUCP) coupled to the memory, wherein the CPUCP is configured to: Determine the operating mode of the computing system; and Based on the determined operating mode, memory segments are allocated to software applications operating on the computing system, each represented by a different partition identifier (PARTID).

11. The computing system of claim 10, wherein the CPUCP is further configured to: The memory system resource partitioning and monitoring (MPAM) operation is divided between the request component included in the kernel portion of the computing system and the configuration component included in the security software portion of the computing system; and The System Control and Management Interface (SCMI) framework is used to transmit MPAM configuration request messages to the configuration component, which is included in the security software portion and operates on the CPUCP.

12. The computing system of claim 11, wherein the CPUCP is further configured to: The cache memory is partitioned based on the specific requirements or priority level of each software application in the software application so that it can be used by multiple software applications operating on the computing system.

13. The computing system of claim 11, wherein the CPUCP is further configured to: The cache memory is partitioned so that one portion is reserved for security applications and the remaining portion is reserved for non-security applications.

14. The computing system according to claim 10, wherein: The kernel portion of the computing system assumes complete control over the MPAM configuration for each memory segment or software application, and when the computing system operates in KERNEL_FULL_CONTROL mode, the CPUCP implements the kernel's commands without modification. The kernel operates as a pass-through component by forwarding received information to the CPUCP, and when the computing system operates in SECURE_SW_FULL_CONTROL mode, the CPUCP assumes complete control over the MPAM configuration for each memory segment or software application; and When the computing system operates in HYBRID mode, the kernel and the CPUCP share control over the MPAM configuration for each memory segment or software application.

15. The computing system according to claim 14, wherein: The computing system operates in the HYBRID mode; The kernel issues a command proposing a specific performance configuration, which may include CPU performance configuration or system performance configuration; and The CPUCP dynamically adjusts the commands to adjust the MPAM configuration based on workload data, real-time system parameters, or data on current resource utilization, network services, current operations, or hardware-specific data on the computing system.

16. A method for allocating memory resources in a computing system, the method comprising: The CPU coprocessor (CPUCP) of the computing system receives kernel requests for memory system resource partitioning and monitoring (MPAM) configuration in the security software portion of the computing system; and The CPUCP configures one or more MPAM registers in the computing system based on received kernel requests.

17. The method of claim 16, wherein configuring the one or more MPAM registers in the computing system based on a received kernel request includes the CPUCP coordinating the MPAM configuration across multiple security states or between secure and insecure operations.

18. The method of claim 16, further comprising selecting one of a plurality of operating modes, the plurality of operating modes including: KERNEL_FULL_CONTROL mode; SECURE / CPUCP_SW_FULL_CONTROL mode, or HYBRID_MODE.

19. The method of claim 16, wherein configuring the one or more MPAM registers in the computing system based on the received kernel request includes allocating cache via MPAM and configuring additional Quality of Service (QOS) parameters using system parameters including thermal parameters, core count parameters, effective frequency parameters, and DDR parameters.

20. A computing system, the computing system comprising: Memory; One or more memory system resource partitioning and monitoring (MPAM) registers; and A central processing unit (CPU) coprocessor (CPUCP) coupled to the memory and the one or more MPAM registers, wherein the CPUCP is configured to: Receive kernel requests for memory system resource partitioning and monitoring (MPAM) configuration in the security software portion of the computing system; Configure one or more MPAM registers in the computing system based on received kernel requests, including coordinating the MPAM configuration across multiple security states or between secure and insecure operations; as well as Select one of a plurality of operating modes, wherein the plurality of operating modes include: KERNEL_FULL_CONTROL mode; SECURE / CPUCP_SW_FULL_CONTROL mode, or HYBRID_MODE.

Images