Server fault positioning system and method

Abstract

The invention relates to a server fault positioning system and method, and the system comprises a debugging card and a mainboard, and the debugging card is electrically connected with the mainboard. The debugging card is used for acquiring a power-on self-test code of the mainboard and matching the power-on self-test code with a pre-stored fault code library; determining a fault code corresponding to the power-on self-test code, and determining a fault module corresponding to the fault code in the target server; the mainboard is used for calling and starting BIOS debugging firmware stored in the debugging card, entering a debugging mode and obtaining enumeration information of a fault module; the debugging card is also used for analyzing the enumeration information and determining a state code corresponding to each unit included in the fault module; respectively matching each state code with a pre-stored state code library; and determining a fault state code which cannot be matched with the correct state code in the state code library, and determining a fault unit corresponding to the fault state code. Through the method and the device, the problem of relatively low fault positioning efficiency of the server in related technologies is solved.

Description

Technical Field

[0001] This application belongs to the technical field of server management, and particularly relates to a server fault location system and method. Background Art

[0002] As the core facility for data storage, processing, and transmission, the stability and reliability of a server are crucial. With the continuous development of the server industry and related technologies, its functions are constantly enriched, the design is becoming more and more complex, and the integration degree is getting higher and higher. This not only increases the design difficulty but also increases the possibility of server failures. These failures may be caused by various factors such as hardware, software, or network.

[0003] When a server issues an alarm message due to a change in the register state inside its Central Processing Unit (CPU), since this alarm message is usually rather general and it is impossible to directly determine which peripheral or component causes the failure, this poses a great challenge to the fault location work of operation and maintenance personnel. Traditional fault location methods usually include steps such as manually disassembling the machine, performing minimum system verification, and powering on peripherals one by one. Such fault location methods often take a long time and are inefficient. Especially when it comes to key components such as power supply, CPU, and memory, inaccurate fault location may lead to an increase in repair efficiency and affect business continuity.

[0004] Currently, no effective solution has been proposed for the problem of low fault location efficiency of servers in related technologies. Summary of the Invention

[0005] Embodiments of this application provide a server fault location system and method to at least solve the problem of low fault location efficiency of servers in related technologies.

[0006] In a first aspect, an embodiment of the present application provides a server fault location system, including: a debug card and a motherboard. Among them, the motherboard is disposed in a target server, and the debug card is electrically connected to the motherboard; the debug card is configured to obtain the power-on self-test code of the motherboard, and match the power-on self-test code with a preset fault code library stored in the debug card; determine the fault code corresponding to the power-on self-test code, and determine the fault module in the target server corresponding to the fault code; the motherboard is configured to call and start the BIOS debug firmware stored in the debug card, enter the debug mode, and obtain the enumeration information of the fault module; the debug card is further configured to parse the enumeration information, determine the status code corresponding to each unit included in the fault module; match each of the status codes with a preset status code library stored in the debug card; determine the fault status code that cannot be matched with any correct status code in the status code library, and determine the fault unit corresponding to the fault status code.

[0007] In some embodiments, the debug card includes a processor, a memory, an interface module, and a communication module, and the motherboard includes a controller, a PCH chip, and a CPLD chip; the debug card establishes communication with the controller, the PCH chip, and the CPLD chip through the communication module, the debug card is electrically connected to the motherboard through the interface module, and the memory stores the fault code library and the status code library. Among them, the fault code library includes multiple fault codes and the fault module information corresponding to each fault code, and the status code library includes multiple correct status codes and the unit information corresponding to each correct status code.

[0008] In some embodiments, the processor includes a first set of GPIO pins and a second set of GPIO pins, the CPLD chip includes a third set of GPIO pins, and the PCH chip includes a fourth set of GPIO pins. Among them, the first set of GPIO pins is connected to the third set of GPIO pins through the interface module, and the second set of GPIO pins is connected to the fourth set of GPIO pins through the interface module; the processor is configured to obtain the power-on self-test code of the motherboard from the PCH chip through the second set of GPIO pins, and send the fault module information of the fault module to the CPLD chip through the first set of GPIO pins.

[0009] In some embodiments, the processor further includes a first group of PG pins, a first group of EN pins, and debug pins. The CPLD chip further includes a second group of PG pins and a second group of EN pins. The first group of PG pins is connected to the second group of PG pins through the interface module, and the first group of EN pins is connected to the second group of EN pins through the interface module. The processor is further configured to, after being electrically connected to the motherboard through the interface module and powered on for the first time, set the debug pins to 1, and obtain the PG signal level status of each standby power supply of the motherboard from the CPLD chip through the first group of PG pins. The processor determines the standby power supply with an abnormal PG signal level status as an abnormal standby power supply, and sends an EN signal to the abnormal standby power supply through the first group of EN pins to forcibly enable the abnormal standby power supply. When the PG signal level status of the abnormal standby power supply changes from abnormal to normal, the processor determines the abnormal standby power supply as a faulty unit.

[0010] In some embodiments, the CPLD chip further includes a fifth group of GPIO pins, and the fifth group of GPIO pins is used to control the power shielding of the peripheral module connected to the target server. The processor is further configured to, when the PG signal level status of each standby power supply of the motherboard is normal, control the CPLD chip through the first group of PG pins, so that the CPLD chip shields the EN signal of the peripheral module through the fifth group of GPIO pins, and enables the target server to perform a minimum system startup operation. When the target server successfully performs the minimum system startup operation, the processor determines that the peripheral module includes the faulty module.

[0011] In some embodiments, the processor is further configured to, when the target server successfully performs the minimum system startup operation, control the CPLD chip through the first group of PG pins, so that the CPLD chip restores the EN signal of the peripheral module through the fifth group of GPIO pins, and enables the target server to restart normally. The processor is further configured to, after the target server restarts normally, obtain the power-on self-test code of the motherboard from the PCH chip through the second group of GPIO pins; match the power-on self-test code with the fault code library stored in the memory to determine the fault code corresponding to the power-on self-test code; and determine the faulty module corresponding to the fault code in the target server, and send the faulty module information to the CPLD chip through the first group of GPIO pins.

[0012] In some embodiments, the processor is further configured to set the debug pin to 0 after sending the fault module information to the CPLD chip; the CPLD chip is configured to control the PCH chip to call and start the BIOS debug firmware, so that the PCH chip enters the debug mode; the PCH chip is configured to send the enumeration information of the fault module to the processor through the fourth set of GPIO pins; the processor is further configured to parse the enumeration information, determine the status code corresponding to each unit included in the fault module; match each status code with the status code library stored in the memory respectively; determine the fault status code that cannot be matched with any correct status code in the status code library, and determine the fault unit corresponding to the fault status code, and send the unit information of the fault unit to the CPLD chip through the first set of GPIO pins.

[0013] In some embodiments, the fifth set of GPIO pins is further configured to control the power shielding of the fault module and the associated module in the target server that has a communication association with the fault module; the processor is further configured to control the CPLD chip through the first set of PG pins after sending the fault module information to the CPLD chip, so that the CPLD chip shields the EN signal of the fault module through the fifth set of GPIO pins and restarts the target server; when the target server restarts normally, the processor records the fault module information; when the target server cannot restart normally, the processor sends each associated module to the CPLD chip through the first set of GPIO pins; the CPLD chip shields the EN signal of each associated module in sequence through the fifth set of GPIO pins and restarts the target server until the target server restarts normally; the processor records the fault module information.

[0014] In some embodiments, the CPLD chip is further configured to send the unit information of the fault unit to the controller, and the controller is configured to generate an alarm log based on the unit information of the fault unit.

[0015] Second aspect, an embodiment of the present application provides a server fault location method, which is applied to the server fault location system described in any one of the above first aspects. The method includes: the debug card obtains the power-on self-test code of the motherboard and matches the power-on self-test code with a preset fault code library stored in the debug card; determines the fault code corresponding to the power-on self-test code and determines the fault module in the target server corresponding to the fault code; the motherboard calls and starts the BIOS debug firmware stored in the debug card to enter the debug mode and obtains the enumeration information of the fault module; the debug card parses the enumeration information to determine the status codes corresponding to each unit included in the fault module; matches each of the status codes with a preset status code library stored in the debug card; determines the fault status codes that cannot be matched with any correct status codes in the status code library and determines the fault units corresponding to the fault status codes.

[0016] Compared with the related art, in the server fault location system and method provided by the embodiment of the present application, when a fault occurs in the target server, by connecting the debug card to the motherboard of the target server, obtaining the power-on self-test code of the motherboard, and matching the power-on self-test code with the fault code library pre-stored in the debug card, the fault code corresponding to the power-on self-test code and the fault module corresponding to the fault code are determined; the motherboard can call and start the BIOS debug firmware pre-stored in the debug card to enter the debug mode and obtain the enumeration information of the fault module; the debug card can parse the enumeration information to determine the status codes of multiple units included in the fault module and match the status codes with the status code library pre-stored in the debug card to determine the fault status codes and the fault units corresponding to the fault status codes, thereby realizing the accurate location of server faults and improving the operation and maintenance efficiency of the server. Through the present application, the problem of low efficiency in fault location of servers in the related art is solved, and the technical effect of improving the efficiency of fault location of servers is achieved.

[0017] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more comprehensible. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1It is a schematic structural diagram of a server fault location system according to an embodiment of the present application;

[0020] Figure 2 It is a schematic structural diagram of a debugging card according to an embodiment of the present application;

[0021] Figure 3 It is a flowchart of a server fault location method according to an embodiment of the present application.

[0022] Among them, each reference numeral in the figure is as follows:

[0023] 10 - Server fault location system; 100 - Debugging card; 101 - Processor; 102 - Memory; 103 - Debugging Flash memory; 110 - Motherboard; 111 - Controller; 112 - PCH chip; 113 - CPLD chip; 114 - Flash memory. Detailed implementation manners

[0024] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are put forward in order to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0025] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0026] It should also be understood that the term "and / or" used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0027] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]" according to the context.

[0028] In addition, in the description of the specification and the appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0029] The reference to "one embodiment" or "some embodiments" etc. described in the specification of the present application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprise", "include", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0030] As the core facility for data storage, processing, and transmission, the stability and reliability of the server are crucial. With the continuous development of the server industry and related technologies, its functions have been continuously enriched, the design has become more and more complex, and the integration degree has become higher and higher, which increases the design difficulty and also increases the possibility of server failures. These failures may be caused by various factors such as hardware, software, or network.

[0031] When the server issues an alarm message due to a change in the register state inside its CPU, since this alarm message is usually rather general and it is impossible to directly determine which peripheral or component causes the failure, this poses a great challenge to the fault location work of the operation and maintenance personnel. Traditional fault location methods usually include steps such as manually disassembling the machine, performing minimum system verification, and powering on peripherals one by one. Such fault location methods often take a long time and are inefficient. Especially when it comes to key components such as power supply, CPU, and memory, inaccurate fault location may lead to an increase in repair efficiency and affect business continuity.

[0032] There are some server fault troubleshooting tools in the related art. These tools usually provide some basic fault troubleshooting functions, for example, log analysis, performance monitoring, etc. However, these tools can only narrow down the fault range, and still require the operation and maintenance personnel to manually disassemble the machine and use the replacement method to locate the specific fault location and eliminate the fault.

[0033] Currently, no effective solution has been proposed for the problem of low fault location efficiency of servers in the related art.

[0034] In view of this, when a target server fails, the server fault location system provided by the embodiments of the present application connects a debug card to the motherboard of the target server, obtains the power-on self-test code of the motherboard, and matches the power-on self-test code with a fault code library pre-stored in the debug card, so as to determine the fault code corresponding to the power-on self-test code and the fault module corresponding to the fault code; the motherboard can call and start the BIOS debug firmware pre-stored in the debug card to enter the debug mode and obtain the enumeration information of the fault module; the debug card can parse the enumeration information, determine the status codes of multiple units included in the fault module, and match the status codes with a status code library pre-stored in the debug card to determine the fault status code and the fault unit corresponding to the fault status code, thereby realizing the accurate location of the server fault, eliminating the need for maintenance personnel to manually disassemble the machine to judge the fault location, improving the server operation and maintenance efficiency, and reducing the server maintenance cost. Through the present application, the problem of low efficiency in fault location of servers in the related art is solved, and the technical effect of improving the efficiency of server fault location is achieved.

[0035] Before further elaborating on the embodiments of the present application, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0036] 1) BMC, full name Baseboard Management Controller, as the management and control core of the server, is responsible for various monitoring, control, and configuration functions of the server.

[0037] 2) CPLD, full name Complex Programmable Logic Device, is a digital logic circuit that allows users to define its logic functions through programming.

[0038] 3) PCH, full name Platform Controller Hub, as the core chip on the motherboard, is mainly responsible for managing input / output functions, peripheral connections, and communication with the CPU.

[0039] 4) MCU, full name Microcontroller Unit, that is, a microcontroller unit. The MCU is equivalent to a miniature computer, which integrates various functional modules internally, such as a CPU, a memory, an input / output interface, etc. It can achieve various complex control functions by writing programs.

[0040] 5) Debug Flash (also known as debug flash memory), which is used to store the BIOS debug firmware. When it is necessary to locate specific faults, the PCH switches to this BIOS debug firmware to provide the underlying hardware environment to the debug card for system fault troubleshooting and hardware diagnosis.

[0041] The following will combine Figure 1 to illustrate the server fault location system provided by an embodiment of the present application. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the server fault location system according to an embodiment of the present application. As Figure 1 shown, the server fault location system includes: a debug card and a motherboard. Among them, the motherboard is disposed in the target server, and the debug card is electrically connected to the motherboard; the debug card is used to obtain the power-on self-test code of the motherboard and match the power-on self-test code with a preset fault code library stored in the debug card; determine the fault code corresponding to the power-on self-test code and determine the fault module in the target server corresponding to the fault code; the motherboard is used to call and start the BIOS debug firmware stored in the debug card, enter the debug mode, and obtain the enumeration information of the fault module; the debug card is also used to parse the enumeration information, determine the status codes corresponding to each unit included in the fault module; match each status code with a preset status code library stored in the debug card respectively; determine the fault status codes that cannot be matched with the correct status codes in the status code library, and determine the fault units corresponding to the fault status codes.

[0042] In this embodiment, when the target server has a fault (for example, problems such as the motherboard cannot be powered on, the host gets stuck during the startup phase and cannot start normally, etc.), the operation and maintenance personnel can externally connect the debug card provided by the embodiment of the present application so that the debug card is electrically connected to the motherboard through a connector.

[0043] After the debug card is connected to the motherboard, it can automatically run the program stored in the debug card, determine the fault module by obtaining the power-on self-test code (postcode) of the motherboard, and send the fault module information of the fault module to the CPLD chip in the motherboard so that the CPLD chip performs a power shielding operation on the fault module; after the power of the fault module is shielded, if the target server restarts normally, it can be determined that the fault module causes the target server to have a fault.

[0044] After determining that the faulty module has caused a fault in the target server, the motherboard can call and start the BIOS debugging firmware stored in the debug card, so that the PCH chip in the motherboard switches to start with the BIOS debugging firmware. After entering the debug mode, the PCH chip can obtain the debugging information of the faulty module, extract the enumeration information about multiple units included in the faulty module from the debugging information, and send the enumeration information to the debug card.

[0045] The debug card can parse the enumeration information, determine the status code corresponding to each unit included in the faulty module, and match each status code with a preset status code library, so as to determine the faulty unit, and send the unit information of the faulty unit to the CPLD chip, so that the CPLD chip performs a power shielding operation on the faulty unit; after the power of the faulty unit is shielded, if the target server restarts normally, it can be determined that the faulty unit has caused a fault in the target server.

[0046] In this way, by connecting an external debug card, it is possible to accurately and quickly locate and debug the faulty unit of the target server without the need for maintenance personnel to manually disassemble and troubleshoot the target server, thereby improving the operation and maintenance efficiency of the target server; by storing the BIOS debugging firmware on the debug card, it is possible to provide a low-level hardware environment for the debug card, so that the debug card can specifically analyze the debugging information (i.e., enumeration information) of the faulty module for troubleshooting and accurately and quickly locate the faulty unit. In addition, the independent design of the debug card can avoid occupying the already crowded space of the motherboard and will not occupy the interface resources of the corresponding hardware devices when the target server is fault-free.

[0047] As Figure 1 shown, in one embodiment, the debug card includes a processor, a memory, an interface module ( Figure 1 not shown in the figure), and a communication module (e.g., Figure 1 the I2C module in the figure), and the motherboard includes a controller (BMC), a PCH chip, and a CPLD chip; the debug card establishes communication with the controller, the PCH chip, and the CPLD chip through the communication module, the debug card is electrically connected to the motherboard through the interface module, and the memory stores a fault code library and a status code library, where the fault code library includes multiple fault codes and the fault module information corresponding to each fault code (e.g., module category, module ID, etc.), and the status code library includes multiple correct status codes and the unit information corresponding to each correct status code.

[0048] In this embodiment, the debug card can be designed as a compact circuit board. The processor included therein can be a microprocessor such as an MCU. The memory in the debug card can be a non-volatile memory (e.g., Electrically Erasable Programmable read only memory (EEPROM)). The interface module in the debug card can be the interface circuit necessary for establishing an electrical connection with the motherboard. The communication module in the debug card can be a communication module such as an I2C (Inter-Integrated Circuit) module, an SPI (Serial Peripheral Interface) module, or a UART (Universal Asynchronous Receiver / Transmitter) module that can be used to establish a communication connection with the motherboard. As Figure 1 shown, the processor can communicate with the memory through the I2C module (I2C data link) to obtain the fault code library or status code library stored in the memory.

[0049] The debug card can communicate with the controller, PCH chip, and CPLD chip in the motherboard through circuits (e.g., the above interface circuit and communication module) to complete the fault location of the target server. The debug card can establish an electrical connection with the motherboard through the reserved interface on the target server. The reserved interface includes but is not limited to at least one of the following: PCIe (peripheral component interconnect express) slot, dedicated debug interface, or expansion slot, etc.

[0050] As Figure 1 shown, in one embodiment, the processor includes a first group of PG pins, a first group of EN pins, and debug pins. The CPLD chip includes a second group of PG pins and a second group of EN pins. Among them, the first group of PG pins is connected to the second group of PG pins through the interface module, and the first group of EN pins is connected to the second group of EN pins through the interface module. The processor is further configured to, after being electrically connected to the motherboard through the interface module and powered on for the first time, set the debug pins to 1, and obtain the PG signal level status of each standby power supply of the motherboard from the CPLD chip through the first group of PG pins; the processor determines the standby power supply with an abnormal PG signal level status as the abnormal standby power supply, and sends an EN signal to the abnormal standby power supply through the first group of EN pins to forcibly enable the abnormal standby power supply; in the case where the PG signal level status of the abnormal standby power supply changes from abnormal to normal, the processor determines the abnormal standby power supply as the faulty unit.

[0051] In this embodiment, the debug card further includes a plurality of LEDs (light-emitting diodes). Each LED is electrically connected to one of the PG pins in the first group of PG pins. The LED can be turned on or off according to the PG signal level status of the standby power supply of the main board obtained by the PG pin. For example, if the PG signal level status of the standby power supply of the main board corresponding to a certain PG pin is abnormal, the PG pin is set to 0, and the LED corresponding to the PG pin is turned off; if the PG signal level status of the standby power supply of the main board corresponding to a certain PG pin is normal, the PG pin is set to 1, and the LED corresponding to the PG pin is turned on. In this way, the operation and maintenance personnel can determine the abnormal / normal condition of the standby power supply by observing the on / off status of each LED on the debug card, so as to accurately and quickly perform fault troubleshooting operations on the abnormal standby power supply and improve the fault location efficiency of the target server.

[0052] As Figure 1 shown, in one embodiment, the processor includes a first group of GPIO pins and a second group of GPIO pins, the CPLD chip includes a third group of GPIO pins, and the PCH chip includes a fourth group of GPIO pins. Among them, the first group of GPIO pins is connected to the third group of GPIO pins through an interface module, and the second group of GPIO pins is connected to the fourth group of GPIO pins through an interface module; the processor is configured to obtain the power-on self-test code of the main board from the PCH chip through the second group of GPIO pins, and send the fault module information of the fault module to the CPLD chip through the first group of GPIO pins.

[0053] Next, a debug card provided by an embodiment of the present application will be described in conjunction with Figure 2 Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a debug card according to an embodiment of the present application. As Figure 2 shown, the processor can use 4 GPIO pins as the first group of GPIO pins and connect them to the third group of GPIO pins of the CPLD chip for transmitting data information between the processor and the CPLD chip. As Figure 2 shown, 4 GPIO pins can be selected from GPIO_0, GPIO_1, ……, GPIO_10 of the processor as the first group of GPIO pins. As an example, GPIO_0, GPIO_1, GPIO_2, and GPIO_3 of the processor can be used as the first group of GPIO pins to form a GPIO[3:0] combined pin.

[0054] In addition, the processor may use six GPIO pins as the second set of GPIO pins, which are connected to the fourth set of GPIO pins of the PCH chip for transmitting data information between the processor and the PCH chip. As Figure 2 shown, as Figure 2 shown, six GPIO pins can be selected from GPIO_0, GPIO_1, ……, GPIO_10 of the processor as the second set of GPIO pins. As an example, GPIO_5, GPIO_6, GPIO_7, GPIO_8, GPIO_9, and GPIO_10 of the processor can be used as the second set of GPIO pins to form the GPIO[10:5] combined pins.

[0055] As Figure 1 shown, in one embodiment, the CPLD chip further includes a fifth set of GPIO pins, which are used to control the power shielding of the peripheral modules connected to the target server; the processor is further configured to control the CPLD chip through the first set of PG pins when the PG signal level status of each standby power supply on the motherboard is normal, so that the CPLD chip shields the EN signal of the peripheral modules through the fifth set of GPIO pins, and causes the target server to perform the minimum system startup operation; when the minimum system startup operation of the target server is successful, the processor determines that the peripheral modules include faulty modules.

[0056] As Figure 1 shown, the fifth set of GPIO pins can be connected to the PCIE*_EN pin, the DIMM*_EN pin, and the PCH_IO*_EN pin to control the power shielding of each module (for example, the module connected to the target server through the PCIe slot, the Dual-Inline-Memory-Modules (DIMM), the module connected to the target server through the IO interface of the PCH chip, etc.).

[0057] In this embodiment, if all the LEDs in the debug card are in the on state, it can be determined that the PG signal level status of each standby power supply on the motherboard is normal; if the CPLD chip on the motherboard recognizes the connection of the debug card, it can shield the EN signals of all peripheral modules of the target server through the fifth set of GPIO pins, so that the target server performs the minimum system startup operation. If the minimum system startup operation of the target server is successful, the processor can determine that the peripheral modules include faulty modules that cause the target server to malfunction. Since the peripheral modules can include multiple types of modules, subsequent location operations need to be performed on the specific faulty modules in the peripheral modules.

[0058] In one embodiment, the processor is further configured to, when the target server successfully performs the minimum system power-on operation, control the CPLD chip through the first set of PG pins, so that the CPLD chip restores the EN signal of the peripheral module through the fifth set of GPIO pins, and cause the target server to restart normally; the processor is further configured to, after the target server restarts normally, obtain the power-on self-test code of the motherboard from the PCH chip through the second set of GPIO pins; match the power-on self-test code with the fault code library stored in the memory to determine the fault code corresponding to the power-on self-test code; and determine the fault module in the target server corresponding to the fault code, and send the fault module information to the CPLD chip through the first set of GPIO pins.

[0059] In this embodiment, the processor can obtain the postcode of the motherboard from the PCH chip through the GPIO[10:5] combined pins (i.e., the second set of GPIO pins); after the processor obtains the postcode, it can start a parsing program to match the postcode with the fault code library pre-stored in the memory (for example, EEPROM), where the fault code library includes multiple fault codes (postcode IDs), the fault types corresponding to each fault code, and the fault module information corresponding to each fault code, etc. For example, if the last digit of the postcode obtained by the processor is 0x53, the parsing program of the processor can query the postcode ID corresponding to 0x53 in the fault code library, the fault type corresponding to this postcode ID is MEMINIT ERROR, and the fault module corresponding to this postcode ID is MEM (memory). Therefore, the processor can quickly point to the faulty module as the memory.

[0060] Subsequently, the processor can send the parsed data (fault module information) to the CPLD chip through the GPIO[3:0] combined pins (i.e., the first set of GPIO pins).

[0061] In one embodiment, after the CPLD chip restores the EN signal of the peripheral module through the fifth set of GPIO pins and causes the target server to restart normally, if the target server cannot power on normally, the processor confirms whether it can obtain the postcode. If it can obtain the postcode, it locates the faulty module according to the above steps; if the processor cannot obtain the postcode, then at this time, the operation and maintenance personnel need to disassemble the target server for inspection to check whether the CPU, memory and other key modules are installed correctly.

[0062] In this embodiment, the processor is further configured to set the debug pin to 0 after sending the fault module information to the CPLD chip; at this time, the LED on the debug card can start to flash, indicating that the debug mode has been enabled.

[0063] In one embodiment, the fifth group of GPIO pins is further used to control the power shielding of the faulty module and the associated module in the target server that has a communication association with the faulty module; the processor is further configured to control the CPLD chip through the first group of PG pins after sending the faulty module information to the CPLD chip, so that the CPLD chip shields the EN signal of the faulty module through the fifth group of GPIO pins and restarts the target server; when the target server restarts normally, the processor records the faulty module information; when the target server fails to restart normally, the processor sends each associated module to the CPLD chip through the first group of GPIO pins; the CPLD chip sequentially shields the EN signals of the associated modules through the fifth group of GPIO pins and restarts the target server until the target server restarts normally; the processor records the faulty module information.

[0064] In this embodiment, by parsing the postcode and controlling the power shielding of the faulty module, the troubleshooting of the faulty module in the target server can be realized, and the fault range caused by the faulty module can be confirmed. In addition, the fault location method of power shielding the faulty module or the associated module by controlling the EN signal of the faulty module or the associated module that has a communication association with the faulty module can reduce the risk of damage to the equipment caused by the maintenance personnel manually disassembling and assembling the target server in the conventional fault location method, and reduce the maintenance cost.

[0065] In one embodiment, the CPLD chip is used to control the PCH chip to call and start the BIOS debug firmware, so that the PCH chip enters the debug mode; the PCH chip is used to send the enumeration information of the faulty module to the processor through the fourth group of GPIO pins; the processor is further configured to parse the enumeration information, determine the status codes corresponding to the respective units included in the faulty module; match each status code with the status code library stored in the memory respectively; determine the faulty status code that cannot be matched with any correct status code in the status code library, and determine the faulty unit corresponding to the faulty status code, and send the unit information of the faulty unit to the CPLD chip through the first group of GPIO pins.

[0066] As Figure 1As shown, in this embodiment, the PCH chip can form an SPI communication circuit with the Flash memory in the motherboard and the debug Flash memory in the debug card to guide the BIOS firmware program to start the target server. The CS signal of the MUX selector can perform a one-for-one selection operation on the BIOS firmware stored in the Flash memory and the debug BIOS firmware stored in the debug Flash memory. For example, the CPLD chip can switch the CS signal of the MUX selector through the GPIO pins, switching the firmware required to start the target server from the BIOS firmware stored in the Flash memory to the debug BIOS firmware stored in the debug Flash memory, and vice versa.

[0067] In this embodiment, the enumeration information includes the unit information of multiple units included in the faulty module and the status code corresponding to each unit. The status code library stores the information of all units of each functional module of the target server, including the unit information corresponding to each unit (for example, the unit information can be unit category, unit ID, etc.) and the correct status code. By comparing the status code corresponding to each unit included in the faulty module with the correct status code in the status code library, the processor can determine the faulty status code that cannot match any of the correct status codes in the status code library, and locate the faulty unit by obtaining the unit information corresponding to the faulty status code.

[0068] In addition, due to reasons such as incorrect installation or line failure of the faulty unit, its related information may not be covered by the enumeration information. Therefore, the processor can compare the unit information (for example, unit ID) of all units in the enumeration information with the unit information (for example, unit ID) in the status code library to determine the unenumerated faulty units. Then, the processor can send the unit information of the unenumerated faulty units or the unit information corresponding to the faulty status code to the CPLD chip through the first group of GPIO pins.

[0069] In one embodiment, the fifth group of GPIO pins is also used to control the power shielding of the faulty unit; the processor is also used to control the CPLD chip through the first group of PG pins after sending the unit information of the faulty unit to the CPLD chip, so that the CPLD chip shields the EN signal of the faulty unit through the fifth group of GPIO pins and restarts the target server; when the target server restarts normally, the processor records the faulty unit.

[0070] In this embodiment, after the processor records the unit information of the faulty unit, the debug pin can be set to 1 to exit the debug mode, and the LED of the debug card can resume constant illumination. The CPLD chip can be used to send the unit information of the faulty unit to the controller, and the controller is used to generate an alarm log based on the unit information of the faulty unit. Specifically, the CPLD chip can communicate with the controller (BMC) through the I2C module to send the unit information of the located faulty unit to the controller, and the operation and maintenance personnel can perform subsequent analysis and processing through the remote management function of the controller. The operation and maintenance personnel can confirm the faulty unit through the alarm log of the controller, replace the corresponding faulty unit, and then can confirm whether the target server is running normally after replacing the faulty unit. If the target server is running normally, the debugging work is completed and the debug card is removed. Otherwise, the debug card can be used to perform the fault location operation again.

[0071] In this way, the debug card records the unit information of the faulty unit, and the CPLD chip sends the unit information of the faulty unit to the controller through the I2C module, which is convenient for the operation and maintenance personnel to perform subsequent analysis and processing, and improves the stability and reliability of the server.

[0072] Next, a server fault location method provided by an embodiment of the present application will be described in conjunction with the accompanying drawings. The server fault location method can be applied to the server fault location system described in the above embodiment. Please refer to Figure 3 , Figure 3 is a flowchart of a server fault location method according to an embodiment of the present application. As shown in Figure 3 , the method includes steps S301 to S303:

[0073] Step S301, the debug card obtains the power-on self-test code of the main board, and matches the power-on self-test code with a preset fault code library stored in the debug card; determines the fault code corresponding to the power-on self-test code, and determines the fault module in the target server corresponding to the fault code.

[0074] Step S302, the main board calls and starts the BIOS debug firmware stored in the debug card, enters the debug mode, and obtains the enumeration information of the fault module.

[0075] Step S303, the debug card parses the enumeration information, determines the status code corresponding to each unit included in the fault module; matches each status code with a preset fault status code library stored in the debug card; determines the fault status code corresponding to the status code, and determines the faulty unit corresponding to the fault status code.

[0076] It should be noted that for the detailed content of each of the above steps, since it is based on the same concept as the system embodiment of this application, for its specific functions and the technical effects brought about, reference can be specifically made to the system embodiment section, and details will not be elaborated here.

[0077] The following will describe the above server fault location method in combination with a specific example. The server fault location method can be divided into six steps:

[0078] Step 1, when a fault occurs in the target server (including but not limited to problems such as the motherboard being unable to power on, or getting stuck during the host startup phase and unable to start normally), connect the debug card to the connector of the motherboard, load and execute the program built into the debug card. After the debug card is powered on for the first time, it is defaulted to the non-debug mode, and the debug pins are defaulted to 1. The debug card first determines whether the fault of the target server is caused by a motherboard circuit fault: the processor of the debug card obtains the PG signal level status of each standby power supply of the motherboard from the CPLD chip through the first group of PG pins. The PG signal level status corresponds one-to-one with the LEDs on the debug card, and the LEDs can be turned on or off according to the PG signal level status of the standby power supply of the motherboard obtained by the PG pins. If all the LEDs on the debug card are fully lit at this time, it means that the standby power supply is powered on normally, and proceed to Step 2. Otherwise, the standby power supply is powered on abnormally, and the LED corresponding to the abnormal standby power supply cannot be lit. At this time, the processor can send an EN signal to the abnormal standby power supply through the first group of EN pins to forcibly enable the abnormal standby power supply; in the case where the PG signal level status of the abnormal standby power supply changes from abnormal to normal, the processor determines the abnormal standby power supply as the faulty unit; if the power supply is still not normal, it is necessary to ask the operation and maintenance personnel to check the corresponding power supply line and impedance situation.

[0079] Step 2: When all the LEDs on the debug card are in the on state and the CPLD chip on the mainboard recognizes the connection of the debug card, the processor controls the CPLD chip through the first set of PG pins, so that the CPLD chip shields the EN signal of the peripheral module through the fifth set of GPIO pins, and makes the target server perform the minimum system startup action. If the target server boots up normally, it can be determined that the peripheral failure includes the faulty module. When the target server successfully performs the minimum system startup action, the processor controls the CPLD chip through the first set of PG pins, so that the CPLD chip restores the EN signal of the peripheral module through the fifth set of GPIO pins, and makes the target server restart normally; the processor is also used to obtain the power-on self-test code of the mainboard from the PCH chip through the second set of GPIO pins after the target server restarts normally; match the power-on self-test code with the fault code library stored in the memory to determine the fault code corresponding to the power-on self-test code; and determine the faulty module in the target server corresponding to the fault code, and send the faulty module information to the CPLD chip through the first set of GPIO pins. At this time, the debug pins of the debug card are set to 0, and the LEDs on the debug card start to flash, indicating that the debug mode has been enabled, and step 3 is entered. In addition, after the CPLD chip restores the EN signal of the peripheral module through the fifth set of GPIO pins and makes the target server restart normally, if the target server cannot boot up normally, the processor confirms whether it can obtain the postcode. If it can obtain the postcode, the faulty module is located according to the above steps; if the processor cannot obtain the postcode, the maintenance personnel need to disassemble and check the target server at this time to check whether the key modules such as the CPU and memory are installed correctly.

[0080] Step 3: After the processor sends the faulty module information to the CPLD chip, it controls the CPLD chip through the first set of PG pins, so that the CPLD chip shields the EN signal of the faulty module through the fifth set of GPIO pins, and makes the target server restart; when the target server restarts normally, the processor records the faulty module information; when the target server cannot restart normally, the processor sends each associated module to the CPLD chip through the first set of GPIO pins; the CPLD chip shields the EN signal of the associated module through the fifth set of GPIO pins in sequence and makes the target server restart until the target server restarts normally; the processor records the faulty module information. Step 4 is entered.

[0081] Step 4, the PCH chip can form an SPI communication circuit with the Flash memory in the motherboard and the debug Flash memory in the debug card to boot the BIOS firmware program to start the target server. The CS signal of the MUX selector can perform a one - in - two selection operation on the BIOS firmware stored in the Flash memory and the debug BIOS firmware stored in the debug Flash memory. Thus, the CPLD chip can control the PCH chip to call and start the BIOS debug firmware, so that the PCH chip enters the debug mode; the PCH chip is used to send the enumeration information of the faulty module to the processor through the fourth group of GPIO pins; the processor is also used to parse the enumeration information, determine the status codes corresponding to each unit included in the faulty module; match each status code with the status code library stored in the memory respectively; determine the faulty status code that cannot be matched with any correct status code in the status code library, and determine the faulty unit corresponding to the faulty status code. The processor can also determine the unenumerated faulty units by comparing the unit information of all units in the enumeration information with the unit information in the status code library. Then, the processor can send the unit information of the unenumerated faulty units or the unit information corresponding to the faulty status code to the CPLD chip through the first group of GPIO pins.

[0082] Step 5, after the processor sends the unit information of the faulty unit to the CPLD chip, it controls the CPLD chip through the first group of PG pins, so that the CPLD chip shields the EN signal of the faulty unit through the fifth group of GPIO pins and restarts the target server; in the case of a normal restart of the target server, the processor records the unit information of the faulty unit. Enter Step 5.

[0083] Step 6, after the processor records the unit information of the faulty unit, it can set the debug pin to 1 to exit the debug mode, and the LED of the debug card can resume normal lighting. The CPLD chip can be used to send the unit information of the faulty unit to the controller, and the controller is used to generate an alarm log based on the faulty unit. Specifically, the CPLD chip can communicate with the controller (BMC) through the I2C module to send the unit information of the located faulty unit to the controller. The operation and maintenance personnel can perform subsequent analysis and processing through the remote management function of the controller. The operation and maintenance personnel can confirm the faulty unit through the alarm log of the controller, replace the corresponding faulty unit, and then can confirm whether the target server is running normally after replacing the faulty unit. If the target server is running normally, the debugging work is completed and the debug card is removed. Otherwise, the debug card can be used to perform the fault location operation again.

[0084] Through the above steps 1 to 6, when the target server fails, by connecting the debug card to the motherboard of the target server, obtaining the power-on self-test code of the motherboard, and matching the power-on self-test code with the fault code library pre-stored in the debug card, the fault code corresponding to the power-on self-test code and the fault module corresponding to the fault code can be determined; the motherboard can call and start the BIOS debug firmware pre-stored in the debug card to enter the debug mode and obtain the enumeration information of the fault module; the debug card can parse the enumeration information, determine the status codes of multiple units included in the fault module, and match the status codes with the status code library pre-stored in the debug card to determine the fault status code and the fault unit corresponding to the fault status code, thereby achieving precise positioning of the server fault and improving the operation and maintenance efficiency of the server. Through this application, the problem of low fault location efficiency of the server in the related art is solved, and the technical effect of improving the fault location efficiency of the server is achieved.

[0085] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0086] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0088] In the embodiments provided in the present application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A server fault location system, characterized in that, Including: A debug card and a main board, wherein the main board is disposed in a target server, and the debug card is electrically connected to the main board; The debug card is configured to obtain a power-on self-test code of the main board, and match the power-on self-test code with a preset fault code library stored in the debug card; Determine a fault code corresponding to the power-on self-test code, and determine a fault module in the target server corresponding to the fault code; The main board is configured to call and start a BIOS debug firmware stored in the debug card, enter a debug mode, and obtain enumeration information of the fault module; The debug card is further configured to parse the enumeration information, determine status codes corresponding to each unit included in the fault module; match each of the status codes with a preset status code library stored in the debug card; determine a fault status code that cannot be matched with any correct status code in the status code library, and determine a fault unit corresponding to the fault status code.

2. The server fault location system according to claim 1, wherein The debug card includes a processor, a memory, an interface module, and a communication module, and the main board includes a controller, a PCH chip, and a CPLD chip; The debug card establishes communication with the controller, the PCH chip, and the CPLD chip through the communication module, and the debug card is electrically connected to the main board through the interface module. The memory stores the fault code library and the status code library, wherein the fault code library includes a plurality of fault codes and fault module information corresponding to each of the fault codes, and the status code library includes a plurality of correct status codes and unit information corresponding to each of the correct status codes.

3. The server fault location system according to claim 2, wherein The processor includes a first group of GPIO pins and a second group of GPIO pins, the CPLD chip includes a third group of GPIO pins, and the PCH chip includes a fourth group of GPIO pins. Among them, the first group of GPIO pins is connected to the third group of GPIO pins through the interface module, and the second group of GPIO pins is connected to the fourth group of GPIO pins through the interface module; The processor is configured to obtain the power-on self-test code of the main board from the PCH chip through the second group of GPIO pins, and send the fault module information of the fault module to the CPLD chip through the first group of GPIO pins.

4. The server fault location system according to claim 3, wherein The processor further includes a first group of PG pins, a first group of EN pins, and debug pins, and the CPLD chip further includes a second group of PG pins and a second group of EN pins. The first group of PG pins is connected to the second group of PG pins through the interface module, and the first group of EN pins is connected to the second group of EN pins through the interface module; The processor is further configured to set the debug pins to 1 after being electrically connected to the main board through the interface module and powered on for the first time, and obtain the PG signal level status of each standby power supply of the main board from the CPLD chip through the first group of PG pins. The processor determines that the standby power supply with an abnormal PG signal level status is an abnormal standby power supply, and sends an EN signal to the abnormal standby power supply through the first set of EN pins to forcibly enable the abnormal standby power supply; In the case where the PG signal level status of the abnormal standby power supply changes from abnormal to normal, the processor determines that the abnormal standby power supply is a faulty unit.

5. The server fault location system according to claim 4, wherein, The CPLD chip further includes a fifth set of GPIO pins, and the fifth set of GPIO pins are used to control the power shielding of the peripheral module connected to the target server; The processor is further configured to, when the PG signal level status of each standby power supply on the motherboard is normal, control the CPLD chip through the first set of PG pins, so that the CPLD chip shields the EN signal of the peripheral module through the fifth set of GPIO pins, and causes the target server to perform a minimum system power-on operation; When the target server successfully performs the minimum system power-on operation, the processor determines that the peripheral module includes the faulty module.

6. The server fault location system according to claim 5, wherein, The processor is further configured to, when the target server successfully performs the minimum system power-on operation, control the CPLD chip through the first set of PG pins, so that the CPLD chip restores the EN signal of the peripheral module through the fifth set of GPIO pins, and causes the target server to restart normally; The processor is further configured to, after the target server restarts normally, obtain the power-on self-test code of the motherboard from the PCH chip through the second set of GPIO pins; Match the power-on self-test code with the fault code library stored in the memory to determine the fault code corresponding to the power-on self-test code; and determine the faulty module corresponding to the fault code in the target server, and send the faulty module information to the CPLD chip through the first set of GPIO pins.

7. The server fault location system according to claim 6, wherein The processor is further configured to set the debug pin to 0 after sending the faulty module information to the CPLD chip; The CPLD chip is used to control the PCH chip to call and start the BIOS debug firmware, so that the PCH chip enters the debug mode; The PCH chip is used to send the enumeration information of the faulty module to the processor through the fourth set of GPIO pins; The processor is further configured to parse the enumeration information to determine the status code corresponding to each unit included in the faulty module; match each status code with the status code library stored in the memory respectively; determine the fault status code that cannot be matched with any correct status code in the status code library, and determine the faulty unit corresponding to the fault status code, and send the unit information of the faulty unit to the CPLD chip through the first set of GPIO pins.

8. The server fault location system according to claim 5 or 6, characterized in that, The fifth group of GPIO pins is also used to control the power shielding of the fault module and the associated module in the target server that has a communication association with the fault module; The processor is further configured to, after sending the fault module information to the CPLD chip, control the CPLD chip through the first group of PG pins, so that the CPLD chip shields the EN signal of the fault module through the fifth group of GPIO pins, and restart the target server; When the target server restarts normally, the processor records the fault module information; When the target server fails to restart normally, the processor sends each of the associated modules to the CPLD chip through the first group of GPIO pins; the CPLD chip sequentially shields the EN signals of the associated modules through the fifth group of GPIO pins, and restarts the target server until the target server restarts normally; the processor records the fault module information.

9. The server fault location system according to any one of claims 2 to 7, characterized in that The CPLD chip is further configured to send the unit information of the fault unit to the controller, and the controller is configured to generate an alarm log based on the unit information of the fault unit.

10. A server fault location method, characterized in that, Applied to the server fault location system according to any one of claims 1 to 9, the method includes: The debug card obtains the power-on self-test code of the motherboard, and matches the power-on self-test code with a preset fault code library stored in the debug card; determines the fault code corresponding to the power-on self-test code, and determines the fault module in the target server corresponding to the fault code; The motherboard calls and starts the BIOS debug firmware stored in the debug card, enters the debug mode, and obtains the enumeration information of the fault module; The debug card analyzes the enumeration information, determines the status codes corresponding to each unit included in the fault module; matches each of the status codes with a preset status code library stored in the debug card; determines the fault status codes that cannot be matched with any correct status codes in the status code library, and determines the fault units corresponding to the fault status codes.

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