Inverter neutral-point balance and circulation suppression cooperative control method

Abstract

The invention discloses a cooperative control method for neutral-point balance and circulation suppression of an inverter. The method comprises the following control steps: collecting three-phase current of a power grid side, and generating a three-phase bridge arm modulation signal through a grid-connected current control loop; collecting a lower half bus voltage and generating a first zero-sequence component through a neutral-point balance control loop; collecting three-phase current on the power grid side, and generating a second zero-sequence component through a circulating current suppression control loop; inputting the first zero-sequence component and the second zero-sequence component into a competition logic processing module, and generating a final zero-sequence component by using a competition mechanism based on dynamic weight distribution; and the final zero-sequence component is subjected to over-modulation processing and then superposed to a three-phase bridge arm modulation signal of a grid-connected current control loop, and then a control signal of the three-level inverter is obtained after PWM (Pulse-Width Modulation). The method has the advantages that by dynamically coordinating the midpoint balance and circulating current restraining requirements, efficient coordination of the midpoint balance and the circulating current restraining requirements can be achieved, the control complexity is reduced, and the method is suitable for low-cost industrial application scenes.

Description

Technical Field

[0001] The present application relates to the technical field of inverters, and particularly to a cooperative control method for midpoint balance and circulating current suppression of an inverter. Background Art

[0002] In a grid-connected inverter system, the three-level topology is widely used due to its advantages such as high efficiency and low harmonics. However, the problems of DC-side midpoint potential fluctuation and zero-sequence circulating current in the parallel system need to be solved urgently.

[0003] The existing technologies mainly adopt two solutions for the above problems: one is to use SVPWM (Space Vector Pulse Width Modulation): the midpoint balance is achieved by adjusting the action time of redundant small vectors, but complex vector partitioning and real-time calculation are required, resulting in high control complexity. The other is to use SPWM (Sinusoidal Pulse Width Modulation) plus zero-sequence injection: the midpoint potential is indirectly regulated by injecting zero-sequence voltage, or the circulating current is indirectly suppressed by injecting zero-sequence circulating current; however, this method only targets a single objective (such as midpoint balance or circulating current suppression), and does not solve the contradiction when the two are coupled. Summary of the Invention

[0004] One object of the present application is to provide a cooperative control method for midpoint balance and circulating current suppression of an inverter that can solve at least one defect in the above background art.

[0005] To achieve at least one of the above objects, the technical solution adopted in the present application is: a cooperative control method for midpoint balance and circulating current suppression of an inverter, which is applied to a scenario where multiple three-level inverters are connected in parallel, and the following control steps are performed on each three-level inverter: collect the three-phase grid-side current to generate three-phase bridge-arm modulation signals through the grid-connected current control loop; collect the lower half-bus voltage to generate a first zero-sequence component through the midpoint balance control loop; collect the three-phase grid-side current to generate a second zero-sequence component through the circulating current suppression control loop; input the first zero-sequence component and the second zero-sequence component into the competition logic processing module, and generate a final zero-sequence component by using a competition mechanism based on dynamic weight distribution; perform overmodulation processing on the final zero-sequence component and then superimpose it on the three-phase bridge-arm modulation signals of the grid-connected current control loop, and then obtain the control signals of the three-level inverter after PWM modulation.

[0006] Preferably, the midpoint balance control loop includes a comparator and a controller; the generation process of the first zero-sequence component is: multiply the lower half-bus voltage by two and compare it with the bus voltage in the comparator to obtain the midpoint voltage fluctuation; input the midpoint voltage fluctuation into the controller to output the first zero-sequence component.

[0007] Preferably, the circulating current suppression control loop includes a comparator and a controller; the generation process of the second zero-sequence component is as follows: after summing the three-phase grid-side currents and dividing by three, the zero-sequence circulating current is obtained; the zero-sequence circulating current is input into the comparator and compared with zero; the comparison result is input into the controller to output the second zero-sequence component.

[0008] Preferably, the competition modes of the competition logic processing module include an emergency mode, a forced mode, and a normal competition mode; the competition logic processing module is adapted to select a competition mode according to the relationships between the midpoint voltage fluctuation and the zero-sequence circulating current and their corresponding set thresholds, and then determine the distribution weights of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component; the final zero-sequence component d z The calculation formula of is: d z =αd z_1 +βd z_2 ; where, d z_1 and d z_2 represent the first zero-sequence component and the second zero-sequence component respectively, and α and β represent the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively.

[0009] Preferably, the calculation formula of the threshold V th corresponding to the midpoint voltage fluctuation is: V th =k1(V max -V bus / 2); where, k1 represents the voltage safety factor, V max represents the maximum withstand voltage of the bus capacitor, and V bus represents the bus voltage.

[0010] Preferably, the calculation formula of the threshold I th corresponding to the zero-sequence circulating current is: ; where, k2 represents the current safety factor, I max represents the maximum allowable current of the line, i line represents the maximum value of the three-phase grid-side currents, and i z represents the zero-sequence circulating current.

[0011] Preferably, when the relationships between the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z and their corresponding set thresholds V th and I th are: |ΔV| < V th and |i z | < I th , the competition logic processing module is in the normal competition mode; at this time, the calculation formulas of the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component respectively are as follows: α=(|ΔV| / V th ) / [(|ΔV| / Vth )+(|i z | / I th )]; β = (|i z | / I th ) / [(|ΔV| / V th )+(|i z | / I th )].

[0012] Preferably, the forced modes of the competition logic processing module include a voltage forced mode and a circulating current forced mode; when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV| ≥ V th and |i z | < I th , the competition logic processing module is in the voltage forced mode; at this time, the relationship between the weights α and β is: α ≥ 2β, α + β = 1; when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV| < V th and |i z | ≥ I th , the competition logic processing module is in the circulating current forced mode; at this time, the relationship between the weights α and β is: β ≥ 2α, α + β = 1.

[0013] Preferably, when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV| ≥ V th and |i z | ≥ I th , the competition logic processing module is in the emergency mode; at this time, the following hierarchical control strategy is adopted: First priority, by setting α ≥ 2β to reduce the midpoint voltage fluctuation; Second priority, by inserting a circulating current suppression pulse compensation amount Δd z into the final zero-sequence component d z within a single switching period, and then the compensated final zero-sequence component d z ´ = d z + Δd z ; The calculation formula for the circulating current suppression pulse compensation amount Δd z is as follows: ; where K p represents the compensation coefficient, L represents the inductance value, and T sw represents the switching period.

[0014] Preferably, the overmodulation process for the final zero-sequence component includes the following steps: According to the current modulation wave d x * Determine the limit values of the final zero-sequence component d z , including the upper limit value d zmax and the lower limit value d zmin ; The calculation formulas for the upper limit value d zmax and the lower limit value d zmin are as follows: d zmax = 1 - max{d a * , d b * , d c *}, d zmin = -1 - min{d a * , d b * , d c *}; When the final zero-sequence component approaches the upper limit value, correct the weights α and β. The calculation formulas for the corrected weights α' and β' are: α' = α × (d zmax - d z ) / d zmax , β' = β × (d zmax - d z ) / d zmax ; When the final zero-sequence component approaches the lower limit value, correct the weights α and β. The calculation formulas for the corrected weights α" and β" are: α" = α × (d z - d zmin ) / d zmin , β" = β × (d z - d zmin ) / d zmin ; Among them, d a * , d b * and d c * represent the three-phase modulation waves.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: This application can achieve the efficient coordination of the two and reduce the control complexity by dynamically coordinating the midpoint balance and the circulating current suppression requirements, and adopting a simple controller and SPWM modulation, which is suitable for low-cost industrial application scenarios. Brief Description of the Drawings

[0016] Figure 1 It is a schematic diagram of the modular parallel structure of two three-level inverters.

[0017] Figure 2 It is a schematic diagram of the overlap between the carrier wave and the modulation wave of a three-level inverter.

[0018] Figure 3 It is a schematic diagram of the equivalent circuit of the parallel zero-sequence circulating current of a three-level inverter.

[0019] Figure 4 It is a schematic diagram of the working process of this application.

[0020] Figure 5 It is a schematic diagram of the specific control loop architecture of this application.

[0021] Figure 6 It is a schematic diagram of the logic for switching different competition modes of this application. Specific embodiments

[0022] Next, in combination with specific embodiments, the present application will be further described. It should be noted that in the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0023] In the description of the present application, it should be noted that for orientation terms, if there are terms such as "center", "horizontal", "vertical", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation and position relationship is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of the present application.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence.

[0025] In this application, unless otherwise clearly defined or limited, terms such as "installed", "connected", "linked", "fixed", etc. shall be understood in a broad sense. For example, it can be a connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] In this application, unless otherwise clearly defined or limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0027] The terms "comprising" and "having" in the description and claims of this application, as well as any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] For the convenience of understanding the technical solution of this application, the mechanism of the conflict between the neutral point balance control and the zero-sequence circulating current suppression of the inverter will be analyzed below.

[0029] As Figure 1 shown, it is a schematic diagram of the modular parallel architecture of two three-level inverters; the two three-level inverters adopt a common AC-DC bus, and this can be extended to the parallel architecture of three or more three-level inverters. The two three-level inverters are respectively marked as three-level inverter #1 and three-level inverter #2. Hereinafter, three-level inverter #1 will be taken as an example to illustrate the cause of the neutral point voltage fluctuation and the regulation effect of the zero-sequence voltage on the neutral point balance.

[0030] For three-level inverter #1, due to the unbalanced charging and discharging of the current i np flowing through the DC-side neutral point O, it will cause the neutral point voltage to fluctuate; the current i np is equal to the currents i p and i n corresponding to two bus capacitors with capacitance values of C cp and C respectivelycn The sum, that is, i np = i cp + i cn .

[0031] The current i cp and i cn The calculation formulas are respectively: i cp = C p × dV p / dt, icn = - C n × dV n / dt.

[0032] Where, V p and V n respectively represent the voltage values corresponding to two bus capacitors with capacitances of C p and C n .

[0033] Assume C p = C n = C, then there is i np = i cp + i cn = C × d(V p - V n ) / dt = C × dΔV / dt; From this, the influence relationship of the midpoint voltage fluctuation ΔV by the midpoint current i np can be obtained as: dΔV / dt = i np / C.

[0034] The switching states of the three-phase bridge arms of the three-level inverter are represented by S x . Only when any one of the bridge arms S x (t) = 0, that is, the bridge arm is connected to the bus midpoint, will the current flow through the midpoint. Therefore, the midpoint current i np can also be expressed by the following formula: .

[0035] Where, a, b, and c respectively represent the three-phase bridge arms, and i x represents the current corresponding to the bridge arm; S x = 1 indicates that the bridge arm is connected to the positive bus and can be represented by the P state; S x = 0 indicates that the bridge arm is connected to the midpoint and can be represented by the O state; S x = - 1 indicates that the bridge arm is connected to the negative bus and can be represented by the N state.

[0036] Due to the zero-sequence circulating current of the three-phase system , then the formula for the midpoint current i np can be simplified to: 。

[0037] When performing SPWM modulation, the three-phase duty cycle d x is the average equivalent of the switching state S x ; therefore, the expression of the neutral point current i np can be equivalently expressed as follows: 。

[0038] In SPWM modulation, a zero-sequence voltage u z is often injected into the three-phase modulation wave. By changing the modulation wave, the duty cycle of the switching state of each phase bridge arm is changed. The expression of the adjusted modulation wave u x is: u x =u x * +u z ; where, u x * represents the original three-phase modulation wave.

[0039] The injection of the zero-sequence voltage u z will change the duty cycle d x of each phase bridge arm. Then, the duty cycle d x can be expressed by the following formula: d x = u x / V bus =(u x * +u z ) / V bus ; where, V bus represents the bus voltage.

[0040] Substituting the expression of the duty cycle d x into the formula of the neutral point current i np can obtain: 。

[0041] Substituting the above formula into the formula of the neutral point voltage fluctuation ΔV, we can obtain: 。

[0042] Assuming that the circulating current remains unchanged, the influence of the zero-sequence component on the neutral point potential will be described in detail below from the process of generating the modulation signal by SPWM modulation.

[0043] As Figure 2 shown, for a three-level inverter, carrier stacking and modulation wave overlapping are often used to generate the modulation signal. u a , u b , u cIt is a three-phase modulation wave. When the modulation wave is above Carrier 1, it is in the P state; when it is below Carrier 1, it is in the O state; when it is above Carrier 2, it is in the O state; when it is below Carrier 2, it is in the N state. Among them, in the POO state, the current flows towards the midpoint of the bus; in the ONN state, the current flows out from the midpoint of the bus. When no control is applied, the action time of the POO state is the same as that of the ONN state within one switching period, so the influence on the midpoint potential cancels out each other.

[0044] Now, by superimposing a zero-sequence component on the modulation wave, the action time of the POO and ONN states can be adjusted, thereby changing the midpoint potential voltage. Specifically: when a positive zero-sequence component is superimposed, the modulation wave moves upward, the action time of the POO state increases, the action time of the ONN state decreases, the current flowing into the midpoint of the bus increases, and the midpoint potential rises. When a negative zero-sequence component is superimposed, the modulation wave moves downward, the action time of the POO state decreases, the action time of the ONN state increases, the current flowing out from the midpoint of the bus increases, and the midpoint potential decreases.

[0045] Next, the cause of the zero-sequence circulating current will be explained; as Figure 1 shown, in a parallel inverter system, the zero-sequence circulating current is mainly caused by the zero-sequence voltage difference of each module. The zero-sequence circulating currents of the three-level inverter #1 and the three-level inverter #2 are respectively i z1 =(i a1 +i b1 +i c1 ) / 3, i z2 =(i a2 +i b2 +i c2 ) / 3. Because for the two parallel-connected ones, there is i z1 =-i z2 , and their zero-sequence voltages are u z1 and u z2 respectively, then the zero-sequence voltage difference Δu z =u z1 - u z2 .

[0046] As Figure 3 shown, it is a schematic diagram of the equivalent circuit of the zero-sequence circulating current; according to Kirchhoff's voltage law, the relationship between the zero-sequence voltage difference and the zero-sequence circulating current can be obtained as: Δu z =2L×di z / dt+2R×i z ; where L and R are the inductance value and resistance value in the equivalent circuit respectively.

[0047] Next, the conflict between midpoint balance and zero-sequence circulating current suppression will be analyzed.

[0048] As Figure 1As shown, in the modular parallel architecture of a three-level inverter, assuming that the three-phase original modulation waves of three-level inverter #1 and three-level inverter #2 are the same, but the load currents are different, then there are: Three-level inverter #1: u x1 * = Usin(ωt - θ x ), .

[0049] Three-level inverter #2: u x2 * = Usin(ωt - θ x ), .

[0050] Among them, ω represents the angular frequency, t represents the time variable, θ x represents the initial phase of the modulation wave, and respectively represent the power factor angles of three-level inverter #1 and #2, and k represents a coefficient, k ≠ 1.

[0051] Based on the foregoing calculation formula for the midpoint voltage fluctuation ΔV, in order to achieve midpoint balance, there should be: Three-level inverter #1: (1).

[0052] Three-level inverter #2: (2).

[0053] Among them, u z1 and u z2 respectively represent the zero-sequence voltages corresponding to three-level inverter #1 and #2; if you want to achieve circulating current balance, you need to have u z1 = u z2 . Obviously, when k ≠ 1 or , the above formula (1) and formula (2) and u z1 = u z2 cannot hold simultaneously, so it is impossible to achieve midpoint balance and zero-sequence circulating current suppression at the same time.

[0054] Aiming at the contradiction between the above midpoint balance and circulating current suppression control, this application proposes a coordinated control method for inverter midpoint balance and circulating current suppression, which can be applied to the parallel scenario of multiple three-level inverters. One preferred embodiment is as Figure 4 and Figure 5As shown in the figure, the following control steps are performed on each three-level inverter: The three-phase grid-side currents are collected, and three-phase bridge-arm modulation signals are generated through the grid-connected current control loop; the lower half-bus voltage is collected, and the first zero-sequence component is generated through the neutral-point balance control loop; the three-phase grid-side currents are collected, and the second zero-sequence component is generated through the circulating-current suppression control loop. The first zero-sequence component and the second zero-sequence component are input into the competition logic processing module, and the final zero-sequence component is generated by using the competition mechanism based on dynamic weight allocation. The final zero-sequence component is subjected to overmodulation processing and then superimposed on the three-phase bridge-arm modulation signals of the grid-connected current control loop, and then the control signals of the three-level inverter are obtained through PWM modulation.

[0055] It can be understood that the technical solution of the present application can generate double zero-sequence components according to the neutral-point voltage fluctuation and zero-sequence circulating current, and then adopt the competition mechanism based on dynamic weight allocation to adaptively process the double zero-sequence components according to the actual working conditions of the neutral-point voltage fluctuation and zero-sequence circulating current, so as to obtain the zero-sequence injection amount injected into the three-phase modulation wave, thereby realizing the coordinated control of neutral-point balance and circulating-current suppression. Compared with the traditional method, the present application can dynamically coordinate the requirements of neutral-point balance and circulating-current suppression, so as to achieve their efficient coordination and reduce the control complexity, and is applicable to low-cost industrial application scenarios.

[0056] In this embodiment, the specific working process of the grid-connected current control loop is well-known to those skilled in the art. For the convenience of understanding, the following takes the three-level inverter #2 in the inverter parallel architecture shown in Figure 1 as an example to briefly describe the working process of the grid-connected current control loop. As shown in Figure 5 the figure, the sampled three-phase currents i a2 , i b2 and i c2 are transformed from abc to dq to obtain the d-axis current i d2 and the q-axis current i q2 ; the d-axis current i d2 and the q-axis current i q2 are respectively compared with the d-axis current reference i d2 * and the q-axis current reference i q2 * , and the errors are respectively superimposed with the grid feed-forwards e d and e q after passing through the controller, and then transformed from dq0 to abc to obtain the three-phase bridge-arm modulation signals d a2 , d b2 and d c2 . These three-phase bridge-arm modulation signals can be superimposed with the final zero-sequence component d z2 after overmodulation processing, and then the switching control signals of the three-phase bridge arms are output through PWM modulation.

[0057] In this embodiment, as shown inFigure 5 As shown, the midpoint balance control loop mainly includes a comparator and a controller. Based on the architecture of the midpoint balance control loop, the generation process of the first zero-sequence component d z_1 is as follows: Sample the lower half-bus voltage V n , multiply the lower half-bus voltage V n by two and compare it with the bus voltage V bus in the comparator to obtain the midpoint voltage fluctuation ΔV. Then input the obtained midpoint voltage fluctuation ΔV into the controller and output the first zero-sequence component d z_1 .

[0058] At the same time, the circulating current suppression control loop also mainly includes a comparator and a controller; based on the architecture of the circulating current suppression control loop, the generation process of the second zero-sequence component d z_2 is as follows: Sum the three-phase grid-side currents i a , i b and i c , and then divide the sum by three to obtain the zero-sequence circulating current i z ; Input the zero-sequence circulating current i z into the comparator to compare it with zero; Input the comparison result into the controller and output the second zero-sequence component d z_2 .

[0059] It can be understood that there are various types of controllers used in the control loop, such as PI control and PR controllers, etc.; in this embodiment, a PI controller is preferably used; then in the controllers of the midpoint balance control loop and the circulating current suppression control loop, the first zero-sequence component d z_1 is generated respectively according to the midpoint voltage fluctuation ΔV, and the second zero-sequence component d z is generated according to the zero-sequence circulating current i z_2 . The specific formulas are as follows: .

[0060] .

[0061] Among them, K p1 and K p2 both represent proportionality coefficients, and K i1 and K i2 both represent integral coefficients.

[0062] It should be known that if the working process of the control loop shown in Figure 5 corresponds to the three-level inverter #2, then the three-phase grid-side currents i a , i b and i c correspond to i a2 , i b2 and i c2 , the first zero-sequence components d z_1 and dz_2 correspond to d respectively z2_1 and d z2_2 , the midpoint voltage fluctuation ΔV corresponds to ΔV2, and the zero-sequence circulating current i z corresponds to i z2 , the lower bus voltage V n corresponds to V n2 , and the final zero-sequence component d z corresponds to d z2 .

[0063] In this embodiment, when designing the competition mechanism of the competition logic processing module, the final zero-sequence component d that dynamically distributes the weights of the first zero-sequence component and the second zero-sequence component according to the working conditions z has the following calculation formula: d z =αd z_1 +βd z_2 . Among them, d z_1 and d z_2 represent the first zero-sequence component and the second zero-sequence component respectively, and α and β represent the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively. After obtaining the calculation formula of the final zero-sequence component d z , the values of the weights α and β can be allocated according to the actual working conditions, and then the specific value of the final zero-sequence component d z can be obtained.

[0064] Specifically, based on the actual working conditions of the inverter, the competition modes of the competition logic processing module can include an emergency mode, a forced mode, and a normal competition mode. Different competition modes correspond to different weight allocation methods. Then, the competition logic processing module can select the competition mode according to the relationship between the midpoint voltage fluctuation and the zero-sequence circulating current and the corresponding set thresholds respectively, and then determine the allocation weights of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component. For the convenience of understanding, the following will describe in detail the setting process of the thresholds and the weight allocation process under different competition modes.

[0065] I. For the setting of the thresholds.

[0066] For the threshold V th corresponding to the midpoint voltage fluctuation ΔV, the withstand voltage situation of the bus capacitor is mainly considered. Therefore, the threshold V th can be set according to the following formula.

[0067] V th =k1(V max -V bus / 2).

[0068] Among them, k1 represents the voltage safety factor, which can be selected according to the user application requirements, and the value is 0.7~0.8; V max represents the maximum withstand voltage of the bus capacitor.

[0069] For the zero-sequence circulating current i z The corresponding threshold value I th , mainly consider the current-carrying capacity of the device, that is, the maximum current I allowed by the line max , so the threshold value I can be set according to the following formula th .

[0070] .

[0071] Among them, k2 represents the current safety factor, which can be selected according to the user's application requirements, and the value is 0.5; i line represents the maximum value of the three-phase current on the grid side, that is, i line = max{i a , i b , i c}.

[0072] II. Weight allocation strategies under different competition modes.

[0073] (1) When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set threshold values V th and I th as follows: |ΔV| < V th and |i z | < I th , the competition logic processing module is in the normal competition mode. At this time, the weights α and β are dynamically allocated according to the deviation magnitude. To avoid the influence of the dimension on the allocation, the per-unit value needs to be used for allocation. Then the calculation formulas for the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component are as follows: α = (|ΔV| / V th ) / [(|ΔV| / V th ) + (|i z | / I th )].

[0074] β = (|i z | / I th ) / [(|ΔV| / V th ) + (|i z | / I th )].

[0075] (2) The forced modes of the competition logic processing module include the voltage forced mode and the circulating current forced mode.

[0076] When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set threshold values V th and I th as follows: |ΔV| ≥ Vth and |i z | < I th When this is the case, the competition logic processing module is in the voltage forced mode. At this time, the relationship between the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component respectively is: α ≥ 2β, α + β = 1; by increasing the value of the weight α and decreasing the value of the weight β, the midpoint voltage fluctuation can be forced to decrease. The specific values of the weights α and β can be selected according to the actual needs of those skilled in the art. For example, α = 0.9 and β = 0.1 can be taken.

[0077] When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z respectively correspond to the set thresholds V th and I th in the relationship of: |ΔV| < V th and |i z | ≥ I th When this is the case, the competition logic processing module is in the circulating current forced mode. At this time, the relationship between the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component respectively is: β ≥ 2α, α + β = 1. By increasing the value of the weight β and decreasing the value of the weight α, the circulating current can be forced to decrease. The specific values of the weights α and β can be selected according to the actual needs of those skilled in the art. For example, α = 0.1 and β = 0.9 can be taken.

[0078] (3) When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z respectively correspond to the set thresholds V th and I th in the relationship of: |ΔV| ≥ V th and |i z | ≥ I th When this is the case, the competition logic processing module is in the emergency mode; at this time, the following hierarchical control strategy is adopted.

[0079] The first priority is midpoint voltage control: by setting α ≥ 2β to preferentially reduce the midpoint voltage fluctuation and prevent overvoltage damage of the bus capacitor.

[0080] The second priority is circulating current suppression: by inserting a circulating current suppression pulse compensation amount Δd sw into the final zero-sequence component d z within a single switching period T z , the influence of midpoint balance on the circulating current is reduced. In this process, the calculation formula of the circulating current suppression pulse compensation amount Δd z is as follows: .

[0081] Among them, K p represents the compensation coefficient, which can be given according to the actual debugging situation; L represents Figure 3The inductance value in the equivalent circuit shown.

[0082] It can be understood that after the insertion of the circulating current suppression pulse compensation amount Δd z the final zero-sequence component d z ´ = d z + Δd z . In the emergency mode, when the midpoint voltage recovers to |ΔV| < V th , it can be switched to the circulating current forced mode to suppress the zero-sequence circulating current until |i z | < I th .

[0083] For the convenience of understanding, the switching process of different competition modes will be described in detail below. For the switching of modes, a hysteresis method can be preferably adopted, and the emergency mode is taken as an example of the initial state for illustration.

[0084] As Figure 6 shown, the initial state is the emergency mode. If the midpoint voltage fluctuates |ΔV| < V th - V exit , then it is switched from the emergency mode to the circulating current forced mode; where V exit represents the voltage hysteresis amount, which can avoid the jitter of mode switching. In the circulating current forced mode, if the midpoint voltage fluctuates |ΔV| ≥ V th , then it is immediately switched back to the emergency mode from the circulating current forced mode; if the zero-sequence circulating current |i z | < I th - I exit , then it is switched from the circulating current forced mode to the normal competition mode; where I exit represents the current hysteresis amount, which can avoid the jitter of mode switching. In the normal competition mode, if the zero-sequence circulating current |i z | ≥ I th , then it is immediately switched to the circulating current forced mode from the normal competition mode; if the midpoint voltage fluctuates |ΔV| ≥ V th , then it is immediately switched to the voltage forced mode from the normal competition mode. In the voltage forced mode, if the midpoint voltage fluctuates |ΔV| < V th - V exit , then it is switched from the voltage forced mode to the normal competition mode; if the zero-sequence circulating current |i z | ≥ I th , then it is immediately switched to the emergency mode from the voltage forced mode.

[0085] It should be known that since the switching control signals of the three-phase bridge arms are superimposed with zero-sequence components, overmodulation may be caused, which may further lead to modulation failure. Therefore, before injecting the final zero-sequence component, overmodulation processing needs to be carried out on the final zero-sequence component; the overmodulation processing of the final zero-sequence component includes the following process: According to the current modulation wave d x * Determine the final zero-sequence component d z The limit values, including the upper limit value d zmax and the lower limit value d zmin ; The upper limit value d zmax and the lower limit value d zmin The calculation formulas are: d zmax =1 - max{d a * , d b * , d c *}, d zmin =-1 - min{d a * , d b * , d c *}; Wherein, d a * , d b * and d c * represent the three-phase modulation waves.

[0086] When the final zero-sequence component is close to the upper limit value d zmax , that is, when the deviation between the final zero-sequence component and the upper limit value d zmax is less than the specified allowable deviation, the weights α and β are corrected. The calculation formulas for the corrected weights α' and β' are: α' = α×(d zmax - d z ) / d zmax , β' = β×(d zmax - d z ) / d zmax .

[0087] When the final zero-sequence component is close to the lower limit value d zmin , that is, when the deviation between the final zero-sequence component and the lower limit value d zmin is less than the specified allowable deviation, the weights α and β are corrected. The calculation formulas for the corrected weights α" and β" are: α" = α×(d z - d zmin ) / d zmin , β" = β×(d z - d zmin ) / d zmin .

[0088] It should be noted that if the competition logic processing module is in the emergency mode before the over-modulation processing, then for the correction formulas of the weights α and β, the final zero-sequence component d zAdopt the inserted circulation suppression pulse compensation amount Δd z The compensated value d z ´.

[0089] The foregoing has described the basic principles, main features, and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present application. Without departing from the spirit and scope of the present application, the present application will have various changes and improvements, and these changes and improvements all fall within the scope of the present application claimed. The scope of protection required by the present application is defined by the appended claims and their equivalents.

Claims

1. A cooperative control method for inverter midpoint balance and circulating current suppression, which is applied to the scenario of multiple three-level inverters in parallel; characterized in that, The following control steps are performed on each three-level inverter: Collect the three-phase grid-side current and generate three-phase bridge-arm modulation signals through the grid-connected current control loop; Collect the lower half-bus voltage and generate the first zero-sequence component through the neutral-point balance control loop; Collect the three-phase grid-side current and generate the second zero-sequence component through the circulating-current suppression control loop; Input the first zero-sequence component and the second zero-sequence component into the competition logic processing module, and generate the final zero-sequence component by using the competition mechanism based on dynamic weight allocation; Perform overmodulation processing on the final zero-sequence component and superimpose it on the three-phase bridge-arm modulation signals of the grid-connected current control loop, and then obtain the control signals of the three-level inverter after PWM modulation.

2. The synergistic control method for inverter neutral point balance and circulating current suppression according to claim 1, wherein The neutral-point balance control loop includes a comparator and a controller; the generation process of the first zero-sequence component is as follows: Multiply the lower half-bus voltage by two and compare it with the bus voltage in the comparator to obtain the neutral-point voltage fluctuation; input the neutral-point voltage fluctuation into the controller to output the first zero-sequence component.

3. The inverter neutral point balance and circulating current suppression collaborative control method according to claim 2, wherein The circulating-current suppression control loop includes a comparator and a controller; the generation process of the second zero-sequence component is as follows: Sum the three-phase grid-side current and divide it by three to obtain the zero-sequence circulating current; input the zero-sequence circulating current into the comparator and compare it with zero; input the comparison result into the controller to output the second zero-sequence component.

4. The coordinated control method for neutral point balance and circulating current suppression of the inverter according to claim 3, wherein The competition modes of the competition logic processing module include the emergency mode, the forced mode, and the normal competition mode; The competition logic processing module is adapted to select the competition mode according to the relationship between the neutral-point voltage fluctuation and the zero-sequence circulating current and their corresponding set thresholds, and then determine the distribution weights of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component; Final zero-sequence component d z The calculation formula is: d z = αd z_1 + βd z_2 ; where d z_1 and d z_2 represent the first zero-sequence component and the second zero-sequence component respectively, and α and β represent the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively.

5. The synergistic control method for inverter neutral point balance and circulating current suppression according to claim 4, characterized in that For the threshold value V corresponding to the midpoint voltage fluctuation th The calculation formula is: V th = k1(V max - V bus / 2); Among them, k1 represents the voltage safety factor, V max represents the maximum withstand voltage of the bus capacitor, V bus represents the bus voltage.

6. The method for cooperative control of neutral point balance and circulating current suppression of the inverter according to claim 4, characterized in that, For the threshold value I corresponding to the zero-sequence circulating current th The calculation formula is as follows: ； Among them, k2 represents the current safety factor, I max represents the maximum current allowed by the line, i line represents the maximum value of the three-phase current on the grid side, i z represents the zero-sequence circulating current.

7. The synergistic control method for inverter midpoint balance and circulating current suppression according to claim 4, characterized in that When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively compared with the corresponding set thresholds V th and I th and the relationships are: |ΔV| < V th and |i z | < I th the competition logic processing module is in the normal competition mode; At this time, the calculation formulas for the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component are as follows: α = (|ΔV| / V th ) / [(|ΔV| / V th ) + (|i z | / I th )]; β = (|i z | / I th ) / [(|ΔV| / V th ) + (|i z | / I th )].

8. The coordinated control method for inverter neutral point balance and circulating current suppression according to claim 4, characterized in that The forced mode of the competition logic processing module includes the voltage forced mode and the circulating-current forced mode; When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV|≥V th and |i z |<I th the competition logic processing module is in the voltage forced mode; at this time, the relationship between the weights α and β is: α≥2β, α + β = 1; When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV| < V th and |i z | ≥ I th the competition logic processing module is in the circulating current forced mode; at this time, the relationship between the weights α and β is: β ≥ 2α, α + β = 1.

9. The synergistic control method for inverter neutral point balance and circulating current suppression according to claim 4, characterized in that When the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z are respectively related to the corresponding set thresholds V th and I th as follows: |ΔV|≥V th and |i z |≥I th , the competition logic processing module is in the emergency mode; at this time, the following hierarchical control strategy is adopted: First priority, set α≥2β to reduce the neutral-point voltage fluctuation; Second priority, by inserting the circulating current suppression pulse compensation amount Δd into the final zero-sequence component d within a single switching cycle, so that the compensated final zero-sequence component d' = d + Δd; z Insert the circulating current suppression pulse compensation amount Δd z , and then the compensated final zero-sequence component d z ´ = d z + Δd z ; Circulation inhibition pulse compensation amount Δd z The calculation formula is as follows: ； Among them, K p represents a compensation coefficient, L represents an inductance value, V bus represents the bus voltage, i z represents the zero-sequence circulating current, I th represents the threshold value corresponding to the zero-sequence circulating current i z T sw represents the switching period.

10. The synergistic control method for inverter midpoint balance and circulating current suppression according to any one of claims 4-9, characterized in that, The overmodulation processing for the final zero-sequence component includes the following process: According to the current modulation wave d x * Determine the final zero-sequence component d z The limit values, including the upper limit value d zmax and the lower limit value d zmin ; The upper limit value d zmax and the lower limit value d zmin The calculation formulas are as follows: d zmax =1 - max{d a * ,d b * ,d c *},d zmin =-1 - min{d a * ,d b * ,d c *}; When the final zero-sequence component approaches the upper amplitude value, the weights α and β are corrected. The calculation formulas for the corrected weights α' and β' are: α' = α × (d zmax - d z ) / d zmax , β' = β × (d zmax - d z ) / d zmax ; When the final zero-sequence component approaches the lower amplitude, the weights α and β are corrected. The calculation formulas for the corrected weights α" and β" are: α" = α × (d z - d zmin ) / d zmin , β" = β × (d z - d zmin ) / d zmin ; Among them, d a * , d b * and d c * represent three-phase modulation waves.

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