Source driver for controlling charge sharing, and display device including the same

Abstract

A source driver for controlling charge sharing and a display device including the same are disclosed. A source driver according to at least one of various embodiments of the present disclosure may include: a first latch unit that stores first image data for each channel; a second latch unit that stores second image data input through the first latch unit; a charge sharing control unit that acquires a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit for a target channel among channels having the same polarity, and acquires a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit for an adjacent channel; the processor is used for acquiring predefined bits of the first image data of the first latch unit and predefined bits of the second image data of the second latch unit, and generating and outputting an MUX operation control signal based on data change; and an MUX that performs a charge sharing operation according to the MUX operation control signal.

Description

Technical Field

[0001] The present disclosure relates to a charge sharing operation, and more particularly, to a source driver that selectively controls charge sharing between channels having the same polarity and a display device including the source driver. Background Art

[0002] A liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal cells according to a video signal.

[0003] To reduce a DC offset component and deterioration of liquid crystal, such a liquid crystal display device employs a dot inversion method to invert the polarity of data voltages for each horizontally adjacent and vertically adjacent liquid crystal cell.

[0004] The polarity of the data voltage is determined based on a common voltage. A data voltage having a positive polarity (+) is selected in a range higher than the common voltage. A data voltage having a negative polarity (-) is selected in a range lower than the common voltage. However, according to this dot inversion method, since the data voltages applied to the same data line must swing between the positive polarity (+) and the negative polarity (-) in each horizontal period, the number of data conversions in each output channel of the source driver (SDIC) increases by an amount as large as the vertical resolution, thereby increasing the power consumption of the source driver.

[0005] Therefore, a so-called column inversion panel rendering method has been proposed, in which the polarity of liquid crystal cells formed in a liquid crystal display panel is controlled according to the dot inversion method to reduce deterioration of liquid crystal, and the number of data conversions in each output channel of the source driver is reduced to once per frame to reduce the power consumption of the source driver.

[0006] For the column inversion panel rendering method, it requires a liquid crystal display panel having TFTs connected in a Z-inversion format and a source driver driven in a column inversion format.

[0007] In a liquid crystal display panel, a plurality of TFTs for switching data voltages supplied to liquid crystal cells are connected to data lines connected to respective output channels in a zigzag form to implement a Z-inversion form.

[0008] In this case, the polarity of the data voltage output from the source driver is controlled to be inverted in adjacent output channels within the same frame, but is controlled to be inverted in all output channels on a per-frame basis to implement column inversion driving.

[0009] Meanwhile, a charge sharing method is known to reduce the power consumption of the source driver.

[0010] However, there is a problem in that the source driver performs charge sharing even when it is not necessary, which may increase the power consumption. Summary of the Invention

[0011] Technical Problem

[0012] An object of the present disclosure is to provide a source driver that selectively or independently controls charge sharing between channels of the same polarity, a display device including the source driver, and an operation method thereof.

[0013] The technical problems to be solved by the embodiments are not limited to the technical problems described in this item, but include technical problems that can be understood through the description of the present invention.

[0014] Technical Solution

[0015] According to an embodiment of the present disclosure, a source driver may include: a first latch unit configured to store first image data for each channel; a second latch unit configured to store second image data input through the first latch unit; a charge sharing controller configured to: for a target channel among channels having the same polarity, obtain a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit, for an adjacent channel, obtain a predefined bit of the first image data of the first latch unit and a predefined bit of the second image data of the second latch unit, and generate and output a multiplexer operation control signal based on data changes; and a multiplexer configured to perform a charge sharing operation according to the multiplexer operation control signal.

[0016] In this case, the charge sharing controller is configured to group a preset number of channels and generate a multiplexer operation control signal for the grouped channels.

[0017] Moreover, the multiplexer is disposed between a target channel and an adjacent channel among channels having the same polarity.

[0018] In addition, the charge sharing controller is configured to: determine that the difference between the predefined bit of the second image data of the second latch unit received for a predetermined channel and the predefined bit of the first image data of the first latch unit received is greater than or equal to a threshold, and generate the multiplexer operation control signal for the multiplexer to perform the charge sharing operation only when the difference between the predefined bit of the second image data of the second latch unit received for an adjacent channel of the predetermined channel and the predefined bit of the first image data of the first latch unit received is greater than the threshold.

[0019] Moreover, whether the difference between the predefined bits of the image data of each latch unit of each channel is greater than or equal to the threshold is determined as the data value of the corresponding bit changes from 0 to 1 or from 1 to 0.

[0020] In addition, whether the difference between predefined bits of the image data of each latch unit of each channel is greater than or equal to a threshold is determined such that the value of the output channel after the charge sharing operation is different from the value of the output channel before the charge sharing operation.

[0021] Moreover, the charge sharing controller is configured to generate an operation control signal for each mux arranged in the unit channel according to the comparison result, and the operation control signal does not include an operation control signal for controlling all multiplexers in the unit channel to operate.

[0022] In addition, the charge sharing controller is configured to generate an operation control signal for all multiplexers in the unit channel according to the comparison result, and the operation control signal includes an operation control signal for controlling all multiplexers in the unit channel not to operate.

[0023] Also, an adjacent channel is one of the channels having the same polarity as a predetermined channel.

[0024] In addition, the predefined bits include the most significant bit (MSB) of each image data of each channel.

[0025] Technical Effects

[0026] According to at least one of the various embodiments of the present disclosure, charge sharing between channels having the same polarity can be selectively or independently controlled, rather than uniformly performed, thereby reducing power consumption.

[0027] The technical effects of the embodiments of the present disclosure are not limited to the above technical effects, and include technical effects that can be understood through the overall description of the present disclosure. Brief Description of the Drawings

[0028] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a diagram showing a pixel array related to the present disclosure.

[0030] Figure 3 is a diagram showing a configuration of a source driver that selectively controls a charge sharing operation according to an input data pattern according to an embodiment of the present disclosure.

[0031] Figure 4 is a diagram showing a configuration of a source driver that selectively controls a charge sharing operation according to an input data pattern according to another embodiment of the present disclosure.

[0032] Figure 5 isFigure 4 Detailed block diagram of a charge sharing controller.

[0033] Figure 6 It is a diagram showing waveforms of data voltages applied to each output channel according to an input data pattern according to an embodiment of the present disclosure.

[0034] Figures 7 to 11 It is a diagram explaining the operation principle of a source driver according to a data pattern according to an embodiment of the present disclosure. Detailed implementation mode

[0035] Hereinafter, the present invention according to an embodiment for solving the above problems will be described in more detail with reference to the accompanying drawings.

[0036] In the following description, the suffixes "module" and "component" for components are given only for the convenience of writing this specification, and they do not give any particularly important meaning or function in themselves. Therefore, the terms "module" and "unit" can be used interchangeably.

[0037] Ordinal numbers such as first, second, etc. may be used to describe various components, but these components are not limited by these terms. The above terms are only used to distinguish one component from another.

[0038] Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0039] In this application, terms such as "including", "having", or "comprising" are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification. It should be understood that it does not preclude the presence or addition of other features, numbers, steps, operations, components, parts, or combinations thereof in advance.

[0040] In the present disclosure, a source driver that independently controls the charge sharing operation between channels, a display device including the source driver, and an operation method thereof will be disclosed.

[0041] For example, channels for which the charge sharing operation is independently controlled may be channels having the same polarity.

[0042] Hereinafter, the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1 It is a diagram of a display device according to an embodiment of the present disclosure.

[0044] Referring to Figure 1 , the display device 10 may include a panel 11, a source driver (SDIC: source driver IC) 12, a gate driver (GDIC: gate driver IC) 13, a timing controller 14, etc.

[0045] A plurality of data lines (DL), a plurality of gate lines (GL), and a plurality of pixels (P) can be provided on the panel 11.

[0046] The plurality of pixels (P) can be arranged adjacent to each other in the horizontal direction (H) and the vertical direction (V) of the panel 11 to form a square shape.

[0047] The square shape is similar to a matrix. A set of the plurality of pixels (P) arranged in the horizontal direction (H) or a horizontal line representing the set is defined as a row or a line. A set of the plurality of pixels (P) arranged in the vertical direction (V) or a vertical line representing the set is defined as a column or a channel.

[0048] The gate driver (GDIC) 13 can provide a scanning signal of a turn-on voltage or a turn-off voltage to the gate line (GL).

[0049] When the scanning signal of the turn-on voltage is provided to the pixel (P), the pixel (P) is connected to the data line (DL). On the other hand, when the scanning signal of the turn-off voltage is provided to the pixel (P), the connection between the pixel (P) and the data line (DL) is released.

[0050] The source driver (SDIC) 12 can provide a data voltage to the data line (DL).

[0051] According to the scanning signal, the data voltage provided to the data line (DL) is transmitted to the pixel (P) connected to the data line (DL).

[0052] The timing controller 14 can provide various control signals to the gate driver (GDIC) 13 and the source driver (SDIC) 12.

[0053] The timing controller 14 can generate a gate control signal (GCS) for controlling the start of scanning according to the timing implemented in each frame, and send it to the gate driver (GDIC) 13.

[0054] The timing controller 14 can convert image data input from an external source (e.g., a host (not shown)) into image data (RGB) according to the data format used by the source driver (SDIC) 12, and the converted image data (RGB) can be output to the source driver (SDIC) 12.

[0055] In addition, the timing controller 14 can send a data timing control signal (DCS) for controlling the source driver (SDIC) 12 to provide a data voltage to each pixel (P) according to each timing.

[0056] Figure 2 It is a diagram showing a pixel array (PA) related to the present disclosure.

[0057] Figure 2 (a) of shows a pixel array (PA) in a normal panel. The pixel array (PA) in the normal panel is a known technique, and detailed description thereof is omitted here.

[0058] Figure 2 (b) of shows a pixel array (PA) in a zigzag panel.

[0059] As Figure 2 shown in (b) of , the polarity of the panel structure or the pixel array (PA) can be changed frame by frame based on the source output.

[0060] Referring to Figure 2 the pixel array (PA) shown in (b) of , data lines (S<1> to S <n>)。

[0061] Meanwhile, in Figure 2 of (b), G<1> to G <n>It can represent a gate line (GL).

[0062] In other words, in the column inversion panel shown in (b) of Figure 2 , the polarity of the data voltage output from the source driver (SDIC) 12 is controlled to be inverted in adjacent (or neighboring) output channels within the same frame, enabling column inversion driving.

[0063] The timing controller 14 can align the input image data (RGB) according to the structure of the pixel array (PA) shown in (a) or (b) of Figure 2 , and then provide it to the source driver (SDIC) 12.

[0064] The timing controller 14 can receive timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a clock (CLK) from the outside, and generate control signals for controlling the operation timing of the gate driver (GDIC) 13 and the source driver (SDIC) 12.

[0065] The control signals can include a gate timing control signal (GCS) for controlling the operation timing of the gate driver (GDIC) 13, and a data timing control signal (DCS) for controlling the operation timing of the source driver (SDIC) 12 and controlling the vertical polarity of the data voltage.

[0066] The timing controller 14 can generate the frequencies of the gate control signal (GCS) and the data timing control signal (DCS) based on the frame frequency, so that the input image data (RGB) at a predetermined frame frequency can be displayed on the pixel array (PA) of the panel 11, as shown in Figure 2 (a) or (b).

[0067] The gate timing control signal (GCS) can include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc. The gate output enable signal (GOE) can control the output of the gate driver IC.

[0068] The data timing control signal (DCS) can include a source start pulse, a source sampling clock, a vertical polarity control signal, a source output enable signal (SOE), a multiplexer (i.e., mux) control signal.

[0069] The vertical polarity control signal (POL) can control the vertical polarity of the data voltage sequentially output from each source driver IC.

[0070] The source output enable signal (SOE) in the data timing control signal (DCS) can control the output timing of the source driver (SDIC) 12.

[0071] During a period when the source output enable signal (SOE) remains high (i.e., the horizontal blanking period), the output of the data voltage from the source driver (SDIC) 12 can be blocked.

[0072] On the other hand, during a period when the source output enable signal (SOE) remains low (i.e., the horizontal blanking period), the output of the data voltage from the source driver (SDIC) 12 can be allowed.

[0073] In the above, the horizontal blanking period can be arranged between adjacent (or neighboring) horizontal periods.

[0074] Figure 3 is a diagram showing the configuration of a source driver (SDIC) 12 that selectively controls a charge sharing operation according to an input data pattern according to an embodiment of the present disclosure.

[0075] Figure 4 is a diagram showing the configuration of a source driver (SDIC) 12 that selectively controls charge sharing according to an input data pattern according to another embodiment of the present disclosure.

[0076] Figure 5 is Figure 4 a detailed block diagram of the charge sharing controller 410.

[0077] Figure 6 is a diagram showing waveforms of data voltages applied to respective output channels according to an input data pattern according to an embodiment of the present disclosure.

[0078] Figures 7 to 11 is a diagram for explaining the operation principle of the source driver (SDIC) 12 according to a data pattern according to an embodiment of the present disclosure.

[0079] Referring to Figure 3 , the source driver (SDIC) 12 can have a plurality of output channels to alternately output a high voltage (VH) data voltage and a low voltage (VL) data voltage.

[0080] Each of the output terminals of the output channels can be connected to the data line on a one-to-one basis.

[0081] The source driver (SDIC) 12 can divide all output channels into n groups (n is a natural number). In each channel group, a charge sharing operation can be performed again according to the polarity (VH / VL).

[0082] In the above, n is preferably a multiple of 6 for a charge sharing operation based on the polarity of the data voltage, etc., but is not limited thereto.

[0083] Hereinafter, in the present disclosure, for convenience, as an example, six channels will be described as a unit or a group, but it is not limited thereto. That is, the number of channels belonging to the unit or the group can be appropriately determined in consideration of efficiency or design purposes. Therefore, 12, 18, 24 channels, etc. can form a unit or a group.

[0084] The source driver (SDIC) 12 may include at least two latches, a processor 330, a charge sharing unit, an output buffer (not shown), etc.

[0085] The processor 330 may include at least one of an amplifier, a digital-to-analog converter (DAC), etc.

[0086] The source driver (SDIC) 12 may latch the input image data (RGB) according to a data timing control signal (DCS), convert the latched data into analog VH / VL voltages, and output the data voltages with inverted polarities within one frame period to the data lines (DL).

[0087] In Figure 3 the source driver (SDIC) 12 may generate a charge sharing control signal by processing the data input to each of the latches 310, 320 corresponding to the same polarity by the processor 330. After the image data is input to the first latch 310 of each channel, the input image data is transmitted to the second latch 320 according to a predetermined signal, and the next image data may be input to the first latch 310. Therefore, the data input to the first latch 310 may be referred to as current data, and the data input to the second latch 320 may be referred to as the previous data of the data input to the first latch 310.

[0088] According to the charge sharing control signal, the charge sharing units corresponding to the respective polarities, that is, all the multiplexers (CS-MUX) 341-343 and 351-353 may be activated or deactivated.

[0089] Referring to Figure 4 and Figure 3 different from

[0090] in this case, for example, the charge sharing controller 410 may be disposed between the second latch 320 and the processor 330.

[0091] The charge sharing controller 410 may generate and send a selective activation / deactivation control signal for the charge sharing units (i.e., multiplexers (CS-MUX)) arranged between the channels having the same polarity.

[0092] Referring to Figure 5 , the charge sharing controller 410 will be described in more detail below.

[0093] The charge sharing controller 410 may include first polarity control logic, i.e., VH control logic (e.g., the first, third, and fifth channels) (511 - 513) and second polarity control logic, i.e., VL control logic (e.g., the second, fourth, and sixth channels) (521 - 523).

[0094] For example, the VH control logic 511 - 513 may be configured to control the charge sharing operation of the outputs for the first, third, and fifth channels.

[0095] In this case, the VH control logic 511 - 513 may generate control signals for activating the first charge sharing unit 341 to the third charge sharing unit 343 based on the values obtained by comparing the data of the first latch 310 and the second latch 320 for each channel.

[0096] The VH control logic 511 - 513 may determine whether to activate the corresponding charge sharing units 341 - 343 by comparing the data of the corresponding channel and the adjacent channel (or neighboring channel) having the same polarity as the corresponding channel.

[0097] For example, the first charge sharing unit 341 is provided between the output terminals of the first channel (corresponding channel) and the third channel (adjacent channel), and its activation is controlled based on the data of the two channels.

[0098] According to an embodiment of the present disclosure, different from Figure 4 , all of the charge sharing units 341 - 343 in the VH control logic 511 - 513 cannot be activated simultaneously.

[0099] According to an embodiment of the present disclosure, different from Figure 4 , only some of all the charge sharing units 341 - 343 in the VH control logic 511 - 513 can be activated.

[0100] According to an embodiment of the present disclosure, different from Figure 4 , all of the charge sharing units 341 - 343 in the VH control logic 511 - 513 may not be activated.

[0101] According to an embodiment of the present disclosure, as described above, it may be determined whether to activate the charge sharing unit based on the data values of the latch units of the corresponding channel (or target channel) and the adjacent channel having the same polarity.

[0102] Referring to Figures 6 to 11 , it will be described in detail below how to control whether the charge sharing controller 410 activates the charge sharing units 341 - 343 and 351 - 353.

[0103] First, as described above Figure 3 shown, when performing charge sharing operations for all cases, power consumption may increase due to unnecessary charge sharing operations.

[0104] Therefore, as Figure 4 shown, by short - circuiting all channels of the same polarity in a group unit to perform charge sharing operations, not all multiplexers of the corresponding polarity are activated at once, but charge sharing operations are performed only for channels of the same polarity when specific conditions are met, so that an unnecessary increase in power consumption can be prevented.

[0105] Figure 4 The charge sharing controller 410 as described above is shown in. One or more charge sharing controllers 410 can be set in a group. In the latter case, for example, a charge sharing controller for VH channels and a charge sharing controller for VL channels can be set separately.

[0106] Above, the specific condition can indicate, for example, a case where the data change between corresponding channels and adjacent channels of the same polarity (VH or VL) is greater than or equal to a threshold. In this case, the data change can indicate, for example, a change in the data conversion width.

[0107] At the same time, a data change greater than or equal to the threshold can indicate, for example, a case where there is current consumption due to the data change in channels of the same polarity, as Figure 6 shown in (b). In other words, for example, by comparing the data values of each latch in corresponding channels and adjacent channels of the same polarity, the data change can be determined. For example, in the VH period, when as a result of the comparison, the data values of each latch in the corresponding channel and the adjacent channel change based on the threshold (e.g., Figure 6 650 in), the corresponding charge sharing unit is activated to perform charge sharing operations.

[0108] Above, according to an embodiment of the present disclosure, the charge sharing controller 410 can use the MSB (i.e., only 1 bit (1 - 0 or 0 - 1) of each latch unit in corresponding channels and adjacent channels of the same polarity) to determine whether to control the charge sharing operation. In this case, since the threshold uses only the MSB (i.e., 1 bit), it can be an intermediate value between 0 and 1. Therefore, as Figure 6 As shown in (b), when a charge sharing operation occurs during the period when the SOE is high in the charge sharing mode and the data correspondingly changes from 1 to 0 or from 0 to 1, according to the data conversion width within a shared channel group corresponding to a threshold value (about 50% of the case without charge sharing operation) (655), the current consumption can be correspondingly reduced, and the power consumption can also be correspondingly reduced.

[0109] Meanwhile, according to another embodiment of the present disclosure, the charge sharing controller 410 can determine whether to control the charge sharing operation by using 2 bits or 3 bits (instead of 1 bit of the MSB) of each latch unit in the corresponding channels and adjacent channels with the same polarity. In the above case, a higher threshold value (e.g., 50% or higher) can be set compared with the case of using only 1 bit (or MSB), so that the reduction of current consumption and power consumption can be achieved.

[0110] Figure 6 (a) shows Figure 3 the waveform of the output data during the charge sharing operation according to Figure 6 (b) shows Figure 4 the waveform of the output data during the charge sharing operation according to

[0111] In Figure 6 the charge sharing controller 410 can selectively generate and send a charge sharing control signal during the period when the source output enable signal (SOE) is high.

[0112] Referring to Figure 6 (a), when the source output enable signal (SOE) remains high, the charge sharing controller 410 can perform the charge sharing operation.

[0113] For example, during the VH period, in SOUT1, the first reference point 610 can be a value less than the midpoint between 0 and 1. Therefore, when the charge sharing operation is performed during the period when the SOE is high, the output (615) is charged to about 33% between 0 and 1 through the charge sharing operation and can become 1 during the period when the SOE is low. Therefore, in the above case, only when consuming the current corresponding to about 67% can the state become 1.

[0114] In addition, also during the VH period, even in SOUT3 where the change amount of the data is the smallest, since the charge sharing operation is performed among all channels in Figure 3 it can be seen that during the period when the SOE is high (625), the charge reaches the second reference point 620. Therefore, in this case, the SOE must fall back to 0 during the period when it becomes low (i.e., the period when the charge sharing operation ends), which reduces the efficiency.

[0115] On the other hand, referring to Figure 6 (b) of, during the VH period, the third reference point 650 in SOUT1 can be a value intermediate between 0 and 1 (as described above, higher or different reference values can be set in the case of using multiple bits instead of 1 bit). Thus, when the charge sharing operation is performed in the period when SOE is high, the output (655) is charged to approximately 50% of the range from 0 to 1 by the charge sharing operation and can become 1 in the period when SOE is low. Therefore, in this case, a current corresponding to approximately 50% of the current needs to be consumed, and thus the same effect can be obtained with a smaller current compared to Figure 6 (a) of.

[0116] In addition, also during the VH period, even if the change in the data in SOUT3 is minimal, since no charge sharing operation is performed between all channels in Figure 4 , it can be seen that during the period when SOE is high, the fourth reference point 660 can be equal to 0 (S625). Therefore, in this case, no additional power consumption is required because the output remains unchanged despite the change in SOE.

[0117] Referring to Figures 7 to 11 , a method of selectively controlling the charge sharing operation in the source driver (SDIC) 12 according to each data pattern will be described in detail. Hereinafter, for ease of explanation, an example will be given in which the charge sharing controller 410 can use the MSB (1 bit) of each latch unit in the corresponding channel and the adjacent channel having the same polarity.

[0118] First, Figure 7 shows the case where the data pattern is R. The values of the R (red) data pattern are as shown in Figure 7 (a) of. In Figure 7 (a) of, the numbers 1 - 6 represent channels, and 1H - 4H represent each horizontal period.

[0119] Referring to Figure 7 (b) of, at the top, the values of the first latch (first) 310 and the second latch (second) in each horizontal period (H) are provided according to the values of the R data pattern shown in Figure 7 (a) of.

[0120] According to the polarity, VH corresponds to the first, third, and fifth channels, and VL corresponds to the second, fourth, and sixth channels.

[0121] Regarding the VH period, the values of the second latch 320 and the first latch 310 in the first channel are (1, 0), (0, 1), (1, 0), (0, 1) in each horizontal period, the values of the second latch 320 and the first latch 310 in the third channel are (0, 0), (0, 0), (0, 0), (0, 0), and the values of the second latch 320 and the first latch 310 in the fifth channel are (0, 1), (1, 0), (0, 1), (1, 0) in each horizontal period.

[0122] For the first multiplexer 341 disposed between the first channel (corresponding channel) and the third channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than the threshold within each horizontal period.

[0123] For the second multiplexer 342 disposed between the third channel (corresponding channel) and the fifth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than the threshold within each horizontal period.

[0124] On the other hand, for the third multiplexer 343 disposed between the fifth channel (corresponding channel) and the first channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned on because the data value of each latch changes by more than the threshold within each horizontal period.

[0125] More specifically, the charge sharing controller 410 can control the execution of the charge sharing operation by activating the corresponding charge sharing unit (i.e., the multiplexer) because the data transition width in the corresponding horizontal period is greater than or equal to the threshold. In this case, the data values of the second latch 320 and the first latch 310 in the fifth channel (corresponding channel) are (0, 1), and the data values of the second latch 320 and the first latch 310 in the first channel (adjacent channel) are (1, 0).

[0126] In summary, in the VH period, when the data pattern is R, in Figure 3 the case of, all of the first multiplexer 341 to the third multiplexer 343 can be turned on, but in Figure 4 the case of, the first multiplexer 341 and the second multiplexer 342 can be turned off, and only the third multiplexer 343 can be turned on, thereby reducing the power consumption.

[0127] For the VL period, the charge sharing operation can be controlled in the same manner as the VH period, such that the fifth multiplexer 352 and the sixth multiplexer 353 can be turned off, and only the fourth multiplexer 351 can be turned on.

[0128] Therefore, even if only one multiplexer (the third multiplexer 343) in the VH period and one multiplexer (the fourth multiplexer 351) in the VL period are activated in the corresponding frame, the effect of the charge sharing operation is the same as that of the conventional charge sharing operation, while the power consumption can be reduced.

[0129] This can be applied to other groups of cells in the same way.

[0130] Next, Figure 8 The case where the data pattern is G (green) is shown. The values of the G data pattern are as Figure 8 shown in (a).

[0131] Referring to Figure 8 in (b), regarding the VH period, the values of the second latch 320 and the first latch 310 in the first channel are (0, 0), (0, 0), (0, 0), (0, 0) in each horizontal period, the values of the second latch 320 and the first latch 310 in the third channel are (0, 1), (1, 0), (0, 1), (1, 0) in each horizontal period, and the values of the second latch 320 and the first latch 310 in the fifth channel are (1, 0), (0, 1), (1, 0), (0, 1).

[0132] For the first multiplexer 341 provided between the first channel (the corresponding channel) and the third channel (the adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data values of each latch do not change by more than the threshold within each horizontal period.

[0133] On the other hand, for the second multiplexer 342 provided between the third channel (the corresponding channel) and the fifth channel (the adjacent channel), the charge sharing controller 410 can be controlled to be turned on because the data values of each latch change by more than the threshold within each horizontal period.

[0134] More specifically, the charge sharing controller 410 can control the execution of the charge sharing operation by activating the corresponding charge sharing unit (i.e., the multiplexer 342) because the data transition width in the corresponding horizontal period is greater than or equal to the threshold. In this case, the data values of the second latch 320 and the first latch 310 in the first channel (the corresponding channel) are (0, 1), and the data values of the second latch 320 and the first latch 310 in the third channel (the adjacent channel) are (1, 0).

[0135] On the other hand, for the third multiplexer 343 provided between the fifth channel (the corresponding channel) and the first channel (the adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data values of each latch do not change by more than the threshold within each horizontal period.

[0136] In summary, during the VH period, when the data mode is G, in the case of Figure 3 , all of the first multiplexer 341 to the third multiplexer 343 can be turned on, but in the case of Figure 4 , the first multiplexer 341 and the third multiplexer 343 can be turned off, and only the second multiplexer 342 can be turned on, thereby reducing power consumption.

[0137] For the VL period, the charge sharing operation can be controlled in the same manner as the VH period, such that the fourth multiplexer 351 and the fifth multiplexer 352 can be turned off, and only the sixth multiplexer 353 can be turned on.

[0138] Next, Figure 9 shows the case where the data mode is B (blue). The values of the B data mode are as shown in Figure 9 (a).

[0139] Referring to Figure 9 (b), regarding the VH period, the values of the second latch 320 and the first latch 310 in the first channel are (0, 1), (1, 0), (0, 1), (1, 0) in each horizontal period, the values of the second latch 320 and the first latch 310 in the third channel are (1, 0), (0, 1), (1, 0), (0, 1) in each horizontal period, and the values of the second latch 320 and the first latch 310 in the fifth channel are (0, 0), (0, 0), (0, 0), (0, 0).

[0140] For the first multiplexer 341 provided between the first channel (corresponding channel) and the third channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned on because the data values of each latch change by more than the threshold within each horizontal period.

[0141] More specifically, the charge sharing controller 410 can control the execution of the charge sharing operation by activating the corresponding charge sharing unit (i.e., the multiplexer 341) because the data transition width in the corresponding horizontal period is greater than or equal to the threshold. In this case, the data values of the second latch 320 and the first latch 310 in the first channel (corresponding channel) are (0, 1), and the data values of the second latch 320 and the first latch 310 in the third channel (adjacent channel) are (1, 0).

[0142] On the other hand, for the second multiplexer 342 provided between the third channel (corresponding channel) and the fifth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data values of each latch do not change by more than the threshold within each horizontal period.

[0143] For the third multiplexer 343 disposed between the fifth channel (corresponding channel) and the first channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0144] In summary, during the VH period, when the data pattern is B, Figure 3 in the case of Figure 4 the first multiplexer 341 to the third multiplexer 343 can all be turned on, but in the case of

[0145] the second multiplexer 342 and the third multiplexer 343 can be turned off, and only the first multiplexer 341 can be turned on, thereby reducing power consumption.

[0146] Next, Figure 10 the case where the data pattern is H bar is shown. The value of the H bar data pattern is as shown in Figure 10 (a) of

[0147] Referring to Figure 10 (b) of

[0148] For the first multiplexer 341 disposed between the first channel (corresponding channel) and the third channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0149] For the second multiplexer 342 disposed between the third channel (corresponding channel) and the fifth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0150] For the third multiplexer 343 disposed between the fifth channel (corresponding channel) and the first channel (adjacent channel), the charge sharing controller 410 can be controlled to turn off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0151] More specifically, the charge sharing controller 410 can control not to perform the charge sharing operation by deactivating the corresponding multiplexers (i.e., the multiplexers in all channels) because the value of each data in the corresponding channel and the adjacent channel in the VH period does not change and remains unchanged.

[0152] In summary, in the VH period, when the data pattern is H stripes, Figure 3 in the case of, the first multiplexer 341 to the third multiplexer 343 can all be turned on, but in Figure 4 in the case of, the first multiplexer 341 to the third multiplexer 343 can be turned off, thereby reducing power consumption.

[0153] For the VL period, the charge sharing operation can be controlled in the same manner as the VH period so that all the multiplexers 351 to 353 can be turned off.

[0154] Therefore, since there is no charge sharing effect in the VH / VL period for the H stripe data pattern in the corresponding frame, there is no need to perform the charge sharing operation. In the present disclosure, in the above cases, all charge sharing operations are deactivated, thereby avoiding unnecessary power consumption.

[0155] Finally, Figure 11 shows the case where the data pattern is a checkerboard. The values of the checkerboard data pattern are as Figure 11 shown in (a) of.

[0156] Referring to Figure 11 in (b) of, regarding the VH period, the values of the second latch 320 and the first latch 310 in the first channel are (0, 0), (0, 0), (0, 0), (0, 0) in each horizontal period, and the values of the second latch 320 and the first latch 310 in the third channel are (0, 0), (0, 0), (0, 0), (0, 0) in each horizontal period, and the values of the second latch 320 and the first latch 310 in the fifth channel are (1, 1), (1, 1), (1, 1), (1, 1).

[0157] For the first multiplexer 341 disposed between the first channel (corresponding channel) and the third channel (adjacent channel), the charge sharing controller 410 can be controlled to turn off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0158] For the second multiplexer 342 disposed between the third channel (corresponding channel) and the fifth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0159] For the third multiplexer 343 disposed between the fifth channel (corresponding channel) and the first channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold within each horizontal period.

[0160] In summary, during the VH period, when the data pattern is the checker, in Figure 3 cases, the first multiplexer 341 to the third multiplexer 343 can all be turned on, but in Figure 4 cases, the first multiplexer 341 to the third multiplexer 343 can be turned off, thus reducing the power consumption.

[0161] On the other hand, referring to Figure 11 (b) of, regarding the VL period, the values of the second latch 320 and the first latch 310 in the second channel are (0, 0), (0, 0), (0, 0), (0, 0) in each horizontal period, the values of the second latch 320 and the first latch 310 in the fourth channel are (1, 0), (0, 1), (1, 0), (0, 1) in each horizontal period, and the values of the second latch 320 and the first latch 310 in the sixth channel are (1, 1), (1, 1), (1, 1), (1, 1).

[0162] For the fourth multiplexer 351 disposed between the second channel (corresponding channel) and the fourth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned on because the data value of each latch does change by more than a threshold in the first horizontal period (1H) and the third horizontal period (3H).

[0163] For the fifth multiplexer 352 disposed between the fourth channel (corresponding channel) and the sixth channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold in the first horizontal period (1H) and the third horizontal period (3H).

[0164] For the sixth multiplexer 353 disposed between the sixth channel (corresponding channel) and the second channel (adjacent channel), the charge sharing controller 410 can be controlled to be turned off because the data value of each latch does not change by more than a threshold in the first horizontal period (1H) and the third horizontal period (3H).

[0165] In summary, during the VH period, when the data mode is the checker, in Figure 3 case, the fourth multiplexer 351 to the sixth multiplexer 353 can all be turned on, but in Figure 4 case, in some horizontal periods (1H, 3H), only the fourth multiplexer 351 can be turned off, and in other horizontal periods, the fifth multiplexer 352 and the sixth multiplexer 353 can be turned off, thereby reducing power consumption.

[0166] In addition, according to another embodiment of the present disclosure, even if no separate charge sharing controller 410 is provided between the second latch 320 and the processor 330, an effect similar to that of the above Figure 4 can be achieved.

[0167] For example, Figures 7 to 11 shows how to control the charge sharing operation in a group unit according to a specific data mode.

[0168] For example, in Figure 7 the case of the R data mode shown, during the VH period, only the third multiplexer 343 is activated, and the remaining multiplexers 341 and 342 are deactivated, and during the VL period, only the fourth multiplexer 351 is activated, and the remaining multiplexers 352 and 353 are deactivated.

[0169] In Figure 8 the case of the G data mode shown, during the VH period, only the second multiplexer 342 is activated, and the remaining multiplexers 341 and 343 are deactivated, and during the VL period, only the sixth multiplexer 353 is activated, and the remaining multiplexers 351 and 352 are deactivated.

[0170] In Figure 9 the case of the B data mode, during the VH period, only the first multiplexer 341 is activated, and the remaining multiplexers 342 and 343 are deactivated, and during the VL period, only the fifth multiplexer 352 is activated, and the remaining multiplexers 351 and 353 are deactivated.

[0171] In Figure 10 the case of the H bar data mode, all multiplexers are deactivated during the VH / VL period.

[0172] In Figure 11 the case of the checker data mode, all multiplexers are deactivated during the VH interval, but during the VL interval, only a part of the fourth multiplexer 351 is activated, and the remaining multiplexers 352 and 353 are deactivated.

[0173] Even without using a separate charge sharing controller 410, the controller of the source driver (SDIC) 12 can pre-identify the pattern of the image data input through the timing controller 14.

[0174] As described above, if the controller of the source driver (SDIC) 12 has identified the data pattern of the corresponding image data before or at the same time as inputting the image data into the latch of each channel, it can control the charge sharing operation using a preset value (i.e., any one of Figures 7 to 11 in response to the identified data pattern. However, in this case, as Figures 7 to 11 shown, it can be used in the case where the setting value for the charge sharing operation is stored in the memory based on a specific data pattern or a data pattern with pre-learned regularity or a preprocessing result.

[0175] For example, when the data pattern to be input into the latch of each channel is R, the controller of the source driver (SDIC) 12 can control the charge sharing operation by setting the third multiplexer 343 in the VH interval and the fourth multiplexer 351 in the VL interval.

[0176] According to at least one embodiment of the various embodiments of the present disclosure described above, when a predetermined data pattern is input, channels that satisfy a specific condition among the output channels having the same polarity within a unit channel during the horizontal blanking period are controlled to perform a charge sharing operation to reduce the amount of current consumption, thereby reducing the power consumption of the device.

[0177] The present disclosure can be applied to various display devices, including, for example, a notebook computer or a laptop computer employing a column inversion panel.

[0178] Although the present disclosure has been described above with respect to embodiments, those skilled in the art will readily understand that the present disclosure can be modified and changed in various ways without departing from the spirit and scope of the present disclosure outlined in the appended claims.

[0179] Industrial Applicability

[0180] The present disclosure relates to charge sharing and can be applied to various display devices including a laptop computer employing a column inversion panel, and thus has industrial applicability.< / n> < / n>

Claims

1. A source driver, the source driver comprising: A first latch unit configured to store first image data for each channel; A second latch unit configured to store second image data input through the first latch unit; A charge sharing controller configured to: For a target channel among channels with the same polarity, obtain a first predefined bit of the first image data of the first latch unit and a second predefined bit of the second image data of the second latch unit, For adjacent channels, obtain a third predefined bit of the first image data of the first latch unit and a fourth predefined bit of the second image data of the second latch unit, and Generate and output a multiplexer operation control signal according to a determination based on data changes of the obtained first predefined bit to the fourth predefined bit; And A multiplexer configured to perform a charge sharing operation according to the output multiplexer operation control signal.

2. The source driver according to claim 1, wherein The charge sharing controller is configured to group a preset number of channels among the channels and generate the multiplexer operation control signal for the grouped channels.

3. The source driver according to claim 2, wherein, The multiplexer is disposed between the target channel and an adjacent channel among channels having the same polarity as the target channel.

4. The source driver according to claim 3, wherein, The charge sharing controller is configured to: Generate the multiplexer operation control signal for the multiplexer to perform the charge sharing operation only when the difference between the predefined bit of the second image data of the second latch unit received for a predetermined channel and the predefined bit of the first image data of the first latch unit received is greater than or equal to a threshold, and the difference between the predefined bit of the second image data of the second latch unit received for the adjacent channel of the predetermined channel and the predefined bit of the first image data of the first latch unit received is greater than the threshold.

5. The source driver according to claim 4, wherein, Whether the difference between the predefined bits of the image data of each latch unit of each channel is greater than or equal to the threshold is determined as a change in the data value of the corresponding bit from 0 to 1 or from 1 to 0.

6. The source driver according to claim 4, wherein Whether the difference between the predefined bits of the image data of each latch unit of each channel is greater than or equal to the threshold is determined as a difference in the value of the output channel after the charge sharing operation and the value of the output channel before the charge sharing operation.

7. The source driver according to claim 1, wherein, The charge sharing controller is configured to: Generate an operation control signal for each multiplexer disposed in a unit channel according to the determination of the data change, and Wherein, the operation control signal does not include an operation control signal for controlling all multiplexers in the unit channel to operate.

8. The source driver according to claim 1, wherein, The charge sharing controller is configured to generate an operation control signal for all multiplexers in a unit channel according to the determination of the data change, and Wherein, the operation control signal includes an operation control signal for controlling all multiplexers in the unit channel not to operate.

9. The source driver according to claim 1, wherein, The adjacent channel is one of the channels having the same polarity as the target channel.

10. The source driver according to claim 1, wherein, The first to fourth predefined bits include the most significant bit (MSB) of each image data of each channel.

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