Non-volatile memory with loop dependent ramp-up rate

Abstract

A non-volatile memory system is configured to program a non-volatile memory cell by applying a plurality of programs to the memory cell and performing a program-verify operation after each program. Each program and the corresponding program-verify operation after that program are referred to as a program loop. The program-verify operation includes applying a verify reference voltage to a selected word line and applying an overdrive voltage to an unselected word line. To reduce the amount of current used, a memory system includes a loop-dependent reduction of a ramp-up rate of an overdrive voltage applied to an unselected word line during program-verify.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 357,339, filed on July 24, 2023, entitled "NON - VOLATILE MEMORY WITH LOOP DEPENDANT RAMP - UP RATE", and hereby incorporates by reference in its entirety for all purposes the entire content of that application, which claims the priority of U.S. Provisional Application No. 63 / 479,409, filed on January 11, 2023. Background of the Disclosure

[0003] This disclosure relates to non - volatile memory.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid - state drives, non - mobile computing devices, and other devices. Semiconductor memories can include non - volatile memories or volatile memories. Non - volatile memories allow the storage and retention of information even when not connected to a power source (e.g., a battery). An example of a non - volatile memory is flash memory (e.g., NAND - type and NOR - type flash memories).

[0005] Many electronic devices that use non - volatile memory are battery - powered mobile devices. Therefore, to most effectively use the battery, it is advantageous for non - volatile memories to operate at lower power (including using lower current). The use of lower current also helps prevent overheating of the electronics. Brief Description of the Drawings

[0006] Elements with the same reference numerals represent common components in different drawings.

[0007] Figure 1 is a block diagram depicting an embodiment of a storage system.

[0008] Figure 2A is a block diagram of an embodiment of a memory die.

[0009] Figure 2B is a block diagram of an embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B depict different embodiments of an integrated memory component.

[0011] Figure 4 is a perspective view of a part of an embodiment of a monolithic three - dimensional memory structure.

[0012] Figure 4A It is a block diagram of an embodiment of a memory structure having two planes.

[0013] Figure 4B It depicts a top view of a portion of an embodiment of a block of memory cells.

[0014] Figure 4C It depicts a cross-sectional view of a portion of an embodiment of a block of memory cells.

[0015] Figure 4D It depicts a cross-sectional view of a portion of an embodiment of a block of memory cells.

[0016] Figure 4E It is a cross-sectional view of an embodiment of a vertical column of memory cells.

[0017] Figure 4F It is a schematic diagram of multiple NAND strings in multiple regions of the same block.

[0018] Figure 5A It depicts a threshold voltage distribution.

[0019] Figure 5B It depicts a threshold voltage distribution.

[0020] Figure 5C It depicts a threshold voltage distribution.

[0021] Figure 5D It depicts a threshold voltage distribution.

[0022] Figure 6 It is a flowchart of an embodiment describing a process for programming a non-volatile memory.

[0023] Figure 7 It depicts a voltage signal applied to a select word line during programming.

[0024] Figure 8A It depicts two programming voltage pulses and a verification voltage pulse between the two programming voltage pulses applied to a select word line during programming.

[0025] Figure 8B It depicts two programming voltage pulses and a verification voltage pulse between the two programming voltage pulses applied to a select word line during programming.

[0026] Figure 9 It is a block diagram of an embodiment of a system for supplying voltage to a word line.

[0027] Figure 10is a timing diagram depicting the voltages applied to a NAND string during a program-verify process.

[0028] Figure 11 Includes graphs of word line voltage and system current.

[0029] Figure 12 is a flow chart that depicts one embodiment of a process for configuring a memory to include a reduced loop dependence of a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0030] Figure 13 is a flow chart that depicts one embodiment of a process for programming memory cells, including a reduced loop dependence of a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0031] Figure 14 is a flow chart that depicts one embodiment of a process for programming memory cells, including a reduced loop dependence of a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0032] Figure 15A is a table for configuring a start program loop to reduce a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0033] Figure 15B is a table for configuring a program loop to end a reduction of a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0034] Figure 16 is a flow chart that depicts one embodiment of a process for programming memory cells, including a reduced loop dependence of a slew rate of an overdrive voltage applied to unselected word lines during program-verify.

[0035] Figure 17 is a flow chart that depicts one embodiment of a process for programming memory cells, including a reduced loop dependence of a slew rate of an overdrive voltage applied to unselected word lines during program-verify, such that loops for reducing the slew rate are adjusted / customized for different word lines. Detailed Description

[0036] A non - volatile memory system is configured to program non - volatile memory cells by applying multiple doses of programming to the memory cells and performing a program - verify operation after each programming. Each programming and the corresponding program - verify operation after that programming are referred to as a program cycle. The program - verify operation includes applying a verify reference voltage to a selected word line and an over - drive voltage to an unselected word line. To reduce the amount of current used, the memory system includes a reduction in the cycle - dependence of the ramp rate of the over - drive voltage applied to unselected word lines during program - verify.

[0037] Figure 1 is a block diagram of an embodiment of a storage system 100 that implements the proposed techniques described herein. In one embodiment, the storage system 100 is a solid - state drive (“SSD”). The storage system 100 can also be a memory card, a USB drive, or other types of storage systems. The proposed techniques are not limited to any one type of memory system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet, or other mobile device), an appliance, or another device that uses memory and has data - processing capabilities. In some embodiments, the host 102 is separate from, but connected to, the storage system 100. In other embodiments, the storage system 100 is embedded within the host 102.

[0038] Figure 1 The components of the storage system 100 depicted in are circuits. The storage system 100 includes a memory controller 120 connected to a non - volatile memory 130 and a local high - speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high - speed volatile memory 140 to perform certain functions. For example, the local high - speed volatile memory 140 stores a logical - to - physical address translation table (“L2P table”).

[0039] The memory controller 120 includes a host interface 152 that is connected to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) over PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use non-clock asynchronous logic. NOC technology applies networking theory and methods to on-chip communication and brings significant improvements compared to conventional buses and crossbar interconnections. Compared to other designs, the NOC improves the scalability of a system-on-chip (SoC) and the power efficiency of complex SoCs. Many signals share the lines and links of the NOC. Because all links in the NOC can operate on different data packets simultaneously, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with the NOC 154. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 may be SRAM or other types of volatile memory.

[0040] The ECC engine 158 performs error correction services. For example, according to the implemented ECC technology, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is a circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0041] The processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is custom and dedicated hardware circuitry without any software. The processor 156 also implements the translation module as a software / firmware process or dedicated hardware circuitry. In many systems, the non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to allocate data to contiguous logical addresses while the storage system is free to store the data it desires between the locations of one or more memory dies. To implement this system, the memory controller 120 (e.g., the translation module) performs the address translation between the logical addresses used by the host and the physical addresses used by the memory die. An exemplary implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current translation between logical addresses and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Although the logical address to physical address table (or L2P table) includes the word "table", they are not necessarily really tables. Instead, the logical address to physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables in the L2P table. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0042] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switching mode interface. Other interfaces can also be used. In some exemplary implementations, the memory interface 160 (or another part of the controller 120) implements a scheduler and buffers for sending data to and receiving data from one or more memory dies.

[0043] In one embodiment, the non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of the memory die 200 that includes the non-volatile memory 130. Each of the one or more memory dies in the non-volatile memory 130 can be implemented as Figure 2A the memory die 200. Figure 2AThe components depicted in [description] are a circuit. Memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include layers of word lines organized in rows and layers of bit lines organized in columns. However, other orientations may also be implemented. Memory die 200 includes row control circuitry 220, the output 208 of which is connected to corresponding word lines of memory array 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic circuitry 260 and typically may include circuitry such as row decoder 222, array terminal driver 224, and block selection circuitry 226 for read and write (programming) operations. Row control circuitry 220 may also contain read / write circuitry. Memory die 200 further includes column control circuitry 210, which includes sense amplifiers 230, the input / output 206 of which is connected to corresponding bit lines of memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that may be accessed separately. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260 and typically may include circuitry such as column decoder 212, array terminal receiver or driver circuitry 214, block selection circuitry 216, and read / write circuitry and I / O multiplexer.

[0044] System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, state machine 262 may be programmed by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor located on or off the memory chip. System control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of memory structure 202 during memory operations and may include charge pumps and regulator circuitry for generating regulated voltages. System control logic 262 includes a storage 366 (e.g., RAM, registers, latches, etc.) that may be used to store parameters for operating memory array 202.

[0045] Commands and data are transferred between the memory controller 120 and the memory die 200 via the memory controller interface 268 (also referred to as the “communication interface”). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a toggle mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0046] In some embodiments, all elements of the memory die 200, including the system control logic 260, may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies.

[0047] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may include any type of non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active regions disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings having charge trapping layers.

[0048] In another embodiment, the memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0049] The exact type of memory array architecture or memory cells included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies may be used to form the memory structure 202. For the purposes of the novel claimed embodiments presented herein, no particular non-volatile memory technology is required. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architectures of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0050] An example of a ReRAM cross-point memory includes reversible resistive switching elements arranged in a cross-point array, which is accessed by X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization cell. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one being relatively inert (e.g., tungsten), and the other being electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, resulting in a decrease in the programming threshold of the conductive bridge memory cell. Thus, the conductive bridge memory element can have a wide range of programming thresholds over a temperature range.

[0051] Another example is a magnetoresistive random access memory (MRAM) that stores data using magnetic storage elements. These elements are formed by two ferromagnetic layers, each of which can maintain magnetization and is separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match an external field to store memory. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other and parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. Memory embodiments based on MRAM will be discussed in more detail below.

[0052] Phase change memory (PCM) utilizes the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms with a laser pulse (or an optical pulse from another source). Thus, the multiple programming is the laser pulse. The memory cell can be prohibited by preventing it from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. Note that the "pulse" used herein does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage light, or another wave. These memory elements within individual selectable memory cells or bits may include another series element as a selector, such as a two-way threshold switch or a metal-insulator substrate.

[0053] One of ordinary skill in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather encompass many related memory structures within the spirit and scope of the techniques described herein, as understood by one of ordinary skill in the art.

[0054] Figure 2AThe components can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral circuit, which includes all of the components among the other components described in Figure 2A All of the components in Figure 2A . An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of the memory die of the memory system 100 for the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuit. This can impose rather stringent limitations on these components of the peripheral circuit. For example, the need to fit a sense amplifier circuit within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic 260, the reduced area availability can limit the available functions that can be implemented on the chip. Thus, in the design of the memory die of the memory system 100, a fundamental trade-off is required between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuit.

[0055] Another aspect where the memory structure 202 and the peripheral circuit often conflict is the processing involved in forming these regions, as these regions often involve different processing techniques and the trade-offs of using different techniques on a single die. For example, when the memory structure 202 is a NAND flash memory, which is an NMOS structure, while the peripheral circuit is typically CMOS-based. For example, components such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 260 typically employ PMOS devices. The processing operations for fabricating a CMOS die will differ in many respects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

[0056] To improve these limitations, the embodiments described below can Figure 2AThe components are separated onto individually formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements including one or more control circuits can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only of memory elements, such as an array of memory cells of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the peripheral circuits, even including elements such as decoders and sense amplifiers, can be moved to a separate control die. This allows each memory die in the memory die to be optimized separately according to its technology. For example, the NAND memory die can be optimized for an NMOS-based memory array structure without worrying about the CMOS elements that have now been moved to the control die that can be optimized for CMOS processing. This provides more space for the peripheral elements, enabling these peripheral elements to now incorporate additional capabilities that could not be easily incorporated if these peripheral elements were restricted to the edges of the same die holding the memory cell array. Then, these two dies can be bonded together in a multi-die memory circuit, where the array on one die is connected to the peripheral elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more dies, such as for example two memory dies and one control die.

[0057] Figure 2B is shown Figure 2A an alternative arrangement of which can be implemented using wafer-to-wafer bonding to provide a pair of bonded dies. Figure 2B FIG. depicts a functional block diagram of one embodiment of an integrated memory component 207. One or more integrated memory components 207 can be used to implement the non-volatile memory 130 of the storage system 100. The integrated memory component 207 includes two types of semiconductor dies (or more simply, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to be connected to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0058] Figure 2B FIG. shows an example of a peripheral circuit, including control circuits formed in the peripheral circuit or the control die 211, the peripheral circuit or the control die being coupled to the memory structure 202 formed in the memory die 201. Common components are in a similar manner to Figure 2Amarked in the manner of. The system control logic 260, row control circuit 220, and column control circuit 210 are located in the control die 211. In some embodiments, all or part of the column control circuit 210 and all or part of the row control circuit 220 are located on the memory die 201. In some embodiments, some of the circuits in the system control logic 260 are located on the memory die 201.

[0059] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by a common process (e.g., a CMOS process) such that adding elements and functions (such as ECC) that are typically present on the memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate the controller 120 can also be used to fabricate the system control logic 260, row control circuit 220, and column control circuit 210). Thus, although moving such circuits from a die such as the memory die 201 can reduce the number of steps required to fabricate such a die, adding such circuits to a die such as the control die 211 may not require many additional process steps. Since CMOS technology is used to implement some or all of the control circuits 260, 210, 220, the control die 211 may also be referred to as a CMOS die.

[0060] Figure 2B The column control circuit 210 including the sense amplifier 230 on the control die 211 is shown, and the control die is coupled to the memory structure 202 on the memory die 201 through the circuit path 206. For example, the circuit path 206 may provide an electrical connection between the column decoder 212, driver circuit 214, and block selection 216 and the bit lines of the memory structure 202. The circuit path may extend from the column control circuit 210 in the control die 211 through pads on the control die 211, and these pads are bonded to corresponding pads on the memory die 201, and these corresponding pads are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding circuit path in the circuit path 206, including a pair of bonding pads connected to the column control circuit 210. Similarly, the row control circuit 220 including the row decoder 222, array driver 224, and block selection 226 is coupled to the memory structure 202 through the circuit path 208. Each circuit path in the circuit path 208 may correspond to a word line, a dummy word line, or a select gate line. Additional circuit paths may also be provided between the control die 211 and the memory die 201.

[0061] For the purposes of this disclosure, the phrase "control circuit" or "one or more control circuits" may include any one or any combination of a memory controller 120, a state machine 262, all or a portion of the system control logic 260, all or a portion of the row control circuit 220, all or a portion of the column control circuit 210, a microcontroller, a microprocessor, and / or other similar functional circuits. The control circuit may consist of only hardware or may include a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit may include a processor, an FGA, an ASIC, an integrated circuit, or other types of circuits.

[0062] In some embodiments, there are more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A A side view of an embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0063] Each control die 211 is fixed (e.g., bonded) to at least one of the memory dies 201 in the memory die. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of an epoxy resin or other resin or polymer. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials may be used as the solid layer 280, but in an embodiment, it may be Hysol epoxy resin from Henkel Corp. (which has an office in California, USA).

[0064] The integrated memory component 207 may be stacked, for example, in a stepped offset such that the bonding pads of each layer are not covered and are accessible from above. Wire bonds 270 connected to the bonding pads connect the control dies 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., into Figure 3A the page).

[0065] Memory die through-silicon vias (TSVs) 276 can be used to route signals through memory die 201. Control die through-silicon vias (TSVs) 278 can be used to route signals through control die 211. TSVs 276, 278 can be formed before, during, or after the formation of integrated circuits in semiconductor dies 201, 211. TSVs can be formed by etching holes through the wafer. These holes can then be lined with a barrier to prevent metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with a conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and their alloys or combinations can also be used.

[0066] Bonding balls 272 can optionally be fixed to contact pads 274 on the lower surface of substrate 271. Bonding balls 272 can be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Bonding balls 272 can be omitted in the case where integrated memory component 207 is to be used as an LGA package. Bonding balls 272 can form part of the interface between integrated memory component 207 and memory controller 120.

[0067] Figure 3B A side view of another embodiment of integrated memory component 207 stacked on substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are far more than three memory dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, controller die 211 can be bonded to two or more memory dies 201.

[0068] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy resin or other resin or polymer. Compared to Figure 3A the example in Figure 3B the integrated memory component 207 in

[0069] Memory die through-silicon vias (TSVs) 276 can be used to route signals through memory die 201. Control die through-silicon vias (TSVs) 278 can be used to route signals through control die 211.

[0070] As briefly discussed above, the control die 211 and the memory die 201 may be bonded together. Bonding pads on each of the dies 201, 211 may be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additive materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment that is substantially free of environmental particulates that could otherwise deposit on the bonding pads and prevent a tight bond. Under such appropriately controlled conditions, the bonding pads are aligned and pressed against each other to form a mutual bond based on surface tension. This bond may be formed at room temperature, but may also be heated. In embodiments using Cu-Cu bonding, the bonding pads may be approximately 5 μm square and spaced from each other by a pitch of 5 μm to 5 μm. Although the process is referred to herein as Cu-Cu bonding, the term may also apply to cases where the bonding pads are formed of materials other than Cu.

[0071] When the area of the bonding pads is small, it may be difficult to bond semiconductor dies together. By providing a film layer on the surface of the semiconductor die including the bonding pads, the size and pitch of the bonding pads can be further reduced. The thin film layer is provided around the bonding pads. When the dies are placed together, the bonding pads may be bonded to each other, and the film layers on the corresponding dies may be bonded to each other. This bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bonding pads may be approximately 5 μm square and spaced from each other by a pitch of 1 μm to 5 μm. Bonding techniques may be used to provide bonding pads with even smaller (or larger) sizes and pitches.

[0072] Some embodiments may include a film on the surface of the dies 201, 211. In cases where such a film is not initially provided, the space between the dies may be underfilled with epoxy resin or other resin or polymer. The underfill material may be applied as a liquid, which then hardens into a solid layer. This underfill step protects the electrical connections between the dies 201, 211 and further secures the dies together. Various materials may be used as the underfill material, but in an embodiment, it may be Hysol epoxy resin from Henkel Corporation (which has an office in California, USA).

[0073] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202, the memory structure including a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4Shows a portion 400 of a block of memory. The depicted structure includes a set of bit lines BL located above a stack 401 of alternating dielectric and conductive layers. For example, one of the dielectric layers in the dielectric layer stack is labeled D, and one of the conductive layers (also known as the word line layer) in the conductive layer stack is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into four or five (or a different number of) regions by isolation regions IR. Figure 4 Shows an isolation region IR separating two regions. Below the alternating dielectric and word line layers is the source line layer SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, one of the memory holes is labeled MH. Note that in Figure 4 , the dielectric layer is depicted in a perspective view so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with a material including charge trapping material to create vertical columns of memory cells. Each memory cell can store one or more bits of data. Thus, non-volatile memory cells are arranged in the memory holes. More details of a three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0074] Figure 4A Is a block diagram explaining an exemplary organization of the memory structure 202 divided into two planes 402 and 404. Then each plane is divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is the erase unit. That is, all the memory cells in a block are erased together. In other embodiments, a block can be divided into sub-blocks, and the sub-blocks can be the erase units. For other reasons, memory cells can also be grouped into blocks, such as organizing the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a set of connected memory cells because the memory cells in a block share a common set of word lines. For example, the word lines of a block are all connected to all the vertical NAND strings in the vertical NAND strings of that block. Although Figure 4A Shows two planes 402 / 404, but more or fewer than two planes can be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0075] Figures 4B to 4 G depicts the structure corresponding to Figure 4 and can be used to implement Figure 2A and Figure 2B of the memory structure 202 of an exemplary three-dimensional (“3D”) NAND structure. Figure 4B Is a block diagram depicting a top view of a portion 406 of block 2 of plane 402. FromFigure 4B It can be seen that Figure 4B the blocks depicted extend in the direction of 432. In one embodiment, the memory array has a number of layers; however, Figure 4B only the top layer is shown.

[0076] Figure 4B A number of circles representing memory holes, also referred to as vertical columns, are depicted. Each memory hole / vertical column in the memory holes / vertical columns includes a number of select transistors (also referred to as select gates) and a number of memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, Figure 4B a subset of memory holes / vertical columns / NAND strings 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0077] Figure 4B A set of bit lines 415 is also depicted, including bit lines 411, 412, 413, 414,..., 419. Figure 4B Twenty-four bit lines are shown as only a part of the block is depicted. More than twenty-four bit lines can be considered to be connected to the memory holes / vertical columns of the block. Each circle in the circles representing the memory holes / vertical columns has an "x" to indicate its connection to a bit line. For example, bit line 411 is connected to memory holes / vertical columns 436, 446, 456, 466, and 476.

[0078] Figure 4B The block depicted in includes a set of isolation regions 482, 484, 486, and 488, which are formed of SiO2; however, other dielectric materials can also be used. The isolation regions 482, 484, 486, and 488 are used to divide the top layer of the block into five regions; for example, Figure 4B the top layer depicted in is divided into regions 430, 440, 450, 460, and 470. In one embodiment, the isolation regions only divide the layer for implementing the select gates such that the NAND strings in different regions can be independently selected. In an exemplary implementation, the bit lines are connected to one memory hole / vertical column / NAND string in each of the regions 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four active columns per row, and each bit line is connected to five rows in each block. In one embodiment, all the memory holes / vertical columns / NAND strings in the five memory holes / vertical columns / NAND strings connected to a common bit line are connected to the same set of word lines; thus, the system uses drain side select lines to select one memory hole / vertical column / NAND string (or another subset) from these five memory holes / vertical columns / NAND strings for memory operations (programming, verifying, reading, and / or erasing).

[0079] Figure 4BAlso shown is a wire interconnect LI, which is a metal connection from above the memory array to the source line SL. The wire interconnect LI is located near regions 430 and 470.

[0080] Although Figure 4B it is shown that each of regions 430, 440, 450, 460, and 470 has four rows of memory holes / vertical columns, and it is shown that there are five regions and twenty-four rows of memory holes / vertical columns in a block, these exact numbers are an exemplary specific implementation. Other embodiments may include more or fewer regions per block, more or fewer rows of memory holes / vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B Also shown are staggered memory holes / vertical columns. In other embodiments, different staggering patterns may be used. In some embodiments, the memory holes / vertical columns are not staggered.

[0081] Figure 4C Depicted is a portion of one embodiment of a three-dimensional memory structure 202, which shows a cross-sectional view along Figure 4B line AA. This cross-sectional view passes through the memory holes / vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4C The structure includes three drain-side select layers SGD0, SGD1, and SGD2; three source-side select layers SGS0, SGS1, and SGS2; three drain-side GIDL generation transistor layers SGDT0, SGDT1, and SGDT2; three source-side GIDL generation transistor layers SGSB0, SGSB1, and SGSB2; four drain-side dummy word line layers DD0, DD1, DD2, and DD3; four source-side dummy word line layers DS0, DS1, DS2, and DS3; dummy word line layers DU and DL; one hundred and sixty-two word line layers WL0 - WL161 for connecting data memory cells, and a dielectric layer DL. Other embodiments may implement a greater or lesser number than that described above for Figure 4C . In one embodiment, SGD0, SGD1, and SGD2 are connected together; and SGS0, SGS1, and SGS2 are connected together. In other embodiments, a greater or lesser number of SGDs (more or less than three) are connected together, and a greater or lesser number of SGSs (more or less than three) are connected together.

[0082] In one embodiment, gate-induced drain leakage (GIDL) is used to perform erasing of memory cells, which includes generating charge carriers at the GIDL generation transistors such that the carriers are injected into the charge trapping layer of the NAND string to change the threshold voltage of the memory cell. Figure 4CThree GIDL generating transistors are shown at each end of the NAND string; however, in other embodiments, there are more or fewer than three GIDL generating transistors. Embodiments using GIDL at both sides of the NAND string may have GIDL generating transistors at both sides. Embodiments using GIDL at only the drain side of the NAND string may have GIDL generating transistors only at the drain side. Embodiments using GIDL at only the source side of the NAND string may have GIDL generating transistors only at the source side.

[0083] Figure 4C Three GIDL generating transistors are shown at each end of the NAND string. Charge carriers are likely generated only by GIDL at one of the three GIDL generating transistors at each end of the NAND string. Due to process variations during manufacturing, one of the three GIDL generating transistors at one end of the NAND string is likely to be most suitable for GIDL. For example, the GIDL generating transistor has a mutant pn junction to generate charge carriers for GIDL, and during manufacturing, phosphorus diffusion is performed at the polysilicon channel of the GIDL generating transistor. In some cases, the GIDL generating transistor with the shallowest phosphorus diffusion is the GIDL generating transistor that generates charge carriers during erasure. However, in some embodiments, charge carriers may be generated by GIDL at multiple GIDL generating transistors at a particular side of the NAND string.

[0084] Storage holes / vertical columns 472 and 474 are depicted as protruding through the drain side select layer, source side select layer, dummy word line layer, GIDL generating transistor layer, and word line layer. In one embodiment, each storage hole / vertical column includes a vertical NAND string. Below the storage holes / vertical columns and the layers listed below are substrate 453, insulating film 454 on the substrate, and source line SL. The NAND string of storage hole / vertical column 472 has a source end at the bottom of the stack and a drain end at the top of the stack. Consistent with Figure 4B one Figure 4C a vertical storage hole / column 472 connected to bit line 414 via connector 417 is shown.

[0085] For ease of reference, the drain-side select layer; the source-side select layer, the dummy word line layer, the GIDL generation transistor layer, and the data word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten), metal silicides (such as nickel silicide, tungsten silicide, aluminum silicide), or combinations thereof. In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is the dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0086] Non-volatile memory cells are formed along memory holes / vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged as NAND strings. The word line layers WL0-W161 are connected to the memory cells (also referred to as data memory cells). The dummy word line layer is connected to dummy memory cells. Dummy memory cells do not store and are not eligible to store host data (data provided by the host, such as user data from the host), while data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain-side select layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND strings to the bit lines. The source-side select layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND strings to the source line SL.

[0087] Figure 4C A memory array is shown implemented as a two-layer architecture, where the layers are separated by a bonding region. In one embodiment, etching so many word line layers that are intermixed with the dielectric layer is expensive and / or challenging. To alleviate this burden, one embodiment includes laying a first stack of alternating word line layers (e.g., WL0-WL80) and dielectric layers, laying a bonding region, and laying a second stack of alternating word line layers (e.g., WL81-WL161) and dielectric layers. The bonding region is located between the first stack and the second stack. In one embodiment, the bonding region is made of the same material as the word line layer. In other embodiments, there may be no bonding region, or there may be multiple bonding regions.

[0088] Figure 4D Depicts a portion of an embodiment of a three-dimensional memory structure 202, which shows a cross-sectional view along Figure 4B line BB. The cross-sectional view passes through the memory holes / vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4D Shows associated with Figure 4CIdentical alternating conductive and dielectric layers. Figure 4D Also shown are isolation regions 482. Isolation regions 482, 484, 486, and 488 occupy space that would otherwise be used for a portion of the storage holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that would otherwise be used for a portion of storage hole / vertical column 434. More specifically, a portion (e.g., half of the diameter) of vertical column 434 has been removed in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1, and DD2 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (having a circular cross-section), the portion of vertical column 434 in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1, and DD2 has a semi-circular cross-section. In one embodiment, after forming the stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation regions, and then the space is filled with SiO2.

[0089] Figure 4E A cross-sectional view of Figure 4C region 429 is depicted that includes a portion of storage hole / vertical column 472. In one embodiment, the storage hole / vertical column is circular; however, in other embodiments, other shapes may be used. In one embodiment, storage hole / vertical column 472 includes a core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that channel 491 is connected to the bit line and the source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0090] Figure 4EDepicts a dielectric layer DL and word line layers WL160, WL159, WL158, WL157, and WL156. Each word line layer in the word line layers includes a word line region 496 surrounded by an alumina layer 497, and the alumina layer is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction between the word line layer and the vertical column forms a memory cell. Thus, in one embodiment, a memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a blocking oxide layer 498, an alumina layer 497, and a word line region 496. For example, the word line layer WL160 and a part of the memory hole / vertical column 472 include a memory cell MC1. The word line layer WL159 and a part of the memory hole / vertical column 472 include a memory cell MC2. The word line layer WL158 and a part of the memory hole / vertical column 472 include a memory cell MC3. The word line layer WL157 and a part of the memory hole / vertical column 472 include a memory cell MC4. The word line layer WL156 and a part of the memory hole / vertical column 472 include a memory cell MC5. In other architectures, the memory cell may have a different structure; however, the memory cell will still be a storage unit.

[0091] When the memory cell is programmed, electrons are stored in the part of the charge trapping layer 493 associated with (e.g., within) the memory cell. In response to an appropriate voltage on the word line region 496, these electrons are drawn from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases proportionally to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, the electrons return to the channel, or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erase is achieved by injecting holes into the charge trapping layer via a physical mechanism such as GIDL.

[0092] Figure 4F is Figures 4 to 4E A schematic diagram of a part of the memory array 202 depicted in Figure 4F Shows the physical data word lines WL0 - WL161 across the entire block. Figure 4F The structure corresponds to Figure 4A Part 406 in block 2 of , including bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings. Thus, Figure 4FShows bit lines connected to NAND string NS0 (which corresponds to memory hole / vertical column 436), NAND string NS1 (which corresponds to memory hole / vertical column 446), NAND string NS2 (which corresponds to vertical column 456), NAND string NS3 (which corresponds to memory hole / vertical column 466), and NAND string NS4 (which corresponds to memory hole / vertical column 476). As mentioned above, in one embodiment, SGD0, SGD1, and SGD2 are connected together to operate as a single logical select gate for each region separated by isolation regions (482, 484, 486, and 486), thereby forming SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4. SGS0, SGS1, and SGS2 are also connected together to operate as a single logical select gate, which is represented as SGS in Figure 4F . Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are isolated from each other due to the isolation regions, the data word lines WL0-WL161 of each region are connected together. Thus, the data word lines WL0-WL161 are connected to the NAND strings (and memory cells) of each (or every) region (430, 440, 450, 460, 470) of the block.

[0093] The isolation regions (482, 484, 486, and 486) are used to allow separate control of regions 430, 440, 450, 460, 470. The first region corresponds to those vertical NAND strings controlled by SGD-s0. The second region corresponds to those vertical NAND strings controlled by SGD-s1. The third region corresponds to those vertical NAND strings controlled by SGD-s2. The fourth region corresponds to those vertical NAND strings controlled by SGD-s3. The fifth region corresponds to those vertical NAND strings controlled by SGD-s4.

[0094] Figure 4F Only the NAND strings connected to bit line 411 are shown. However, a complete schematic of the block would show each bit line and the five vertical NAND strings (which are in separate regions) connected to each bit line.

[0095] Although Figures 4 to 4F the exemplary memory is a three-dimensional memory structure including vertical NAND strings having charge trapping material, other (2D and 3D) memory structures may also be used with the techniques described herein.

[0096] The storage system discussed above can be erased, programmed, and read. At the end of a successful programming process, depending on the situation, the threshold voltage of the memory cell should be within one or more threshold voltage distributions of the programmed memory cell, or within the threshold voltage distribution of the erased memory cell. Figure 5Ais a graph of threshold voltage and number of memory cells and shows an exemplary threshold voltage distribution of a memory array when each memory cell stores one bit of data per memory cell. A memory cell storing one bit of data per memory cell is referred to as a single-level cell (“SLC”). The data stored in an SLC memory cell is referred to as SLC data; thus, SLC data includes one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Shows two threshold voltage distributions: E and P. The threshold voltage distribution E corresponds to the erased data state. The threshold voltage distribution P corresponds to the programmed data state. Thus, memory cells having threshold voltages in the threshold voltage distribution E are in the erased data state (e.g., they are erased). Thus, memory cells having threshold voltages in the threshold voltage distribution P are in the programmed data state (e.g., they are programmed). In one embodiment, the erased memory cells store data “1” and the programmed memory cells store data “0”. Figure 5A Depicts a read reference voltage Vr. By testing whether the threshold voltage of a given memory cell is higher or lower than Vr (e.g., performing one or more sensing operations), the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicts a verify reference voltage Vv. In some embodiments, when programming memory cells to the data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv.

[0097] Figure 5B -D shows an exemplary threshold voltage distribution of a memory array when each memory cell stores multiple bits of data per memory cell. A memory cell storing multiple bits of data per memory cell is referred to as a multi-level cell (“MLC”). The data stored in an MLC memory cell is referred to as MLC data; thus, MLC data includes multiple bits per memory cell. Data stored as multiple bits per memory cell is MLC data. In Figure 5B the exemplary embodiment, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell).

[0098] Figure 5B Shows a first threshold voltage distribution E of erased memory cells. Also depicts three threshold voltage distributions A, B, and C of programmed memory cells. In one embodiment, the threshold voltages in distribution E are negative while the threshold voltages in distributions A, B, and C are positive. Figure 5BEach different threshold voltage distribution corresponds to a predetermined value of the set of data bits. In one embodiment, each of the two bits of data stored in a memory cell is located in a different logical page referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are located in a common logical page. The specific relationship between the data programmed into a memory cell and the threshold voltage level of that cell depends on the data encoding scheme employed for those cells. Table 1 provides an example encoding scheme.

[0099] Table 1

[0100] E A B C LP 1 0 0 1 UP 1 1 0 0

[0101] In one embodiment referred to as full sequence programming, a Figure 6 process can be used to program a memory cell directly from an erased data state E to any one of programmed data states A, B, or C (discussed below). For example, a group of memory cells to be programmed can first be erased so that all memory cells in the group are in the erased data state E. Then, the memory cells are directly programmed to data states A, B, and / or C using a programming process. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows of

[0102] Figure 5C depict an exemplary threshold voltage distribution of memory cells where each memory cell stores three bits of data per memory cell (which is another example of MLC data). Figure 5CShows eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A - G represent programmed memory cells and are thus also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of the set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of that cell depends on the data encoding scheme employed for those cells. In one embodiment, Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of a memory erroneously shifts to its adjacent physical state, only one bit is affected. Table 2 provides an example of the encoding scheme for the embodiment, where each bit of the three - bit data stored in a memory cell is in a different logical page referred to as the lower page (LP), middle page (MP), and upper page (UP).

[0103] Table 2

[0104] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0105] Figure 5C Shows seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages (e.g., performing a sense operation), the system can determine what data state (i.e., A, B, C, D, ……) the memory cell is in.

[0106] Figure 5C Also shows seven verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming a memory cell to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming a memory cell to data state B, the system will test whether the memory cell has a threshold voltage greater than or equal to VvB. When programming a memory cell to data state C, the system will determine whether the memory cell has a threshold voltage greater than or equal to VvC. When programming a memory cell to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming a memory cell to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming a memory cell to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming a memory cell to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG. Figure 5CAlso shown is Vev, which is an erase verification reference voltage used to test whether a memory cell has been properly erased.

[0107] In an embodiment utilizing full-sequence programming, the process of Figure 6 can be used to program a memory cell directly from an erased data state Er to any one of programmed data states A - G (discussed below). For example, a group of memory cells to be programmed can first be erased so that all memory cells in the group are in the erased data state Er. Then, the memory cells are directly programmed to data states A, B, C, D, E, F, and / or G using the programming process. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 5C The arrows of

[0108] represent full-sequence programming. In some embodiments, data states A - G can overlap, where the control die 211 and / or the memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system can use a multi-pass programming process known in the art instead of full-sequence programming.

[0108] Generally, during a verify operation and a read operation, a select word line is connected to a voltage (an example of a reference signal), the level of which is specified for each read operation (e.g., see Figure 5C the read comparison voltages / levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verify operation (e.g., see Figure 5C the verify target voltages / levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG) in order to determine whether the threshold voltage of the memory cell of interest has reached this level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell conducts (conducts current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell does not conduct and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, unselected memory cells are provided with one or more read-through voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased).

[0109] During a read or verify operation, there are many ways to measure the conduction current of a memory cell. In one example, the conduction current of a memory cell is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a memory cell is selected to allow (or not allow) a NAND string including the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see if it has discharged. Note that the techniques described herein can be used in conjunction with different methods known in the art for verification / reading. Other read and verify techniques known in the art can also be used.

[0110] Figure 5D Depicts the threshold voltage distribution when each memory cell stores four bits of data (which is another example of MLC data). Figure 5D Depicts that there may be some overlap between the threshold voltage distributions (data states) S0 - S15. This overlap may occur due to factors such as a memory cell losing charge (thereby causing the threshold voltage to drop). Programming interference can inadvertently increase the threshold voltage of a memory cell. Similarly, read interference can inadvertently increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution may change. This change may increase the bit error rate, thereby increasing the decoding time and even making decoding impossible. Changing the read reference voltage can help mitigate this effect. Using ECC during the read process can correct errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of a group of memory cells storing four bits of data per memory cell do not overlap but are separated from each other. As discussed above, Figure 5D the threshold voltage distribution will include a read reference voltage and a verify reference voltage.

[0111] When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi - pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value of the set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of that cell depends on the data encoding scheme employed for those cells. Table 3 provides an example of an encoding scheme for an embodiment, where each of the four bits of data stored in a memory cell is located in a different logical page called the lower page (LP), middle page (MP), upper page (UP), and top page (TP).

[0112] Table 3

[0113] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0114] Figure 6is a flowchart depicting one implementation of a process for programming memory cells. For the purposes of this document, the term programming is synonymous with writing. In one exemplary implementation, the memory array 202 is executed using one or more of the control circuits discussed above (e.g., system control logic 260, column control circuit 210, row control circuit 220) Figure 6 of the process. In one exemplary implementation, Figure 6 of the process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory die 201. The process includes a number of cycles, each cycle including a programming phase and a verification phase. Performing Figure 6 of the process enables full-sequence programming as well as other programming schemes including multi-stage programming. When multi-stage programming is implemented, Figure 6 of the process is used to implement any / each stage of the multi-stage programming process.

[0115] Typically, the programming voltage applied to the control gate during a programming operation (via a selected data word line) is applied as a series of programming voltage pulses. Interspersed between the programming voltage pulses are a set of verification pulses (e.g., voltage pulses) for performing verification. In many implementations, the amplitude of the programming voltage pulses increases by a predetermined step with each successive pulse. In Figure 6In step 602, the programming voltage signal (Vpgm) is initialized to a starting amplitude (e.g., ~12V - 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, the group of memory cells selected to be programmed (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (selected word line). It is very likely that there are other memory cells not selected for programming that are also connected to the selected word line (unselected memory cells). That is, the selected word line will also be connected to memory cells for which programming should be prohibited. In addition, when the memory cells reach their expected target data state, they will be prohibited from further programming. Those NAND strings that include memory cells connected to the selected word line that is to be prohibited from programming (e.g., unselected NAND strings) boost their channels to prohibit programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not sufficient to cause programming. To assist with the boosting, in step 604, the control die will pre-charge the channels of the NAND strings that include memory cells connected to the selected word line that is to be prohibited from programming. In step 606, the NAND strings that include memory cells connected to the selected word line that is to be prohibited from programming boost their channels to prohibit programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word line receives one or more boosting voltages (e.g., ~7 volts - 11 volts) to perform the boosting scheme. A programming inhibit voltage is applied to the bit lines coupling the unselected NAND strings.

[0116] In step 608, a programming voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If the memory cells on the NAND string are to be programmed, the corresponding bit lines are biased with a programming enable voltage. In step 608, the programming pulses are applied simultaneously to all the memory cells connected to the selected word line such that all the memory cells in the memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during an overlapping time period (both are considered simultaneous). In this way, all the memory cells in the memory cells connected to the selected word line will have their threshold voltages changed simultaneously, unless they are prohibited from programming.

[0117] In step 610, program-verify is performed, which includes testing whether the memory cells being programmed have successfully reached their target data states. Memory cells that have reached their target states are locked by the control die and cannot be programmed further. Step 610 includes performing verification of the programming by sensing one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cells selected for programming has reached an appropriate verification reference voltage. In step 610, after the memory cells have been verified (by testing of Vt) to have reached their target states, the memory cells can be locked.

[0118] In one embodiment of step 610, intelligent verification techniques are used such that the system verifies only a subset of the data states during the programming loop (steps 604 - 628). For example, the first programming loop includes verification of data state A (see Figure 5C ), depending on the result of the verification operation, the second programming loop may perform verification of data states A and B, and depending on the result of the verification operation, the third programming loop may perform verification of data states B and C, and so on.

[0119] In step 616, the number of memory cells that have not reached their corresponding target threshold voltage distributions is counted. That is, the number of memory cells that have not reached their target states so far is counted. This counting can be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is an overall count that reflects the total number of memory cells that are currently being programmed but have not passed the last verification step. In another embodiment, separate counts are maintained for each data state.

[0120] In step 617, the system determines whether the verification operation in the most recent execution of step 610 included verification of the last data state (e.g., Figure 5CVerification of the data state G). If so, at step 618, determine whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of the page memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process may stop, and a "pass" status is reported at step 614. In such a case, enough memory cells are programmed correctly such that the ECC can be used during the read process to correct the few remaining memory cells that have not been fully programmed. In some embodiments, the predetermined limit used at step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When not all of the memory cells in a page of memory cells are programmed, the predetermined limit can be a fraction (proportional or non-proportional) of the number of bits that can be corrected by the ECC during the read process of the page memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles that have been performed, or other criteria.

[0121] If in step 617 it is determined that the verification operation in the most recent execution of step 610 does not include verification of the last data state, or if in step 618 it is determined that the number of failed memory cells is not less than the predetermined limit, then in step 619, the data state to be verified in the next execution of step 610 (in the next programming cycle) is adjusted according to the intelligent verification scheme discussed above. At step 620, check the programming counter PC against the programming limit value (PL). Examples of programming limit values include 6, 12, 16, 19, 20, and 30; however, other values may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed, and a fail status is reported at step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1, and the programming voltage signal Vpgm steps to the next amplitude. For example, the next pulse will have an amplitude that is one step ΔVpgm larger than the previous pulse (e.g., the step size is 0.1 volts - 1.0 volts). After step 626, the process continues at step 604, and another programming pulse is applied to the selected word line (through the control die), thereby performing Figure 6 another programming cycle (steps 604 - 626) of the programming process.

[0122] In one embodiment, the memory cells are erased before programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from Figure 5AThe state P changes to state E, from Figure 5B The states A / B / C change to state E, from Figure 5C The states A - G change to state Er, or from Figure 5D The states S1 - S15 change to state S0.

[0123] A technique for erasing memory cells in some memory devices is to bias a p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the memory cell. In this document, this is referred to as p-well erase.

[0124] Another method of erasing memory cells is to generate a gate-induced drain leakage ("GIDL") current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. In this document, this is referred to as GIDL erase. Both p-well erase and GIDL erase can be used to reduce the threshold voltage (Vt) of the memory cell.

[0125] In one embodiment, a GIDL current is generated by creating a drain-to-gate voltage at a GIDL generation transistor (e.g., transistors connected to SGDT0, SGDT1, SGDT2, SGSB0, SGSB1, and SGSB2). In some embodiments, a select gate (e.g., SGD or SGS) can be used as the GIDL generation transistor. The drain-to-gate voltage of the transistor that generates the GIDL current is referred to as the GIDL voltage in this document. A GIDL current may be generated when the drain voltage of the GIDL generation transistor is significantly higher than the control gate voltage of the GIDL generation transistor. The GIDL current is the result of carrier generation (i.e., electron-hole pair generation due to band-to-band tunneling and / or trap-assisted generation). In one embodiment, the GIDL current can generate one type of carrier (also referred to as a charge carrier), such as holes, which mainly move into the NAND channel, thereby increasing or changing the potential of the channel. Another type of carrier, such as electrons, is extracted from the channel by an electric field in the bit line direction or in the source line direction. During erase, holes can tunnel from the channel to the charge storage region of the memory cell (e.g., to the charge trapping layer 493) and recombine with electrons there to reduce the threshold voltage of the memory cell.

[0126] GIDL current can be generated at either (or both) ends of the NAND string. A first GIDL voltage can be generated between two terminals of a GIDL generation transistor (e.g., connected to SGDT0, SGDT1, SGDT2) connected to or near the bit line to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a GIDL generation transistor (e.g., SGSB0, SGSB1, and SGSB2) connected to or near the source line to generate a second GIDL current. Erasure based on GIDL current at only one end of the NAND string is referred to as single-sided GIDL erasure. Erasure based on GIDL currents at both ends of the NAND string is referred to as two-sided GIDL erasure. The techniques described herein can be used with single-sided GIDL erasure and two-sided GIDL erasure.

[0127] Figure 7 The programming signal Vpgm is depicted as a series of programming voltage pulses such that one pulse of the programming signal Vpgm is applied each time step Figure 6 608 is executed. These programming voltage pulses are an example of multiple programings applied to the plurality of non-volatile memory cells being programmed. In one embodiment, the programming voltage pulses increase in voltage amplitude by a step ΔVpgm from pulse to pulse. In some embodiments, ΔVpgm can change during the programming process. As Figure 6 described, the system performs program-verify between multiple programings (between or after the programming voltage pulses), as Figure 8A and Figure 8B depicted. Figure 8A shows an example of performing program-verify for one verify level, which depicts Figure 7 two of the programming voltage pulses 702 and 704. Between the programming voltage pulses 702 and 704 is a verify voltage pulse 710. In one embodiment, the verify voltage pulse 710 has the amplitude of any of the verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG (see Figure 5C ), and represents a system that performs program-verify (step 610) between multiple programings (successive iterations of step 608). In some embodiments, between the programming voltage pulses, the system will perform program-verify for multiple or all data states, while in other embodiments, the system will perform program-verify one data state at a time or for a subset of the data states. Figure 8B shows an example of performing program-verify for two verify levels, which depicts Figure 7Two of the programming voltage pulses 702 and 704. Between the programming voltage pulses 702 and 704 are verification voltage pulses 710 and 712. In one embodiment, the verification voltage pulses 710 and 712 are for different data states.

[0128] The programming, verification / sensing, and erasing processes discussed above all require applying various voltages to the word lines of selected memory cell blocks. Figure 9 is a block diagram depicting a charge pump, a control gate driver, a switching network, and word line switches for applying those voltages to the word lines. Figure 9 A set of charge pumps 902 is shown, which provides multiple different voltage sources to multiple sets of control gate drivers, the multiple sets of control gate drivers including a first set of control gate drivers 904, a second set of control gate drivers 906, a third set of control gate drivers 908, … a Xth set of control gate drivers 910. The charge pumps 902 include multiple charge pumps that provide different voltages required to perform memory operations. In some embodiments, a voltage generator may also generate some of the different voltages required to perform memory operations. In one embodiment, for each voltage that needs to be applied to the word lines, there is a separate set of one or more charge pumps or voltage generators. In other embodiments, some charge pumps and / or voltage generators can be sources of multiple voltages by using voltage dividers or other circuits.

[0129] In one embodiment, the first set of control gate drivers 904 includes multiple control gate drivers for providing the necessary voltages to data word lines (e.g., Wl-WL161) in order to perform programming, erasing, and reading. The output CGout_A of the first set of control gate drivers 904 (which includes a separate output signal for each control gate driver) is provided (connected) to the switching network 920. The first set of control gate drivers 904 is connected to the data word lines via the switching network 920. In one embodiment, all of the control gate drivers in the first set of control gate drivers 904 have the same structure, receive the same input (voltage source), and provide the same set of voltage outputs.

[0130] In one embodiment, the second set of control gate drivers 906 includes a plurality of control gate drivers for providing the necessary voltages to the dummy word lines to perform programming, erasing, and reading. The output CGout_B of the second set of control gate drivers 906, which includes a separate output signal for each control gate driver, is provided (connected) to the switch network 920. The second set of control gate drivers 906 is connected to the dummy word lines via the switch network 920. In one embodiment, all of the control gate drivers in the second set of control gate drivers 906 have the same structure, receive the same input (voltage source), and provide the same set of voltage outputs.

[0131] In one embodiment, the third set of control gate drivers 908 includes a plurality of control gate drivers for providing the necessary voltages to the select lines (e.g., SGD and SGS) to perform programming, erasing, and reading. The output CGout_C of the third set of control gate drivers 908, which includes a separate output signal for each control gate driver, is provided (connected) to the switch network 920. The third set of control gate drivers 908 is connected to the select lines via the switch network 920. In one embodiment, all of the control gate drivers in the third set of control gate drivers 908 have the same structure, receive the same input (voltage source), and provide the same set of voltage outputs.

[0132] Figure 9 The word lines WL0-WL161 of two exemplary blocks (block A and block B) are shown. Each word line WL0-WL161 of each block is connected to the output of the switch network 920 via word line switch transistors (e.g., 940-966). For example, the word line WL0 of block A is connected to the output of the word line switch transistor 966, the WL159 of block A is connected to the output of the word line switch transistor 964, the WL160 of block A is connected to the output of the word line switch transistor 962, the WL161 of block A is connected to the output of the word line switch transistor 960, the WL0 of block B is connected to the output of the word line switch transistor 946, the WL159 of block B is connected to the output of the word line switch transistor 944, the WL160 of block B is connected to the output of the word line switch transistor 942, and the WL161 of block 1 is connected to the output of the word line switch transistor 960. The inputs of the word line switches are connected to the output of the switch network 920. In one embodiment, the switch network 920 includes a plurality of high voltage switches (e.g., transistors) to connect the control gate drivers to the appropriate word lines by routing the output voltages from the control gate drivers to the appropriate word line switch transistors 940-966 connected to the word lines WL0-WL161 of each block. Note that in some embodiments, multiple word lines may share a single control gate driver. The switch network is also connected to the select lines SGS and SGD (in order to makeFigure 9 Easier to read, and they are omitted from Figure 9 them).

[0133] Figure 9 Also depicted is a voltage control circuit 903 connected to a charge pump 902. The voltage control circuit 903 controls the output of the charge pump. In one embodiment, the voltage control circuit 903 receives a digital signal indicating a desired charge pump output from a state machine or other processor, and the voltage control circuit 903 includes a digital-to-analog conversion circuit that outputs a signal 905 to the charge pump, the signal indicating a requested voltage signal to be output by the charge pump.

[0134] Figure 10 is a timing diagram depicting the behavior of the following signals during a program-verify operation: BL(sel), BL(unsel), SGD(sel), SGD(unsel), WLunsel, WLn, SGS, and SL. The signal BL(sel) is the voltage applied to bit lines that are connected to NAND strings having memory cells selected for sensing / reading. The signal BL(unsel) is the voltage applied to bit lines that are connected to NAND strings having no memory cells selected for sensing / reading. In some embodiments, all bit lines will be selected for sensing / reading. The signal SGD(sel) is the voltage applied to drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 that are connected together for one region) of a region selected for sensing / reading (e.g., regions 420, 430, 440, 450, 460, and 470). The signal SGD(unsel) is the voltage applied to drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 that are connected together for one region) of a region not selected for sensing / reading (e.g., regions 420, 430, 440, 450, 460, and 470). The signal SGS is the voltage applied to source side select (SGS) lines (e.g., SGS0, SGS1, and SGS2 that are connected together). The signal SL is the voltage applied to the source line. The signal WLn is the voltage applied to the word line selected for programming and program-verify (i.e., the word line connected to the memory cell selected for programming). The signal WLunsel is the voltage applied to the word line not selected for programming.

[0135] At Figure 10 time t0 of Figure 10All signals depicted are at Vss (ground or 0 volts). At time t1, BL(sel) rises to Vbl (e.g., 0.5v - 1.5v), and WLunsel rises to Vread (e.g., 6 volts - 8 volts). Vread is an example of an overdrive voltage as it is high enough to turn on the memory cell regardless of which data state the memory cell has been programmed to. Also at time t1, SGD(sel) rises in two steps to Vsg (e.g., 3.5v - 6v) (i.e., an example of a sense enable voltage), such that it reaches Vdd at t2 and Vsg at t3. At t1, a voltage spike is applied to WLn, and after the voltage on WLn stabilizes, WLn rises to Vcgv (e.g., Figure 5C one of the verification reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG of Figure 5C ). At time t4, SGS rises to Vsg, which provides a path for the bit line voltage dissipation. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will conduct current, and the bit line voltage will dissipate via the source line, as depicted by curve 994. If Vcgv is not greater than the threshold voltage of the selected memory cell, the selected memory cell will not conduct current, and the bit line voltage will not dissipate via the source line, as depicted by curve 992. The sense amplifier will sense whether the selected memory cell conducts at time t5. At time t6, BL(sel) drops to Vss. At time t7, SGD(sel), WLunsel, WLn, and SGS drop to Vss. When sensing at t5, the sensed result is stored in the latch at the corresponding sense amplifier. After that, the system (e.g., the control circuit) scans all the latches in the latches of the sense amplifiers to determine which memory cells conduct and which memory cells do not conduct.

[0136] At Figure 10 Figure 10 , during t1 - t3, the unselected word line WLunsel rises to Vread (overdrive voltage) during the program - verify operation. The rate at which the unselected word line rises to Vread is called the slew rate. A higher slew rate will cause WLunsel to reach Vread from 0 faster, and its slope is steeper than that of a lower slew rate.

[0137] Figure 11 depicts two graphs horizontally aligned with each other. The upper graph describes the voltage applied to the unselected word line (WLunsel), and the lower graph depicts the current drawn by the memory system (ICC). The horizontal axis of both graphs represents time and is divided into two time periods: R1 and R2. Time period R1 corresponds to the time period between t1 and t2 of Figure 10 Figure 10 . Time period R2 corresponds to Figure 10The time period between t2 and t3. The upper graph includes four curves: 1102, 1104, 1106, and 1108. Curves 1102 and 1106 represent two exemplary options for the signal 905 output from the voltage control circuit 903 (see Figure 9 ) and input to the charge pump 902. Curve 1102 is a control signal that configures the charge pump 902 to ramp the word line voltage to Vread as fast as possible (e.g., a first or higher ramp rate). Curve 1106 is a control signal that configures the charge pump 902 to increase the word line voltage at a slower rate (e.g., a second or lower ramp rate). Curve 1106 may be referred to as a step signal because it raises the voltage in a series of steps. Curve 1104 is the output of the charge pump 902 supplied to the unselected word lines during program-verify in response to the voltage control circuit 903 inputting curve 1102 to the charge pump 902. Curve 1108 is the output of the charge pump 902 supplied to the unselected word lines during program-verify in response to the voltage control circuit 903 inputting curve 1106 to the charge pump 902. It can be seen that curve 1108 has a more gradual increase in voltage amplitude than curve 1104. Curve 1108 shows a step-by-step increase in the word line voltage.

[0138] The lower graph shows three curves: 1120, 1122, and 1124. Curve 1120 shows the moving average of the current ICC drawn in the memory die when curve 1104 is the output of the charge pump 902 in response to the voltage control circuit 903 inputting curve 1102 to the charge pump 902. Curve 1122 shows the moving average of the current ICC drawn in the memory die when curve 1108 is the output of the charge pump 902 in response to the voltage control circuit 903 inputting curve 1106 to the charge pump 902. Curve 1124 (including a series of bell-shaped curves) represents the raw current (rather than the moving average) when curve 1108 is the output of the charge pump 902 in response to the voltage control circuit 903 inputting curve 1106 to the charge pump 902. From Figure 11It can be seen that reducing the ramp rate of the word line voltage applied to unselected word lines during programming-verification (e.g., incrementally increasing the word line voltage rather than a single high-slope ramp) results in a lower current ICC. However, using a smaller ramp rate of the word line voltage applied to unselected word lines during programming-verification results in a slower programming process. Thus, adjusting the ramp rate of the word line voltage applied to unselected word lines during programming-verification requires a balance between the current used and the speed (performance). To address this balance, a reduction in the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification is proposed to be loop-dependent in order to reduce current consumption. That is, the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification is reduced (i.e., slowed down) for some programming loops rather than all programming loops. In one embodiment, it is determined which programming loops exhibit a higher current peak, and the ramp rate of the overdrive voltage applied to unselected word lines is reduced (slowed down) for those programming loops that exhibit a higher current peak.

[0139] Figure 12 is a flowchart that depicts one embodiment of a process for configuring a memory to include a loop-dependent reduction in the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification. Figure 12 The process of can be performed on a representative block, a set of representative blocks, or all blocks of the memory. In step 1202, the memory cells connected to each word line are programmed with data (e.g., using Figure 6(process). In one embodiment, the programmed data is random data. In step 1204, the current drawn by the memory die is measured during each programming cycle. In step 1206, for each word line, identify / determine the programming cycle with the highest drawn current (relative to all programming cycles of step 1202 for that word line). In step 1208, for each word line, identify / determine the programming cycle in which the drawn current returns to a standard (nominal) current (or a value less than the highest current) (relative to all programming cycles of step 1202 for that word line). In step 1210, identify / determine the word line with the highest current draw and the programming cycle of that word line. In step 1212, for the word line determined during step 1210 to have the highest current draw, the memory system is configured to indicate that the programming cycle start has a reduced ramp rate, as the programming cycle with the highest drawn current (see step 1206). In one embodiment, step 1212 includes setting a parameter of the memory. In step 1214, for the word line determined during step 1210 to have the highest current draw, the memory system is configured to indicate that the programming cycle end has a reduced ramp rate, as the programming cycle in which the drawn current returns to the standard current (see step 1208). In one embodiment, step 1214 includes setting a parameter of the memory. In other embodiments, different criteria may be used to select when to start and when to stop the reduced ramp rate. In some embodiments, the memory will start the reduced ramp rate based on step 1212; however, the reduced ramp rate will continue until the programming process ends (e.g., obviating the need for step 1214). In some embodiments, for all word lines of a block, all word lines of a plane, or all word lines of the memory, the start and stop of the reduced ramp rate are the same. In some embodiments, based on steps 1206 and 1208, the start and stop of the reduced ramp rate are configured separately for each word line. In some embodiments, the start and stop of the reduced ramp rate are configured separately for each block. In some embodiments, the start and stop of the reduced ramp rate are configured separately for each plane.

[0140] Figure 13 is a flowchart that depicts one embodiment of a process for programming memory cells, including a cycle-dependent reduction in the ramp rate of an overdrive voltage applied to unselected word lines during program-verify. Figure 13 The process may be performed by any of the one or more control circuits discussed above. Figure 13 The process may be performed entirely by the control circuit on the memory die 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B) is performed by, rather than by the memory controller 120. In one example, using other components of the system control logic 260, column control circuit 210, and row control circuit 220, it is performed by or under the guidance of the state machine 262 Figure 13 The process. In another embodiment, it is performed by or under the guidance of the memory controller 120 Figure 13 The process. In implementation Figures 1 to 4F And Figure 9 Executed on a memory of any of the structures depicted in the structure Figure 13 The process.

[0141] In step 1302, the control circuit programs the memory cells by applying multiple programming to the memory cells. For example, a set of programming voltage pulses is applied to the selected word line (WLn) (see steps 608 and Figure 7 ). In step 1304, the control circuit performs program-verify between multiple programming (see Figure 6 Steps 610 of and Figure 8A / B pulses 710 / 712). In one embodiment, performing program-verify between multiple programming includes applying a verify reference voltage (Vcgv) to the selected word line (WLn) and an overdrive voltage (e.g., Vread) to the unselected word line (WLunsel) between multiple programming (e.g., see Figure 10 ). The control circuit is configured to apply an overdrive voltage to the unselected word line by applying an overdrive voltage to the unselected word line at a first ramp rate between a first set of multiple programming, applying an overdrive voltage to the unselected word line at a second ramp rate between a second set of multiple programming after the first set of multiple programming (the second set of multiple programming is after the first set of multiple programming), and applying an overdrive voltage to the unselected word line at a first ramp rate between a third set of multiple programming after the second set of multiple programming (the third set of multiple programming is after the second set of multiple programming). Compared with the first ramp rate, the second ramp rate is lower (more gradual or smaller slope). An example of the first ramp rate is Figure 11 Signal 1104 of. An example of the second ramp rate is Figure 11 Signal 1108 of. As Figure 11 Depicted, in one embodiment, the second ramp rate is performed step by step. In an exemplary embodiment, Figure 12 The process is used to configure the start of the reduced ramp rate in step 1212, which corresponds to the start of the second set of multiple programming; and Figure 12 The process is used to configure the end of the reduced ramp rate in step 1214, which corresponds to the start of the third set of multiple programming. In a set of embodiments, the control circuit is configured to switch from the first ramp rate to the second ramp rate when the current in the memory die and / or memory system is at a relatively maximum value.

[0142] As discussed above, Figure 12 the process includes programming cycles in which the current reaches a peak (e.g., see steps 1206 and 1212) and programming cycles in which the current returns to the nominal amplitude (e.g., see steps 1208 and 1214). In a set of embodiments, the programming cycle in which the current reaches a peak occurs when programming-verification for a first data state is completed, and the programming cycle in which the current returns to the nominal amplitude occurs when programming-verification for a second data state is completed. For example, the current may reach a peak during a programming cycle that includes completing programming-verification for data state C, and the current returns to the nominal amplitude during a programming cycle that includes completing programming-verification for data state E. In this example, for programming cycles executed after completing programming-verification for data state C and until completing programming-verification for data state E, the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification is slowed or reduced such that after completing programming-verification for data state E, the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification is no longer slowed or reduced. In this example, Figure 13 a first set of multiple programming of Figure 13 occurs before completing programming-verification for data state C; Figure 13 a second set of multiple programming of

[0143] Figure 14 is a flowchart that depicts one embodiment of a process for programming memory cells, including a cyclic dependence reduction of the ramp rate of the overdrive voltage applied to unselected word lines during programming-verification. Figure 14 The process of Figure 13 is an exemplary implementation of the process of Figure 14 that includes starting and / or stopping the reduced ramp rate in response to completing programming-verification for a predetermined data state. Figure 14 The process of Figure 2A can be performed by any one of the one or more control circuits discussed above. Figure 2B The process of Figure 14 can be performed entirely by the control circuit on the memory die 200 (seeFigure 14 The process. In implementing Figures 1 to 4F and Figure 9 Execute on the memory of any structure depicted in the structure Figure 14 The process.

[0144] In Figure 14 In step 1402, the control circuit stores indications of the first predetermined data state and the second predetermined data state in one or more data structures. Step 1402 corresponds to Figure 12 Steps 1212 and 1214. In step 1404, the control circuit accesses one or more data structures to identify the first predetermined data state and the second predetermined data state. In step 1406, the control circuit programs the memory cells by applying multiple programings to the memory cells. For example, applying a set of programming voltage pulses to the selected word line (see steps 608 and Figure 7 ). In step 1408, the control circuit performs program-verify between multiple programings (see Figure 6 Steps 610 and Figure 8A Pulses 710 / 712 of / B).

[0145] In one embodiment, performing program-verify between multiple programings includes applying a verify reference voltage (Vcgv) to the selected word line (WLn) and an overdrive voltage (e.g., Vread) to the unselected word line between multiple programings. During the programming process, the control circuit is configured to initially apply an overdrive voltage to the unselected word line at a first ramp rate between multiple programings, and in response to the completion of program-verify for the first predetermined data state (e.g., see Figure 5C State C), switch to applying an overdrive voltage to the unselected word line at a second ramp rate between multiple programings, and (after applying the overdrive voltage to the unselected word line at the second ramp rate) in response to the completion of program-verify for the second predetermined data state (e.g., see Figure 5C State E), switch to applying an overdrive voltage to the unselected word line at a first ramp rate between multiple programings. In a set of embodiments, the control circuit is configured to switch from the first ramp rate to the second ramp rate when the current in the memory die or memory system is at a relatively maximum value.

[0146] Figure 15A Is a table for configuring the start programming loop to reduce the ramp rate of the overdrive voltage applied to the unselected word line during program-verify. That is, Figure 15A Shows the possible values of the parameters indicating the first predetermined data state of step 1422. Figure 15Bis a table for configuring a programming loop to end a ramp rate reduction of an overdrive voltage applied to an unselected word line during programming-verification. That is, Figure 15B shows possible values of parameters indicating a second predetermined data state of step 1422. In one embodiment, step 1402 and / or step 1212 / 1214 include storing Figure 15A and Figure 15B one or more of the values in a table or other data structure stored in the memory array 202 and / or the volatile memory 140.

[0147] Figure 16 is a flowchart that describes one embodiment of a process for programming memory cells, including a loop-dependent reduction of a ramp rate of an overdrive voltage applied to an unselected word line during programming-verification. Figure 16 The process of Figure 13 is and / or Figure 14 is an exemplary implementation of the process of Figure 16 The process of can be performed by any one of the one or more control circuits discussed above. Figure 16 The process of can be performed entirely by a control circuit on the memory die 200 (see Figure 2A ) or entirely by a control circuit on the integrated memory component 207 (see Figure 2B ), rather than by the memory controller 120. In one example, using other components of the system control logic 260, the column control circuit 210, and the row control circuit 220, the process of Figure 16 is performed or directed by the state machine 262. In another embodiment, the process of Figure 16 is performed or directed by the memory controller 120. In implementing Figures 1 to 4F and Figure 9 the process of is performed on a memory implementing any of the structures depicted in Figure 16 .

[0148] In step 1602, the control circuit applies a plurality of programming voltage pulses to a set of non-volatile memory cells connected to a selected word line. For example, Figure 6Step 608 is performed multiple times (during different programming cycles). In step 1604, the control circuit performs a program-verify operation after each programming voltage pulse among a plurality of programming voltage pulses. Each programming voltage pulse among the plurality of programming voltage pulses and the corresponding program-verify operation after the corresponding programming voltage pulse include a programming cycle. Performing the program-verify operation after each programming voltage pulse includes: applying a verify reference voltage to the selected word line (1620); applying an overdrive voltage to the unselected word lines at a first ramp rate during a first set of programming cycles (1622); detecting completion of the program-verify for a first predetermined data state (1624); in response to detecting completion of the program-verify for the first predetermined data state, applying an overdrive voltage to the unselected word lines at a second ramp rate during a second set of programming cycles after the first set of programming cycles, where the second ramp rate is lower (slower or has a smaller slope) than the first ramp rate (1626); detecting completion of the program-verify for a second predetermined data state (1628); and applying an overdrive voltage to the unselected word lines at a first ramp rate during a third set of programming cycles, where the third set of programming cycles is initiated in response to detecting completion of the program-verify for the second predetermined data state (1630). In one embodiment, the overdrive voltage is applied at the second ramp rate when the non-volatile memory draws maximum current during programming. In one embodiment, the first predetermined data state is identified by the table of Figure 15A (based on step 1212), and the second predetermined data state is identified by the table of Figure 15A (based on step 1214).

[0149] In Figure 16 an exemplary embodiment of the process, after completion of the program-verify for data state C, the ramp rate is reduced to a slower ramp rate (e.g., from the first ramp rate to the second ramp rate), and then after completion of the program-verify for data state E, the ramp rate changes back to the faster ramp rate (e.g., from the second ramp rate to the first ramp rate). Figure 16 Another embodiment of the process includes not performing steps 1628 and 1630, such that after completion of the program-verify for the first predetermined data state, the ramp rate is reduced to a slower ramp rate (e.g., from the first ramp rate to the second ramp rate), and the ramp rate remains at the reduced / slower ramp rate (e.g., the second ramp rate) until the end of the programming process.

[0150] In some embodiments, the process of Figure 13 , Figure 14 and / or Figure 16 may be performed on the memory cells connected to one word line. In other embodiments, the process of Figure 13 , Figure 14and / or Figure 16 The process. In other embodiments, Figure 13 , Figure 14 and / or Figure 16 The process may be performed multiple times to program memory cells connected to multiple word lines such that Figure 13 , Figure 14 and / or Figure 16 The process is performed once for each word line.

[0151] Figure 17 is a flow chart that depicts one embodiment of a process for programming memory cells, including reducing the loop dependence of the ramp rate of the overdrive voltage applied to unselected word lines during program-verify, such that the loop for reducing the ramp rate is adjusted and customized for each different word line (each of which). Figure 17 The process may be performed by any one of the one or more control circuits discussed above. Figure 17 The process may be performed entirely by the control circuit on the memory die 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than by the memory controller 120. In one example, using other components of the system control logic 260, column control circuit 210, and row control circuit 220, the process of Figure 17 is performed by or under the direction of the state machine 262. In another embodiment, the process of Figure 17 is performed by or under the direction of the memory controller 120. In implementing Figures 1 to 4F and Figure 9 The process is performed on any memory implementing any of the structures depicted in Figure 17 .

[0152] In Figure 17 At step 1702, the control circuit receives a command to program data into the memory. At step 1704, the control circuit receives the data to be programmed. In one embodiment, the data is received from a host. At step 1706, the control circuit programs the memory cells connected to the same word line with a customized start programming loop and stop programming loop to change the ramp rate of the overdrive voltage applied to unselected word lines during program-verify. That is, Figure 12 The process is adapted to determine separately / individually for each word line at which programming loop the reduced ramp rate should start and at which programming loop the reduced ramp rate should end. For each word line, the programming loop at which the reduced ramp rate should start and the programming loop at which the reduced ramp rate should end will likely be different. In one embodiment, step 1706 includes performing Figure 13 , Figure 14 and / orFigure 16 During the process, if there are more word lines to be programmed (e.g., more data to be programmed) in step 1708, then in step 1710, the next word line is selected and step 1706 is executed again to program the memory cells connected to the next word line with separate (customized) start programming cycles and stop programming cycles, thereby changing the ramp rate of the overdrive voltage applied to the unselected word lines during program-verify. If there are no more word lines to be programmed (e.g., no more data to be programmed), then in step 1712, a successful completion of the programming is reported (e.g., to the host).

[0153] In Figure 17 one embodiment of the process, when step 1706 includes executing Figure 13 the process, the first set of multiple programming and the second set of multiple programming change for different selected word lines. In Figure 17 one embodiment of the process, the control circuit is configured to switch from a first ramp rate to a second ramp rate when the current is at a relative maximum. In Figure 17 one embodiment of the process, when step 1706 includes executing Figure 16 the process, the first set of programming cycles and the second set of programming cycles change for different selected word lines.

[0154] In some embodiments, before the process of Figure 13 , Figure 14 , Figure 16 and / or Figure 17 , the process of Figure 12 is executed to configure the memory to execute the process of Figure 13 , Figure 14 , [[ and / or ​ .

[0155] In some embodiments, the ramp rate is slowed down midway through the programming process and then restored to the original ramp rate during the programming process. In other embodiments, the ramp rate is slowed down midway through the programming process and remains at the slowed-down ramp rate for the remainder of the programming process.

[0156] A memory system has been proposed that includes a reduced loop dependence of the ramp rate of the overdrive voltage applied to unselected word lines during program-verify to reduce current consumption.

[0157] One embodiment includes a non - volatile storage device that includes: a plurality of non - volatile memory cells; a plurality of word lines connected to the memory cells; and a control circuit connected to the memory cells and the word lines. The control circuit is configured to program the memory cells by applying multiple program operations to the memory cells and performing program - verify between the multiple program operations. The control circuit is configured to perform program - verify between the multiple program operations by applying a verify reference voltage to selected word lines and an over - drive voltage to unselected word lines between the multiple program operations. The control circuit is configured to apply the over - drive voltage to the unselected word lines at a first ramp rate between a first set of the multiple program operations and at a second ramp rate between a second set of the multiple program operations. The second ramp rate is lower than the first ramp rate. The second set of the multiple program operations is after the first set of the multiple program operations.

[0158] In some specific implementations, the control circuit is configured to apply the over - drive voltage to the unselected word lines at the first ramp rate between a third set of the multiple program operations after the second set of the multiple program operations.

[0159] In an exemplary specific implementation, the control circuit is configured to initially apply the over - drive voltage to the unselected word lines at the first ramp rate between the multiple program operations and switch to applying the over - drive voltage to the unselected word lines at the second ramp rate between the multiple program operations in response to completion of program - verify for a first predetermined data state; after applying the over - drive voltage to the unselected word lines at the second ramp rate, the control circuit is configured to switch to applying the over - drive voltage to the unselected word lines at the first ramp rate between the multiple program operations in response to completion of program - verify for a second predetermined data state; one or more data structures that store indications of the first predetermined data state and the second predetermined data state; and the control circuit accesses the one or more data structures to identify the first predetermined data state and the second predetermined data state.

[0160] In an exemplary specific implementation, each program operation and the corresponding program - verify after the corresponding program operation include a program cycle; the control circuit is configured to apply the over - drive voltage to the unselected word lines at the first ramp rate during a first set of the program cycles; the control circuit is configured to apply the over - drive voltage to the unselected word lines at the second ramp rate during a second set of the program cycles after the first set of the program cycles; the control circuit is configured to apply the over - drive voltage to the unselected word lines at the first ramp rate during a third set of the program cycles after the second set of the program cycles.

[0161] In one example, the second ramp rate is performed in steps.

[0162] In an exemplary specific implementation, the first set of the multiple program operations and the second set of the multiple program operations are changed for different selected word lines.

[0163] In an exemplary embodiment, the control circuit is configured to switch from a first slew rate to a second slew rate when the current is at a relative maximum value.

[0164] In an exemplary embodiment, multiple programming is a programming voltage pulse.

[0165] One embodiment includes a non-volatile memory device that includes: a plurality of non-volatile memory cells; a plurality of word lines connected to the memory cells; and a control circuit connected to the memory cells and the word lines. The control circuit is configured to program the memory cells by applying multiple programming to the memory cells and performing program-verification between the multiple programming. The control circuit is configured to perform program-verification between the multiple programming by applying a verification reference voltage to the selected word line and an overdrive voltage to the unselected word lines between the multiple programming. The control circuit is configured to initially apply an overdrive voltage to the unselected word lines at a first slew rate between the multiple programming and switch to applying an overdrive voltage to the unselected word lines at a second slew rate between the multiple programming in response to completion of program-verification for a first predetermined data state, the second slew rate being lower than the first slew rate.

[0166] One embodiment includes a method for programming an enabled volatile memory, the method including: applying a plurality of programming voltage pulses to a set of non-volatile memory cells connected to a selected word line; and performing a program-verification operation after each of the plurality of programming voltage pulses, each of the plurality of programming voltage pulses and the corresponding program-verification operation after the corresponding programming voltage pulse including a programming cycle. Performing the program-verification operation after each programming voltage pulse includes: applying a verification reference voltage to the selected word line, applying an overdrive voltage to the unselected word lines at a first slew rate during a first set of programming cycles, and applying an overdrive voltage to the unselected word lines at a second slew rate during a second set of programming cycles after the first set of programming cycles, the second slew rate being lower than the first slew rate.

[0167] An exemplary embodiment further includes detecting completion of program-verification for a first predetermined data state, and the second set of programming cycles is initiated in response to the detection.

[0168] An exemplary embodiment further includes detecting completion of program-verification for a second predetermined data state; and applying an overdrive voltage to the unselected word lines at a first slew rate during a third set of programming cycles, the third set of programming cycles being initiated in response to the detection.

[0169] In an exemplary embodiment, the first set of programming cycles and the second set of programming cycles vary for different selected word lines.

[0170] In an exemplary embodiment, when the non-volatile memory draws the maximum current during programming, an overdrive voltage is applied at a second ramp rate.

[0171] For the purposes of this disclosure, references in the specification to "one embodiment", "some embodiments", or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0172] For the purposes of this disclosure, a connection can be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is said to be connected or coupled to another element, the element can be directly connected to the other element or indirectly connected to the other element via one or more intermediate elements. When an element is said to be directly connected to another element, there are no intermediate elements between the element and the other element. Two devices "communicate" if they are directly or indirectly connected such that they can transfer an electrical signal therebetween.

[0173] For the purposes of this disclosure, the term "based on" can be understood as "at least partially based on".

[0174] For the purposes of this disclosure, in the absence of additional context, the use of numerical terms such as "first" object, "second" object, and "third" object may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0175] For the purposes of this disclosure, a "set" of objects can refer to a "set" of one or more of the objects.

[0176] For purposes of illustration and description, the foregoing detailed description has been given. It is not intended to be exhaustive or to limit the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and make various modifications as considered appropriate for the particular use contemplated. The scope is intended to be defined by the appended claims.

Claims

1. A non-volatile storage device, the non-volatile storage device comprising: A plurality of non-volatile memory cells; A plurality of word lines connected to the memory cells; And A control circuit connected to the memory cells and the word lines, the control circuit being configured to program the memory cells by applying multiple programming to the memory cells and performing program-verification between the multiple programming, the control circuit being configured to perform program-verification between the multiple programming by applying a verification reference voltage to a selected word line and an over-drive voltage to an unselected word line between the multiple programming, the control circuit being configured to apply the over-drive voltage to the unselected word line at a first ramp rate between a first set of the multiple programming and at a second ramp rate between a second set of the multiple programming, the second ramp rate being lower than the first ramp rate.

2. The non-volatile storage device according to claim 1, wherein: The second set of the multiple programming is after the first set of the multiple programming.

3. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to apply the over-drive voltage to the unselected word line at the first ramp rate between a third set of the multiple programming after the second set of the multiple programming.

4. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to initially apply the over-drive voltage to the unselected word line at a first ramp rate between multiple programming and switch to applying the over-drive voltage to the unselected word line at a second ramp rate between multiple programming in response to completion of program-verification for a first predetermined data state.

5. The non-volatile storage device according to claim 4, wherein: After applying the over-drive voltage to the unselected word line at the second ramp rate, the control circuit is configured to switch to applying the over-drive voltage to the unselected word line at the first ramp rate between multiple programming in response to completion of program-verification for a second predetermined data state.

6. The non-volatile storage device according to claim 5, wherein: One or more data structures that store indications of the first predetermined data state and the second predetermined data state; and The control circuit accesses the one or more data structures to identify the first predetermined data state and the second predetermined data state.

7. The non-volatile storage device according to claim 1, wherein: Each programming and the corresponding program-verification after the corresponding programming include a programming cycle; The control circuit is configured to apply the over-drive voltage to the unselected word line at the first ramp rate during a first set of programming cycles; And The control circuit is configured to apply the over-drive voltage to the unselected word line at the second ramp rate during a second set of programming cycles after the first set of programming cycles.

8. The non-volatile storage device according to claim 7, wherein: The control circuit is configured to apply the over-drive voltage to the unselected word line at the first ramp rate during a third set of programming cycles after the second set of programming cycles.

9. The non-volatile storage device according to claim 7, wherein: The second ramp rate is executed step by step.

10. The non-volatile storage device according to claim 1, wherein: The first set of the multiple programming and the second set of the multiple programming are changed for different select word lines.

11. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to switch from the first ramp rate to the second ramp rate when the current is at a relative maximum value.

12. The non-volatile storage device according to claim 1, wherein: The multiple programming is a programming voltage pulse.

13. A non-volatile storage device, the non-volatile storage device comprising: A plurality of non-volatile memory cells; A plurality of word lines connected to the memory cells; And A control circuit connected to the memory cells and the word lines, the control circuit being configured to program the memory cells by applying multiple programming to the memory cells and performing program-verification between the multiple programming, the control circuit being configured to perform program-verification between the multiple programming by applying a verification reference voltage to a select word line and an over-drive voltage to an unselected word line between the multiple programming, the control circuit being configured to initially apply the over-drive voltage to the unselected word line at a first ramp rate between the multiple programming and switch to applying the over-drive voltage to the unselected word line at a second ramp rate between the multiple programming in response to completion of the program-verification for a first predetermined data state, the second ramp rate being lower than the first ramp rate.

14. The non-volatile storage device according to claim 13, wherein: After applying the over-drive voltage to the unselected word line at the second ramp rate, the control circuit is configured to switch to applying the over-drive voltage to the unselected word line at the first ramp rate between the multiple programming in response to completion of the program-verification for a second predetermined data state.

15. The non-volatile storage device according to claim 13, wherein: The control circuit is configured to switch from the first ramp rate to the second ramp rate when the current is at a relative maximum value.

16. A method for programming an open volatile memory, the method comprising: Applying a plurality of programming voltage pulses to a group of non-volatile memory cells connected to a select word line; And Performing a program-verification operation after each of the plurality of programming voltage pulses, each of the plurality of programming voltage pulses and the corresponding program-verification operation after the corresponding programming voltage pulse including a programming cycle, the performing the program-verification operation after each programming voltage pulse including: Applying a verification reference voltage to the select word line, Applying an over-drive voltage to an unselected word line at a first ramp rate during a first set of programming cycles, and Applying the over-drive voltage to the unselected word line at a second ramp rate during a second set of programming cycles after the first set of programming cycles, the second ramp rate being lower than the first ramp rate.

17. The method according to claim 16, the method further comprising: Detecting completion of programming-verification for a first predetermined data state, and starting the second set of programming cycles in response to the detection.

18. The method according to claim 17, the method further comprising: Detecting completion of programming-verification for a second predetermined data state; and Applying an overdrive voltage to the unselected word lines at the first ramp rate during a third set of programming cycles, the third set of programming cycles being started in response to the detection.

19. The method according to claim 16, wherein: The first set of programming cycles and the second set of programming cycles are changed for different selected word lines.

20. The method according to claim 16, wherein: When the non-volatile memory draws the maximum current during the programming, applying the overdrive voltage at the second ramp rate is performed.

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