Parallel bit error rate detection method and device, medium and product

Abstract

The invention provides a parallel bit error rate detection method and device, a medium and a product, and belongs to the technical field of communication, and the method comprises the steps: detecting the bit error rate of a parallel signal of each channel, and obtaining the channel bit error rate; summarizing the channel bit error rates of all the channels to obtain a total bit error rate; wherein for each channel, the step of obtaining the channel bit error rate comprises the following steps: dividing a parallel signal of the channel into a plurality of first data segments according to a preset length; comparing the first data segment with a corresponding second data segment in a lookup table to obtain a comparison result of the first data segment; and calculating a channel error rate according to a comparison result of all the first data segments in the channel. According to the method, the bit error rates are independently counted in parallel in the multiple channels, the bit error rates of all the channels are summarized through the bus, data segmentation comparison is carried out on all the channels, the channel bit error rates are obtained, the bit error rate detection efficiency is improved through a double parallel processing mechanism, and the bit error rates of hundreds of parallel signals can be monitored in real time.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a parallel bit error rate detection method, apparatus, medium, and product. Background Art

[0002] Currently, most traditional bit error rate detection methods directly detect serial data, and these methods are effective in low-speed or low-concurrency scenarios. However, with the increase in data transmission rate and the demand for parallel detection, in high-speed communication systems, especially when multi-channel parallel transmission is involved, traditional bit error detection methods are difficult to cope with the rapid change of signal rate and high-concurrency data streams, resulting in poor bit error rate statistical efficiency. Summary of the Invention

[0003] This application provides a parallel bit error rate detection method, apparatus, medium, and product, aiming to solve the technical problem that traditional bit error detection methods are difficult to cope with the rapid change of signal rate and high-concurrency data streams, resulting in poor bit error rate statistical efficiency.

[0004] In a first aspect, this application provides a parallel bit error rate detection method, including: Detect the bit error rate of the parallel signals of each channel to obtain the channel bit error rate; wherein, the parallel signals of each channel are obtained when converting the serial input signal from serial to parallel; Summarize the channel bit error rates of all channels to obtain the total bit error rate; Wherein, for each channel, obtaining the channel bit error rate specifically includes: Divide the parallel signals of the channel into multiple first data segments according to a preset length; Compare the first data segment with the corresponding second data segment in the lookup table to obtain the comparison result of the first data segment; Calculate the channel bit error rate based on the comparison results of all first data segments in the channel.

[0005] As an embodiment, the bit error rate detection method further includes: When the signal flow in the channel is not in a stable state, adaptively adjust the bit error rate detection parameters of the channel according to the feedback data during the transmission of the signal flow in the channel.

[0006] As an embodiment, the bit error rate detection parameters include bit error rate detection sensitivity, detection window size, and error count threshold.

[0007] As an embodiment, the adjustment of the bit error rate detection sensitivity includes the adjustment of the bit error detection threshold, and the bit error detection threshold includes an amplitude decision threshold and a delay decision threshold.

[0008] As an embodiment, adjusting the amplitude decision threshold specifically includes: Calculate the real-time noise variance of the signal flow in the channel; Adjust the amplitude decision threshold of the channel according to the real-time noise variance.

[0009] As an embodiment, adjusting the delay decision threshold specifically includes: Calculate the real-time jitter variance of the signal flow in the channel; Adjust the delay decision threshold of the channel according to the real-time jitter variance.

[0010] As an embodiment, determining whether the signal flow in the channel is in a stable state specifically includes: Calculate the real-time noise mean and the real-time jitter mean of the signal flow in the channel respectively; Calculate the first ratio between the real-time noise mean and the historical noise mean; Calculate the second ratio between the real-time jitter mean and the historical jitter mean; If the first ratio is greater than the first ratio threshold and / or the second ratio is greater than the second ratio threshold, it is determined that the signal flow is not in a stable state.

[0011] As an embodiment, the adjustment of the bit error rate detection sensitivity specifically includes: Detect the signal strength of the signal flow in each channel and the signal strength error between two channels; If the maximum value of the signal strength error is greater than the error threshold, scan the amplitude noise of the high-speed counter on each channel, draw the amplitude-bit error rate bathtub curve, and determine the optimal value of the amplitude noise according to the amplitude-bit error rate bathtub curve as the amplitude decision threshold; Scan the local clock delay based on the amplitude decision threshold, draw the delay-bit error rate bathtub curve, and determine the optimal value of the timing jitter according to the delay-bit error rate bathtub curve as the delay decision threshold.

[0012] As an embodiment, adaptively adjusting the bit error rate detection parameters of the channel according to the feedback data specifically includes: Detect the characteristic data of the signal flow of the channel, and the characteristic data includes the number of bit errors, the code rate, the code element content, the jitter situation, the noise situation, and the bit error rate; Input the characteristic data into the user data model to obtain the bit error rate detection parameters matching the characteristic data; The user data model is trained based on a data set, and the data set includes the characteristic data of each channel and the adjustment strategy of the bit error rate detection parameters corresponding to the characteristic data.

[0013] As an embodiment, the training of the user data model includes: For each data stream rate, based on all the feature data in the dataset that has that data stream rate, multiple fitting curves are fitted to obtain the corresponding fitting functions. The independent variable of the fitting function is the feature data, and the dependent variable is the delay value; For each fitting function, select multiple groups of first feature data with the data stream rate from the dataset, input the multiple groups of first feature data into the fitting function respectively to obtain the delay values corresponding to each group of first feature data. Subsequently, set the hardware parameters of the communication system according to each delay value respectively, and obtain the first bit error rate error corresponding to each delay value during the operation of the communication system; Calculate the second bit error rate error of the fitting function based on all the first bit error rate errors of the fitting function; Take the fitting function with the minimum second bit error rate error as the fitting function corresponding to the data stream rate in the user data model; Select second feature data with the data stream rate from the dataset, use the fitting function to obtain the bit error rate detection parameter and clock synchronization parameter corresponding to the second feature data, and combine the second feature data, the corresponding bit error rate detection parameter and clock synchronization parameter into a template data, and store it in the database of the user data model.

[0014] As an embodiment, the bit error rate detection method further includes: Obtain the real-time clock phase of the serial input signal; Adjust the local clock phase to the real-time clock phase.

[0015] In a second aspect, the present application further provides a parallel bit error rate detection device, including a summary module and multiple channel detection modules; Each channel detection module is used to detect the bit error rate of the parallel signal of the corresponding channel to obtain the channel bit error rate; wherein, the parallel signal of each channel is obtained when converting the serial input signal from serial to parallel; The summary module is used to summarize the channel bit error rates of all channels to obtain the total bit error rate.

[0016] As an embodiment, the bit error rate detection device further includes an adaptive adjustment module, and the adaptive adjustment module is used to adaptively adjust the bit error rate detection parameter of the channel according to the feedback data during the transmission of the signal flow in the channel when the signal flow in the channel is not in a stable state.

[0017] In a third aspect, the present application further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements any one of the above-mentioned parallel bit error rate detection methods.

[0018] Fourthly, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements any of the above parallel bit error rate detection methods. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 is one of the flowcharts of the parallel bit error rate detection method provided by the present application; Figure 2 is another flowchart of the parallel bit error rate detection method provided by the present application; Figure 3 is the flowchart for determining whether the signal flow is in a stable state provided by the present application; Figure 4 is one of the flowcharts for adjusting the sensitivity of bit error rate detection provided by the present application; Figure 5 is the flowchart for adaptively adjusting the bit error rate detection parameters of the channel based on the feedback data provided by the present application; Figure 6 is the flowchart for dynamically synchronizing the clock provided by the present application; Figure 7 is the structural schematic diagram of the communication system provided by the present application; Figure 8 is one of the structural schematic diagrams of the parallel bit error rate detection device provided by the present application; Figure 9 is one of the structural schematic diagrams of the adaptive adjustment module provided by the present application. Detailed Embodiments

[0021] To make the objectives, technical solutions, and advantages of the present application clearer, the following will clearly and completely describe the technical solutions in the present application with reference to the drawings in the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0022] It should be noted that in the description of the present invention, the terms "comprise", "include" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0023] The terms "first", "second", etc. in the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category and do not limit the number of objects. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0024] The following Figures 1 to 9 describes the parallel bit error rate detection method, device, medium and product provided by the present application.

[0025] It should be noted that the parallel bit error rate detection method provided by the embodiments of the present application is implemented based on a parallel bit error rate detection device. The parallel bit error rate detection method adopts a parallel processing mechanism, can parallel process the bit error rate detection in multiple channels, and simultaneously process thousands of data streams in real time to ensure a high bit error rate statistical efficiency in the case of ultra-high concurrency in a high-speed communication system.

[0026] The embodiments of the present application describe the parallel bit error rate detection method by taking the parallel bit error rate detection device as the execution subject as an example.

[0027] Figure 1 is one of the flow diagrams of the parallel bit error rate detection method provided by the present application. Figure 2 is the second flow diagram of the parallel bit error rate detection method provided by the present application.

[0028] As Figure 1 shown, the parallel bit error rate detection method provided by the present application includes: S110: Detect the bit error rate of the parallel signals of each channel to obtain the channel bit error rate. Among them, the parallel signals of each channel are obtained when converting the serial input signal from serial to parallel.

[0029] It should be noted that the bit error rate detection of each channel is independent of each other.

[0030] S120: Aggregate the channel bit error rates of all channels to obtain the total bit error rate.

[0031] Please combine Figure 2 In the embodiments of the present application, first, the serial input signal is converted from serial to parallel to obtain multiple parallel signals, thereby forming multiple parallel channels. Subsequently, the bit error rate within each channel is statistically calculated in parallel and independently as the channel bit error rate. Finally, based on the channel bit error rates of all channels, aggregation is performed to obtain the total bit error rate.

[0032] In one possible embodiment, the total bit error rate can be calculated by calculating the average value or weighted sum of all channel bit error rates.

[0033] Specifically, in the embodiments of the present application, the parallel bit error rate detection device detects the bit error rate of the parallel signal of each channel to obtain the channel bit error rate; subsequently, the parallel bit error rate detection device aggregates the channel bit error rates of all channels through the data bus to obtain the total bit error rate.

[0034] As an embodiment, the architecture of the present application can support high-speed signal transmission at a data rate of 64 Gb / s or higher, meeting the requirements of ultra-high-speed data communication.

[0035] The embodiments of the present application independently and parallelly process bit error data in multiple channels, realizing real-time statistics of the bit error rate of multiple channels, and aggregating the bit error rate of each channel through the bus. This architecture supports real-time monitoring of the bit error rate of hundreds or thousands of parallel signals without significant performance degradation, improving the high-speed performance of bit error rate detection.

[0036] In one possible embodiment, a pipelined architecture is adopted to achieve fast data transmission and calculation through memory caching and the data bus. The pipelined architecture is a technology that decomposes complex tasks into multiple independent subtasks and allows these subtasks to be executed simultaneously at different stages. The core idea of this architecture is to split a large task into multiple small, sequentially executed stages, and different tasks can be processed simultaneously at different stages, thereby improving the overall processing speed and throughput of the system.

[0037] In step S110, the bit error rate of the parallel signal of each channel is detected to obtain the channel bit error rate.

[0038] In one possible embodiment, for each channel, obtaining the channel bit error rate specifically includes: S1101: Divide the parallel signal of this channel into multiple first data segments according to a preset length.

[0039] Specifically, each parallel signal is sequentially divided into first data segments of a preset length according to the data bits.

[0040] S1102: Compare the first data segment with the corresponding second data segment in the lookup table to obtain the comparison result of the first data segment.

[0041] Each channel corresponds to a lookup table. The length of each second data segment stored at each position in the lookup table is also a preset length, and each second data segment in the lookup table corresponds uniquely to a first data segment.

[0042] In a possible embodiment, by comparing the first data segment and the second data segment, error code data is obtained, and this error code data is used as the comparison result.

[0043] S1103: Calculate the channel bit error rate based on the comparison results of all the first data segments in the channel. Thus, by collecting and summarizing the error code data of each channel, the bit error rate calculation of the input signal is achieved.

[0044] Specifically, when the parallel bit error rate detection device obtains the channel bit error rate, first divide the parallel signal of the channel into multiple first data segments according to the preset length. Then compare the first data segment with the corresponding second data segment in the lookup table to obtain the comparison result of the first data segment. Finally, statistically calculate the channel bit error rate based on the comparison results of all the first data segments.

[0045] In the embodiment of the present application, the parallel signal of each channel is divided into data segments with equal length and compared with the corresponding data segments in the lookup table to ensure that real-time comparison results can be output in each clock cycle. Subsequently, the comparison results of all data segments are statistically calculated to obtain the channel bit error rate, and the dual parallel processing mechanism can further improve the bit error rate statistical efficiency.

[0046] In a high-speed communication environment, various factors such as the network environment and device status are changing in real time. On this basis, using a fixed bit error rate detection strategy cannot adapt to this change, resulting in a decrease in the accuracy of bit error rate detection.

[0047] Based on such considerations, on the above basis, in a possible embodiment, the bit error rate detection method provided by the present application further includes: S130: Adaptively adjust the bit error rate detection parameters of the channel according to the feedback data during the transmission of the signal flow in the channel.

[0048] Specifically, after the parallel bit error rate detection device dynamically adjusts the bit error rate detection parameters of the channel, execute steps S110 and S120 according to the adjusted bit error rate detection parameters.

[0049] In the embodiment of the present application, the bit error rate detection parameters of each channel are independently adjusted through the feedback data during the transmission of the signal flow, so that each channel has a flexible adaptability to improve the bit error rate detection quality of each channel.

[0050] In a possible embodiment, in step S130, the bit error rate detection parameters of the channel are adaptively adjusted according to the feedback data during the transmission of the signal flow in the channel, specifically including: S1301: Determine whether the signal flow is in a stable state based on the feedback data during the transmission of the signal flow in the channel.

[0051] Specifically, the parallel bit error rate detection devices continuously collect various feedback data during the transmission of the signal flow in each channel, including but not limited to key indicators such as signal strength, noise level, timing jitter, transmission rate, etc., and determine whether the signal flow is in a stable state based on this feedback data, so as to adjust the error detection parameters accordingly.

[0052] S1302: If the signal flow is not in a stable state, adaptively adjust the bit error rate detection parameters of the channel according to the analysis result of the feedback data. The bit error rate detection parameters include bit error rate detection sensitivity, detection window size, error count threshold, etc.

[0053] For example, on a channel with high noise, increase the frequency and sensitivity of bit error rate detection to capture smaller errors; while on a channel with better signal quality, reduce the sensitivity to improve detection efficiency.

[0054] In the embodiment of the present application, the stability of the signal flow is judged through the feedback data, and the bit error rate detection parameters are dynamically adjusted when the signal flow is unstable, ensuring the stable transmission of the signal flow, providing a basis for the stability and accuracy of bit error rate detection. Moreover, in the embodiment of the present application, the adjustment strategies of the bit error rate detection parameters of different channels are independent of each other, which can significantly reduce the errors caused by the data rate differences of different channels and ensure that the bit error rate statistical results of each channel are accurate.

[0055] In a possible embodiment, as Figure 3 shown, in step S1301, determining whether the signal flow is in a stable state based on the feedback data during the transmission of the signal flow in the channel specifically includes: S310: Calculate the real-time noise mean and real-time jitter mean of the signal flow in the channel respectively to understand the average state of the signal flow; S320: Calculate the first ratio between the real-time noise mean and the historical noise mean. The smaller the first ratio, the more stable the noise of the signal flow.

[0056] S330: Calculate the second ratio between the real-time jitter mean and the historical jitter mean. The smaller the second ratio, the more stable the jitter of the signal flow.

[0057] S340: If the first ratio is greater than the first ratio threshold and / or the second ratio is greater than the second ratio threshold, it is determined that the signal flow is not in a stable state. If the first ratio is less than or equal to the first ratio threshold and the second ratio is less than or equal to the second ratio threshold, it is determined that the signal flow is in a stable state.

[0058] When both the first ratio and the second ratio are within the corresponding ratio thresholds, it indicates that both the noise and jitter of the signal flow are within the allowable range, and the signal flow is stable. Otherwise, the noise or jitter of the signal flow is greater than the allowable value, and the signal flow is unstable.

[0059] Noise and jitter affect the quality of the signal flow. Therefore, in the embodiments of the present application, the stability of the signal flow can be accurately judged by the degree of similarity between the noise mean and jitter mean and the historical means.

[0060] In a possible embodiment, the adjustment of the bit error rate detection sensitivity includes the adjustment of the bit error detection threshold, and the bit error detection threshold includes an amplitude decision threshold and a delay decision threshold. The amplitude decision threshold and the delay decision threshold are set in the high-speed counter of the communication system and are used to determine whether the noise amplitude and delay exceed the allowable range. For the signal within the enclosed range of the amplitude decision threshold and the delay decision threshold, its signal strength is stable and the bit error rate detection is accurate.

[0061] Specifically, noise interferes with the signal in the vertical amplitude, and the jitter of the signal flow is a short-term deviation phenomenon of the signal edge relative to its ideal position in the time domain, which reflects the signal delay. Therefore, noise and jitter have a greater impact on the quality of the signal flow, and the amplitude decision threshold related to noise and the delay decision threshold related to jitter have a greater impact on the bit error rate detection sensitivity. The larger the area enclosed by the two end values of the amplitude decision threshold and the two end values of the delay decision threshold, the shorter the time required to statistically detect bit error data, the higher the feedback efficiency of the signal flow, and ultimately the faster the dynamic clock locking.

[0062] In the embodiments of the present application, the bit error rate detection sensitivity is adjusted by adjusting the amplitude decision threshold and the delay decision threshold to ensure that the bit error rate detection sensitivity can quickly adapt to the real-time changes of the signal flow.

[0063] In a possible embodiment, the adjustment of the amplitude decision threshold specifically includes: Q1: Calculate the real-time noise variance of the signal flow in the channel.

[0064] Q2: Adjust the amplitude decision threshold of the channel according to the real-time noise variance.

[0065] The real-time noise variance is used to measure the degree of dispersion of the noise feedback data of the signal flow, and is used to reflect the degree of signal flow fluctuation caused by noise.

[0066] In a possible embodiment, when the real-time noise variance is greater than the first variance threshold, the amplitude decision threshold is shifted towards the center direction, making it easier to detect error-coded data and improving the sensitivity of the error rate detection. When the real-time noise variance is less than or equal to the second variance threshold, the amplitude decision threshold is shifted towards the upper and lower sides, reducing the range of error-coded data and lowering the sensitivity of the error rate detection.

[0067] In the embodiment of the present application, the amplitude decision threshold of the channel is adjusted according to the real-time noise variance, and the amplitude decision threshold can be quickly adjusted by accurately grasping the influence of noise on the signal flow fluctuation, so as to reduce false alarms and missed alarms during error rate detection.

[0068] In a possible embodiment, adjusting the delay decision threshold specifically includes: R1: Calculate the real-time jitter variance of the signal flow in the channel.

[0069] R2: Adjust the delay decision threshold of the channel according to the real-time jitter variance.

[0070] The real-time jitter variance is used to measure the dispersion degree of the jitter feedback data of the signal flow, reflecting the signal flow fluctuation degree caused by jitter.

[0071] In a possible embodiment, when the real-time jitter variance is greater than the third variance threshold, the delay decision threshold is shifted towards the center direction, making it easier to detect error-coded data and improving the sensitivity of the error rate detection. When the real-time jitter variance is less than or equal to the fourth variance threshold, the delay decision threshold is shifted towards the left and right sides, reducing the range of error-coded data and lowering the sensitivity of the error rate detection.

[0072] In the embodiment of the present application, the delay decision threshold of the channel is adjusted according to the real-time jitter variance, and the delay decision threshold can be quickly adjusted by accurately grasping the influence of jitter on the signal flow fluctuation, so as to reduce false alarms and missed alarms during error rate detection.

[0073] In another possible embodiment, as Figure 4 shown, the adjustment of the error rate detection sensitivity specifically includes: S410: Detect the signal strength of the signal flow in each channel and the signal strength error between two channels.

[0074] A high-speed counter is set on each parallel channel. The high-speed counter is used to measure the signal strength and carrier frequency of the parallel signals in each channel. When there is a large error in the signal strength detected by multiple high-speed counters, it indicates that the noise level or timing jitter of the signal is large.

[0075] S420: If the maximum value of the signal strength error is greater than the error threshold, scan the amplitude noise of the high-speed counter on each channel, plot the amplitude-bit error rate bathtub curve, and determine the optimal value of the amplitude noise based on the amplitude-bit error rate bathtub curve as the amplitude decision threshold.

[0076] The shape of the bathtub curve is high at both ends and low in the middle, resembling a bathtub, so it is called the "bathtub curve". The critical points between the two high and low positions on the amplitude-bit error rate bathtub curve can be used as the optimal value of the amplitude noise, and these two critical points are used as the amplitude decision threshold.

[0077] S430: Scan the local clock delay based on the amplitude decision threshold, plot the delay-bit error rate bathtub curve, and determine the optimal value of the timing jitter based on the delay-bit error rate bathtub curve as the delay decision threshold.

[0078] Similarly, the critical points between the two high and low positions on the delay-bit error rate bathtub curve can be used as the optimal value of the timing jitter, and these two critical points are used as the delay decision threshold.

[0079] The embodiments of the present application respectively use the bathtub curves obtained in real time to determine the amplitude decision threshold and the delay decision threshold, thereby accurately and adaptively adjusting the sensitivity of the bit error rate detection.

[0080] In another possible embodiment, as Figure 5 shown, adaptively adjust the bit error rate detection parameters of the channel according to the feedback data, specifically including: S510: Detect the characteristic data of the signal flow of the channel, and the characteristic data includes the code rate, code element content, jitter situation, noise situation, and bit error rate.

[0081] S520: Input the characteristic data into the user data model to obtain the bit error rate detection parameters and clock synchronization parameters that match the characteristic data.

[0082] The user data model is trained based on a data set. The data set includes the characteristic data of each channel (including but not limited to the number of bit errors, bit error rate, code rate, code element content, noise situation, jitter situation) and the bit error rate detection parameters and dynamic clock synchronization adjustment strategies corresponding to the characteristic data. This user data model not only reflects the network environment, device configuration, and transmission quality, but also contains the potential laws and trends of bit error generation, providing a solid foundation for subsequent data analysis and algorithm optimization.

[0083] The embodiments of the present application accumulate the data set and the user data model, and directly obtain the bit error rate detection parameters and clock synchronization parameters that match the characteristic data of the current signal flow through the user data model, realizing fast and accurate adaptive adjustment of the bit error rate detection parameters and clock synchronization, and ensuring the accuracy and stability of the bit error rate detection and clock synchronization.

[0084] In a possible embodiment, training the user data model includes: P1: For each data stream rate, based on all the feature data with this data stream rate in the dataset, fit multiple fitting curves to obtain the corresponding fitting functions. The independent variable of the fitting function is the feature data, and the dependent variable is the delay value.

[0085] In a possible embodiment, the multiple fitting curves include fitting curves in exponential form, linear form, logarithmic form, polynomial form, etc.

[0086] In a possible embodiment, the least squares method or other regression analysis algorithms can be used to fit the curves.

[0087] P2: For each fitting function, select multiple groups of first feature data with this data stream rate from the dataset, input the multiple groups of first feature data into the fitting function respectively to obtain the delay values corresponding to each group of first feature data. Subsequently, set the hardware parameters of the communication system according to each delay value respectively, and obtain the first bit error rate error corresponding to each delay value during the operation of the communication system.

[0088] P3: Calculate the second bit error rate error of the fitting function based on all the first bit error rate errors of the fitting function.

[0089] P4: Take the fitting function with the minimum second bit error rate error as the fitting function corresponding to this data stream rate in the user data model.

[0090] P5: Select second feature data with the data stream rate from the dataset, use the fitting function to obtain the bit error rate detection parameter and clock synchronization parameter corresponding to the second feature data, and combine the second feature data, the corresponding bit error rate detection parameter and clock synchronization parameter into a piece of template data, which is stored in the database of the user data model.

[0091] Based on the above, in a possible embodiment, when using the user data model, the current signal stream feature data of the channel can be input into the user data model, and the bit error rate detection parameter and clock synchronization parameter corresponding to the output data of the fitting function are obtained by using the fitting function corresponding to the current data stream rate, and used as the target values of the bit error rate detection parameter and clock synchronization parameter of this channel.

[0092] In another possible embodiment, after the current feature data is input into the user data model, the user data model first finds template data with the same or similar jitter and noise conditions and the same or similar bit error rate under the same code rate and the same code element content. At this time, the current environment is basically the same as the historical environment corresponding to this data. Then, the bit error rate detection parameters (including amplitude decision threshold, delay decision threshold, etc.) and clock synchronization parameters corresponding to the template data are used as the current adaptively adjusted bit error rate detection parameters and clock synchronization parameters to improve the adjustment efficiency of the bit error rate detection parameters.

[0093] In the embodiments of the present application, a fitting function corresponding to each data stream rate is fitted using a data set, and bit error rate detection parameters and clock synchronization parameters corresponding to each group of feature data are obtained based on the fitting function, thereby providing a basis for quickly determining the bit error rate detection parameters and clock synchronization parameters corresponding to the current data stream subsequently. This mechanism is based on long-term accumulated user data, and optimizes the synchronization algorithm and bit error detection process by intelligently analyzing and adjusting the model. It can improve the synchronization accuracy and bit error detection ability under various device and network conditions through "learning", so as to ensure that the system can maintain the optimal performance in a complex and changing network environment.

[0094] In another possible embodiment, as Figure 6 shown, the bit error rate detection method further includes dynamically synchronizing the clock, specifically including: S610: Obtain the real-time clock phase of the serial input signal; S620: Adjust the local clock phase to the real-time clock phase to calibrate and correct the clock signal in real time.

[0095] In a possible embodiment, digital phase-locked loop technology is used to achieve real-time dynamic adjustment of the local clock, ensuring that the communication system can still maintain high-precision synchronization in the case of frequent signal changes or delays.

[0096] As Figure 7 shown, a delay-locked loop (DLL, a digital phase-locked loop technology) includes a frequency divider and a phase detector. The output signal of the digital phase-locked loop is input into a field programmable gate array (FPGA) through a filter and an analog-to-digital converter. The frequency divider is used to divide the input signal frequency to solve the problem that the frequency of the input signal exceeds the frequency range of the phase detector. The phase detector is used to compare the phase of the output signal of the frequency divider with the phase of the local clock. The FPGA dynamically adjusts the phase of the local clock based on the error between the two phases to keep the phase of the local clock synchronized with the output signal of the frequency divider.

[0097] In the embodiments of the present application, the synchronous clock is intelligently adjusted according to the change of the real-time data stream rate to ensure precise synchronization between channels. This synchronization mechanism can dynamically optimize the synchronization signal according to the characteristics of signal changes, eliminating the clock drift problem in traditional static synchronization, thereby greatly improving the accuracy and efficiency of error code detection.

[0098] Based on the above, the system in the embodiments of the present application realizes asynchronous data stream processing through dynamic clock synchronization and pipelined parallel bit error rate detection mechanism, ensuring synchronization even in high parallelism situations and avoiding clock offset and data delay problems caused by multi-channel parallelism. This high-efficiency parallel processing ability is particularly suitable for the bit error rate detection requirements of high-speed large-scale parallel data streams, and this solution has good scalability and can support parallel processing of more channels in the future to meet the requirements of higher concurrency and higher-speed data stream processing. In addition, the dynamic adjustment mechanism in the embodiments of the present application dynamically adjusts the algorithm of the synchronous clock, the threshold of error code statistics, and the strategy of error code detection according to the comprehensive analysis results of historical data and real-time data, can flexibly cope with different signal conditions, and adapt to a wide range of application scenarios, including ultra-high-speed communication devices, optical fiber communication, data center devices, etc. In particular, when the system detects that there is a clock synchronization drift problem in a certain channel under a specific environment, it will quickly start the adaptive adjustment mechanism to finely adjust the clock calibration parameters of this channel to ensure that the accuracy of error code detection is not affected.

[0099] Figure 7 The schematic structural diagram of a communication system based on the above parallel bit error rate detection method is shown. As Figure 7 shown, the communication system includes multiple data splitters, serial-to-parallel conversion circuits, and FPGAs. The serial-to-parallel conversion circuit converts the input signal into multiple parallel signals, and each parallel signal corresponds to one channel. The data splitter copies the input signal intact into multiple outputs, and each path is used to implement different signal acquisition functions. The FPGA is used to execute the above parallel bit error rate detection method, calculate the corresponding bit error rate, frequency, etc. based on the received data, and realize the dynamic synchronization and parallel bit error rate detection of high-speed signals.

[0100] In Figure 7 the shown example, the serial-to-parallel conversion circuit converts the input signal into two parallel signals, and each parallel signal is divided into two paths by the data splitter. One path is directly connected to the FPGA signal to collect the error code data of this channel; the other path collects the signal strength and carrier frequency of this channel through a high-speed counter and transmits them to the FPGA.

[0101] Based on the above, the present application also provides a parallel bit error rate detection device. The parallel bit error rate detection device and the above parallel bit error rate detection method can be correspondingly referred to each other.

[0102] In a possible embodiment, the parallel bit error rate detection device includes Figure 7 the FPGA in

[0103] As an embodiment, as Figure 8 shown, the parallel bit error rate detection device includes a summarization module 820 and a plurality of channel detection modules 810.

[0104] Each channel detection module 810 is used to detect the bit error rate of the parallel signal of the corresponding channel and obtain the channel bit error rate. Among them, the parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel.

[0105] The summarization module 820 is used to summarize the channel bit error rates of all channels to obtain the total bit error rate.

[0106] In the embodiment of the present application, the bit error data is independently and parallelly processed in multiple channels to realize real-time statistics of the bit error rate of multiple channels, and the bit error rate of each channel is summarized through a bus. This architecture supports real-time monitoring of the bit error rate of hundreds or thousands of parallel signals without causing significant performance degradation, improving the high-speed performance of bit error rate detection.

[0107] In a possible embodiment, the channel detection module 810 is specifically used for: Dividing the parallel signal of the channel into multiple first data segments according to a preset length; Comparing the first data segment with the corresponding second data segment in the look-up table to obtain the comparison result of the first data segment; Calculating the channel bit error rate based on the comparison results of all the first data segments in the channel.

[0108] In the embodiment of the present application, the parallel signal of each channel is divided into data segments of equal length and compared in parallel to ensure that real-time comparison results can be output in each clock cycle. Subsequently, the comparison results of all data segments are statistically analyzed to obtain the channel bit error rate. The dual parallel processing mechanism can further improve the efficiency of bit error rate statistics.

[0109] In a possible embodiment, the parallel bit error rate detection device further includes an adaptive adjustment module 830, and the adaptive adjustment module 830 is used to adaptively adjust the bit error rate detection parameters of the channel according to the feedback data during the transmission of the signal flow in the channel.

[0110] In the embodiment of the present application, the bit error rate detection parameters of each channel are independently adjusted through the feedback data during the transmission of the signal flow, so that each channel has flexible adaptability to improve the bit error rate detection quality of each channel.

[0111] In a possible embodiment, as Figure 9As shown, the adaptive adjustment module 830 includes a status judgment module 8301 and a detection parameter adjustment module 8302.

[0112] The status judgment module 8301 is used to judge whether the signal flow is in a stable state based on the feedback data during the transmission of the signal flow in the channel; The detection parameter adjustment module 8302 is used to adaptively adjust the error rate detection parameters of the channel according to the analysis result of the feedback data when the signal flow is not in a stable state. The error rate detection parameters include error rate detection sensitivity, detection window size, and error count threshold.

[0113] In the embodiment of the present application, the stability of the signal flow is judged through the feedback data, and the error rate detection parameters are dynamically adjusted when the signal flow is unstable, ensuring the stable transmission of the signal flow and providing a basis for the stability and accuracy of the error rate detection. Moreover, in the embodiment of the present application, the adjustment strategies of the error rate detection parameters of different channels are independent of each other, which can significantly reduce the error caused by the data rate difference of different channels and ensure that the error rate statistical results of each channel are accurate.

[0114] In a possible embodiment, the adjustment of the error rate detection sensitivity includes the adjustment of the error detection threshold, and the error detection threshold includes an amplitude decision threshold and a delay decision threshold.

[0115] In the embodiment of the present application, the error rate detection sensitivity is adjusted by adjusting the amplitude decision threshold and the delay decision threshold, ensuring that the error rate detection sensitivity can quickly adapt to the real-time changes of the signal flow.

[0116] In a possible embodiment, the detection parameter adjustment module 8302 is specifically used for: Calculating the real-time noise variance of the signal flow in the channel; Adjusting the amplitude decision threshold of the channel according to the real-time noise variance.

[0117] In the embodiment of the present application, the amplitude decision threshold of the channel is adjusted according to the real-time noise variance, which can quickly adjust the amplitude decision threshold by accurately grasping the influence of noise on the signal flow fluctuation, so as to reduce false alarms and missed reports during error rate detection.

[0118] In a possible embodiment, the detection parameter adjustment module 8302 is also specifically used for: Calculating the real-time jitter variance of the signal flow in the channel; Adjusting the delay decision threshold of the channel according to the real-time jitter variance.

[0119] In the embodiment of the present application, the delay decision threshold of the channel is adjusted according to the real-time jitter variance, which can quickly adjust the delay decision threshold by accurately grasping the influence of jitter on the signal flow fluctuation, so as to reduce false alarms and missed reports during error rate detection.

[0120] In a possible embodiment, the state judgment module 8301 is specifically configured to: Calculate the real-time noise mean and the real-time jitter mean of the signal flow in the channel respectively; Calculate the first ratio between the real-time noise mean and the historical noise mean; Calculate the second ratio between the real-time jitter mean and the historical jitter mean; If the first ratio is greater than the first ratio threshold and / or the second ratio is greater than the second ratio threshold, it is determined that the signal flow is not in a stable state.

[0121] In the embodiment of the present application, the stability of the signal flow can be accurately judged by the proximity of the noise mean and the jitter mean to the historical means.

[0122] In a possible embodiment, the detection parameter adjustment module 8302 is further specifically configured to: Detect the signal strength of the signal flow in each channel and the signal strength error between two channels; If the maximum value of the signal strength error is greater than the error threshold, scan the amplitude noise of the high-speed counter on each channel, draw an amplitude-bit error rate bathtub curve, and determine the optimal value of the amplitude noise based on the amplitude-bit error rate bathtub curve as the amplitude decision threshold; Scan the local clock delay based on the amplitude decision threshold, draw a delay-bit error rate bathtub curve, and determine the optimal value of the timing jitter based on the delay-bit error rate bathtub curve as the delay decision threshold.

[0123] In the embodiment of the present application, the amplitude decision threshold and the delay decision threshold are respectively determined by using the bathtub curves obtained in real time, so as to accurately and adaptively adjust the sensitivity of the bit error rate detection.

[0124] In a possible embodiment, the detection parameter adjustment module 8302 is further specifically configured to: Detect the characteristic data of the signal flow of the channel, where the characteristic data includes the code rate, the symbol content, the jitter situation, the noise situation, and the bit error rate; Input the characteristic data into the user data model to obtain the bit error rate detection parameters matching the characteristic data; The user data model is trained based on a data set, and the data set includes the characteristic data of each channel and the adjustment strategy of the bit error rate detection parameters corresponding to the characteristic data.

[0125] In the embodiment of the present application, by accumulating the user data set and the user data model, the bit error rate detection parameters matching the characteristic data of the current signal flow can be directly obtained through the user data model, realizing the fast and accurate adaptive adjustment of the bit error rate detection parameters and the clock synchronization, as well as the accuracy and stability of the bit error rate detection.

[0126] In a possible embodiment, the parallel bit error rate detection device further includes a training module, and the training module is configured to: For each data stream rate, based on all the feature data in the data set having that data stream rate, fit multiple fitting curves to obtain corresponding fitting functions, where the independent variable of the fitting function is the feature data and the dependent variable is the delay value; For each fitting function, select multiple groups of first feature data having the data stream rate from the data set, input the multiple groups of first feature data into the fitting function respectively to obtain the delay value corresponding to each group of first feature data, and then set the hardware parameters of the communication system according to each delay value respectively. During the operation of the communication system, obtain the first bit error rate error corresponding to each delay value; Calculate the second bit error rate error of the fitting function based on all the first bit error rate errors of the fitting function; Take the fitting function with the minimum second bit error rate error as the fitting function corresponding to the data stream rate in the user data model; Select second feature data having the data stream rate from the data set, use the fitting function to obtain the bit error rate detection parameter and the clock synchronization parameter corresponding to the second feature data, and combine the second feature data, the corresponding bit error rate detection parameter and the clock synchronization parameter into a template data and store it in the database of the user data model.

[0127] In the embodiment of the present application, fitting functions corresponding to each data stream rate are fitted using the data set, and bit error rate detection parameters and clock synchronization parameters corresponding to each group of feature data are obtained based on the fitting functions, thereby providing a basis for quickly determining the bit error rate detection parameters and clock synchronization parameters corresponding to the current data stream subsequently. This mechanism is based on long-term accumulated user data, and optimizes the synchronization algorithm and bit error detection process by intelligently analyzing and adjusting the model, and can improve the synchronization accuracy and bit error detection ability under various device and network conditions through "learning", so as to ensure that the system can maintain the optimal performance in a complex and changing network environment.

[0128] In a possible embodiment, the parallel bit error rate detection further includes a dynamic clock synchronization module, and the dynamic clock synchronization module is configured to: Obtain the real-time clock phase of the serial input signal; Adjust the local clock phase to the real-time clock phase.

[0129] In the embodiment of the present application, the synchronization clock is intelligently adjusted according to the change of the real-time data stream rate to ensure precise synchronization between each channel. This synchronization mechanism can dynamically optimize the synchronization signal according to the characteristics of the signal change, eliminate the clock drift problem in the traditional static synchronization, and thus greatly improve the accuracy and efficiency of bit error detection.

[0130] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the parallel bit error rate detection method provided in each of the above embodiments. The method includes: detecting the bit error rate of the parallel signals of each channel to obtain the channel bit error rate; summarizing the channel bit error rates of all channels to obtain the total bit error rate; Among them, for each channel, obtaining the channel bit error rate specifically includes: dividing the parallel signals of the channel into multiple first data segments according to a preset length; comparing the first data segments with the corresponding second data segments in the lookup table to obtain the comparison results of the first data segments; calculating the channel bit error rate based on the comparison results of all the first data segments in the channel.

[0131] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is configured to execute the parallel bit error rate detection method provided in each of the above embodiments. The method includes: detecting the bit error rate of the parallel signals of each channel to obtain the channel bit error rate; summarizing the channel bit error rates of all channels to obtain the total bit error rate; Among them, for each channel, obtaining the channel bit error rate specifically includes: dividing the parallel signals of the channel into multiple first data segments according to a preset length; comparing the first data segments with the corresponding second data segments in the lookup table to obtain the comparison results of the first data segments; calculating the channel bit error rate based on the comparison results of all the first data segments in the channel.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0133] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solutions, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0134] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a read-only memory (ROM) / random access memory (RAM), magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A parallel bit error rate detection method, characterized in that Including: Detecting the bit error rate of the parallel signals of each channel to obtain the channel bit error rate; wherein, the parallel signals of each channel are obtained when converting the serial input signal from serial to parallel; Summarizing the channel bit error rates of all channels to obtain the total bit error rate; Among them, for each channel, obtaining the channel bit error rate specifically includes: Dividing the parallel signals of the channel into multiple first data segments according to a preset length; Comparing the first data segment with the corresponding second data segment in the look-up table to obtain the comparison result of the first data segment; Calculating the channel bit error rate based on the comparison results of all the first data segments in the channel.

2. The parallel bit error rate detection method according to claim 1, wherein The bit error rate detection method further includes: When the signal flow in the channel is not in a stable state, adaptively adjusting the bit error rate detection parameters of the channel according to the feedback data during the transmission of the signal flow in the channel.

3. The parallel bit error rate detection method according to claim 2, characterized in that, The bit error rate detection parameters include bit error rate detection sensitivity, detection window size, and error counting threshold.

4. The parallel bit error rate detection method according to claim 3, wherein Adjusting the bit error rate detection sensitivity includes adjusting the bit error detection threshold, and the bit error detection threshold includes amplitude decision threshold and delay decision threshold.

5. The parallel bit error rate detection method according to claim 4, wherein, Adjusting the amplitude decision threshold specifically includes: Calculating the real-time noise variance of the signal flow in the channel; Adjusting the amplitude decision threshold of the channel according to the real-time noise variance.

6. The parallel bit error rate detection method according to claim 4, characterized in that, Adjusting the delay decision threshold specifically includes: Calculating the real-time jitter variance of the signal flow in the channel; Adjusting the delay decision threshold of the channel according to the real-time jitter variance.

7. The parallel bit error rate detection method according to claim 2, wherein Judging whether the signal flow in the channel is in a stable state specifically includes: Respectively calculating the real-time noise mean and real-time jitter mean of the signal flow in the channel; Calculating a first ratio between the real-time noise mean and the historical noise mean; Calculating a second ratio between the real-time jitter mean and the historical jitter mean; If the first ratio is greater than the first ratio threshold and / or the second ratio is greater than the second ratio threshold, it is determined that the signal flow is not in a stable state.

8. The parallel bit error rate detection method according to claim 4, wherein Adjusting the bit error rate detection sensitivity specifically includes: Detecting the signal strength of the signal flow in each channel and the signal strength error between two channels; If the maximum value of the signal strength error is greater than the error threshold, scanning the amplitude noise of the high-speed counter on each channel, drawing an amplitude-bit error rate bathtub curve, and determining the optimal amplitude noise value based on the amplitude-bit error rate bathtub curve as the amplitude decision threshold; Scanning the local clock delay based on the amplitude decision threshold, drawing a delay-bit error rate bathtub curve, and determining the optimal timing jitter value based on the delay-bit error rate bathtub curve as the delay decision threshold.

9. The parallel bit error rate detection method according to claim 2, characterized in that Adapting to adjust the bit error rate detection parameters of the channel according to the feedback data specifically includes: Detecting the characteristic data of the signal flow of the channel, and the characteristic data includes the number of bit errors, code rate, code element content, jitter situation, noise situation, and bit error rate; Inputting the characteristic data into the user data model to obtain the bit error rate detection parameters matching the characteristic data; The user data model is trained based on a data set, and the data set includes feature data of each channel and an adjustment strategy for bit error rate detection parameters corresponding to the feature data.

10. The parallel bit error rate detection method according to claim 9, characterized in that, Training the user data model includes: For each data stream rate, based on all the feature data in the data set having that data stream rate, multiple fitting curves are fitted to obtain corresponding fitting functions, where the independent variable of the fitting function is the feature data and the dependent variable is the delay value; For each fitting function, multiple groups of first feature data having the data stream rate are selected from the data set, the multiple groups of first feature data are respectively input into the fitting function to obtain delay values corresponding to each group of first feature data, and then the hardware parameters of the communication system are set according to each delay value respectively, and first bit error rate errors corresponding to each delay value are obtained during the operation of the communication system; Calculating the second bit error rate error of the fitting function based on all the first bit error rate errors of the fitting function; Taking the fitting function with the smallest second bit error rate error as the fitting function corresponding to the data stream rate in the user data model; Selecting second feature data having the data stream rate from the data set, obtaining bit error rate detection parameters and clock synchronization parameters corresponding to the second feature data by using the fitting function, and combining the second feature data, the corresponding bit error rate detection parameters and clock synchronization parameters into a template data, and storing it in the database of the user data model.

11. The parallel bit error rate detection method according to claim 1 or 2, characterized in that The bit error rate detection method further includes: Obtaining the real-time clock phase of the serial input signal; Adjusting the local clock phase to the real-time clock phase.

12. A parallel bit error rate detection device, characterized in that, It includes a summarization module and multiple channel detection modules; Each of the channel detection modules is used to detect the bit error rate of the parallel signal of the corresponding channel to obtain the channel bit error rate; wherein, the parallel signal of each channel is obtained when the serial input signal is converted from serial to parallel; The summarization module is used to summarize the channel bit error rates of all channels to obtain the total bit error rate.

13. The parallel bit error rate detection device according to claim 12, wherein The bit error rate detection device further includes an adaptive adjustment module, and the adaptive adjustment module is used to adaptively adjust the bit error rate detection parameters of the channel according to the feedback data during the transmission of the signal flow in the channel when the signal flow in the channel is not in a stable state.

14. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the parallel bit error rate detection method according to any one of claims 1 to 11.

15. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the parallel bit error rate detection method according to any one of claims 1 to 11.

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