Carbon nanotube field effect transistor comprising gate dielectric substrate layer and preparation method

Abstract

The invention discloses a carbon nanotube field effect transistor containing a gate dielectric substrate layer and a preparation method. The carbon nanotube field effect transistor with a top gate structure comprises a substrate, the gate dielectric substrate layer, a semiconductor carbon nanotube film, a source metal electrode, a drain metal electrode, a gate dielectric layer and a gate electrode. A'gate dielectric substrate layer 'is introduced below a carbon nanotube film, and a sandwich device structure of'gate dielectric substrate layer / CNT / gate dielectric layer' is constructed. By means of the pore structure between the gate dielectric substrate layer and the carbon nanotube film, a stable, uniform and consistent nucleation environment can be provided, the deposition quality of the gate dielectric is remarkably improved, the gate electric field control capability is enhanced, and the switching performance and the working stability of a device are improved.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and further relates to a carbon nanotube field effect transistor including a gate dielectric substrate layer and a preparation method thereof in the field of semiconductor device technology. By optimizing the gate dielectric substrate structure, the present invention can be widely applied to the manufacture of carbon nanotube thin film transistors with high requirements for electrical performance stability, gate control ability and dielectric quality, and is particularly suitable for emerging application fields of high-performance logic devices, low-power integrated circuits, flexible electronics and wearable devices. Background Art

[0002] Due to its unique semiconductor properties, high carrier mobility and one-dimensional quantum confinement effect, carbon nanotubes reduce electron scattering, thereby improving the switching speed and energy efficiency of field effect transistors. At the same time, its excellent thermal conductivity helps the device to dissipate heat and improve stability, while the nanoscale size is suitable for ultra-small and high-density integrated circuits. The gate dielectric in a carbon nanotube field effect transistor not only affects the distribution of the gate electric field, but also directly determines the working current, switching performance and leakage current of the device. An ideal gate dielectric should have a high dielectric constant (high-K) to ensure effective control of the electric field and good bonding with the carbon nanotube film. However, due to the rough surface and poor wettability of the carbon nanotube film, the deposition process of the gate dielectric is often uneven. In particular, the deposition of high-K dielectric materials (such as hafnium oxide HfO2) will form uneven thickness, defects or unevenness on the surface. Uneven deposition of the gate dielectric will lead to uneven distribution of the gate electric field, affect the switching performance and driving ability of the device, increase the leakage phenomenon, and reduce the efficiency and stability of the device. In addition, poor contact between the gate dielectric and the carbon nanotube film will also exacerbate the instability of current transmission and further reduce the long-term stability and reliability of the device.

[0003] Christopher Rutherglen developed a preparation process for field-effect transistors with an ordered carbon nanotube structure suitable for large-area wafer manufacturing in his published paper "Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz" (Nature Electronics volume 2, pages 530-539 (2019)). In this solution, the gate dielectric is prepared by directly depositing an Al / Ni / Au metal gate on the carbon nanotube film and baking it on a hot plate at 120 °C to form an AlO gate dielectric layer with a thickness of approximately 4.5 nm. Although this method is relatively simple, there are still deficiencies in the preparation method of this field-effect transistor. Using alumina (AlO) formed by thermal oxidation as the gate dielectric layer has many defects. First, it is difficult to precisely control the film thickness with this method, and the film thickness uniformity is poor, which is not conducive to optimizing the equivalent oxide thickness (EOT) of the gate dielectric. Second, thermal oxidation of AlO generally has a high defect density and oxygen vacancies, which easily lead to an increase in leakage current and an enhanced charge trapping effect, resulting in a shift in the device threshold voltage and a decrease in stability. In addition, the AlO film layer formed during thermal oxidation has low density and a low dielectric constant, making it difficult to meet the requirements of advanced devices for high dielectric performance.

[0004] Lijun Liu developed a scalable preparation of high-density, high-purity, and well-aligned semiconducting single-walled carbon nanotube arrays and their applications in high-performance electronic devices in his published paper "Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics" (Science 368, 850-856 (2020)). During the preparation of the gate dielectric, first, photoresist was used for patterning, and then a 4.8-nm-thick HfO film was deposited by low-temperature atomic layer deposition (ALD) at 90 °C. This low-temperature preparation process has certain advantages in terms of process compatibility, especially suitable for heat-sensitive substrate materials such as flexible electronics or organic devices. However, this method still has several deficiencies: due to the low deposition temperature, the formed HfO film has insufficient density and poor structural stability, resulting in unsatisfactory electrical properties and reliability. Specifically, the gate control ability is weakened and the leakage current increases, thus affecting the switching characteristics, driving ability, and long-term stability of the device. In addition, depositing HfO on the surface of carbon nanotubes (CNT) still faces significant challenges, mainly due to the chemical inertness of the CNT surface and the difficulty of nucleation, making it difficult to form a uniform and continuous dielectric layer. This problem is further exacerbated under low-temperature deposition conditions, severely restricting the formation of high-quality gate dielectrics and affecting the overall performance of the device.

[0005] Zhongshan College of the University of Electronic Science and Technology of China discloses a molybdenum disulfide field-effect transistor and its preparation method and application in the patent document "A Molybdenum Disulfide Field-Effect Transistor and Its Preparation Method and Application" (application number: 202010748373.2, publication number: CN 111969058 A). The molybdenum disulfide field-effect transistor includes a substrate layer, a first metal layer, a first gate dielectric layer, and a molybdenum disulfide semiconductor thin film layer arranged in sequence. A source contact electrode and a drain contact electrode are respectively arranged on both sides of the molybdenum disulfide semiconductor thin film layer, as well as a second and a third gate dielectric layer and a second metal layer. The second metal layer passes through the first gate dielectric layer, the second and the third gate dielectric layers and contacts the first metal layer. By setting the first metal layer and the second metal layer as the bottom gate and the top gate respectively to simultaneously control the molybdenum disulfide channel, the electrostatic control ability of the channel is enhanced, which helps to further reduce the size and improve the low-power consumption performance and high-frequency performance of the device, solving the problem of the existing molybdenum disulfide field-effect transistor structure having deficiencies in low-power consumption performance and high-frequency performance. In this invention, alumina (AlO) and hafnium oxide (HfO) are used in combination as the gate dielectric material to solve the problem of difficult nucleation when directly depositing a high-k gate dielectric on the surface of two-dimensional molybdenum disulfide (MoS) by atomic layer deposition (ALD), thus facilitating the construction of a uniform, dense and high-quality molybdenum disulfide gate dielectric structure at the interface. However, the preparation method of this field-effect transistor still has deficiencies. Although the alumina seed layer can improve the nucleation behavior of high-k materials on an inert surface, its relatively low dielectric constant may lead to a decrease in the overall capacitance of the gate dielectric, resulting in an increase in the equivalent oxide thickness (EOT) and affecting the gate control ability and electrical performance of the device.

[0006] Xi'an Jiaotong University discloses a carbon nanotube field-effect transistor with a top-gate structure and a preparation method thereof in its patent document "A Carbon Nanotube Field-Effect Transistor with a Top-Gate Structure and a Preparation Method Thereof" (Application No. CN 202310962495.5, Publication No. CN 116940130 A). This field-effect transistor relates to a carbon nanotube field-effect transistor with a top-gate structure. A carbon nanotube thin film is provided on the upper surface of a silicon-based substrate; a drain electrode and a source electrode are provided on the surface of the carbon nanotube thin film; the carbon nanotube thin film between the drain electrode and the source electrode is etched to form a CNT channel layer; a dielectric layer is provided on the upper surface of the CNT channel layer; a dielectric layer is located on the upper surfaces of the dielectric layer, the drain electrode, and the source electrode; a top-gate electrode is provided in the middle of the dielectric layer; metal particles are dispersed on the surface part of the dielectric layer that does not contact the top-gate electrode. This field-effect transistor uses yttrium oxide (YO) formed by thermal oxidation as a seed layer for the hafnium oxide (HfO) atomic layer deposition (ALD) process. Compared with the traditional aluminum oxide (AlO) seed layer, yttrium oxide is more superior in promoting HfO nucleation, improving the crystallization quality of the thin film, and enhancing the gate control ability. It is particularly suitable for new semiconductor channel materials such as carbon nanotubes and can effectively improve the electrostatic regulation performance of the device. However, compared with the structure of directly depositing an HfO thin film on the substrate, introducing a yttrium oxide seed layer not only adds additional process steps but also may bring problems such as complex interface structure and decreased thermal stability. Especially in a multi-layer dielectric structure, there may be phenomena such as lattice mismatch, charge accumulation, or oxygen vacancy migration at the interface between yttrium oxide and HfO, which will lead to an increase in the interface trap state density (Dit). These interface defects will have an adverse impact on the channel carrier mobility, subthreshold swing, and switching characteristics of the device. Summary of the Invention

[0007] The object of the present invention is to address the deficiencies of the above-mentioned existing technologies and provide a carbon nanotube field-effect transistor and a preparation method thereof including a gate dielectric substrate layer structure, aiming to solve the problems of difficult gate dielectric nucleation, poor film layer quality, many interface defects, unstable electrical properties, and complex multi-layer structure processes in existing carbon nanotube field-effect transistors.

[0008] The technical concept for achieving the object of the present invention is to introduce a "gate dielectric underlayer" under the carbon nanotube film. By constructing a sandwich structure of "gate dielectric underlayer / CNT / gate dielectric layer", the deposition process and performance of the gate dielectric are optimized. Among them, the gate dielectric underlayer and the gate dielectric layer are made of the same material (preferably a high dielectric constant material). The lower gate dielectric underlayer can provide a stable and uniform nucleation environment through the pore structure between it and the carbon nanotube film, significantly improving the deposition quality of the upper gate dielectric, making its film formation denser and flatter, thereby effectively solving the problems of difficult nucleation of high-K dielectrics on the surface of carbon nanotubes and film layer defects. The consistency of the upper and lower layer materials helps to reduce the interface defect density and charge trap effect, enhance the gate electric field control ability, and improve the switching performance and working stability of the device. At the same time, the unified deposition process simplifies the manufacturing process, improves the preparation consistency and process compatibility, and demonstrates excellent electrical performance and scalability for large-scale manufacturing.

[0009] A carbon nanotube field effect transistor including a gate dielectric underlayer for achieving the object of the present invention comprises a substrate, a gate dielectric underlayer, a semiconducting carbon nanotube film, source and drain metal electrodes, a gate dielectric layer, and a gate electrode; a gate dielectric underlayer is disposed between the substrate and the semiconducting carbon nanotube film to form a device structure in a "sandwich" shape of "gate dielectric underlayer / CNT / gate dielectric layer".

[0010] Further, the gate dielectric underlayer covers the surface of the substrate, and the semiconducting carbon nanotube film is laid on the surface of the gate dielectric underlayer in a porous network structure; the gate dielectric layer coats the semiconducting carbon nanotube film and the gate dielectric underlayer through a deposition process, wherein the dielectric materials of the gate dielectric underlayer and the gate dielectric layer are tightly connected through the pore structure of the semiconducting carbon nanotube film to form a continuous interface structure.

[0011] Further, the thickness of the gate dielectric underlayer is the same as that of the gate dielectric layer, and the value range of the thickness is 9 - 11 nm.

[0012] Further, the gate dielectric underlayer and the gate dielectric layer adopt the same high dielectric constant material.

[0013] Further, the high dielectric constant material is any one of Y2O3, HfO2, Ta2O5 or ZrO2, and its dielectric constant is greater than 10.

[0014] Further, the gate dielectric layer fills the pores of the carbon nanotube film and coats the surface of the semiconducting carbon nanotube film through an atomic layer deposition (ALD) process, and the porosity of the carbon nanotube film is 20 - 50%.

[0015] A method for fabricating a carbon nanotube field effect transistor including a gate dielectric substrate layer structure of the present invention comprises the following steps:

[0016] Step 1, cleaning the Si substrate and performing photolithography alignment marks;

[0017] Step 2, using atomic layer deposition (ALD) process to deposit a gate dielectric substrate layer on the treated substrate;

[0018] Step 3, depositing a high-purity semiconducting carbon nanotube film on the gate dielectric substrate layer, and then forming a conductive channel region covering between the source and drain metal electrodes;

[0019] Step 4, using photolithography and plasma etching processes to remove the semiconducting carbon nanotube film in the non-conductive channel region, and only retaining the conductive channel region between the required source and drain metal electrodes;

[0020] Step 5, using photolithography, resist stripping treatment, metal evaporation and metal lift-off processes to form a source-drain electrode structure connected to the channel;

[0021] Step 6, using the same atomic layer deposition (ALD) process as in Step 2 to deposit a gate dielectric layer above the semiconducting carbon nanotube film;

[0022] Step 7, forming a gate structure by photolithography and metal deposition;

[0023] Step 8, opening holes in the metal electrode regions of the source and drain to complete the fabrication of the carbon nanotube field effect transistor.

[0024] Further, the steps of the atomic layer deposition (ALD) process in Step 2 are as follows:

[0025] The first step, precursor preparation:

[0026] Using tetrakis(dimethylamino)hafnium (TDMAH) as the hafnium source and H2O as the oxygen source, performing the ALD process at a deposition temperature of 300 ± 5 °C;

[0027] The second step, pulse deposition cycle, sequentially performing the following sub-steps:

[0028] Step 2.1, injecting the TDMAH precursor into the reaction chamber with a pulse time of 0.1 - 0.5 seconds to complete the chemisorption of the hafnium source on the surface of the carbon nanotube intermediate layer;

[0029] Step 2.2, introducing nitrogen or argon and purging for 1 - 5 seconds to remove the unreacted TDMAH precursor and by-products;

[0030] Step 2.3: Inject an H2O oxygen source pulse with a pulse time of 0.05 - 0.3 seconds to undergo a surface oxidation reaction with the adsorbed TDMAH to form HfO2;

[0031] Step 2.4: Purge with nitrogen or argon again for 1 - 5 seconds to remove residual reactants;

[0032] Step 3: Repeat the pulsed deposition cycle of Step 2, with a deposition thickness of 0.09 - 0.11 nm for each cycle, until the total thickness of the HfO2 thin film is 9.5 - 10.5 nm, forming a gate dielectric substrate layer.

[0033] Furthermore, the steps for depositing the carbon nanotube thin film in Step 3 are as follows:

[0034] Step 1: Immerse the silicon wafer with the prepared gate dielectric substrate into a solution of semiconducting carbon nanotubes and keep it in a static state to deposit a semiconducting carbon nanotube thin film;

[0035] Step 2: Keep the deposition time at 12 hours to enable the uniform and stable deposition of semiconducting carbon nanotubes on the silicon wafer surface, forming a large - area continuous semiconducting carbon nanotube thin film;

[0036] Step 3: Take out the silicon wafer and perform appropriate drying or post - treatment to ensure that the semiconducting carbon nanotube thin film adheres well as a conductive channel layer and has good conductivity.

[0037] Furthermore, the steps for depositing the gate dielectric layer above the semiconducting carbon nanotube thin film in Step 6 are as follows:

[0038] Step 1: Upper layer precursor preparation:

[0039] Use the same hafnium source and oxygen source as for the deposition of the bottom - layer gate dielectric substrate. Take tetrakis(dimethylamino)hafnium (TDMAH) as the hafnium source and H2O as the oxygen source, and perform atomic layer deposition (ALD) process at a deposition temperature of 300 ± 5 °C;

[0040] Step 2: Upper layer pulsed deposition cycle, and successively execute the following sub - steps:

[0041] Step 2.1: Inject the TDMAH precursor into the reaction chamber with a pulse time of 0.1 - 0.5 seconds to enable the chemical adsorption of the hafnium source on the surface of the carbon nanotube intermediate layer;

[0042] Step 2.2: Introduce nitrogen or argon and purge for 1 - 5 seconds to remove the unreacted TDMAH precursor and by - products;

[0043] Step 2.3: Inject an H2O oxygen source pulse with a pulse time of 0.05 - 0.3 seconds to undergo a surface oxidation reaction with the adsorbed TDMAH to form HfO2;

[0044] Step 2.4: Again introduce nitrogen or argon gas to purge for 1 - 5 seconds to remove residual reactants;

[0045] Step 3: Repeat the deposition cycle of Step 2. The deposition thickness per single cycle is 0.09 - 0.11 nm. Control the total thickness of the HfO2 thin film to reach 9.5 - 10.5 nm through the number of cycles to form a dense gate dielectric layer.

[0046] Furthermore, the deposition temperature, precursor type, and number of cycles of the upper gate dielectric are consistent with the process parameters of the gate dielectric substrate to ensure the interface continuity between the gate dielectric substrate layer and the gate dielectric layer.

[0047] Compared with the prior art, the present invention has the following advantages:

[0048] First, since the carbon nanotube field - effect transistor of the present invention forms a device structure of "gate dielectric substrate layer / CNT / gate dielectric layer" by setting a gate dielectric substrate layer between the substrate and the semiconducting carbon nanotube thin film, it overcomes the deficiencies of difficult nucleation, discontinuous film layer, and uneven deposition faced when a high - dielectric - constant medium is directly deposited on the surface of carbon nanotubes in the prior art. The gate dielectric substrate layer covers the surface of the substrate, and the semiconducting carbon nanotube thin film is laid on the surface of the substrate layer in a porous network structure; the upper gate dielectric layer coats the carbon nanotube thin film and the substrate layer through a deposition process, and utilizes the pore structure of the carbon nanotube thin film to achieve tight connection of the upper and lower gate dielectrics, forming a continuous interface structure. This way of structure optimization not only enhances the gate control ability of the device but also improves the overall consistency and manufacturing yield of the device.

[0049] Second, since the carbon nanotube field - effect transistor of the present invention preferably uses a high - dielectric - constant material (such as hafnium oxide HfO) as the gate dielectric and the substrate layer, it overcomes the defects of low dielectric constant and difficulty in compressing the equivalent oxide thickness (EOT) existing in the commonly used low - dielectric - constant medium (such as thermally oxidized aluminum oxide AlO) in the prior art, and significantly improves the gate electric - field control ability of the device.

[0050] Third, since the high - dielectric - constant material of the carbon nanotube field - effect transistor of the present invention has better thermal stability and denseness, it can effectively reduce the interface defect density and charge trap effect, overcomes the defects of increased leakage current, threshold voltage drift, and decreased device stability easily caused by low - dielectric - constant media, and thus realizes the optimization of device performance with low power consumption and high reliability.

[0051] Fourth, since the same material (such as HfO) is selected for the upper and lower layers of the gate dielectric in the present invention, many problems caused by material differences in the existing heterogeneous dielectric stack structure, such as interfacial lattice mismatch, inconsistent thermal expansion coefficients, charge accumulation, and oxygen vacancy migration, are avoided. The consistency of the upper and lower layer materials helps to form a continuous dielectric interface, reduce the density of interface trap states (Dit), and thus improve the subthreshold characteristics and carrier mobility of the device.

[0052] Fifth, since the carbon nanotube field effect transistor of the present invention uses a unified material and deposition process, it can also simplify the process flow, enhance process compatibility, and is conducive to large-scale integrated manufacturing and industrial application. Description of the Drawings

[0053] Figure 1 is a schematic structural diagram of the carbon nanotube transistor of the present invention;

[0054] Figure 2 is a process flow chart of the preparation of the carbon nanotube transistor of the present invention;

[0055] Figure 3 is an SEM characterization diagram of the carbon nanotube transistor of the present invention;

[0056] Figure 4 is an electrical characteristic curve diagram of the carbon nanotube transistor of the present invention;

[0057] Figure 5 is a comparison diagram of the gate leakage current characteristics curves of the traditional structure device and the "sandwich" structure device of the present invention. Detailed Embodiments

[0058] The present invention will be further described in detail below with reference to the drawings and embodiments.

[0059] Referring to Figure 1 , the structure of the carbon nanotube transistor according to the embodiment of the present invention will be further described in detail.

[0060] The structure of the carbon nanotube field effect transistor sequentially includes, from bottom to top: a substrate, a gate dielectric substrate layer covering the surface of the substrate, a semiconducting carbon nanotube thin film laid on the surface of the gate dielectric substrate layer in a porous network structure, source and drain metal electrodes electrically connected to both ends of the carbon nanotubes respectively, a gate dielectric layer covering the carbon nanotube thin film and the gate dielectric substrate layer, and a gate electrode provided on the surface of the gate dielectric layer.

[0061] Figure 1 The s-SWCNT in

[0062] The "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure means that a gate dielectric substrate layer is pre-deposited under the carbon nanotube film. Utilizing the pore structure of the carbon nanotube film itself, it provides a stable and uniform nucleation environment for the deposition of the upper gate dielectric layer. This structure effectively improves the nucleation and growth conditions of the high-k dielectric on the surface of the carbon nanotubes, thereby significantly enhancing the density and surface flatness of the upper gate dielectric film layer. Through this structure optimization method, not only the gate electric field control ability of the device is enhanced, but also the overall process consistency and manufacturing yield of the device are improved, with good process scalability.

[0063] The gate dielectric substrate layer and the gate dielectric layer are made of the same material. The selected material is a high dielectric constant (High-k) dielectric, which can be selected and optimized according to specific application requirements. In the embodiments of the present invention, the gate dielectric material is hafnium oxide (HfO). Hafnium oxide has the characteristics of high dielectric constant, good thermal stability, and excellent interface matching with various semiconductor materials. It is suitable for realizing high-quality thin film growth by atomic layer deposition (ALD), which can effectively reduce the equivalent oxide thickness (EOT), enhance the gate electric field regulation ability, and suppress leakage current at the same time.

[0064] The design of using the same material for the gate dielectric substrate layer and the gate dielectric layer helps to simplify the deposition process flow, avoid problems such as lattice mismatch, inconsistent thermal expansion coefficient, and interface reaction that may occur between heterogeneous materials, thereby enhancing the structural continuity and interface stability between the dielectric layers. This structural configuration is not only beneficial to reducing the interface trap state density, enhancing the carrier transport stability, but also can improve the overall consistency, electrical performance, and long-term reliability of the device, and is suitable for the large-scale preparation of high-performance integrated devices.

[0065] Refer to Figure 2 The process flow of the carbon nanotube transistor with the "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure in the embodiments of the present invention is further described.

[0066] Step 1, cleaning of the substrate and lithography of the alignment marks.

[0067] Step 1.1, cleaning the Si substrate.

[0068] The cleaning process includes acetone ultrasonic cleaning (3 minutes, 80 - 100W), 60°C stripping solution treatment (15 minutes), isopropyl alcohol ultrasonic cleaning (3 minutes, 80 - 100W), and ultrapure water rinsing (2 - 3 minutes), and finally drying with N gas.

[0069] Step 1.2, performing lithography.

[0070] First, bake it on a hot plate at 200°C for 5 minutes to remove moisture and enhance the adhesion of the photoresist. The photoresist used is AZ5214, and it is spin-coated at a speed of 5000 rpm / s for 30 seconds to form a photoresist layer with a thickness of 1.25 μm. Perform pre-baking (1 minute, 100°C), then expose it. The exposure conditions are ultraviolet light with a light intensity of 400 W / cm 2 , the exposure time is 22 seconds, and finally develop it for 60 seconds, rinse it with ultrapure water for 2 minutes, and then dry it with N gas.

[0071] Step 1.3, fabricate the "FIDU" alignment mark.

[0072] After lithography is completed, use SF6 / O2 gas for etching. The gas flow rates are 50 sccm and 30 sccm respectively. The etching power is 150 W for the upper electrode and 50 W for the lower electrode, the etching time is 10 minutes, and the etching depth is 200 - 400 nm.

[0073] Step 2, atomic layer deposition (ALD) growth of the gate dielectric liner layer.

[0074] After the etching process is completed, use atomic layer deposition (ALD) technology to grow a 10-nm-thick hafnium oxide (HfO) gate dielectric liner layer on the substrate surface. During the deposition process, tetrakis(dimethylamino)hafnium (TDMAH) is selected as the hafnium source, and water (H2O) is used as the oxygen source. They are alternately pulsed-injected at a temperature of 300°C, and an inert gas purge is used to remove unreacted substances and by-products. By controlling the number of deposition cycles (a total of 100 times, about 0.1 nm each time), precise control of the film thickness can be achieved, obtaining a dense, uniform, and high-quality HfO film, providing a good nucleation basis for the deposition of the upper-layer gate dielectric, and further improving the overall electrical performance and stability of the device.

[0075] Step 3, deposition of the carbon nanotube film.

[0076] Use a solution of semiconducting single-walled carbon nanotubes (s-SWCNTs) with a purity as high as 99.9%, place the silicon wafer in the solution, and perform deposition for 12 hours. This process can enable the s-SWCNTs to be deposited evenly and stably on the silicon wafer surface, forming a large-area carbon nanotube film as the conductive channel of the device.

[0077] Step 4, isolation process (MESA) of the device.

[0078] After the deposition of the carbon nanotube film, the device is isolated. The carbon nanotubes outside the channel are etched away, and only the carbon nanotubes within the channel region are retained. First, photolithography of the channel pattern is performed, using photoresist as a mask to protect the carbon nanotubes in the channel region. The process parameters are the same as those of the photolithography process of "FIDU". Then, an inductively coupled plasma (ICP) device is used for etching. During the etching process, oxygen plasma is used, with the gas flow rate set at 200 sccm, the power at 100 W, and the processing time at 1 minute. During the etching process, the carbon nanotubes outside the channel are selectively removed by oxygen plasma, while the channel region is protected by the photoresist and not affected by the etching. Care should be taken to avoid damage or denaturation of the photoresist due to excessive temperature during the etching process.

[0079] Step 5, preparation of the source and drain electrodes of the device.

[0080] Step 5.1, perform photolithography to define the source and drain electrode patterns, and use the "FIDU" alignment marks to achieve accurate pattern overlay. The photolithography parameters used are the same as those for the preparation of the aforementioned alignment marks. After photolithography, an oxygen plasma (O, flow rate 200 sccm, power 100 W, processing time 5 minutes) is used for photoresist removal to ensure a clean substrate surface.

[0081] Step 5.2, perform Ti / Pd metal evaporation within the photolithography pattern area. The thicknesses of both Ti and Pd are 10 nm. The evaporation process is completed under a vacuum of ≤2.0×10 -6 Torr, and the deposition thickness is controlled by a quartz crystal oscillator monitor. After the metal deposition is completed, ultrasonic stripping and cleaning are performed successively using acetone, isopropyl alcohol, and ultrapure water to remove the excess metal and residual photoresist, finally forming a patterned source and drain ohmic electrode structure.

[0082] Step 6, growth of the gate dielectric layer oxide (HfO2) based on the "sandwich" structure

[0083] To ensure the consistency between the gate dielectric layer HfO and the underlying HfO, the same deposition method and temperature as those for the growth of the gate dielectric substrate layer HfO are used for growth. The upper and lower layers of HfO and the middle layer of carbon nanotubes together form a sandwich structure.

[0084] Step 7, preparation of the gate of the device and opening of the source and drain electrodes.

[0085] The gate metal is prepared by the Lift-off process, which is consistent with the preparation scheme of the source and drain electrodes. First, photolithography technology is used to define the gate pattern on the substrate; subsequently, a 10-nm titanium (Ti) layer and a 50-nm palladium (Pd) layer are sequentially evaporated and deposited to form the gate electrode, and ultrasonic stripping is used to remove the excess metal. Finally, after the device preparation is completed, photolithography and etching processes are used to open holes in the source and drain electrodes. The etching gas is Cl / BCl, and the etching rate is 1.35 nm / min.

[0086] Step 8, device annealing treatment.

[0087] The annealing temperature is set at 200 °C, and the annealing time is 2 hours. The annealing process is carried out in an air environment to remove residual impurities such as moisture and oxygen introduced during the preparation process and improve the quality of the material interface. After annealing is completed, the device is allowed to cool naturally to room temperature to ensure the stability of the device structure and performance.

[0088] Refer to Figure 3 , and a further detailed description is made of the channel carbon nanotube arrangement, device structure design, and elemental energy spectrum distribution under the gate of the carbon nanotube field-effect transistor with the "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure.

[0089] Figure 3 (a), Figure 3 (b), Figure 3 (c) is the SEM image of the channel carbon nanotubes of the carbon nanotube transistor. The carbon nanotube film at the channel of the carbon nanotube transistor is a random network structure with a porosity of 20 - 50%. The gate dielectric material (such as HfO) fills the pores of the carbon nanotube network through atomic layer deposition and conformally coats the surface of the carbon nanotubes to form a continuous and dense covering layer.

[0090] Figure 3 (d) is the EDS image of the elemental energy spectrum distribution under the gate of the carbon nanotube transistor. The results show that the elemental composition distribution of each functional layer is clear, and the interlayer interface transition is distinct, verifying the rationality of the device structure design and the uniformity of material deposition. Among them, strong Hf signals are detected in the dielectric regions of both the gate dielectric substrate layer and the gate dielectric layer, indicating that the hafnium oxide (HfO) film is successfully deposited on and under the carbon nanotubes and is uniformly distributed, and no obvious doping impurities or composition diffusion phenomena are observed. The region where the carbon nanotubes are located shows an obvious C element signal and forms a clear interlayer between the upper and lower Hf distributions, further proving that the "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure is complete and controllable, with a clear structure interface and no obvious mixed layer.

[0091] Figure 3(e) is a schematic cross-sectional structure diagram of the device of the present invention, where the labeled S, G, and D respectively represent the source (Source), gate (Gate), and drain (Drain). From bottom to top, it successively includes: a substrate, a gate dielectric substrate layer, a semiconducting carbon nanotube thin film, source-drain metal electrodes, a gate dielectric layer, and a top gate electrode. A gate dielectric substrate layer is introduced under the carbon nanotube thin film of this transistor, and together with the upper gate dielectric layer, it forms a "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure, which is used to optimize the nucleation behavior and film formation quality of the high-k gate dielectric on the surface of the carbon nanotubes, thereby improving the gate control ability and overall electrical performance of the device.

[0092] Referring to Figure 4 , the electrical characteristic curves of the carbon nanotube transistor with the "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure of the embodiment of the present invention are further described.

[0093] Figure 4 (a) is the output characteristic curve graph of the carbon nanotube transistor with the "sandwich" structure of the embodiment of the present invention, Figure 4 The curves marked with different colors in (a) correspond to different gate-source voltage (Vgs) test conditions, and the corresponding gate voltages are 0V, -0.4V, -0.8V, -1.2V, -1.6V, -2.0V, -2.4V, -2.8V, -3.2V, -3.6V, -4.0V respectively.

[0094] Figure 4 (b) is the transfer characteristic curve graph of the carbon nanotube transistor with the "sandwich" structure of the embodiment of the present invention, where the bias voltage (Vds) is -1V, and the maximum current (Idmax) of the device under this condition is 5.62 mA / mm, and the on-off ratio (Ion / Ioff) reaches 10 5 .

[0095] It can be seen from Figure 4 that the device of the present invention has good overall electrical performance and current driving ability.

[0096] Referring to Figure 5 , the gate leakage current characteristic curves of the traditional structure device and the "sandwich" structure device of the present invention are compared.

[0097] Figure 5 (a) is the current characteristic curve of the traditional structure device, Figure 5 (b) is the current characteristic curve of the "sandwich" structure device of the present invention. Among them, DrainI, SourceI, and GateI respectively represent the drain current, source current, and gate current.

[0098] Comparing Figure 5 (a) with Figure 5(b) It can be seen that there is an obvious gate leakage phenomenon in the traditional structure device, while the "gate dielectric substrate layer / CNT / gate dielectric layer" sandwich structure adopted in the present invention significantly reduces the value of GateI, indicating that the gate leakage has been effectively suppressed.

Claims

1. A carbon nanotube field effect transistor comprising a gate dielectric substrate layer, including a substrate, a gate dielectric substrate layer, a semiconducting carbon nanotube film, source and drain metal electrodes, a gate dielectric layer, and a gate electrode; characterized in that, A gate dielectric substrate layer is disposed between the substrate and the semiconducting carbon nanotube film to form a device structure of gate dielectric substrate layer / CNT / gate dielectric layer.

2. The carbon nanotube field effect transistor according to claim 1, wherein The gate dielectric substrate layer covers the surface of the substrate, and the semiconducting carbon nanotube film is laid on the surface of the gate dielectric substrate layer in a porous network structure; the gate dielectric layer coats the semiconducting carbon nanotube film and the gate dielectric substrate layer through a deposition process, wherein the gate dielectric substrate layer and the gate dielectric layer are tightly connected through the pore structure of the semiconducting carbon nanotube film to form a continuous interface structure.

3. The carbon nanotube field effect transistor according to claim 2, wherein, The thickness of the gate dielectric substrate layer is the same as that of the gate dielectric layer, and the value range of the thickness is 9 - 11 nm.

4. The carbon nanotube field effect transistor according to claim 2, wherein The gate dielectric substrate layer and the gate dielectric layer adopt the same high-k dielectric constant material.

5. The carbon nanotube field effect transistor according to claim 4, characterized in that, The high-k dielectric constant material is any one of Y2O3, HfO2, Ta2O5 or ZrO2, and its dielectric constant is greater than 10.

6. The carbon nanotube field effect transistor according to claim 2, characterized in that, The gate dielectric layer fills the pores of the carbon nanotube film and coats the surface of the semiconducting carbon nanotube film through atomic layer deposition (ALD) process, and the porosity of the carbon nanotube film is 20 - 50%.

7. A method for fabricating a carbon nanotube field effect transistor including a gate dielectric substrate layer structure according to any one of claims 1-6, characterized in that, The steps of this preparation method are as follows: Step 1, clean the Si substrate and lithographically align the marks; Step 2, deposit the gate dielectric substrate layer on the treated substrate by atomic layer deposition (ALD) process; Step 3, after depositing a high-purity semiconducting carbon nanotube film on the gate dielectric substrate layer, form a conductive channel region covering between the source and drain metal electrodes; Step 4, use photolithography and plasma etching processes to remove the semiconducting carbon nanotube film in the non-conductive channel region, and only retain the conductive channel region between the required source and drain metal electrodes; Step 5, use photolithography, resist stripping treatment, metal evaporation and metal lift-off processes to form a source-drain electrode structure connected to the channel; Step 6, use the same atomic layer deposition (ALD) process as in Step 2 to deposit the gate dielectric layer above the semiconducting carbon nanotube film; Step 7, form a gate structure through photolithography and metal deposition; Step 8, open holes in the metal electrode regions of the source and drain to complete the preparation of the carbon nanotube field effect transistor.

8. The method for preparing a carbon nanotube field effect transistor according to claim 7, wherein The steps of the atomic layer deposition (ALD) process in Step 2 are as follows: The first step, precursor preparation: Use tetrakis(dimethylamino)hafnium (TDMAH) as the hafnium source and H2O as the oxygen source, and perform the ALD process at a deposition temperature of 300 ± 5 °C; The second step, pulse deposition cycle, and the following sub-steps are executed in sequence: Step 2.1, inject the TDMAH precursor into the reaction chamber with a pulse time of 0.1 - 0.5 seconds to complete the chemisorption of the hafnium source on the surface of the carbon nanotube intermediate layer; Step 2.2, introduce nitrogen or argon, and use a purge time of 1 - 5 seconds to remove the unreacted TDMAH precursor and by-products; Step 2.3, inject the H2O oxygen source pulse with a pulse time of 0.05 - 0.3 seconds to undergo a surface oxidation reaction with the adsorbed TDMAH to generate HfO2; Step 2.4, introduce nitrogen or argon again for purging for 1 - 5 seconds to remove the residual reactants; In the third step, repeat the pulsed deposition cycle in the second step, with a deposition thickness of 0.09 - 0.11 nm for each cycle until the total thickness of the HfO2 thin film reaches the design requirement, forming a gate dielectric substrate layer; the total thickness of the HfO2 thin film is 9.5 - 10.5 nm.

9. The method for preparing a carbon nanotube field effect transistor according to claim 7, wherein The steps of depositing the carbon nanotube thin film in Step 3 are as follows: In the first step, immerse the silicon wafer with the prepared gate dielectric substrate into the semiconducting carbon nanotube solution and keep it in a static state to deposit the semiconducting carbon nanotube thin film. In the second step, keep the deposition time at 12 hours to enable the uniform and stable deposition of semiconducting carbon nanotubes on the silicon wafer surface, forming a large-area continuous semiconducting carbon nanotube thin film. In the third step, take out the silicon wafer and perform appropriate drying or post-treatment to ensure that the semiconducting carbon nanotube thin film adheres well as a conductive channel layer and has good conductivity.

10. The method for preparing a carbon nanotube field effect transistor according to claim 7, wherein The steps of depositing the gate dielectric layer above the semiconducting carbon nanotube thin film in Step 6 are as follows: In the first step, upper precursor preparation: Use the same hafnium source and oxygen source as those for depositing the bottom gate dielectric substrate. Take tetrakis(dimethylamino)hafnium (TDMAH) as the hafnium source and H2O as the oxygen source, and perform atomic layer deposition (ALD) process at a deposition temperature of 300 ± 5 °C. In the second step, upper pulsed deposition cycle, and successively perform the following sub-steps: In Step 2.1, inject the TDMAH precursor into the reaction chamber with a pulse time of 0.1 - 0.5 seconds to complete the chemisorption of the hafnium source on the surface of the carbon nanotube intermediate layer. In Step 2.2, introduce nitrogen or argon and purge for 1 - 5 seconds to remove the unreacted TDMAH precursor and by-products. In Step 2.3, inject the H2O oxygen source pulse with a pulse time of 0.05 - 0.3 seconds to undergo a surface oxidation reaction with the adsorbed TDMAH to generate HfO2. In Step 2.4, introduce nitrogen or argon for purging again for 1 - 5 seconds to remove the residual reactants. In the third step, repeat the deposition cycle in the second step, with a deposition thickness of 0.09 - 0.11 nm for each cycle. Control the total thickness of the HfO2 thin film to reach the design requirement through the number of cycles, forming a dense gate dielectric layer. The total thickness of the HfO2 thin film is 9.5 - 10.5 nm.

11. The method for preparing a carbon nanotube field effect transistor according to claims 7-10, characterized in that, The deposition temperature, precursor type, and number of cycles of the gate dielectric are consistent with the process parameters of the gate dielectric substrate to ensure the interface continuity between the gate dielectric substrate layer and the gate dielectric layer.

12. A carbon nanotube field effect transistor prepared by the method according to claims 7-11, characterized in that, This carbon nanotube field-effect transistor can be applied to the carbon nanotube field-effect transistors in the preparation of high-frequency electronic devices, flexible display driving circuits, or low-power Internet of Things sensors.

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