Self-gating memory, reading circuit of self-gating memory and reading method

Abstract

The invention discloses a readout circuit selected from a strobe memory, comprising: a clamp voltage generating circuit for clamping a word line readout voltage of a memory cell and generating a read current; the current bias circuit is externally connected with a bias voltage, generates a bias current according to the bias voltage, and compensates the read current; the current acquisition circuit is used for acquiring read current on the storage unit and mirroring the acquired read current to the sensitive amplifier circuit; the reference current generating circuit is used for generating reference read current and mirroring the reference read current to the sensitive amplifier circuit; and the sensitive amplifier circuit is used for generating a first voltage and a second voltage according to the read current and the reference read current, comparing the first voltage with the second voltage, and outputting storage data in the storage unit according to a comparison result. According to the reading circuit disclosed by the invention, reading errors caused by inconsistency of device parameters are overcome, and high-speed reading can be realized.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to a read circuit and a read method for a self - gated memory. Background Art

[0002] The three - dimensional phase - change memory 3D PCM (3D Phase - Change Memory) has become one of the main SCM (Storage Class Memory) solutions due to its high technology maturity and low - cost advantages. However, during the operation of PCM, problems such as crystallization delay, thermal shock, and phase separation are faced. In recent years, it has been found that non - volatile storage functions can be achieved only through OTS (Ovonic Threshold Switch) devices, that is, self - gated memories. The self - gated memory abandons the PCM part in the 3D PCM architecture, can solve the above problems, and is expected to achieve a new non - volatile memory with significantly improved speed and lifespan compared to 3D PCM and a technology maturity close to that of 3D PCM. The self - gated memory is expected to achieve a more competitive SCM with low latency and long lifespan to meet the demand for large - capacity memory in new information systems.

[0003] The read operation of the self - gated memory is achieved by applying a voltage across the two ends of the storage unit under test and detecting the magnitude of its current. Existing read circuits mainly select and read the target storage unit by connecting a gated MOS transistor in series with the storage unit and based on the on - off state of the MOS transistor. When applied to a self - gated memory, since the self - gated memory does not use a MOS transistor as the gating transistor, there is a problem that the target storage unit cannot be selected for reading.

[0004] In order to implement the read operation of the self - gated memory, a voltage - biasing scheme is selected to achieve the selection of the target unit by combining the characteristics of the self - gating transistor of the OTS storage unit itself. During the read operation, the potentials on the word line and bit line on both sides of the storage unit under test change, and the generated voltage difference is the read voltage, and the current flowing through the storage unit is the read current. The read current is compared with a reference current to read the storage state of the storage unit. How to combine the voltage - biasing scheme to achieve the selection of the target unit while implementing the read operation poses requirements for the circuit design of the self - gated memory. How to implement the read circuit of the self - gated memory and improve the read speed is an urgent problem to be solved at present. Summary of the Invention

[0005] Aiming at the defects and improvement requirements of the prior art, the present invention provides a self - gated memory, a read circuit and a read method for the self - gated memory, aiming to solve the problems that the existing read circuit in the prior art is not applicable to the self - gated memory and the read speed is slow.

[0006] To achieve the above object, the present invention discloses a read circuit for a self-gating memory, and the self-gating memory read circuit includes:

[0007] A clamping voltage generation circuit, connected to the word line of the storage unit in the self-gating memory, clamping the read voltage of the word line of the storage unit and generating a read current;

[0008] A current biasing circuit, connected to the clamping voltage generation circuit, externally connected with a bias voltage, and generating a bias current according to the bias voltage to compensate the read current;

[0009] A current acquisition circuit, connected to the word line of the storage unit, for acquiring the read current on the storage unit and mirroring the acquired read current to a sense amplifier circuit;

[0010] A reference current generation circuit, connected to the sense amplifier circuit and the storage unit, for generating a reference read current and mirroring the reference read current to the sense amplifier circuit;

[0011] A sense amplifier circuit, connected to the clamping voltage generation circuit and the reference current generation circuit, for generating a first voltage and a second voltage according to the read current and the reference read current, comparing the first voltage and the second voltage, and outputting the stored data in the storage unit according to the comparison result.

[0012] Preferably, the clamping voltage generation circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first capacitor, wherein:

[0013] A first NMOS transistor, the gate of the first NMOS transistor is connected to the word line read voltage;

[0014] A first PMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the source is connected to the power supply voltage;

[0015] A second PMOS transistor, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the power supply voltage, and the gate is connected to the drain;

[0016] A third PMOS transistor, the source of the third PMOS transistor is connected to the power supply voltage, the gate is connected to the drain of the first NMOS transistor, the drain is connected to the storage unit array in the self-gating memory, and a first capacitor is connected between the drain and the gate;

[0017] A second NMOS transistor, the gate of the second NMOS transistor is connected to the storage unit array, and the drain is connected to the drain of the second PMOS transistor;

[0018] A third NMOS transistor, the drain of the third NMOS transistor is connected to the sources of the first NMOS transistor and the second NMOS transistor, the gate is connected to a bias voltage, and the source is grounded;

[0019] A first capacitor, the first capacitor is connected between the drain and the gate of the third PMOS transistor.

[0020] Preferably, the current bias circuit includes:

[0021] A fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate is connected to the bias voltage, and the drain is connected to the word line of the memory cell array. The fourth NMOS transistor generates a bias current; and

[0022] A fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the gate is connected to the bias voltage, and the fifth NMOS transistor cancels the bias current generated by the fourth NMOS transistor.

[0023] Preferably, the current acquisition circuit includes a third PMOS transistor and a fourth PMOS transistor, where:

[0024] The source of the fourth PMOS transistor is connected to the power supply voltage, the gate is connected to the gate of the third PMOS transistor. The current flowing through the third PMOS transistor is the sum of the read current and the bias current. The third PMOS transistor and the fourth PMOS transistor form a current mirror, and the current flowing through the fourth PMOS transistor is proportional to the current flowing through the third PMOS transistor.

[0025] Preferably, the sense amplifier circuit includes a current conversion circuit and a first voltage comparison circuit. The current conversion circuit is used to convert the word line read current and the reference read current into a first voltage and a second voltage respectively;

[0026] The first voltage comparison circuit, connected to the current conversion circuit, is used to compare the first voltage and the second voltage, and output the stored data according to the comparison result; and

[0027] The reference current generation circuit includes a reference current acquisition circuit and a second voltage comparison circuit, where: The reference current acquisition circuit includes: a twelfth PMOS transistor, a tenth NMOS transistor, and a first reference storage unit and a second reference storage unit; the source of the twelfth PMOS transistor is connected to the power supply voltage, the gate is connected to the drain, and the drain is connected to the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is connected to the first reference storage unit and the second reference storage unit, the gate is connected to the first output terminal of the second voltage comparison circuit, and the drain is connected to the drain of the twelfth PMOS transistor; the source voltage of the tenth NMOS transistor is clamped to the voltage of the first comparison terminal in the second voltage comparison circuit, and the two ends of the first reference storage unit and the second reference storage unit are respectively connected to the word line read voltage and the bit line read voltage of the storage unit.

[0028] Optionally, the first voltage comparison circuit and the second voltage comparison circuit are connected to an external circuit through a first comparison terminal, a second comparison terminal, and a first output terminal, where:

[0029] The voltage comparison circuit includes: a first P-switch transistor, a second P-switch transistor, a first N-switch transistor, a second N-switch transistor, and a third N-switch transistor, where:

[0030] The source of the first P-switch transistor is connected to the power supply voltage, the gate is connected to the drain, and the drain is connected to the drain of the first N-switch transistor;

[0031] The source of the second P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the first P-switch transistor, the drain is connected to the drain of the second N-switch transistor, and the first output terminal is led out from the drain of the second P-switch transistor;

[0032] The source of the first N-switch transistor is connected to the drain of the third N-switch transistor, the gate is the first comparison terminal and is connected to the external circuit, and the drain is connected to the drain of the first P-switch transistor;

[0033] The source of the second N-switch transistor is connected to the drain of the third N-switch transistor, the gate is the second comparison terminal, and the drain is connected to the drain of the second P-switch transistor;

[0034] The source of the third N-switch transistor is grounded, the gate is connected to the bias voltage, and the drain is connected to the source of the first N-switch transistor and the source of the second N-switch transistor;

[0035] Or the voltage comparison circuit includes: a first P-switch transistor, a second P-switch transistor, a third P-switch transistor, a first N-switch transistor, a second N-switch transistor, and a third N-switch transistor, where:

[0036] The source of the first P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the third N-switching transistor, the drain of the first N-switching transistor, and the drain of the second P-switching transistor, and the drain is connected to the source of the second P-switching transistor and the source of the third P-switching transistor;

[0037] The source of the second P-switching transistor is connected to the source of the third P-switching transistor and the drain of the first P-switching transistor; the gate is connected to the gate of the first N-switching transistor, serving as the first comparison terminal and connected to an external circuit; the drain is connected to the drain of the first N-switching transistor, the gate of the third N-switching transistor, and the gate of the first P-switching transistor;

[0038] The source of the third P-switching transistor is connected to the source of the second P-switching transistor and the drain of the first P-switching transistor; the gate is connected to the gate of the second N-switching transistor, serving as the second comparison terminal and connected to an external circuit; the drain is connected to the drain of the second N-switching transistor, serving as the first output terminal and connected to an external circuit;

[0039] The source of the first N-switching transistor is connected to the source of the second N-switching transistor and the drain of the third N-switching transistor; the gate is connected to the gate of the second P-switching transistor, and the drain is connected to the gate of the first P-switching transistor, the gate of the third N-switching transistor, and the drain of the second P-switching transistor;

[0040] The source of the second N-switching transistor is connected to the source of the first N-switching transistor and the drain of the third N-switching transistor, and the gate is connected to the gate of the third P-switching transistor; the drain is connected to the drain of the third P-switching transistor; and

[0041] The source of the third N-switching transistor is grounded, the gate is connected to the gate of the first P-switching transistor, the drain of the first N-switching transistor, and the drain of the second P-switching transistor, and the drain is connected to the source of the first N-switching transistor and the source of the second N-switching transistor;

[0042] Alternatively, the voltage comparison circuit includes: a first P-switching transistor, a second P-switching transistor, a third P-switching transistor, a first N-switching transistor, a second N-switching transistor, a third N-switching transistor, and a fourth N-switching transistor, where:

[0043] The source of the first P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the second P-switching transistor, and the drain is connected to the source;

[0044] The source of the second P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the first P-switching transistor, and the drain is connected to the gate of the third P-switching transistor and the drain of the second N-switching transistor;

[0045] The source of the third P-switching transistor is connected to the power supply voltage, the gate is connected to the drain of the second P-switching transistor, and the drain is connected to the drain of the fourth N-switching transistor, serving as the first output terminal and connected to an external circuit;

[0046] The source of the first N-type switching transistor is connected to the sources of the second N-type switching transistor and the drain of the third N-type switching transistor. Its gate is the first comparison terminal and is connected to an external circuit, and its drain is connected to the drain of the first P-type switching transistor;

[0047] The source of the second N-type switching transistor is connected to the sources of the first N-type switching transistor and the drain of the third N-type switching transistor. Its gate is the second comparison terminal and is connected to an external circuit, and its drain is connected to the drain of the second P-type switching transistor and the gate of the third P-type switching transistor;

[0048] The source of the third N-type switching transistor is grounded. Its gate is connected to a bias voltage and the gate of the fourth N-type switching transistor, and its drain is connected to the sources of the first N-type switching transistor and the second N-type switching transistor; and

[0049] The source of the fourth N-type switching transistor is grounded. Its gate is connected to a bias voltage and the gate of the third N-type switching transistor, and its drain is connected to the drain of the third P-type switching transistor. The drain leads out a first output terminal.

[0050] Preferably, the current conversion circuit includes: first to eighth P-type switching transistors and first to fourth N-type switching transistors, where:

[0051] The source of the first P-type switching transistor is connected to the power supply voltage, and its drain is connected to the source of the third P-type switching transistor;

[0052] The source of the second P-type switching transistor is connected to the power supply voltage. Its gate is connected to the gate of the first P-type switching transistor, and its drain is connected to the source of the fourth P-type switching transistor;

[0053] The source of the third P-type switching transistor is connected to the drain of the first P-type switching transistor. Its gate is connected to the inverted read enable signal, and its drain is connected to the drain of the first N-type switching transistor;

[0054] The source of the fourth P-type switching transistor is connected to the drain of the second P-type switching transistor. Its gate is connected to the inverted read enable signal, and its drain is connected to the drain of the second N-type switching transistor;

[0055] The source of the first N-type switching transistor is grounded. Its gate is connected to the gate of the third N-type switching transistor, and its drain is connected to the drain of the third P-type switching transistor. The drain is connected to the gate;

[0056] The source of the second N-type switching transistor is grounded. Its gate is connected to the gate of the fourth N-type switching transistor, and its drain is connected to the drain of the fourth P-type switching transistor. The voltage on the drain is the first voltage;

[0057] The source of the fifth P-type switching transistor is connected to the power supply voltage. Its gate is connected to the gate of the sixth P-type switching transistor, and its drain is connected to the source of the seventh P-type switching transistor;

[0058] The source of the sixth P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the twelfth PMOS transistor in the reference current generation circuit, and the drain is connected to the source of the eighth P-switching transistor;

[0059] The source of the seventh P-switching transistor is connected to the drain of the fifth P-switching transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the third N-switching transistor;

[0060] The source of the eighth P-switching transistor is connected to the drain of the sixth P-switching transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the fourth N-switching transistor;

[0061] The source of the third N-switching transistor is grounded, the gate is connected to the gate of the first N-switching transistor, the drain is connected to the drain of the seventh P-switching transistor, and the voltage on the drain is the second voltage;

[0062] The source of the fourth N-switching transistor is grounded, the gate is connected to the gate of the second N-switching transistor, the drain is connected to the drain of the eighth P-switching transistor, and the drain is connected to the gate;

[0063] Alternatively, the current conversion circuit includes: first to second P-switching transistors and first to fourth N-switching transistors, where:

[0064] The source of the first P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the PMOS transistor corresponding to the read current mirror, and the drain is connected to the drain of the first N-switching transistor, the drain of the second N-switching transistor, and the gate of the third N-switching transistor;

[0065] The source of the second P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the PMOS transistor corresponding to the reference read current mirror, and the drain is connected to the drain of the third N-switching transistor and the drain of the fourth N-switching transistor;

[0066] The source of the first N-switching transistor is grounded, the gate is connected to the drain of the first N-switching transistor and the drain of the second N-switching transistor, and the drain is connected to the gate;

[0067] The source of the second N-switching transistor is grounded, the gate is connected to the drain of the second P-switching transistor and the drain of the third N-switching transistor, and the drain is connected to the drain of the first N-switching transistor and the gate of the third N-switching transistor;

[0068] The source of the third N-switching transistor is grounded, the gate is connected to the drain of the first P-switching transistor and the drain of the second N-switching transistor, and the drain is connected to the drain of the fourth N-switching transistor and the gate of the second P-switching transistor;

[0069] The source of the fourth N-switching transistor is connected to ground, the gate is connected to the drain of the second P-switching transistor and the drain of the third N-switching transistor, and the drain is connected to the gate.

[0070] The present invention also discloses a self - gated memory, including a self - gated memory cell array and a read - out circuit of the above - mentioned self - gated memory.

[0071] Furthermore, the present invention discloses a read - out method for a self - gated memory, which is applied to the above - mentioned self - gated memory. The method includes:

[0072] Step S1: When the read - enable signal is valid, the memory array in the self - gated memory selects a memory cell. The word line on the memory cell is clamped to the word - line read - out voltage, the bit line is connected to the bit - line read - out voltage, the voltage on the memory cell is the read - out voltage, and a read current is generated.

[0073] Step S2: Generate a bias current to compensate the read current.

[0074] Step S3: Collect the read current flowing through the memory cell and mirror the read current to the sense - amplifier circuit.

[0075] Step S4: Generate a reference read current and mirror the reference read current to the sense - amplifier circuit.

[0076] Step S5: Generate a first voltage and a second voltage according to the read current and the reference read current respectively.

[0077] Step S6: Compare the first voltage with the second voltage and output the stored data in the memory cell according to the comparison result. When the first voltage is greater than the second voltage, the stored data output is a first signal; when the first voltage is less than the second voltage, the stored data output is a second signal.

[0078] Optionally, the method further includes: when the read - enable signal is invalid, the stored data output by the self - gated memory is a third signal.

[0079] Generally speaking, through the above - mentioned technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0080] (1) Through the coordinated operation of the sense - amplifier circuit, the clamping - voltage generation circuit, the current - bias circuit, the current - acquisition circuit, and the reference - current generation circuit, the present invention realizes the read - out operation while selecting the target cell by combining the voltage - bias scheme, and realizes a read - out circuit applicable to the self - gated memory.

[0081] (2) The circuit realizes that the reference read current is The reference read current generated by this circuit can overcome the inconsistency of process parameters, improve the accuracy of the read - out circuit, and solve the problem that the read - out accuracy is affected by process - parameter fluctuations.

[0082] (3) The readout method proposed by the present invention simplifies the read operation steps and control signals, and is easy to operate; it improves the readout speed, realizes readout within 500 ps, and achieves high-speed readout of the self-gating memory. Description of the Drawings

[0083] Figure 1 It is a schematic diagram of the modules of a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0084] Figure 2 It is a schematic diagram of the internal circuit of a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0085] Figure 3a It is a schematic diagram of a voltage comparison circuit in a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0086] Figure 3b It is a schematic diagram of another voltage comparison circuit in a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0087] Figure 3c It is a schematic diagram of yet another voltage comparison circuit in a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0088] Figure 4a It is a schematic diagram of a current conversion circuit in a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0089] Figure 4b It is a schematic diagram of another current conversion circuit in a readout circuit of a self-gating memory according to an embodiment of the present invention;

[0090] Figure 5 It is a schematic diagram of a storage unit in a self-gating memory being selected through voltage biasing according to an embodiment of the present invention;

[0091] Figure 6 It is a flowchart of a method for reading data from a storage unit in a self-gating memory according to an embodiment of the present invention;

[0092] Figure 7 It is a simulation diagram of a self-gating memory in an embodiment of the present invention reading stored data '0';

[0093] Figure 8 It is a simulation diagram of a self-gating memory in an embodiment of the present invention reading stored data '1';

[0094] Among them, 10 - clamping voltage generation circuit, 20 - current biasing circuit, 201 - current biasing stable loop, 202 - current biasing cancellation loop, 30 - current acquisition circuit, 40 - reference current generation circuit, 401 - voltage comparison circuit, 402 - reference current acquisition circuit, 50 - sense amplifier circuit, 501 - current conversion circuit, 502 - voltage comparison circuit, 60 - self - gated memory storage cell array. Detailed implementation manners

[0095] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0096] In the present invention, the terms "first", "second", etc. (if any) in the present invention and the drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0097] Embodiment 1:

[0098] Figure 1 Shown is a module schematic diagram of a read - out circuit of a self - gated memory according to an embodiment of the present invention. As Figure 1 shown, the read - out circuit includes: a clamping voltage generation circuit, a current biasing circuit, a current acquisition circuit, a reference current generation circuit, and a sense amplifier circuit. Among them, the clamping voltage generation circuit is connected to the word line of the storage cell in the self - gated memory, clamps the read voltage Vread1 of the word line of the storage cell, and generates a read current I READ ; the current biasing circuit, which is connected to the clamping voltage generation circuit, and an external power supply provides a bias voltage Vb to the current biasing circuit. The current biasing circuit generates a bias current Ibias according to the bias voltage to compensate the read current I READ . Specifically, when the stored data value in the storage cell is at a low level, such as 0, at this time the read current I READ is at the nA level. An excessively low current will reduce the stability of the clamping voltage generation circuit. By providing the bias current Ibias as a compensation current for the clamping voltage generation circuit, the stability of the output circuit is improved. The current acquisition circuit is connected to the word line of the storage cell and is used to acquire the read current I READ flowing through the storage cell, and mirrors the acquired read current I READ to the sense amplifier circuit; the reference current generation circuit, which is connected to the sense amplifier circuit and the storage cell, is used to generate a reference read current I REF , and mirrors the reference read current I REFTo a sense amplifier circuit; and a sense amplifier circuit, connected to a clamping voltage generation circuit and a reference current generation circuit, for generating a first voltage U1 and a second voltage U2 according to a read current I READ And a reference read current I REF To generate a first voltage U1 and a second voltage U2, compare the first voltage U1 and the second voltage U2, and output the stored data in the memory cell according to the comparison result. For example, if U1 > U2, output the stored data DATA = 1; conversely, if U1 < U2, DATA = 0. Here, the value of the output stored data DATA is only an example and not a limitation of the present invention. The output setting here can also be the opposite of the above example.

[0099] Specifically, the clamping voltage generation circuit is connected to the word line of the storage array of the self - gated memory, clamping the potential of the word line of the storage array to the external word line read voltage Vread1. The bit line of the storage array is connected to the external bit line read voltage Vread. When a certain memory cell in the storage array is selected, the read voltage on the selected memory cell is: Vread - Vread1.

[0100] Figure 2 Is an internal circuit schematic diagram of a read - out circuit of a self - gated memory according to an embodiment of the present invention. As Figure 2 Shown, the clamping voltage generation circuit 10 includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first capacitor C1. The gate of the first NMOS transistor is connected to the word line read voltage Vread1; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the source is connected to the power supply voltage VDD; the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the power supply voltage VDD, and the gate is connected to the drain; the source of the third PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the drain of the first NMOS transistor, the drain is connected to the word line of the storage array in the self - gated memory, and a first capacitor is connected between the drain and the gate; the gate of the second NMOS transistor is connected to the word line of the storage array, and the drain is connected to the drain of the second PMOS transistor; the drain of the third NMOS transistor is connected to the sources of the first NMOS transistor and the second NMOS transistor, the gate is connected to the bias voltage Vb, and the source is grounded; the first capacitor C1 is connected between the drain and the gate of the third PMOS transistor. The word line voltage of the storage array is clamped to the value of the external word line read voltage Vread1 through the clamping voltage generation circuit 10. In this way, the voltages at both ends of the memory cell array 60 are Vread1 and Vread respectively, and the current I flowing into the word line of the storage array READ Is the read current generated by the clamping voltage generation circuit 10.

[0101] Further, the current bias circuit 20 includes a current bias stabilization loop 201, such as a fourth NMOS transistor, and a current bias cancellation loop 202, such as a fifth NMOS transistor. The source of the fourth NMOS transistor is grounded, the gate is connected to the bias voltage Vb, and the drain is connected to the word line of the memory array. The fourth NMOS transistor generates a bias current Ibias. The source of the fifth NMOS transistor is grounded, the gate is connected to the bias voltage Vb, and the fifth NMOS transistor is used to cancel the bias current Ibias generated on the fourth NMOS transistor. In this way, while maintaining the stability of the clamping voltage generation circuit 10, the bias current Ibias does not change with the read current I READ mirrored to the sense amplifier circuit.

[0102] Further, the current acquisition circuit 30 includes a third PMOS transistor and a fourth PMOS transistor, where: the source of the fourth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor, and the current flowing through the third PMOS transistor is the sum of the read current I READ and the bias current Ibias. The third PMOS transistor and the fourth PMOS transistor form a current mirror, and the current flowing through the fourth PMOS transistor is proportional to the current flowing through the third PMOS transistor. Since the fifth NMOS transistor in the current bias circuit 20 cancels the bias current Ibias, the current entering the sense amplifier circuit is the read current I READ .

[0103] In an embodiment of the present invention, Figure 2 as shown, the reference current generation circuit 40 includes a voltage comparison circuit 401 and a reference current acquisition circuit 402. The voltage comparison circuit 401 includes: a thirteenth PMOS transistor, a fourteenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor. The source voltage of the tenth NMOS transistor is clamped to the external word line read voltage Vread1. Then, the potentials at both ends of the first reference memory cell OTS0 and the second reference memory cell OTS1 are the external word line read voltage Vread1 and the external bit line read voltage Vread, respectively. Therefore, the voltage across the reference memory cell is: Vread - Vread1, where the value of Vread is: (VDD / 2 - V READ / 2), and the value of Vread1 is (VDD / 2 + V READ / 2). Therefore, the value of Vread - Vread1 is -V READ , that is, the voltage across the reference memory cell is -V READ .

[0104] The reference current acquisition circuit 402 includes: a twelfth PMOS transistor, a tenth NMOS transistor, a first reference storage unit, and a second reference storage unit. The reference read current flowing through the tenth NMOS transistor and the twelfth PMOS transistor is where I OTS0 and I OTS1 are the currents flowing through the first reference storage unit OTS0 and the second reference storage unit OTS1 respectively. The reference current acquisition circuit 402 mirrors the reference read current I REF to the sense amplifier circuit 50.

[0105] The voltage comparison circuit 401 includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor. The source of the twelfth PMOS transistor is connected to the power supply voltage, its gate is connected to its drain, and its drain is connected to the drain of the tenth NMOS transistor. The source of the thirteenth PMOS transistor is connected to the power supply voltage VDD, its gate is connected to its drain, and its drain is connected to the drain of the eleventh NMOS transistor. The source of the fourteenth PMOS transistor is connected to the power supply voltage VDD, its gate is connected to the gate of the thirteenth PMOS transistor, and its drain is connected to the drain of the twelfth NMOS transistor. The source of the tenth NMOS transistor is connected to the first reference storage unit and the second reference storage unit, its gate is connected to the drain of the fourteenth PMOS transistor, and its drain is connected to the drain of the twelfth PMOS transistor. The source of the eleventh NMOS transistor is connected to the drain of the thirteenth NMOS transistor, its gate is connected to the word line read voltage, and its drain is connected to the drain of the thirteenth PMOS transistor. The source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, its gate is connected to the source of the tenth NMOS transistor, and its drain is connected to the drain of the fourteenth PMOS transistor. The source of the thirteenth NMOS transistor is grounded, its gate is connected to the bias voltage, and its drain is connected to the drains of the eleventh NMOS transistor and the twelfth NMOS transistor. The thirteenth PMOS transistor, the fourteenth PMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor form a voltage comparison circuit, also known as a clamping voltage circuit, which clamps the source voltage of the tenth NMOS transistor to the word line read voltage Vread1. The two ends of the first reference storage unit and the second reference storage unit are respectively connected to the word line read voltage Vread1 of the storage unit and the bit line read voltage Vread. Further, the sense amplifier circuit 50 includes a current conversion circuit 501 and a voltage comparison circuit 502. The current conversion circuit 501 converts the differential current signal into a differential voltage, namely a first voltage U1 and a second voltage U2, according to the magnitude relationship between the reference read current I REF and the acquired word line read current I READ . The voltage comparison circuit 502 is used to compare the magnitudes of U1 and U2. When I READ >I REF, U1 > U2; I READ <I REF , U1 < U2; The voltage comparison circuit 502 outputs the stored data DATA in the storage unit according to the comparison result. For example, when U1 > U2, DATA = 1; when U1 < U2, DATA = 0. The output of the stored data here is only an embodiment and not a limitation.

[0106] Specifically, the current conversion circuit 501 includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the voltage comparison circuit 502 includes: a fifteenth PMOS transistor, a sixteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, and a sixteenth NMOS transistor. The source of the fourth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor, and the drain is connected to the source of the sixth PMOS transistor and the drain of the fifth NMOS transistor; the source of the fifth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor, and the drain is connected to the source of the seventh PMOS transistor; the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate is connected to the inverted read enable signal RE_, and the drain is connected to the drain of the sixth NMOS transistor; the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate is connected to the inverted read enable signal RE_, and the drain is connected to the drain of the seventh NMOS transistor; the source of the sixth NMOS transistor is grounded, the gate is connected to the gate of the eighth NMOS transistor, the drain is connected to the drain of the sixth PMOS transistor, and the drain is connected to the gate; the source of the seventh NMOS transistor is grounded, the gate is connected to the gate of the ninth NMOS transistor, the drain is connected to the drain of the seventh PMOS transistor, and the voltage on the drain is the first voltage U1; the source of the eighth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the ninth PMOS transistor, and the drain is connected to the source of the tenth PMOS transistor; the source of the ninth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the twelfth PMOS transistor, and the drain is connected to the source of the eleventh PMOS transistor; the source of the tenth PMOS transistor is connected to the drain of the eighth PMOS transistor, the gate is connected to the inverted read enable signal RE_, and the drain is connected to the drain of the eighth NMOS transistor; the source of the eleventh PMOS transistor is connected to the drain of the ninth PMOS transistor, the gate is connected to the inverted read enable signal RE_, and the drain is connected to the drain of the ninth NMOS transistor; the source of the eighth NMOS transistor is grounded, the gate is connected to the gate of the sixth NMOS transistor, the drain is connected to the drain of the tenth PMOS transistor, and the voltage on the drain is the second voltage U2; the source of the ninth NMOS transistor is grounded, the gate is connected to the gate of the seventh NMOS transistor, the drain is connected to the drain of the eleventh PMOS transistor, and the drain is connected to the gate; the source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, the gate is connected to the drain of the seventh NMOS transistor, and the drain is connected to the drain of the fifteenth PMOS transistor and the gate of the sixteenth PMOS transistor; the source of the fifteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor, the gate is connected to the drain of the eighth NMOS transistor, the drain is connected to the drain of the sixteenth PMOS transistor, and the stored data DATA is output;The source of the sixteenth NMOS transistor is grounded, the gate is connected to the bias voltage Vb, and the drain is connected to the sources of the fourteenth NMOS and fifteenth PMOS transistors; the source of the fifteenth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the gate of the sixteenth PMOS transistor, the drain is connected to the drain of the fourteenth NMOS transistor, and the gate is connected to the drain; the source of the sixteenth PMOS transistor is connected to the power supply voltage VDD, the gate is connected to the drain of the fifteenth PMOS transistor, and the drain is connected to the drain of the fifteenth NMOS transistor.

[0107] Figure 3a FIG. is a schematic diagram of a voltage comparison circuit in a readout circuit of a self-gated memory according to an embodiment of the present invention. As shown in the figure, the voltage comparison circuit includes switching transistors P1, P2, N1, N2, and N3, where P1 and P2 are PMOS transistors, also known as P-switching transistors, and N1-N3 are NMOS transistors, also known as N-switching transistors. The specific connection relationship between the switching transistors refers to the connection relationship of the switching transistors in the above voltage comparison circuits 401 and 502, which will not be elaborated here.

[0108] Figure 3b FIG. is a schematic diagram of another voltage comparison circuit in a readout circuit of a self-gated memory according to an embodiment of the present invention. As shown in the figure, the voltage comparison circuit includes switching transistors P1, P2, P3, N1, N2, and N3. Similar to Figure 3a above, P1-P3 are PMOS transistors and N1-N3 are NMOS transistors. The voltage comparison circuit includes a first comparison terminal, a second comparison terminal, and a first output terminal for connection to an external circuit. As shown in the figure, the source of P1 is connected to the power supply voltage VDD, the gate is connected to the gates of N3, the drain of N1, and the drain of P2, and the drain is connected to the sources of P2 and P3. The source of P2 is connected to the sources of P3 and the drain of P1, the gate is connected to the gate of N1 and the first comparison terminal Vin1. For example, when the voltage comparison circuit is used as Figure 2 the voltage comparison circuit 401 in Figure 2 above, the first comparison terminal Vin1 is externally connected to the word line read voltage Vread1 in the storage unit. When used as Figure 2 the voltage comparison circuit 502 in Figure 2 above, the first comparison terminal Vin1 is connected to the first voltage U1; the drain of P2 is connected to the drain of N1, the gate of N3, and the gate of P1. The source of P3 is connected to the sources of P2 and the drain of P1, the gate is connected to the gate of N2 and the second comparison terminal Vin2. For example, when the voltage comparison circuit is used as Figure 2 the voltage comparison circuit 401 in Figure 2 above, the second comparison terminal Vin2 is connected to the word line read voltage Vread1 in the reference storage unit (such as OTS0 and OTS1). When used as Figure 2 the voltage comparison circuit 502 inFigure 2 When it is the medium voltage comparison circuit 401, the first output terminal Vout is connected to the gate of the tenth NMOS transistor in the reference current acquisition circuit 402. When acting as Figure 2 When it is the medium voltage comparison circuit 502, the first output terminal Vout outputs the stored data DATA in the storage unit. The source of N1 is connected to the sources of N2 and the drain of N3, the gate is connected to the gates of P2 and Vin1, and the drain is connected to the gates of P1, the gate of N3, and the drain of P2. The source of N2 is connected to the sources of N1 and the drain of N3, the gate is connected to the gate of P3 and Vin2, and the drain is connected to the drain of P3 and Vout; the source of N3 is connected to the reference ground GND, the gate is connected to the gates of P1, the drain of N1, and the drain of P2, and the drain is connected to the sources of N1 and N2.

[0109] Figure 3c It is a schematic diagram of another voltage comparison circuit in the readout circuit of a self-gating memory according to an embodiment of the present invention. Figure 3c It will be described in conjunction with Figure 2 and Figure 3b As shown in the figure, the voltage comparison circuit includes switching transistors P1 - P3, N1 - N4. Among them, the source of P1 is connected to the power supply voltage VDD, the gate is connected to the gate of P2, and the drain is connected to the source; the source of P2 is connected to the power supply voltage VDD, the gate is connected to the gate of P1, and the drain is connected to the gate of P3 and the drain of N2; the source of P3 is connected to the power supply voltage VDD, the gate is connected to the drain of P2, and the drain is connected to the drain of N4 and Vout; the source of N1 is connected to the sources of N2 and the drain of N3, the gate is connected to Vin1, and the drain is connected to the drain of P1; the source of N2 is connected to the sources of N1 and the drain of N3, the gate is connected to Vin2, and the drain is connected to the drain of P2 and the gate of P3; the source of N3 is connected to the reference ground GND, the gate is connected to the bias voltage Vb and the gate of N4, and the drain is connected to the drains of N1 and N2; the source of N4 is connected to the reference ground GND, the gate is connected to the bias voltage Vb and the gate of N3, and the drain is connected to the drain of P3 and Vout. Figure 3c When the voltage comparison circuits in Figure 3b are used as the voltage comparison circuits 401 and 502 respectively, the connection relationship with the external circuit through the first comparison terminal Vin1, the second comparison terminal Vin2, and the first output terminal Vout is similar to the description in

[0110] Figure 4aSchematic diagram of a current conversion circuit in a readout circuit of a self-gated memory according to an embodiment of the present invention. As shown in the figure, the current conversion circuit includes switching transistors P1-P8, N1-N4, where P1-P8 are PMOS transistors and N1-N4 are NMOS transistors. For the specific connection relationship between the switching transistors, refer to the connection relationship of the switching transistors in the above current conversion circuit 501, which will not be elaborated here.

[0111] Figure 4b Schematic diagram of another current conversion circuit in a readout circuit of a self-gated memory according to an embodiment of the present invention. Figure 4b will be described in conjunction with Figure 2 As shown in the figure, the current conversion circuit includes switching transistors P1-P2, N1-N4, where P1-P2 are PMOS transistors and N1-N4 are NMOS transistors. The source of P1 is connected to the power supply voltage VDD, and the gate is connected to the read current I READ the gate of the PMOS transistor corresponding to the current mirror (corresponding to Figure 2 PM3 in Figure 2 ), and the drain is connected to the drain of N1, the drain of N2, the gate of N3, and U1 (corresponding to the first voltage U1); the source of P2 is connected to the power supply voltage VDD, and the gate is connected to the gate of the PMOS transistor corresponding to the reference read current mirror (corresponding to PM12 in

[0112] ), and the drain is connected to the drain of N3, the drain of N4, and U2 (corresponding to the second voltage U2); the source of N1 is connected to the reference ground GND, the gate is connected to the drain of N2 and U1 (corresponding to the first voltage U1), and the drain is connected to the gate; the source of N2 is connected to the reference ground GND, the gate is connected to the drain of P2, the drain of N3, and U2 (corresponding to the second voltage U2), and the drain is connected to the drain of N1, the gate of N3, and U1 (corresponding to the first voltage U1); the source of N3 is connected to the reference ground GND, the gate is connected to the drain of P1, the drain of N2, and U1 (corresponding to the first voltage U1), and the drain is connected to the drain of N4, the drain of P2, and U2 (corresponding to the second voltage U2); the source of N4 is connected to the reference ground GND, the gate is connected to the drain of P2, the drain of N3, and U2 (corresponding to the second voltage U2), and the drain is connected to the gate.

[0112] Figure 5Schematic diagram of a storage cell in a self - selected access memory being selected through voltage biasing according to an embodiment of the present invention. As shown in the figure, the storage cell array 60 includes: storage cells, bit - line transfer gates TGBL (BL0 - BLn - 1), and word - line transfer gates TGWL (WL0 - WL0 - WLn - 1). The storage cell consists of an Ovonic Threshold Switch (OTS), not limited to this embodiment; or considering the current - limiting problem, it can also be composed of an Ovonic Threshold Switch (OTS) in series with a resistor. The bit - line transfer gate TGBL includes: a bit - line holding transfer gate and a bit - line reading transfer gate. The first transfer end of the bit - line holding transfer gate is connected to the external bias holding voltage VDD / 2, and the second transfer end of the bit - line holding transfer gate is connected to one end of the storage cell OTS; the first transfer end of the bit - line reading transfer gate is connected to the external bit - line read voltage Vread, and the second transfer end of the bit - line reading transfer gate is connected to one end of the storage cell OTS.

[0113] Specifically, the word - line transfer gate TGWL includes: a word - line holding transfer gate and a word - line reading transfer gate. The first transfer end of the word - line holding transfer gate is connected to the external bias holding voltage VDD / 2, and the second transfer end of the word - line holding transfer gate is connected to one end of the storage cell OTS; the first transfer end of the word - line reading transfer gate is connected Figure 2 to the drain of the third PMOS transistor in

[0114] In an alternative embodiment, the size of the storage cell array 60 of the self - selected access memory can be 32*32, 64*64, etc. The size of the storage array can be set according to actual requirements, not limited to this embodiment.

[0115] Embodiment 2:

[0116] Figure 6 Flowchart of a method for reading data from a storage cell in a self - selected access memory according to an embodiment of the present invention, Figure 6 will be described in combination with Figure 1 and Figure 2 and includes the following steps:

[0117] Step S1: When the read enable signal RE is valid, the storage array in the self - selected access memory selects a storage cell. The clamp voltage generation circuit clamps the word - line potential on the storage cell to the word - line read voltage Vread1, the bit - line is connected to the bit - line read voltage Vread, and the voltage on the storage cell is the read voltage - V READ , and a read current I READ is generated;

[0118] Step S2: The current - bias circuit generates a bias current Ibias to compensate for the read current I READ ;

[0119] Step S3: The current acquisition circuit acquires the read current I flowing through the storage unit READ , and mirrors the read current I READ to the sense amplifier circuit;

[0120] Step S4: The reference current generation circuit generates a reference read current I REF , and mirrors the reference read current I REF to the sense amplifier circuit;

[0121] Step S5: The sense amplifier circuit generates a first voltage U1 and a second voltage U2 according to the read current I READ and the reference read current I REF respectively;

[0122] Step S6: The sense amplifier circuit compares the first voltage U1 with the second voltage U2, and outputs the stored data DATA in the storage unit according to the comparison result. When the first voltage U1 is greater than the second voltage U2, the output stored data is the first signal, such as a high level; when the first voltage is less than the second voltage, the output stored data is the second signal, such as a low level.

[0123] When the read enable signal RE is invalid, the sense amplifier circuit is in the off state, and the output stored data DATA is maintained between the first signal and the second signal, which is called the third signal.

[0124] Specifically, when the read enable signal RE is valid, the storage unit array 60 is set to the readout voltage: the clamp voltage generation circuit 10 takes effect, the word line potential of the storage unit array 60 is clamped to the external word line readout voltage Vread1, the bit lines of the storage unit array 60 are connected to the external bit line readout voltage Vread, and the readout voltage across the selected storage unit in the storage unit array 60 is Vread - Vread1 (VBL - VWL); the current acquisition circuit 30 mirrors the current flowing through the third PMOS transistor, that is, the read current I READ to the fourth PMOS transistor through the current mirror formed by the third PMOS transistor and the fourth PMOS transistor, and mirrors the read current I READ to the sense amplifier circuit 50; the reference current generation circuit 40 generates a reference read current I REF For example: The reference read current I generated by the reference current generation circuit 40 REF can overcome the inconsistency of process parameters and improve the accuracy of the readout circuit; when the storage state of the storage unit is at a low level, such as 0, the read current I READOnly at the nA level, the current bias circuit generates a uA-level bias current Ibias to improve the phase margin and stabilize the critical node. In the sense amplifier circuit 50, the current conversion circuit 501 generates a first voltage U1 and a second voltage U2 according to the read current I READ and the reference read current I REF ; the voltage comparison circuit 502 in the sense amplifier circuit 50 compares U1 and U2 and outputs the stored data DATA in the memory cell according to the result.

[0125] Furthermore, in order to verify the effect of the output circuit in the present invention, the simulation results of the output voltage are read as shown in Figure 7 and Figure 8 . It can be seen from the figure that when the storage state of the memory cell in the self-gated memory is at a low level, such as '0', the read time is 343 ps, and when the storage state of the memory cell in the self-gated memory is at a high level, such as '1', the read time is 237 ps. Thus, it can be seen that through the coordinated operation of the sense amplifier circuit, the clamping voltage generation circuit, the current bias circuit, the current acquisition circuit, and the reference current generation circuit, the readout circuit of the self-gated memory in this embodiment solves the problem that the read accuracy is affected by process parameter fluctuations; simplifies the read operation steps and control signals, and is easy to operate; realizes the high-speed readout of the self-gated memory, improves the readout speed, and realizes the readout within 500 ps.

[0126] Embodiment 3:

[0127] The present invention also discloses a self-gated memory, which is composed of the above-mentioned readout circuit and a memory cell array.

[0128] In summary, through the coordinated operation of the sense amplifier circuit, the clamping voltage generation circuit, the current bias circuit, the current acquisition circuit, and the reference current generation circuit, the present invention realizes the readout operation while selecting the target cell by combining the voltage bias scheme, and realizes a readout circuit applicable to the self-gated memory. Secondly, the circuit realizes a reference read current of The reference read current generated by this circuit can overcome the inconsistency of process parameters, improve the accuracy of the readout circuit, and solve the problem that the read accuracy is affected by process parameter fluctuations; finally, the readout method proposed by the present invention simplifies the read operation steps and control signals, and is easy to operate; improves the readout speed, realizes the readout within 500 ps, and realizes the high-speed readout of the self-gated memory.

[0129] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A read circuit for a self-selective memory, characterized in that, The self - gated memory readout circuit includes: A clamping voltage generation circuit, connected to the word line of the memory cell in the self - gated memory, clamping the read voltage of the word line of the memory cell and generating a read current; A current biasing circuit, connected to the clamping voltage generation circuit, externally connected to a bias voltage, and generating a bias current according to the bias voltage to compensate the read current; A current acquisition circuit, connected to the word line of the memory cell, for acquiring the read current on the memory cell and mirroring the acquired read current to a sense amplifier circuit; A reference current generation circuit, connected to the sense amplifier circuit and the memory cell, for generating a reference read current and mirroring the reference read current to the sense amplifier circuit; A sense amplifier circuit, connected to the clamping voltage generation circuit and the reference current generation circuit, for generating a first voltage and a second voltage according to the read current and the reference read current, comparing the first voltage and the second voltage, and outputting the stored data in the memory cell according to the comparison result.

2. The read circuit of the self-selective memory according to claim 1, characterized in that, The clamping voltage generation circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first capacitor, where: The first NMOS transistor, the gate of the first NMOS transistor is connected to the word line read voltage; The first PMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the source is connected to the power supply voltage; The second PMOS transistor, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the power supply voltage, and the gate is connected to the drain; The third PMOS transistor, the source of the third PMOS transistor is connected to the power supply voltage, the gate is connected to the drain of the first NMOS transistor, the drain is connected to the memory cell array in the self - gated memory, and a first capacitor is connected between the drain and the gate; The second NMOS transistor, the gate of the second NMOS transistor is connected to the memory cell array, and the drain is connected to the drain of the second PMOS transistor; The third NMOS transistor, the drain of the third NMOS transistor is connected to the sources of the first NMOS transistor and the second NMOS transistor, the gate is connected to the bias voltage, and the source is grounded; The first capacitor, the first capacitor is connected between the drain and the gate of the third PMOS transistor.

3. The readout circuit of the self-selective memory according to claim 1, characterized in that, The current biasing circuit includes: A fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate is connected to the bias voltage, and the drain is connected to the word line of the memory cell array, and the fourth NMOS transistor generates a bias current; and A fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the gate is connected to the bias voltage, and the fifth NMOS transistor cancels the bias current generated by the fourth NMOS transistor.

4. The read circuit of the self-selective memory according to claim 1, wherein The current acquisition circuit includes a third PMOS transistor and a fourth PMOS transistor, where: The source of the fourth PMOS transistor is connected to the power supply voltage, the gate is connected to the gate of the third PMOS transistor, the current flowing through the third PMOS transistor is the sum of the read current and the bias current, the third PMOS transistor and the fourth PMOS transistor form a current mirror, and the current flowing through the fourth PMOS transistor is proportional to the current flowing through the third PMOS transistor.

5. The read circuit of the self-gating memory according to claim 1, characterized in that The sense amplifier circuit includes a current conversion circuit and a first voltage comparison circuit. The current conversion circuit is used to convert the word line read current and the reference read current into a first voltage and a second voltage respectively. The first voltage comparison circuit, connected to the current conversion circuit, is used to compare the first voltage and the second voltage and output the stored data according to the comparison result. And The reference current generation circuit includes: a reference current acquisition circuit and a second voltage comparison circuit. Among them: the reference current acquisition circuit includes: a twelfth PMOS transistor, a tenth NMOS transistor, and a first reference storage unit and a second reference storage unit; the source of the twelfth PMOS transistor is connected to the power supply voltage, the gate is connected to the drain, and the drain is connected to the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is connected to the first reference storage unit and the second reference storage unit, the gate is connected to the first output terminal of the second voltage comparison circuit, and the drain is connected to the drain of the twelfth PMOS transistor; the source voltage of the tenth NMOS transistor is clamped to the voltage of the first comparison terminal in the second voltage comparison circuit, and the two ends of the first reference storage unit and the second reference storage unit are respectively connected to the word line read voltage and the bit line read voltage of the storage unit.

6. The readout circuit of the self-gating memory according to claim 5, wherein the first voltage comparison circuit and the second voltage comparison circuit are connected to an external circuit through a first comparison terminal, a second comparison terminal, and a first output terminal, wherein: The first and second voltage comparison circuits include: a first P-switch transistor, a second P-switch transistor, a first N-switch transistor, a second N-switch transistor, and a third N-switch transistor. Among them: The source of the first P-switch transistor is connected to the power supply voltage, the gate is connected to the drain, and the drain is connected to the drain of the first N-switch transistor. The source of the second P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the first P-switch transistor, the drain is connected to the drain of the second N-switch transistor, and the first output terminal is led out from the drain of the second P-switch transistor. The source of the first N-switch transistor is connected to the drain of the third N-switch transistor, the gate is the first comparison terminal, connected to the external circuit, and the drain is connected to the drain of the first P-switch transistor. The source of the second N-switch transistor is connected to the drain of the third N-switch transistor, the gate is the second comparison terminal, and the drain is connected to the drain of the second P-switch transistor. The source of the third N-switch transistor is grounded, the gate is connected to the bias voltage, and the drain is connected to the source of the first N-switch transistor and the source of the second N-switch transistor. Or the first and second voltage comparison circuits include: a first P-switch transistor, a second P-switch transistor, a third P-switch transistor, a first N-switch transistor, a second N-switch transistor, and a third N-switch transistor. Among them: The source of the first P-switching transistor is connected to the power supply voltage, the gate is connected to the gates of the third N-switching transistor, the drain of the first N-switching transistor, and the drain of the second P-switching transistor, and the drain is connected to the source of the second P-switching transistor and the source of the third P-switching transistor; The source of the second P-switching transistor is connected to the source of the third P-switching transistor and the drain of the first P-switching transistor; the gate is connected to the gate of the first N-switching transistor, serves as the first comparison terminal, and is connected to an external circuit; the drain is connected to the drain of the first N-switching transistor, the gate of the third N-switching transistor, and the gate of the first P-switching transistor; The source of the third P-switching transistor is connected to the source of the second P-switching transistor and the drain of the first P-switching transistor; the gate is connected to the gate of the second N-switching transistor, serves as the second comparison terminal, and is connected to an external circuit; the drain is connected to the drain of the second N-switching transistor, serves as the first output terminal, and is connected to an external circuit; The source of the first N-switching transistor is connected to the source of the second N-switching transistor and the drain of the third N-switching transistor; the gate is connected to the gate of the second P-switching transistor, and the drain is connected to the gate of the first P-switching transistor, the gate of the third N-switching transistor, and the drain of the second P-switching transistor; The source of the second N-switching transistor is connected to the source of the first N-switching transistor and the drain of the third N-switching transistor, and the gate is connected to the gate of the third P-switching transistor; the drain is connected to the drain of the third P-switching transistor; and The source of the third N-switching transistor is grounded, the gate is connected to the gate of the first P-switching transistor, the drain of the first N-switching transistor, and the drain of the second P-switching transistor, and the drain is connected to the source of the first N-switching transistor and the source of the second N-switching transistor; Or the first and second voltage comparison circuits include: a first P-switching transistor, a second P-switching transistor, a third P-switching transistor, a first N-switching transistor, a second N-switching transistor, a third N-switching transistor, and a fourth N-switching transistor, wherein: The source of the first P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the second P-switching transistor, and the drain is connected to the source; The source of the second P-switching transistor is connected to the power supply voltage, the gate is connected to the gate of the first P-switching transistor, and the drain is connected to the gate of the third P-switching transistor and the drain of the second N-switching transistor; The source of the third P-switching transistor is connected to the power supply voltage, the gate is connected to the drain of the second P-switching transistor, and the drain is connected to the drain of the fourth N-switching transistor, serves as the first output terminal, and is connected to an external circuit; The source of the first N-switching transistor is connected to the source of the second N-switching transistor and the drain of the third N-switching transistor, the gate serves as the first comparison terminal and is connected to an external circuit, and the drain is connected to the drain of the first P-switching transistor; The source of the second N-switching transistor is connected to the source of the first N-switching transistor and the drain of the third N-switching transistor, the gate serves as the second comparison terminal and is connected to an external circuit, and the drain is connected to the drain of the second P-switching transistor and the gate of the third P-switching transistor; The source of the third N-switching transistor is grounded, the gate is connected to the bias voltage and the gate of the fourth N-switching transistor, and the drain is connected to the source of the first N-switching transistor and the source of the second N-switching transistor; and The source of the fourth N-switching transistor is grounded, the gate is connected to the bias voltage and the gate of the third N-switching transistor, and the drain is connected to the drain of the third P-switching transistor, and the drain leads out the first output terminal.

7. The readout circuit of the self-selective memory according to claim 5, characterized in that, The current conversion circuit includes: first to eighth P-switch transistors and first to fourth N-switch transistors, where: The source of the first P-switch transistor is connected to the power supply voltage, and the drain is connected to the source of the third P-switch transistor; The source of the second P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the first P-switch transistor, and the drain is connected to the source of the fourth P-switch transistor; The source of the third P-switch transistor is connected to the drain of the first P-switch transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the first N-switch transistor; The source of the fourth P-switch transistor is connected to the drain of the second P-switch transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the second N-switch transistor; The source of the first N-switch transistor is grounded, the gate is connected to the gate of the third N-switch transistor, the drain is connected to the drain of the third P-switch transistor, and the drain is connected to the gate; The source of the second N-switch transistor is grounded, the gate is connected to the gate of the fourth N-switch transistor, the drain is connected to the drain of the fourth P-switch transistor, and the voltage on the drain is the first voltage; The source of the fifth P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the sixth P-switch transistor, and the drain is connected to the source of the seventh P-switch transistor; The source of the sixth P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the twelfth PMOS transistor in the reference current generation circuit, and the drain is connected to the source of the eighth P-switch transistor; The source of the seventh P-switch transistor is connected to the drain of the fifth P-switch transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the third N-switch transistor; The source of the eighth P-switch transistor is connected to the drain of the sixth P-switch transistor, the gate is connected to the inverted read enable signal, and the drain is connected to the drain of the fourth N-switch transistor; The source of the third N-switch transistor is grounded, the gate is connected to the gate of the first N-switch transistor, the drain is connected to the drain of the seventh P-switch transistor, and the voltage on the drain is the second voltage; The source of the fourth N-switch transistor is grounded, the gate is connected to the gate of the second N-switch transistor, the drain is connected to the drain of the eighth P-switch transistor, and the drain is connected to the gate; Or the current conversion circuit includes: first to second P-switch transistors and first to fourth N-switch transistors, where: The source of the first P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the corresponding PMOS transistor of the read current mirror, and the drain is connected to the drains of the first N-switch transistor, the second N-switch transistor, and the gate of the third N-switch transistor; The source of the second P-switch transistor is connected to the power supply voltage, the gate is connected to the gate of the corresponding PMOS transistor of the reference read current mirror, and the drain is connected to the drains of the third N-switch transistor and the fourth N-switch transistor; The source of the first N-switch transistor is grounded, the gate is connected to the drains of the first N-switch transistor and the second N-switch transistor, and the drain is connected to the gate; The source of the second N-switch transistor is grounded, the gate is connected to the drains of the second P-switch transistor and the third N-switch transistor, and the drain is connected to the drains of the first N-switch transistor and the gate of the third N-switch transistor; The source of the third N-type switching transistor is grounded, the gate is connected to the drain of the first P-type switching transistor and the drain of the second N-type switching transistor, and the drain is connected to the drain of the fourth N-type switching transistor and the gate of the second P-type switching transistor; The source of the fourth N-type switching transistor is connected to ground, the gate is connected to the drain of the second P-type switching transistor and the drain of the third N-type switching transistor, and the drain is connected to the gate.

8. A self-gating memory, characterized in that It includes a self-gating memory cell array and the readout circuit according to any one of claims 1-7.

9. A method for reading a self-selective memory, characterized in that, Applied to the self-gating memory as claimed in claim 8, the method includes: Step S1: When the read enable signal is valid, a memory cell is selected in the memory array of the self-gating memory, the word line on the memory cell is clamped to the word line read voltage, the bit line is connected to the bit line read voltage, the voltage on the memory cell is the read voltage, and a read current is generated; Step S2: Generate a bias current to compensate the read current; Step S3: Collect the read current flowing through the memory cell and mirror the read current to the sense amplifier circuit; Step S4: Generate a reference read current and mirror the reference read current to the sense amplifier circuit; Step S5: Generate a first voltage and a second voltage according to the read current and the reference read current respectively; Step S6: Compare the first voltage with the second voltage and output the stored data in the memory cell according to the comparison result, wherein when the first voltage is greater than the second voltage, the stored data output is the first signal; when the first voltage is less than the second voltage, the stored data output is the second signal.

10. A method for reading a self-selective memory, characterized in that, Applied to the self-gating memory as claimed in claim 8, the method includes: when the read enable signal is invalid, the stored data output by the self-gating memory is the third signal.

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