Overlay mark pattern and overlay error acquisition method

Abstract

The invention relates to an overlay mark pattern and an overlay error acquisition method. The overlay mark pattern comprises a first process layer mark used as a reference mark and a second process layer mark used for being aligned with the first process layer mark, and the first process layer mark and the second process layer mark comprise at least one group of corresponding main scale pattern and first vernier scale pattern, the line widths of the main scale zero line, the main scale graduation line, the first vernier scale zero line and the first vernier scale graduation line and the line spacing of the main scale graph are equal to the set width, the main scale zero line and the first vernier scale zero line are aligned, and the actual position deviation is the overlay error of the second process layer mark in the corresponding line width direction relative to the first process layer mark. The overlay error can be quickly and accurately obtained by utilizing the overlay mark graph, and the scale line of the first vernier scale can be aligned with the scale line of the main scale or the gap, so that the continuity of a calculation result can be improved, and the overlay error precision can be flexibly adjusted as required.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an overlay mark pattern and a method for obtaining overlay error. Background Art

[0002] The semiconductor manufacturing process generally includes a combination of multiple processes (i.e., multiple process layers) performed on a wafer. In each process layer, lithography and etching processes are usually used to transfer patterns onto the wafer. With the progress of the process, the line width of semiconductor devices continues to decrease, and the device density increases. A tiny positional deviation value may lead to circuit connection errors, signal transmission obstacles, or performance degradation, thereby affecting the reliability and stability of the final product. Therefore, the alignment accuracy requirements for different process layers are also more stringent.

[0003] Currently, the overlay error (Overlay, OVL) is used to characterize the positional deviation value between the patterns of the subsequently completed process layer (or the current layer) and the previously completed process layer (or the previous layer, reference layer), and it is an important parameter for measuring the alignment accuracy between layers. To obtain the overlay error, when designing the mask, an overlay mark pattern is set in a specified area. After lithography, the corresponding overlay mark pattern is transferred to the corresponding position on the wafer. By the positional deviation value between the sequentially formed overlay mark patterns, the overlay error between two process layers can be obtained.

[0004] Figure 1 is a schematic diagram of an overlay mark pattern. Referring to Figure 1 , this overlay mark pattern includes the current layer pattern 10 and the previous layer pattern 20. To obtain the overlay error between the two, after being formed on the wafer, first, an image including the current layer pattern 10 and the previous layer pattern 20 is acquired, and then the center positions of the current layer lines arranged horizontally and the center positions of the previous layer lines arranged horizontally are measured respectively. The difference between the two center position data is used to obtain the overlay error in the horizontal direction; then the center positions of the current layer lines arranged vertically and the center positions of the previous layer lines arranged vertically are measured respectively. The difference between the two center position data is used to obtain the overlay error in the vertical direction. Based on the overlay errors in the horizontal and vertical directions, the total overlay error between the current layer pattern 10 and the previous layer pattern 20 is obtained. The above process is cumbersome and time-consuming, and the process of measuring the center position will also introduce measurement errors, affecting the accuracy of the overlay error. Summary of the Invention

[0005] In order to obtain the overlay error conveniently and time - savingly and ensure the accuracy of the overlay error, the present invention provides an overlay mark pattern. The present invention also provides a method for obtaining the overlay error.

[0006] On the one hand, the present invention provides an overlay mark pattern, which includes:

[0007] The first process layer mark, used as a reference mark, the first process layer mark includes at least one main scale pattern, the main scale pattern includes a main scale zero line and a plurality of main scale graduation lines arranged in sequence at a first pitch; and

[0008] The second process layer mark, used to align with the first process layer mark, the second process layer mark includes a first vernier scale pattern corresponding to each main scale pattern in the first process layer mark, the first vernier scale pattern includes a first vernier scale zero line and a plurality of first vernier scale graduation lines arranged in sequence at a second pitch;

[0009] Wherein, the line widths of the main scale zero line, the main scale graduation lines, the first vernier scale zero line and the first vernier scale graduation lines are equal to a set width and equal to the first pitch, the first pitch is greater than the second pitch, the main scale zero line and the first vernier scale zero line are aligned and the actual position deviation is the overlay error of the second process layer mark relative to the first process layer mark in the corresponding line width direction.

[0010] Optionally, the difference between the total length of N first pitches in the main scale pattern and the total length of N second pitches in the first vernier scale pattern is equal to the set width, the actual position deviation is an integer multiple of d / N, N is a positive integer greater than 1, and d represents the set width.

[0011] Optionally, in a set of corresponding main scale patterns and the first vernier scale patterns formed on the same substrate, the nth first vernier scale graduation line after the first vernier scale zero line is aligned left and right with a main scale graduation line, n is a positive integer and 1 < n ≦ N.

[0012] Optionally, in a set of corresponding main scale patterns and the first vernier scale patterns formed on the same substrate, the nth first vernier scale graduation line after the first vernier scale zero line is aligned left and right with the gap between two adjacent main scale graduation lines, n is a positive integer and 1 < n ≦ N.

[0013] Optionally, in the first process layer mark, the line width directions of one main scale pattern and another corresponding main scale pattern are perpendicular.

[0014] Optionally, the overlay mark pattern further includes:

[0015] The third process layer mark, used to align with the first process layer mark, the third process layer mark includes a second vernier scale pattern corresponding to each main scale pattern in the first process layer mark, the second vernier scale pattern includes a second vernier scale zero line and a plurality of second vernier scale graduation lines arranged in sequence at a third pitch, and the second vernier scale zero line and the plurality of second vernier scale graduation lines have a third line width;

[0016] Wherein, the line widths of the second vernier zero line and the second vernier scale lines are equal to the set width, the first spacing is greater than the third spacing, and when formed on the same substrate, the main scale zero line and the second vernier zero line are aligned and the actual position deviation is the overlay error of the third process layer mark relative to the first process layer mark.

[0017] Optionally, the second process layer mark also serves as a reference mark, and the overlay mark pattern further includes:

[0018] A fourth process layer mark for aligning with the second process layer mark, the fourth process layer mark includes third vernier patterns corresponding to each of the first vernier patterns in the second process layer mark, and the third vernier patterns include a third vernier zero line and a plurality of third vernier scale lines arranged in sequence at a fourth spacing;

[0019] Wherein, the line widths of the third vernier zero line and the third vernier scale lines are equal to the set width, the second spacing is greater than the fourth spacing, and when formed on the same substrate, the third vernier zero line and the first vernier zero line are aligned and the actual position deviation is the overlay error of the fourth process layer mark relative to the second process layer mark.

[0020] Optionally, the first process layer mark and the second process layer mark are formed in the cross area or the T-shaped area of the substrate scribe lane region.

[0021] On the other hand, the present invention provides an overlay error acquisition method using the above overlay mark pattern, and the overlay error acquisition method includes:

[0022] Providing a substrate on which the first process layer mark and the first process layer mark are formed; and

[0023] According to the image including the first process layer mark and the second process layer mark, selecting the corresponding main scale pattern and the first vernier pattern, and calculating the actual position deviation between the main scale zero line and the first vernier zero line to obtain the overlay error of the second process layer mark relative to the first process layer mark in the corresponding line width direction.

[0024] Optionally, the actual position deviation satisfies: X_OVL = L1 + L2, where X_OVL represents the actual position deviation, L1 represents the offset of the first vernier zero line relative to the main scale zero line that is an integer multiple of the set width, and L2 represents the offset of the first vernier zero line relative to the main scale zero line that is less than the set width.

[0025] Optionally, the difference between the total length of the N first spacings in the main scale pattern and the total length of the N second spacings in the first vernier scale pattern is equal to the set width; when calculating the actual position deviation, read the serial number n of the first vernier scale line that is aligned with the gap between the main scale line or two adjacent main scale lines after the first vernier zero line, and L2 is equal to the product of n and d / N.

[0026] The overlay mark pattern provided by the present invention has the following advantages: after the first process layer mark and the second process layer mark are successively formed on the substrate and an image including both is obtained, the first vernier scale line aligned with the main scale pattern can be read by the vernier principle, and the actual position deviation of the first vernier zero line relative to the main scale zero line can be calculated quickly and accurately, so as to obtain the overlay error in the corresponding line width direction; moreover, the main scale line is equal to the first spacing, and when reading the aligned first vernier scale line, the first vernier scale line aligned with the main scale line or the first vernier scale line aligned with the gap between two adjacent main scale lines can be selected, which helps to improve the continuity of the actual position deviation value and is convenient for reducing the number and area of the main scale lines; in addition, by setting the difference between the total length of the N first spacings in the main scale pattern and the total length of the N second spacings in the first vernier scale pattern to be equal to the set width, the position deviation caused by each second spacing is d / N, and the actual position deviation is an integer multiple of d / N. The smaller d / N is, the higher the calculation accuracy of the overlay error (i.e., the overlay error accuracy). The values of d and N can be adjusted according to needs, so as to flexibly adjust the overlay error accuracy, which helps to further improve the accuracy of the overlay error.

[0027] The overlay error acquisition method provided by the present invention uses the above overlay error pattern. For the first process layer mark and the first process layer mark successively formed on the substrate, according to the corresponding main scale pattern and the first vernier scale pattern, calculate the actual position deviation between the main scale zero line and the first vernier zero line, so as to obtain the overlay error of the second process layer mark relative to the first process layer mark in the corresponding line width direction, and has the same or similar advantages as the overlay mark pattern. Description of the Drawings

[0028] Figure 1 is a schematic diagram of a commonly used overlay mark pattern.

[0029] Figure 2 is a schematic diagram of the overlay mark pattern according to an embodiment of the present invention.

[0030] Figures 3A to 3C is a schematic diagram when the main scale zero line of the main scale pattern and the first vernier zero line of the first vernier scale pattern are aligned in the embodiment of the present invention.

[0031] Figure 4A and Figure 4B are schematic diagrams of the main scale pattern and the first vernier scale pattern with actual position deviations in the embodiments of the present invention.

[0032] Figure 5 are schematic diagrams of various arrangements of the first process layer mark and the second process layer mark in the embodiments of the present invention.

[0033] Figure 6 is a schematic diagram of the overlay mark pattern of another embodiment of the present invention.

[0034] Figure 7 is a schematic flowchart of a method for obtaining overlay error according to an embodiment of the present invention. Detailed implementation manners

[0035] The overlay mark pattern and the method for obtaining overlay error of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the terms "first", "second", etc. in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that, under appropriate circumstances, these terms used in this way can be replaced. It should be understood that the accompanying drawings of the specification all adopt very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the spatially relative terms are intended to include different orientations in use or operation in addition to the orientation described in the figures of the device. For example, if the structure in the drawings is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." can also include "under..." and other orientation relationships.

[0036] As described in the background art, when using Figure 1 the overlay mark pattern shown to obtain the overlay error, the process is cumbersome and time-consuming, and measurement errors will also be introduced, affecting the accuracy of the overlay error. The overlay mark pattern and the method for obtaining overlay error involved in the embodiments of the present invention can obtain the overlay error more conveniently and time-savingly compared with Figure 1 the overlay mark pattern shown, and ensure the accuracy of the overlay error. The specific description is as follows.

[0037] In an embodiment of the present invention, the overlay mark pattern includes at least two process layer marks, and each process layer mark is formed by a corresponding layer of process. Each layer of process includes a patterning process performed on a substrate (such as a silicon wafer or other suitable semiconductor substrate). In order to form the patterns of each layer of process at the set positions, the pattern of the later process layer (i.e., the alignment pattern) needs to be aligned with the pattern of the earlier process layer (i.e., the reference pattern). The process layer marks can be formed on the corresponding mask and transferred to the substrate through a patterning process on the substrate. By obtaining the overlay error of the later-formed process layer mark relative to the earlier-formed process layer mark on the same substrate, the alignment accuracy of the corresponding two layers of process can be characterized.

[0038] Referring to Figure 2 , in one embodiment, the overlay mark pattern includes a first process layer mark 110 (such as shown by the blue line in Figure 2 ) used as a reference mark and a second process layer mark 120 (such as shown by the green line in Figure 2 ) for aligning with the first process layer mark 110. By obtaining the overlay error of the second process layer mark 120 formed on the same substrate relative to the first process layer mark 110, the alignment accuracy of the corresponding two layers of process can be characterized. The process layer marks in the overlay mark pattern are not limited to two layers, and can also be three layers or more. First, the overlay mark pattern of the embodiment of the present invention will be described below by taking the first process layer mark 110 and the second process layer mark 120 shown in Figure 2 as an example.

[0039] The first process layer mark 110 includes at least one main scale pattern. As shown in Figure 2 , as an example, the first process layer mark 110 includes four main scale patterns 110a, 110b, 110c, and 110d, and the four main scale patterns respectively form a part of the four sides of a square. Taking the main scale pattern 110a located in the upper right corner in Figure 2 as an example, it includes a main scale zero line 111 and a plurality of main scale graduation lines 112 arranged in sequence at a first pitch S1. The line width direction of the main scale zero line 111 and the main scale graduation lines 112 is the scale length direction of the corresponding main scale pattern 110a. In this embodiment, the line widths of the main scale zero line 111 and the main scale graduation lines 112 and the first pitch S1 are equal, and are all equal to a set width d.

[0040] The second process layer mark 120 includes a first vernier scale pattern corresponding to each of the main scale patterns in the first process layer mark 110. The first vernier scale pattern and the corresponding main scale pattern form a vernier scale structure, and the vernier scale principle can be used for reading. As shown in Figure 2As shown, for example, the second process layer mark 120 includes four first vernier scale patterns 120a, 120b, 120c, and 120d corresponding to the four main scale patterns in the first process layer mark 110 respectively, and the four first vernier scale patterns are arranged parallel to the main scale patterns 110a, 110b, 110c, and 110d respectively. Taking Figure 2 the first vernier scale pattern 120a located in the upper right corner in Figure 2 as an example, it includes a first vernier zero line 121 and multiple first vernier scale lines 122 arranged in sequence at a second pitch S2. The line width direction of the first vernier zero line 121 and the first vernier scale lines 122 is the scale length direction of the first vernier scale pattern 120a. In this embodiment, the line widths of the first vernier zero line 121 and the first vernier scale lines 122 are equal to those of the main scale zero line 111, the main scale lines 112, and the first pitch S1 above, and are all a set width d.

[0041] As Figure 2 shown, for a set of corresponding main scale pattern (such as the main scale pattern 110a) and the first vernier scale pattern (such as the first vernier scale pattern 120a) formed on the same substrate, the line width directions of the main scale zero line 111, the main scale lines 112, the first vernier zero line 121, and the first vernier scale lines 122 are the same. When formed on the substrate, the first vernier zero line 121 is aligned with the main scale zero line 111 (i.e., designed to be aligned), but due to the overlay error, there is a deviation in the actual positions of the first vernier zero line 121 and the main scale zero line 111. By obtaining the actual position deviation of the first vernier zero line 121 relative to the main scale zero line 111, the overlay error of the second process layer mark 120 relative to the first process layer mark 110 in the corresponding line width direction (i.e., the line width direction of the main scale zero line 111) can be obtained.

[0042] As Figure 2 shown, the first process layer mark 110 and the second process layer mark 120 may include at least two sets of vernier scale structures composed of main scale patterns and corresponding first vernier scale patterns. Using each set of vernier scale structures, at least two overlay errors can be calculated respectively. These overlay errors can be directly used as the overlay error of the second process layer mark 120 relative to the first process layer mark 110, or can be further calculated from the at least two overlay errors and then used as the overlay error of the second process layer mark 120 relative to the first process layer mark 110. For example, in the first process layer mark 110, the line width directions corresponding to one main scale pattern (such as the main scale pattern 110a) and another main scale pattern (such as the main scale pattern 110b) are perpendicular to each other. The second process layer mark 120 has two corresponding first vernier scale patterns (such as the first vernier scale patterns 120a and 120b) that are perpendicular to each other. The overlay errors in the two perpendicular line width directions can be calculated respectively, and then the overlay error in the combined direction of the two line width directions can be calculated.

[0043] As an example, for a set of corresponding main scale patterns and first vernier scale patterns formed on the same substrate, the first vernier scale pattern includes N first vernier scale lines 122, and the main scale pattern includes M main scale lines 112 with M > N (M and N are positive integers). In a set of corresponding main scale patterns and first vernier scale patterns, for convenient reading, multiple main scale lines 112 after the main scale zero line 111 in the main scale pattern can be numbered in ascending order, and multiple first vernier scale lines 122 after the first vernier scale zero line 121 in the first vernier scale pattern can be numbered in ascending order. As Figures 3A to 3C and Figure 4A and Figure 4B shown, each line in the main scale pattern and the first vernier scale pattern has a serial number. Among them, the serial numbers of the main scale zero line 111 and the first vernier scale zero line 121 are 0, multiple main scale lines 112 after the main scale zero line 111 are respectively 1 to M (for example, M = 12), and multiple first vernier scale lines 122 after the first vernier scale zero line 121 are respectively 1 to N (for example, N = 10). It should be noted that Figures 3A to 3C and Figure 4A and Figure 4B the serial numbers on the lines shown are only markings for conveniently explaining the embodiments of the present invention below, and do not mean that these numbers are actually formed on the lines in the overlay mark pattern.

[0044] In this embodiment, since the first spacing S1 is greater than the second spacing S2, when the main scale zero line 111 and the first vernier scale zero line 121 are aligned left and right, that is, the overlay error is 0, the main scale line 112 and the first vernier scale line 122 with the same serial number are not aligned, and as the serial number increases, the position deviation between the main scale line 112 and the first vernier scale line 122 with the same serial number gradually increases. For example, it can increase to the above-mentioned set width d, that is, the difference between the total length of N first spacings S1 in the main scale pattern and the total length of N second spacings S2 in the first vernier scale pattern is equal to the set width d (i.e., equal to the line width in the main scale pattern and the first vernier scale pattern and the first spacing S2).

[0045] Referring to Figure 3A, for a set of corresponding main scale patterns (taking the above-mentioned main scale pattern 110a as an example, represented by blue lines, the same below) and first vernier scale patterns (taking the above-mentioned first vernier scale pattern 120a as an example, represented by green lines, the same below) formed on the same substrate, when the main scale zero line 111 and the first vernier scale zero line 121 are aligned left and right, the position deviation between the main scale graduation lines 112 and the first vernier scale graduation lines 122 with the same serial number gradually increases as the serial number increases, and the position deviation of the Nth first vernier scale graduation line 122 relative to the Nth main scale graduation line 112 is equal to the set width d (for example, N = 10). It can be understood that the position deviation of the Nth first vernier scale graduation line 122 relative to the Nth main scale graduation line 112 is formed by the accumulation of the change of N first intervals S1 between the first vernier scale zero line 121 and the Nth first vernier scale graduation line 122 compared with the second interval S2, and the position deviation caused by each second interval S2 is d / N. As Figure 3A shown, N is, for example, 10, d / N = d / 10. The position deviation value between the first first vernier scale graduation line 122 after the first vernier scale zero line 121 and the first main scale graduation line 112 after the main scale zero line 111 is d / 10, the position deviation value between the second first vernier scale graduation line 122 and the second main scale graduation line 112 is 2d / 10, the position deviation value between the third first vernier scale graduation line 122 and the third main scale graduation line 112 is 3d / 10, and so on. The position deviation value between the 10th first vernier scale graduation line 122 and the 10th main scale graduation line 112 is d. It can be seen that the position deviation between the first vernier scale graduation line 122 with a later serial number and the main scale graduation line 112 with the same serial number increases by d / N on the basis of the position deviation value corresponding to the first vernier scale graduation line 122 with the previous serial number. The actual position deviation of the first vernier scale zero line 121 relative to the main scale zero line 111 is an integer multiple of the position deviation d / N caused by each second interval S2. The larger d / N is, the lower the resolution of the corresponding main scale pattern and the first vernier scale pattern, that is, the lower the calculation accuracy of the overlay error (i.e., the overlay error accuracy). The smaller d / N is, the higher the resolution and the higher the overlay error accuracy. Therefore, the overlay error accuracy can be adjusted by adjusting the value of d / N. Referring to Figure 3B , in one embodiment, the value of N is the same as that in the embodiment shown in Figure 3A , and the value of d is smaller than that in the embodiment shown in Figure 3A , then Figure 3B the d / N in the embodiment shown is smaller, and the overlay error accuracy is higher than that in the embodiment shown in Figure 3A . Referring to Figure 3C , in another embodiment, the value of d is smaller than that in the embodiment shown in Figure 3A , and the value of N is larger than that in the embodiment shown in Figure 3A , then Figure 3CThe d / N of the shown embodiment is small, and the overlay error precision is relatively Figure 3A higher than that of the shown embodiment.

[0046] The above-mentioned first process layer mark 110 and second process layer mark 120 can be formed in the scribe lane area on the substrate. Since the smaller the d / N, the higher the overlay error precision. When the difficulty of reducing d is limited, improving the overlay error precision means that N needs to be increased, which will make the shapes of a group of corresponding main scale patterns and first vernier scale patterns become more "narrow". Considering the characteristics of the scribe lane area, the first process layer mark 110 and the second process layer mark 120 can be arranged in the cross area or T-shaped area of the scribe lane area. In this way, different vernier scale structures including main scale patterns and first vernier scale patterns can be arranged along different side lines of the cross area or T-shaped area, which is convenient for obtaining a higher overlay error precision without causing overcrowding in the scribe lane area.

[0047] In this embodiment, the actual position deviation between the main scale zero line 111 and the first vernier scale zero line 121 formed on the same substrate is calculated to obtain the overlay error in the corresponding line width direction. The actual position deviation can be greater than, equal to, or less than the set width d. The actual position deviation satisfies equation (1):

[0048] X_OVL = L1 + L2 (1)

[0049] Wherein, X_OVL represents the actual position deviation, L1 represents the integer multiple offset equal to the set width d of the first vernier scale zero line 121 relative to the main scale zero line 111 formed on the same substrate, and L2 represents the offset less than the set width d of the first vernier scale zero line 121 relative to the main scale zero line 111 formed on the same substrate. When calculating L1, according to the image including the corresponding main scale pattern and first vernier scale pattern, it can be judged whether the offset of the first vernier scale zero line 121 relative to the main scale zero line 111 includes one or more set widths d. If it includes, L1 is equal to the product of the set width d and the corresponding multiple. If it does not include, L1 = 0. When calculating L2, check the first vernier scale line 122 after the first vernier scale zero line 121, and read the serial number of the first vernier scale line 122 that is aligned with the gap between the main scale line 112 or two adjacent main scale lines 112. This serial number is the number of the second spacing S2 causing the deviation, and L2 is the product of the number of the second spacing S2 causing the deviation and the position deviation d / N caused by each second spacing S2. It can be seen that L2 is related to the serial number of the first vernier scale line 122 and has nothing to do with the serial number of the main scale line 112.

[0050] Such as Figure 4AAs shown, in one embodiment, among a set of corresponding main scale patterns (taking the main scale pattern 110a as an example above) and the first vernier scale pattern (taking the first vernier scale pattern 120a as an example above) formed on the same substrate, the nth first vernier scale line 122 after the first vernier zero line 121 is aligned left and right with a main scale line 112, where n is a positive integer and 1 < n ≤ N. For example, when n = 3, then L2 = 3d / N; as Figure 4B As shown, in another embodiment, among a set of corresponding main scale patterns and the first vernier scale pattern formed on the same substrate, the nth first vernier scale line 122 after the first vernier zero line 121 is aligned left and right with the gap between two adjacent main scale lines 112, where n is a positive integer and 1 < n ≤ N. For example, when n = 5, then L2 = 5d / N. It can be seen that when checking the alignment position of the first vernier scale line 122, since the line widths of the main scale zero line 111, the main scale line 112, the first vernier zero line 121, and the first vernier scale line 122 and the first spacing S1 are all equal to the set width, readings can be taken either according to the position aligned with the main scale line 112 or according to the position aligned with the gap between two adjacent main scale lines 112, which is convenient for improving the continuity of the calculation results and reducing the number and area of the main scale lines 112.

[0051] The above embodiments describe the arrangement of a set of corresponding main scale patterns and the first vernier scale pattern in the first process layer mark 110 and the second process layer mark 120 and the process of obtaining the actual position deviation. When the first process layer mark 110 and the second process layer mark 120 include more than one set of corresponding main scale patterns and the first vernier scale pattern, the other sets of main scale patterns and the first vernier scale pattern can also obtain the actual position deviation in the line width direction, that is, the overlay error, according to the description of the above embodiments.

[0052] The arrangement of the first process layer mark 110 and the second process layer mark 120 is not limited to Figure 2 the shape shown, but can be set as needed. As an example, Figure 5 shows six other arrangement shapes of the first process layer mark 110 and the second process layer mark 120, where the blue line represents the first process layer mark 110 and the green line represents the second process layer mark 120; among them, the first process layer mark 110 and the second process layer mark 120 shown in (a) are Figure 2 rotated 45° clockwise or counterclockwise; compared with (a), in the first process layer mark 110 and the second process layer mark 120 shown in (b), the distance between different sets of vernier scale structures including the main scale pattern and the first vernier scale pattern increases, and the second process layer mark 120 has a cross center point; compared with Figure 2, among the first process layer marks 110 and the second process layer marks 120 shown in (c), the distances between different groups of vernier structures including main scale patterns and first vernier scale patterns increase, and the second process layer marks 120 have cross center points; compared with (a), (c) and (b) respectively, the aspect ratios of the lines in the four groups of main scale patterns and first vernier scale patterns shown in (d), (e) and (f) decrease.

[0053] The overlay mark patterns of the embodiments of the present invention may also include marks corresponding to other layer processes. Refer to Figure 6 , in one embodiment, the overlay mark pattern includes, in addition to the first process layer marks 110 (represented by blue lines) used as reference marks and the second process layer marks 120 (represented by green lines) for aligning with the first process layer marks 110, a third process layer mark 130 (represented by yellow lines). The third process layer mark 130, the first process layer mark 110, and the second process layer mark 120 are all formed by different layer processes, and the third process layer mark 130 is also used to align with the first process layer mark 110. By obtaining the actual position deviation of the third process layer mark 130 formed on the same substrate relative to the first process layer mark 110, the overlay error and alignment accuracy of the corresponding two-layer processes can be obtained. Similar to the second process layer marks 120, the third process layer marks 130 include second vernier scale patterns corresponding to each of the main scale patterns in the first process layer marks 110. The second vernier scale patterns include second vernier zero lines and a plurality of second vernier scale lines arranged at a third pitch in sequence. The line widths of the second vernier zero lines and the second vernier scale lines are equal to the set width d. The first pitch S1 is greater than the third pitch. The second vernier zero line is aligned with the main scale zero line 111, and the actual position deviation is the overlay error of the third process layer mark 130 relative to the first process layer mark 110.

[0054] In the overlay mark pattern, according to the alignment requirement, a process layer mark formed first can be selected as a reference mark, and an alignment is performed using a process layer mark formed later. For example, in addition to being used to align with the first process layer mark 110 serving as a reference mark, the second process layer mark 120 described above can also serve as a reference mark for aligning with process layer marks formed later as needed. As an example, in an embodiment, the second process layer mark 120 also serves as a reference mark, and the overlay mark pattern further includes a fourth process layer mark (not shown in the figure). The fourth process layer mark is used to align with the second process layer mark 120. Similar to the features of the two process layer marks to be aligned described above, the fourth process layer mark includes third vernier patterns corresponding to each of the first vernier patterns in the second process layer mark 120. The third vernier patterns include a third vernier zero line and a plurality of third vernier scale lines arranged in sequence at a fourth pitch. The line widths of the third vernier zero line and the third vernier scale lines are equal to a set width d. The second pitch S2 is greater than the fourth pitch. The third vernier zero line is aligned with the first vernier zero line 121, and the actual position deviation is the overlay error of the fourth process layer mark relative to the second process layer mark 120.

[0055] Using the overlay mark pattern described in the above embodiment, the alignment position of the first vernier scale line of the first vernier pattern on the main scale pattern can be quickly read through the vernier principle. Furthermore, the actual position deviation of the first vernier zero line relative to the main scale zero line can be conveniently and accurately calculated, so as to obtain the overlay error in the corresponding line width direction. When reading the aligned first vernier scale line, the first vernier scale line aligned with the main scale line or the first vernier scale line aligned with the gap between two adjacent main scale lines can be selected, which helps to improve the continuity of the actual position deviation value and facilitates reducing the number and area of the main scale lines. In addition, by setting the difference between the total length of the N first pitches in the main scale pattern and the total length of the N second pitches in the first vernier pattern to be equal to the set width d, the position deviation caused by each second pitch S2 is d / N. The smaller d / N is, the higher the overlay error accuracy. The values of d and N can be adjusted according to needs, so as to flexibly adjust the overlay error accuracy and help to further improve the accuracy of the overlay error.

[0056] An embodiment of the present invention further relates to a method for obtaining an overlay error. The method for obtaining an overlay error uses the overlay mark pattern described in the above embodiment.

[0057] Refer to Figures 2 to 7, the overlay error acquisition method includes: first, perform step S1 to provide a substrate (such as a silicon wafer or other suitable semiconductor substrate), on which a first process layer mark 110 and a second process layer mark 120 are successively formed; then perform step S2, according to the image including the first process layer mark 110 and the second process layer mark 120, select the corresponding main scale pattern and the first vernier scale pattern, and calculate the actual position deviation between the main scale zero line 111 and the first vernier scale zero line 121, so as to obtain the overlay error of the second process layer mark 120 relative to the first process layer mark 110 in the corresponding line width direction.

[0058] When the first process layer mark 110 and the second process layer mark 120 include multiple groups of the main scale pattern and the first vernier scale pattern, the overlay errors in the corresponding line width directions can be respectively calculated by using each group of the main scale pattern and the first vernier scale pattern. The at least two obtained overlay errors can be directly used as the overlay error of the second process layer mark 120 relative to the first process layer mark 110, or the at least two overlay errors can be further calculated to obtain the overlay error of the second process layer mark 120 relative to the first process layer mark 110. For example, if the first process layer mark 110 includes two main scale patterns perpendicular to the line width direction, in combination with the corresponding two mutually perpendicular first vernier scale patterns, the overlay errors in the two mutually perpendicular line width directions can be respectively calculated, and then the overlay error in the combined direction of the two line width directions can be calculated.

[0059] Refer to Figure 4A and Figure 4B , when calculating the actual position deviation between the main scale zero line 111 and the first vernier scale zero line 121, the actual position deviation value can be calculated by the following formula: X_OVL = L1 + L2, where X_OVL represents the actual position deviation, L1 represents the integer multiple offset equal to the set width d of the first vernier scale zero line 121 compared with the main scale zero line 111 formed on the same substrate, and L2 represents the offset less than the set width d of the first vernier scale zero line 121 compared with the main scale zero line 111 formed on the same substrate. When calculating L1, according to the image including the corresponding main scale pattern and the first vernier scale pattern, it can be judged whether the offset of the first vernier scale zero line 121 compared with the main scale zero line 111 includes one or more set widths d. If it includes, L1 is equal to the product of the set width d and the corresponding multiple. If it does not include, L1 = 0. When calculating L2, check the first vernier scale line 122 after the first vernier scale zero line 121, and read the serial number of the first vernier scale line 122 aligned with the gap between the main scale line 112 or two adjacent main scale lines 112. This serial number is the number of the second spacing S2 causing the deviation, and L2 is the product of the number of the second spacing S2 causing the deviation and the position deviation d / N caused by each second spacing S2.

[0060] Using the overlay error acquisition method described above, the first vernier scale line 122 aligned with the main scale pattern can be read according to the vernier principle, and the actual position deviation of the first vernier zero line 121 relative to the main scale zero line 111 can be quickly calculated, so as to obtain the overlay error in the corresponding line width direction and ensure accuracy. Since the line widths of the main scale zero line 111, the main scale scale line 112, the first vernier zero line 121 and the first vernier scale line 122 are equal to the set width d and equal to the first spacing S1, when reading the aligned first vernier scale line 122, the first vernier scale line 122 aligned with the main scale scale line 112 or the first vernier scale line 122 aligned with the gap between two adjacent main scale scale lines 112 can be selected, which helps to improve the continuity of the actual position deviation value and facilitates reducing the number and area of the main scale scale lines 112. In addition, the overlay error accuracy can be adjusted as needed, which helps to further improve the accuracy of the overlay error.

[0061] It should be noted that the embodiments in this specification are described in a progressive manner, and the key points of each part are the differences from the previous part. The relevant parts can be understood by reference.

[0062] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the technical solutions of the present invention all belong to the protection scope of the technical solutions of the present invention.

Claims

1. A lithography mark pattern, characterized in that Including: A first process layer mark, used as a reference mark, the first process layer mark includes at least one main scale pattern, the main scale pattern includes a main scale zero line and a plurality of main scale graduation lines arranged in sequence at a first pitch; And A second process layer mark, used to align with the first process layer mark, the second process layer mark includes a first vernier scale pattern corresponding to each main scale pattern in the first process layer mark, the first vernier scale pattern includes a first vernier scale zero line and a plurality of first vernier scale graduation lines arranged in sequence at a second pitch; Wherein, the line widths of the main scale zero line, the main scale graduation lines, the first vernier scale zero line and the first vernier scale graduation lines are equal to a set width and equal to the first pitch, the first pitch is greater than the second pitch, the main scale zero line and the first vernier scale zero line are aligned and the actual position deviation is the overlay error of the second process layer mark relative to the first process layer mark in the corresponding line width direction.

2. The overlay mark pattern according to claim 1, wherein The difference between the total length of N first pitches in the main scale pattern and the total length of N second pitches in the first vernier scale pattern is equal to the set width, the actual position deviation is an integer multiple of d / N, N is a positive integer greater than 1, and d represents the set width.

3. The overlay mark pattern according to claim 1, wherein In a set of corresponding main scale patterns and the first vernier scale patterns formed on the same substrate, the nth first vernier scale graduation line after the first vernier scale zero line is aligned left and right with a main scale graduation line, where n is a positive integer and 1 < n ≤ N.

4. The overlay mark pattern according to claim 1, wherein In a set of corresponding main scale patterns and the first vernier scale patterns formed on the same substrate, the nth first vernier scale graduation line after the first vernier scale zero line is aligned left and right with the gap between two adjacent main scale graduation lines, where n is a positive integer and 1 < n ≤ N.

5. The overlay mark pattern according to claim 1, wherein In the first process layer mark, the line width directions of one main scale pattern and another corresponding main scale pattern are perpendicular to each other.

6. The overlay mark pattern according to claim 1, wherein Further including: A third process layer mark, used to align with the first process layer mark, the third process layer mark includes a second vernier scale pattern corresponding to each main scale pattern in the first process layer mark, the second vernier scale pattern includes a second vernier scale zero line and a plurality of second vernier scale graduation lines arranged in sequence at a third pitch, and the second vernier scale zero line and the plurality of second vernier scale graduation lines have a third line width; Wherein, the line widths of the second vernier scale zero line and the second vernier scale graduation lines are equal to the set width, the first pitch is greater than the third pitch, and when formed on the same substrate, the main scale zero line and the second vernier scale zero line are aligned and the actual position deviation is the overlay error of the third process layer mark relative to the first process layer mark.

7. The overlay mark pattern according to claim 1, wherein The second process layer mark also serves as a reference mark, and the overlay mark pattern further includes: The fourth process layer mark is used to align with the second process layer mark. The fourth process layer mark includes third vernier graphics corresponding to each of the first vernier graphics in the second process layer mark. The third vernier graphics include a third vernier zero line and a plurality of third vernier scale lines arranged at a fourth interval in sequence. Among them, the line widths of the third vernier zero line and the third vernier scale lines are equal to the set width. The second interval is greater than the fourth interval. When formed on the same substrate, the third vernier zero line and the first vernier zero line are aligned and the actual position deviation is the overlay error of the fourth process layer mark relative to the second process layer mark.

8. The overlay mark pattern according to claim 1, wherein The first process layer mark and the second process layer mark are formed in the cross area or the T-shaped area of the substrate scribe lane area.

9. A method for obtaining overlay error by using an overlay mark pattern as described in any one of claims 1 to 8, characterized in that, The method for obtaining the overlay error includes: According to the image including the first process layer mark and the second process layer mark, select the corresponding main scale graphics and the first vernier graphics, and calculate the actual position deviation between the main scale zero line and the first vernier zero line to obtain the overlay error of the second process layer mark relative to the first process layer mark in the corresponding line width direction.

10. The overlay error obtaining method according to claim 9, wherein, The actual position deviation satisfies: X_OVL = L1 + L2, where X_OVL represents the actual position deviation, L1 represents the offset of the first vernier zero line relative to the main scale zero line that is an integer multiple of the set width, and L2 represents the offset of the first vernier zero line relative to the main scale zero line that is less than the set width.

11. The overlay error acquisition method according to claim 10, wherein, The difference between the total length of N first intervals in the main scale graphics and the total length of N second intervals in the first vernier graphics is equal to the set width. When calculating the actual position deviation, read the serial number n of the first vernier scale line that is aligned with the gap between the main scale line or two adjacent main scale lines after the first vernier zero line, and L2 is equal to the product of n and d / N.

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