Tunneling field effect transistor, preparation method thereof, photon chip and optical communication equipment

Abstract

The invention belongs to the technical field of transistors, and particularly relates to a tunneling field effect transistor, a preparation method thereof, a photon chip and optical communication equipment. According to the tunneling field effect transistor, the tunnel junction is formed in the tunneling field active layer, the tunnel junction has a certain junction area and is perpendicular to the gate electrode, the distance of a tunneling channel is further shortened through the strong control force of the gate electrode on the whole tunnel junction, the on-state current of the tunneling field effect transistor can be improved, and the power consumption of a device can be reduced. Meanwhile, according to the design mode, the reconfigurable characteristic of the field tunneling effect transistor can be conveniently achieved, so that the flexibility and adaptability of the device are improved, and the design mode is crucial for developing smaller and more energy-saving circuits.

Description

Technical Field

[0001] This application belongs to the technical field of transistors, and particularly relates to a tunneling field effect transistor, a preparation method thereof, a photon chip, and an optical communication device. Background Art

[0002] Since the steep subthreshold swing (SS) characteristic has a great influence on the characteristics of thin film transistors (TFTs), in order to improve the SS of TFTs, tunneling field effect transistors (TFETs) have been widely studied. The working principle of TFETs is band-to-band tunneling, rather than the thermal injection effect of electrons and holes, which can effectively suppress the adverse effects brought by the short-channel effect. Its SS can be less than the limit of 60 mV / decade, the gate control efficiency is improved, the device can achieve the on-state faster, and the leakage current (Ioff) of TFETs is very low. Therefore, TFETs can reduce the working voltage of field effect transistors (FETs) without increasing Ioff. For low-frequency applications dominated by static power consumption, it is expected to greatly reduce the device power consumption.

[0003] Therefore, TFETs are regarded as very promising low working voltage and low power consumption complementary metal oxide semiconductor (CMOS) devices.

[0004] However, the performance of TFETs is not yet ideal enough, which greatly limits their practical applications. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail in this application. This summary is not intended to limit the protection scope of this application.

[0006] The purpose of the embodiments of this application is to provide a tunneling field effect transistor, a preparation method thereof, a photon chip, and an optical communication device, which are used to improve the performance of the tunneling field effect transistor. The specific technical solutions are as follows:

[0007] The first aspect of this application is to provide a tunneling field effect transistor, including: a substrate, a gate electrode, a tunneling field active layer, a source electrode, and a drain electrode stacked along a first direction;

[0008] The tunneling field active layer includes a first active layer and a second active layer that are spaced apart in a second direction; a channel region is provided between the first active layer and the second active layer; the second direction is different from the first direction; the first active layer has a first type of doping, the second active layer has a second type of doping, and the first type of doping is different from the second type of doping;

[0009] The first active layer is connected to the source electrode, and the second active layer is connected to the drain electrode;

[0010] The positive projection of the gate electrode on the substrate and the positive projection of the first active layer on the substrate have a first partial overlap;

[0011] The positive projection of the gate electrode on the substrate and the positive projection of the second active layer on the substrate have a second partial overlap.

[0012] In some embodiments of the present application, the first type of doping is N-type heavy doping, and the second type of doping is P-type heavy doping;

[0013] Or, the first type of doping is P-type heavy doping, and the second type of doping is N-type heavy doping.

[0014] In some embodiments of the present application, a first metal barrier layer is provided between the first active layer and the source electrode, and the positive projection of the first metal barrier layer on the substrate is located within the positive projection of the first active layer on the substrate;

[0015] A second metal barrier layer is provided between the second active layer and the drain electrode, and the positive projection of the second metal barrier layer on the substrate is located within the positive projection of the second active layer on the substrate.

[0016] In some embodiments of the present application, along the second direction, the width of the first partial overlap is equal to the width of the second partial overlap.

[0017] In some embodiments of the present application, it further includes an isolation layer, and the isolation layer is disposed to cover the tunneling field active layer;

[0018] The isolation layer is provided with a first trench and a second trench, and the source electrode penetrates through the first trench to connect to the first active layer; the drain electrode penetrates through the second trench to connect to the second active layer.

[0019] In some embodiments of the present application, it further includes a gate insulating layer, wherein the gate insulating layer is disposed to cover the gate;

[0020] Or, the gate insulating layer is disposed on the side of the gate facing the substrate.

[0021] In some embodiments of the present application, it includes a plurality of tunneling field effect transistors, and each of the tunneling field effect transistors is arranged at intervals along the second direction on the same substrate;

[0022] It further includes a common gate, a common source and a common drain, and the common gate, the common source and the common drain are arranged above the substrate along the first direction;

[0023] The gate electrodes of each of the tunneling field effect transistors are respectively connected to the common gate;

[0024] The source electrodes of each of the tunneling field effect transistors are respectively connected to the common source;

[0025] The drain electrodes of each of the tunneling field effect transistors are respectively connected to the common drain.

[0026] In some embodiments of the present application, each of the tunneling field effect transistors is arranged at equal-distance intervals along the second direction on the same substrate.

[0027] In some embodiments of the present application, the first direction is perpendicular to the second direction.

[0028] In some embodiments of the present application, the material of the gate insulating layer includes a stack formed by any one or more of silicon oxide, silicon nitride, silicon oxynitride and other high-K materials; the thickness of the gate insulating layer is 10 nm to 100 nm.

[0029] In some embodiments of the present application, the substrate is a glass substrate.

[0030] In some embodiments of the present application, the material of the tunneling field active layer includes metal oxide semiconductor or Group IV elements.

[0031] In some embodiments of the present application, the metal oxide semiconductor includes any one of zinc oxide, indium oxide, titanium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium titanium zinc oxide or indium tin oxide;

[0032] The Group IV elements include one or two of silicon and germanium.

[0033] The second aspect of the present application is to provide a photon chip, including the tunneling field effect transistor described in the first aspect as a rectifying switch.

[0034] The third aspect of the present application is to provide an optical communication device, including the photon chip described in the second aspect.

[0035] The fourth aspect of the present application is to provide a preparation method of a tunneling field effect transistor, including the following preparation process:

[0036] Provide a substrate;

[0037] Deposit and form a tunneling field active layer on one surface of the substrate;

[0038] Perform ion implantation on both sides of the tunneling field active layer in the first direction to form a first active layer with a first type of doping and a second active layer with a second type of doping, wherein the first type of doping is different from the second type of doping; the first active layer and the second active layer are spaced apart in the second direction, and a channel region is formed between the first active layer and the second active layer;

[0039] Deposit and form an isolation layer on the surface of the tunneling field active layer facing away from the substrate;

[0040] First trenches and second trenches are etched in the isolation layer;

[0041] Deposit and form a source electrode, a drain electrode, and a gate electrode on the surface of the isolation layer facing away from the substrate. The source electrode penetrates the isolation layer to connect to the first active layer, and the drain electrode penetrates the isolation layer to connect to the second active layer; the positive projection of the gate electrode on the substrate partially overlaps with the positive projection of the first active layer on the substrate; the positive projection of the gate electrode on the substrate partially overlaps with the positive projection of the second active layer on the substrate.

[0042] In some embodiments of the present application, before depositing and forming the isolation layer on the surface of the tunneling field active layer facing away from the substrate, deposit and form a first metal barrier layer on the surface of the first active layer facing away from the substrate, and deposit and form a second metal barrier layer on the surface of the first active layer facing away from the substrate, wherein the positive projection of the first metal barrier layer on the substrate is within the positive projection range of the first active layer on the substrate, and the positive projection of the second metal barrier layer on the substrate is within the positive projection range of the second active layer on the substrate. Description of the Drawings

[0043] The drawings are used to provide an understanding of the technical solutions of the present application and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application and do not constitute a limitation to the technical solutions of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0044] Figure 1 Schematically shows a structural diagram of a thin film transistor according to some embodiments of the present application;

[0045] Figure 2ASchematically shows a structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0046] Figure 2B Schematically shows another structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0047] Figure 3A Schematically shows a structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0048] Figure 3B Schematically shows another structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0049] Figure 4A Schematically shows a structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0050] Figure 4B Schematically shows another structural schematic diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0051] Figure 5A Schematically shows a structural schematic diagram of a tunneling field-effect unit according to some embodiments of the present application;

[0052] Figure 5B Schematically shows Figure 5A the electrode connection diagram of;

[0053] Figure 6A Schematically shows another structural schematic diagram of a tunneling field-effect unit according to some embodiments of the present application;

[0054] Figure 6B Schematically shows Figure 6A the electrode connection diagram of;

[0055] Figure 7 Schematically shows the circuit diagram of a tunneling field-effect transistor according to some embodiments of the present application;

[0056] Figure 8 Schematically shows the circuit diagram of an existing field-effect transistor;

[0057] Figure 9 Schematically shows the schematic diagram of the manufacturing process steps of a tunneling field-effect transistor according to some embodiments of the present application;

[0058] Figures 10 to 22 Schematically shows Figure 1 the structural schematic diagrams obtained in each step during the preparation process of a thin-film transistor;

[0059] Figures 23 to 24Schematically shows the test result diagram of the tunneling field-effect transistor according to some embodiments of the present application;

[0060] The reference numerals in the drawings are as follows:

[0061] 10000, tunneling field-effect transistor;

[0062] 1000, substrate;

[0063] 1100, buffer layer;

[0064] 1200, channel region;

[0065] 1300, first active layer;

[0066] 1400, second active layer;

[0067] 1500, metal barrier layer; 1510, first metal barrier layer; 1520, first metal barrier layer;

[0068] 1600, isolation layer;

[0069] 1700, electrode; 1710, source electrode; 1710a, first source electrode; 1710b, second source electrode;

[0070] 1720, drain electrode; 1720a, first drain electrode; 1720b, second drain electrode;

[0071] 1800, gate insulating layer;

[0072] 1900, gate electrode; 1900a, first gate electrode; 1900b, second gate electrode;

[0073] A, first trench;

[0074] B, second trench;

[0075] 10000a, first tunneling field-effect transistor;

[0076] 10000b, second tunneling field-effect transistor;

[0077] 20000, common gate electrode;

[0078] 30000, common source electrode;

[0079] 40000, common drain electrode. Detailed implementation manners

[0080] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described below with reference to the accompanying drawings and specific embodiments. The implementation modes in the present application can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation modes and contents can be transformed into various forms without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited only to the contents described in the following implementation modes. Without conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0081] Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. The drawing scale can be used as a reference in actual processes, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The accompanying drawings described in the present application are only structural schematic diagrams, and one implementation mode of the present application is not limited to the shapes or values shown in the accompanying drawings.

[0082] In the context of the present application, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0083] In the description of the present application, ordinal numbers such as "first" and "second" are set to avoid confusion of components and are not used to limit the quantity.

[0084] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of components with reference to the accompanying drawings, only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. The positional relationships of the components are appropriately changed according to the directions for describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0085] In this specification, unless otherwise clearly specified and defined, the terms "arrangement" and "connection" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application may be understood according to specific circumstances.

[0086] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain, and a source. The transistor has a channel region between the drain and the source, and current can flow through the drain, the channel region, and the source. Note that in this specification, the channel region refers to the region where current mainly flows.

[0087] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "buffer layer" can be changed to "buffer film".

[0088] TFET is a new type of device that replaces MOSFET. It uses the quantum mechanical tunneling effect instead of thermionic emission to overcome the high energy consumption limitation faced by MOSFET devices. The on-current of TFET is mainly affected by band-to-band tunneling and is not affected by the drift-diffusion mechanism. When the device is in the off state, the energy band barrier between the source region and the channel is very wide, and there are no carriers in the channel, so the off-state current is extremely low to reduce the high energy consumption of the device. When the device is in the on state, under a relatively high gate voltage, a relatively small barrier is formed between the source region and the surface of the channel of the device. For example, the energy band of the existing N-type TFET in the on state is as Figure 1 shown.

[0089] Analyzed from the perspective of quantum mechanics, once the conduction band in the channel region is lower than the valence band in the source region, a large number of electron states with higher energy below the valence band in the source region can easily tunnel into the channel region and be absorbed by the empty states in the channel. The electrons tunneling from the source region to the channel will form a tunneling current, which is not affected by temperature but determined by the band-to-band tunneling rate. The band-to-band tunneling rate is as follows:

[0090]

[0091] where λ is the barrier width of the tunneling junction, which is related to the gate voltage and the tunneling junction material, and m* is the effective mass of the tunneling carrier. The tunneling current of the TFET device is related to various factors such as the device structure and materials. Usually, narrow bandgap materials such as germanium, germanium selenide, InAs, etc. are used in the source region, and materials with a large bandgap are selected for the channel and drain regions, which helps to reduce the tunneling barrier width and increase the band-to-band tunneling current. In particular, some III-V materials and silicon-germanium heterojunctions can enable TFET to obtain a high on-off current ratio and an ultra-low subthreshold swing.

[0092] Existing TFET devices mostly use silicon materials as the substrate to form silicon-based TFETs. On the one hand, silicon materials are indirect bandgap with a large bandgap width, resulting in a relatively low electron migration rate in the channel. On the other hand, the conduction mechanism of silicon-based TFETs, such as the band-to-band tunneling mechanism mentioned above, has its tunneling current limited by the tunneling probability, such as the band-to-band tunneling rate in formula (1) above. Therefore, silicon-based TFETs do not have as high a drive current (on-state current) as traditional MOSFETs, and the on-state current largely determines the operating speed of transistor circuits. Generally speaking, if the on-state current is too low, the performance will be difficult to meet. In practical applications, this will bring great delays to the circuits composed of TFET devices, which is not conducive to large-scale integration and limits its application.

[0093] An embodiment of the present application provides a tunneling field effect transistor, which includes a substrate, a gate electrode, a tunneling field active layer, and source / drain electrodes stacked along a first direction; the tunneling field active layer includes a first active layer and a second active layer spaced along a second direction; a channel region is provided between the first active layer and the second active layer; the second direction is different from the first direction; the first active layer has a first type of doping, the second active layer has a second type of doping, and the first type of doping is different from the second type of doping; and the first active layer is connected to the source electrode, the second active layer is connected to the drain electrode; the positive projection of the gate electrode on the substrate and the positive projection of the first active layer on the substrate have a first partial overlap; the positive projection of the gate electrode on the substrate and the positive projection of the second active layer on the substrate have a second partial overlap.

[0094] The tunneling field effect transistor of the present application forms a tunnel junction in the tunneling field active layer. The tunnel junction has a certain junction area and is perpendicular to the gate electrode. Further, by the strong control force of the gate electrode on the entire tunnel junction, the distance of the tunneling channel is shortened, which is beneficial to improving the on-state current of the tunneling field effect transistor.

[0095] In some embodiments of the present application, the first type of doping is N-type heavy doping, and the second type of doping is P-type heavy doping. In some other embodiments of the present application, the first type of doping is P-type heavy doping, and the second type of doping is N-type heavy doping.

[0096] The tunneling field effect transistor of the present application forms a heterojunction tunnel junction in the tunneling field active layer. The heterojunction tunnel junction is beneficial to further shortening the distance between tunneling channels to improve the on-state current of the tunneling field effect transistor. On the other hand, the design method of the present application facilitates the realization of the reconfigurable characteristics of the field tunneling effect transistor, such as realizing P / N type switching by inputting a positive voltage or a negative voltage to the gate electrode. Therefore, the attributes of the transistor can be changed after the transistor is formed, thereby providing higher flexibility and adaptability, and this adaptability is crucial for the development of smaller and more energy-efficient circuits.

[0097] In some embodiments of the present application, a first metal barrier layer is provided between the first active layer and the source electrode, and the orthographic projection of the first metal barrier layer on the substrate is within the orthographic projection range of the first active layer on the substrate;

[0098] A second metal barrier layer is provided between the second active layer and the drain electrode, and the orthographic projection of the second metal barrier layer on the substrate is within the orthographic projection range of the second active layer on the substrate.

[0099] The selected metal barrier layer in the present application is conducive to ensuring the flow of electrons between the source electrode and the drain electrode without affecting the on-state current, on the premise of not affecting the control force of the gate electrode on the tunnel junction; at the same time, it can also reduce the unnecessary etching probability of the tunneling field active layer when forming the tunneling field effect transistor, and increase the forming stability of the device.

[0100] In some embodiments of the present application, along the second direction, the width of the first overlapping part is equal to the width of the second overlapping part.

[0101] The gate electrode of the tunneling field effect transistor provided by the present application can be used to stably and powerfully control the tunnel junction.

[0102] In some embodiments of the present application, the tunneling field effect transistor further includes an isolation layer, the isolation layer is disposed to cover the tunneling field active layer, and a first trench and a second trench are provided on the isolation layer, the source electrode penetrates through the first trench to connect to the first active layer; the drain electrode penetrates through the second trench to connect to the second active layer.

[0103] In some embodiments of the present application, the tunneling field effect transistor further includes a gate insulating layer, wherein the gate insulating layer is disposed to cover the gate electrode. In some other embodiments of the present application, it is also disclosed that the gate insulating layer is disposed on the side of the gate electrode facing the substrate.

[0104] In some embodiments of the present application, the tunneling field effect transistor further includes a buffer layer, and the buffer layer is located between the substrate and the tunneling field active layer.

[0105] In some embodiments of the present application, along the second direction, the distance L between the first active layer and the second active layer is 1 μm to 10 μm. In these embodiments of the present application, it is disclosed that the distance between the first active layer and the second active layer includes any one of 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or satisfies any one of the above range values. At the same time, the distance L between the first active layer and the second active layer can be specifically illustrated in the following drawings.

[0106] To more specifically illustrate the structure of the tunneling field effect transistor, the following will be elaborated in detail with specific drawings.

[0107] As Figure 2AAs shown, the present application provides a specific structure of a tunneling field effect transistor. The tunneling field effect transistor 10000 includes a substrate 1000, a buffer layer 1100, a tunneling field active layer, an isolation layer 1600, a source electrode 1710, a drain electrode 1720, a gate insulating layer 1800, and a gate electrode 1900 stacked in a first direction. The first direction is Figure 2A the z-axis direction of the coordinate axis shown, and is also the thickness direction or the stacking direction of each layer. Among them, the buffer layer 1100 is disposed on the substrate 1000, and the tunneling field active layer is disposed on the side of the buffer layer 1100 away from the substrate 1000. The tunneling field active layer includes a first active layer 1300 and a second active layer 1400 spaced apart in a second direction; the first direction is Figure 2A the x-axis direction of the coordinate axis shown, and is also the length direction or the width direction of each layer. A channel region 1200 is provided between the first active layer 1300 and the second active layer 1400. The first active layer 1300 has a first type of doping, and the second active layer 1400 has a second type of doping. The doping types of the first type of doping and the second type of doping are different. The doping type of the channel region 1200 may be the same as any one of the first type of doping and the second type of doping, but the doping concentration of the channel region is much lower than the doping concentrations of the first type of doping and the second type of doping. At the same time, the channel region 1200 may also be an intrinsic semiconductor without doping treatment. Therefore, the first active layer 1300, the second active layer 1400, and the channel region 1200 form a p-i-n tunnel junction under the strong control of the gate electrode 1900. The p-i-n tunnel junction has a certain junction area and is perpendicular to the gate electrode. Combining Figure 2AIt is also known that the isolation layer 1600 is disposed on the side of the buffer layer 1100 away from the substrate 1000 and covers the tunneling field active layer. A first trench and a second trench are provided on the isolation layer 1600. The source electrode 1710 penetrates through the first trench to connect to the first active layer 1300, and the drain electrode 1720 penetrates through the second trench to connect to the second active layer 1400. The source electrode 1710 and the drain electrode 1720 are both located on the side of the isolation layer 1600 away from the substrate 1000 and are spaced apart along the second direction. The top surfaces of the source electrode 1710 and the drain electrode 1720 are flush. On the side of the source electrode 1710 and the drain electrode 1720 away from the substrate 1000, a gate insulating layer 1800 and a gate electrode 1900 are sequentially provided. The gate insulating layer 1800 is disposed on the side of the gate electrode 1900 facing the substrate 1000, that is, the gate insulating layer 1800 is located between the gate electrode 1900 and the source electrode 1710 and the drain electrode 1720. The orthographic projection of the gate electrode 1900 on the substrate 1000 and the orthographic projection of the first active layer 1300 on the substrate 1000 have a first partial overlap; the orthographic projection of the gate electrode 1900 on the substrate 1000 and the orthographic projection of the second active layer 1400 on the substrate 1000 have a second partial overlap. This way of partial overlap setting is beneficial to achieving a stronger control force of the gate electrode on the entire tunnel junction to shorten the distance of the tunneling channel, and further improving the on-state current of the tunneling field effect transistor. As Figure 2A It is also shown that along the second direction, the width L of the first partial overlap 11 is equal to the width L of the second partial overlap 12 The present application selects the same overlap width along the second direction, which is convenient for fabrication and formation of a symmetric device, and is also beneficial for the gate electrode of the tunneling field effect transistor to stably and strongly control the tunnel junction.

[0108] As Figure 2B shown, based on the specific structure of the tunneling field effect transistor provided by the present application, a first metal barrier layer 1510 is provided between the first active layer 1300 and the source electrode 1710. The orthographic projection of the first metal barrier layer 1510 on the substrate 1000 is within the orthographic projection range of the first active layer 1300 on the substrate 1000; the present application also shows in Figure 2A that a second metal barrier layer 1520 is provided between the second active layer 1400 and the drain electrode 1720. The orthographic projection of the second metal barrier layer 1520 on the substrate 1000 is within the orthographic projection range of the second active layer 1400 on the substrate 1000. Although Figure 2B it is shown in the present application that a second metal barrier layer 1520 is provided between the second active layer 1400 and the drain electrode 1720. The orthographic projection of the second metal barrier layer 1520 on the substrate 1000 is within the orthographic projection range of the second active layer 1400 on the substrate 1000. Although Figure 2BIt is shown that a metal blocking layer is provided between the first active layer 1300 and the source electrode 1710 and between the second active layer 1400 and the drain electrode 1720 at the same time. However, the design method of providing a metal blocking layer for any one of them is also within the protection scope of this application. The metal blocking layer selected in this application is conducive to ensuring the flow of electrons between the source electrode and the drain electrode without affecting the control force of the gate electrode on the tunnel junction and without affecting the on-state current, on the premise of not affecting the control force of the gate electrode on the tunnel junction; at the same time, it can also reduce the unnecessary etching probability of the tunneling field active layer when forming the tunneling field effect transistor and increase the forming stability of the device.

[0109] As Figure 3A shown, this application provides a specific structure of another tunneling field effect transistor. The tunneling field effect transistor 10000 includes a substrate 1000, a buffer layer 1100, a tunneling field active layer, an isolation layer 1600, a source electrode 1710, a drain electrode 1720, a gate insulating layer 1800, and a gate electrode 1900 stacked along a first direction. As described above, the first direction is Figure 3A the z-axis direction of the coordinate axis shown, and is also the thickness direction or the stacking direction of each layer. Among them, the buffer layer 1100 is provided on the substrate 1000, and the tunneling field active layer is provided on the side of the buffer layer 1100 facing away from the substrate 1000. The tunneling field active layer includes a first active layer 1300 and a second active layer 1400 arranged at intervals along a second direction; the first direction is Figure 3A the x-axis direction of the coordinate axis shown, and is also the length direction or the width direction of each layer. A channel region 1200 is provided between the first active layer 1300 and the second active layer 1400. The first active layer 1300 has a first type of doping, and the second active layer 1400 has a second type of doping. The doping types of the first type of doping and the second type of doping are different. The doping type of the channel region 1200 can be the same as any one of the first type of doping and the second type of doping, but the doping concentration of the channel region is much lower than the doping concentrations of the first type of doping and the second type of doping. At the same time, the channel region 1200 can also select an intrinsic semiconductor without doping treatment. Therefore, the first active layer 1300, the second active layer 1400, and the channel region 1200 form a p-i-n tunnel junction under the strong control of the gate electrode 1900. The p-i-n tunnel junction has a certain junction area and is perpendicular to the gate electrode. Combined with Figure 3AIt is also known that the isolation layer 1600 is disposed on the side of the buffer layer 1100 facing away from the substrate 1000 and covers the tunneling field active layer. A gate electrode 1900 is provided on the side of the isolation layer 1600 facing away from the substrate 1000. The orthographic projection of the gate electrode 1900 on the substrate 1000 and the orthographic projection of the first active layer 1300 on the substrate 1000 have a first partial overlap; the orthographic projection of the gate electrode 1900 on the substrate 1000 and the orthographic projection of the second active layer 1400 on the substrate 1000 have a second partial overlap. This partial overlap setting is conducive to achieving a stronger control force of the gate electrode on the entire tunnel junction to shorten the distance of the tunneling channel, and further improve the on-state current of the tunneling field effect transistor. As Figure 3A It is also shown that along the second direction, the width L of the first partial overlap 21 is equal to the width L of the second partial overlap 22 This application selects the same overlap width along the second direction, which is convenient for preparation and formation of a symmetric device, and is also conducive to the stable and powerful control of the gate electrode of the tunneling field effect transistor on the tunnel junction. Combining Figure 3A It is also known that the tunneling field effect transistor further includes a gate insulating layer 1800, a source electrode 1710, and a drain electrode 1720. The gate insulating layer 1800 is disposed to cover the gate electrode 1900; along the first direction, a first trench and a second trench are provided on the gate insulating layer 1800 and the isolation layer 1600. The source electrode 1710 penetrates the first trench to connect to the first active layer 1300, and the drain electrode 1720 penetrates the second trench to connect to the second active layer 1400. The source electrode 1710 and the drain electrode 1720 are both located on the side of the gate insulating layer 1800 facing away from the substrate 1000, and are spaced apart along the second direction. The top surfaces of the source electrode 1710 and the drain electrode 1720 are flush with each other.

[0110] As Figure 3B shown, based on the specific structure of the tunneling field effect transistor provided by this application, a first metal barrier layer 1510 is provided between the first active layer 1300 and the source electrode 1710. The orthographic projection of the first metal barrier layer 1510 on the substrate 1000 is within the orthographic projection range of the first active layer 1300 on the substrate 1000; this application also shows in Figure 3A that a second metal barrier layer 1520 is provided between the second active layer 1400 and the drain electrode 1720. The orthographic projection of the second metal barrier layer 1520 on the substrate 1000 is within the orthographic projection range of the second active layer 1400 on the substrate 1000. Although Figure 3B it is shown in Figure 3BIt is shown that a metal barrier layer is provided between the first active layer 1300 and the source electrode 1710, and between the second active layer 1400 and the drain electrode 1720. However, the design method of providing a metal barrier layer for any one of them is also within the protection scope of this application. The selected metal barrier layer in this application is conducive to ensuring the flow of electrons between the source electrode and the drain electrode without affecting the control force of the gate electrode on the tunnel junction and without affecting the on-state current, on the premise of not affecting the control force of the gate electrode on the tunnel junction; at the same time, it can also reduce the unnecessary etching probability on the tunneling field active layer when forming the tunneling field effect transistor, and increase the forming stability of the device.

[0111] As Figure 4A shown, this application provides a specific structure of another tunneling field effect transistor. The tunneling field effect transistor 10000 includes a substrate 1000, a buffer layer 1100, a tunneling field active layer, an isolation layer 1600, a source electrode 1710, a drain electrode 1720, a gate insulating layer 1800, and a gate electrode 1900 stacked along a first direction. The first direction is Figure 2A the z-axis direction shown, and is also the thickness direction or the stacking direction of each layer. Among them, the buffer layer 1100 is provided on the substrate 1000, and the tunneling field active layer is provided on the side of the buffer layer 1100 facing away from the substrate 1000. The tunneling field active layer includes a first active layer 1300 and a second active layer 1400 arranged at intervals along a second direction; the first direction is Figure 4A the x-axis direction shown, and is also the length direction or the width direction of each layer. A channel region 1200 is provided between the first active layer 1300 and the second active layer 1400. The first active layer 1300 has a first type of doping, and the second active layer 1400 has a second type of doping. The doping types of the first type of doping and the second type of doping are different. The doping type of the channel region 1200 can be the same as any one of the first type of doping and the second type of doping, but the doping concentration of the channel region is much lower than the doping concentrations of the first type of doping and the second type of doping. At the same time, the channel region 1200 can also select an intrinsic semiconductor without doping treatment. Therefore, the first active layer 1300, the second active layer 1400, and the channel region 1200 form a p-i-n tunnel junction under the strong control of the gate electrode 1900. The p-i-n tunnel junction has a certain junction area and is perpendicular to the gate electrode. Combining Figure 4AIt can also be known that the isolation layer 1600 is arranged on the side of the buffer layer 1100 away from the substrate 1000 and covers the tunneling field active layer, and a first groove and a second groove are arranged on the isolation layer 1600. The source 1710 penetrates the first groove to connect to the first active layer 1300, and the drain 1720 penetrates the second groove to connect to the second active layer 1400. The source 1710 and the drain 1720 are simultaneously located on the side of the isolation layer 1600 away from the substrate 1000, and are spaced apart along the second direction, and the top surfaces of the source 1710 and the drain 1720 are arranged flush. The gate electrode 1900 is arranged on the side of the isolation layer 1600 away from the substrate 1000, and the gate electrode 1900 is located between the source 1710 and the drain 1720, and the gate electrode 1900 is arranged flush with the top surfaces of the source 1710 and the drain 1720. In addition, the orthographic projection of the gate electrode 1900 on the substrate 1000 overlaps with the orthographic projection of the first active layer 1300 on the substrate 1000 in a first part; the orthographic projection of the gate electrode 1900 on the substrate 1000 overlaps with the orthographic projection of the second active layer 1400 on the substrate 1000 in a second part. This partially overlapping arrangement is conducive to achieving a strong control of the gate electrode over the entire tunnel junction to shorten the distance of the tunneling channel and further increase the on-state current of the tunneling field effect transistor. Figure 2A It can also be seen from the diagram that along the second direction, the width L of the first part overlaps 31 The width L of the overlap with the second part 32 The present application selects the same overlapping width along the second direction, which is convenient for manufacturing and forming symmetrical devices, and is also conducive to the stable and powerful control of the tunnel junction by the gate electrode of the tunnel field effect transistor.

[0112] like Figure 4B In other words, the tunneling field effect transistor provided by the present application is Figure 4A Based on the specific structure, a first metal barrier layer 1510 is provided between the first active layer 1300 and the source electrode 1710, and the orthographic projection of the first metal barrier layer 1510 on the substrate 1000 is located within the orthographic projection range of the first active layer 1300 on the substrate 1000; Figure 4B It is also shown that a second metal barrier layer 1520 is disposed between the second active layer 1400 and the drain electrode 1720, and the orthographic projection of the second metal barrier layer 1520 on the substrate 1000 is located within the orthographic projection range of the second active layer 1400 on the substrate 1000. Figure 4BIt is shown that a metal blocking layer is provided between the first active layer 1300 and the source electrode 1710, and between the second active layer 1400 and the drain electrode 1720 at the same time. However, the design method of providing a metal blocking layer for any one of them is also within the protection scope of this application. The selected metal blocking layer of this application is conducive to ensuring the flow of electrons between the source electrode and the drain electrode without affecting the control force of the gate electrode on the tunnel junction and without affecting the on-state current on the premise of not affecting the control force of the gate electrode on the tunnel junction; at the same time, it can also reduce the unnecessary etching probability on the tunneling field active layer when forming the tunneling field effect transistor, and increase the forming stability of the device.

[0113] As can be seen from the above drawings, in this application Figure 2A , Figure 2B , Figure 3A and Figure 3B , a gate insulating layer is provided between the gate electrode and the source electrode and the drain electrode, that is, the gate electrode and the source electrode and the drain electrode are arranged in different film layers. The tunneling field effect transistor with this structure is easy to manufacture. And Figure 3A and Figure 3B show that the transistor does not need to increase the thickness between the gate electrode and the tunneling field active layer, which is more convenient for the gate electrode to control the channel.

[0114] The Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B shown single tunneling field effect transistor designed in this application forms a strong control force on the entire tunnel junction through the gate electrode to shorten the distance of the tunneling channel, which is conducive to improving the on-state current of the tunneling field effect transistor. On this basis, in order to further increase the on-state current, this application further includes connecting the Figures 2A to 4B shown single tunneling field effect transistors together to form a transistor unit composed of multiple single tunneling field effect transistors. In some embodiments of this application, the transistor unit includes multiple tunneling field effect transistors, and each tunneling field effect transistor is arranged at intervals along the second direction on the same substrate; the transistor unit further includes a common gate electrode, a common source electrode and a common drain electrode, and the common gate electrode, the common source electrode and the common drain electrode are arranged above the substrate along the first direction; the gate electrodes of each tunneling field effect transistor are respectively connected to the common gate electrode; the source electrodes of each tunneling field effect transistor are respectively connected to the common source electrode; the drain electrodes of each tunneling field effect transistor are respectively connected to the common drain electrode. This application discloses in these embodiments that each tunneling field effect transistor is arranged at equal-distance intervals along the second direction on the same substrate. In these embodiments of this application, there are more than two, and this application mainly shows a transistor unit composed of two tunneling field effect transistors in the following drawings, but this application is not limited to two.

[0115] As Figure 5A shown, this application provides Figure 2BTwo tunneling field effect transistors shown schematically form a transistor unit. Combining Figure 5A it can be seen that the two tunneling field effect transistors share the substrate 1000 and the buffer layer 1100, and are spaced apart along the second direction above the substrate 1000. Among them, along the second direction, the distance between the two tunneling field effect transistors, which is reflected in the drawing as the distance between the first drain 1720a and the first source 1710b, can be adjusted according to actual needs. If the transistor unit includes three or more tunneling field effect transistors, to ensure the structural stability of the entire device and facilitate fabrication, in this application, the distance between adjacent tunneling field effect transistors is selected to be equal, that is, the tunneling field effect transistors are arranged equidistantly above the substrate 1000. Figure 5B shows Figure 5A a top view, and further schematically shows the connection relationship between the gate electrodes, source electrodes, and drain electrodes of each tunneling field effect transistor. Combining Figure 5B it can be seen that the first gate electrode 1900a of the first tunneling field effect transistor 10000a and the second gate electrode 1900b of the second tunneling field effect transistor 10000b are each independently connected to the common gate electrode 20000, the first source electrode 1710a of the first tunneling field effect transistor 10000a and the second source electrode 1710b of the second tunneling field effect transistor 10000b are each independently connected to the common source electrode 30000, and the first drain electrode 1720a of the first tunneling field effect transistor 10000a and the second drain electrode 1720b of the second tunneling field effect transistor 10000b are each independently connected to the common drain electrode 40000. The illustrated transistor unit designed in this application is convenient for large-scale fabrication on the premise that each tunneling field effect transistor shares the substrate. On the other hand, connecting each tunneling field effect transistor in parallel is beneficial to further increasing the on-state current.

[0116] In some embodiments of this application, it is disclosed that Figure 2B four tunneling field effect transistors shown schematically are connected in the manner shown Figure 5B to form a transistor unit. The on-state current of the transistor unit satisfying this structure is increased by about two to three times compared to a single transistor.

[0117] As Figure 6A shown schematically, this application provides Figure 3B a transistor unit formed by two tunneling field effect transistors shown schematically. Combining Figure 6AIt can be known that the two tunneling field effect transistors share the substrate 1000 and the buffer layer 1100, and are spaced apart along the second direction above the substrate 1000. Among them, along the second direction, the distance between the two tunneling field effect transistors, which is reflected in the accompanying drawings as the distance between the first drain 1720a and the first source 1710b, can be adjusted according to the actual needs. If the transistor unit includes three or more tunneling field effect transistors, to ensure the structural stability of the entire device and facilitate manufacturing, in this application, the distance between adjacent tunneling field effect transistors is selected to be equal, that is, each tunneling field effect transistor is arranged above the substrate 1000 at equal intervals. Figure 6B gives Figure 6A a top view of, and further shows the connection relationship between the gate electrodes, source electrodes, and drain electrodes of each tunneling field effect transistor. Combining Figure 6B it can be known that the first gate electrode 1900a of the first tunneling field effect transistor 10000a and the second gate electrode 1900b of the second tunneling field effect transistor 10000b are respectively and independently connected to the common gate electrode 20000, the first source electrode 1710a of the first tunneling field effect transistor 10000a and the second source electrode 1710b of the second tunneling field effect transistor 10000b are respectively and independently connected to the common source electrode 30000, and the first drain electrode 1720a of the first tunneling field effect transistor 10000a and the second drain electrode 1720b of the second tunneling field effect transistor 10000b are respectively and independently connected to the common drain electrode 40000. The illustrated transistor unit designed in this application is convenient for large-scale manufacturing on the premise that each tunneling field effect transistor shares the substrate. On the other hand, connecting each tunneling field effect transistor in parallel is beneficial to further increase the on-state current.

[0118] For Figure 4B the single tunneling field effect transistor shown, when the top surfaces of the gate electrode, source electrode, and drain electrode are not flush with each other, a transistor unit can also be formed, which is not directly shown in the accompanying drawings of this application.

[0119] In some embodiments of this application, the length w of the channel region in the third direction in a single tunneling field effect transistor is 4 μm to 10 μm, specifically, it can be any one of 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or any one that satisfies the above range values. Among them, the length w of the channel region in the third direction can be as Figure 5B shown.

[0120] In some embodiments of the present application, the material of the substrate includes, but is not limited to, glass, and the glass substrate contains any conventional materials in the art, such as inorganic material glasses such as silicon dioxide, phosphate, and silicate. The present application selects to fabricate a tunneling field effect transistor on the surface of the glass substrate to develop a glass-based active device. The glass substrate first has the following two main advantages:

[0121] First, the glass substrate does not require N / P well doping, which is beneficial to reducing the influence of random doping fluctuations on the threshold voltage, thereby increasing the stability of the device;

[0122] Second, on the basis of the first aspect, the glass substrate eliminates the mutual influence between it and the channel, which is beneficial to reducing the parasitic capacitance and improving the device response speed.

[0123] In addition, considering the preparation process and cost, the cost of the glass substrate is lower than that of the existing silicon substrate and it is easier to fabricate on a large scale.

[0124] In some embodiments of the present application, the buffer layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (Si 1- x N x ) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer, etc. The formation method of the buffer layer in the present application includes, but is not limited to, deposition, and the deposition methods include, but are not limited to, PVD (physical vapor deposition), CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), inductively coupled plasma chemical vapor deposition (ICP CVD) or any combination thereof.

[0125] The high-K (dielectric constant > 3.9 F / m) materials of the present application include aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide (HfO2), etc. First, the silicon nitride of the present application can sufficiently passivate the tunneling field active layer to ensure its electrical properties. And the high-K (dielectric constant > 3.9 F / m) materials have a smaller equivalent oxide thickness, stronger channel scaling ability and insulation ability, which is beneficial to reducing the probability of gate electrode leakage current. In some embodiments of the present application, Al2O3 / Si 1-x N xStacked layer, and the thickness of the stacked layer is between 10 nm and 100 nm. Compared with the thickness of a conventional gate insulating layer, its thickness is greatly reduced. On the one hand, it is because the stacked layer with this material is convenient to thin, and on the other hand, this relatively thin thickness can also achieve a relatively thick equivalent oxide thickness, reducing the probability of gate electrode leakage current. In addition, the gate insulating layer with this thickness can also effectively achieve a strong control force on the tunnel junction to shorten the distance of the tunneling channel, which is beneficial to increasing the on-state current of the tunneling field effect transistor. In some embodiments of the present application, it is disclosed that Al2O3 / Si is used 1-x N x The thickness of the formed stacked layer can be any one of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or any one that satisfies the above range values. In some embodiments of the present application, it is also disclosed that Al2O3 / Si is used 1-x N x (5 nm / 5 nm) The formed stacked layer is used as the gate insulating layer. The formation method of the gate insulating layer of the present application includes first depositing to form a film layer, and then patterning the film layer. Among them, the patterning process includes any conventional form in the art, such as specific process flows including exposure, development, etching, etc.

[0126] In some embodiments of the present application, it is disclosed that the gate electrode, source electrode, and drain electrode can be formed of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), iron (Ti), molybdenum (Mo), niobium (Nb), or an alloy material of the above metals, such as aluminum alloy (AlNd) or molybdenum niobium alloy (MoNb). It can be a single-layer structure, such as a single-layer metal of Mo or Cu, or a multi-layer composite structure, such as a bilayer structure of MTD / Cu, MoNb / Cu / MTD, MTD / Cu / MTD, Ti / Al / Ti and other three-layer structures.

[0127] The formation methods for the gate electrode, source electrode, and drain electrode include: forming a metal thin film by physical vapor deposition (PVD), spin coating, etc., and then patterning the metal thin film to form the source electrode, drain electrode, and gate electrode. It is also possible to directly form the source electrode, drain electrode, and gate electrode by methods such as screen printing. The present application does not make special limitations.

[0128] In some embodiments of the present application, it is disclosed that the material of the isolation layer includes but is not limited to any one or more of silicon oxide (SiOx), silicon nitride (Si 1-x Nx), silicon oxynitride (SiON), aluminum oxide (Al2O3). The formation method of the isolation layer of the present application includes deposition.

[0129] In some embodiments of the present application, the material of the metal barrier layer can be a metal that is convenient for wet etching, such as, but not limited to, molybdenum (Mo), copper (Cu), etc. The wet etching of the present application includes any conventional method in the art.

[0130] In some embodiments of the present application, the material of the tunneling field active layer includes, but is not limited to, metal oxide semiconductors or Group IV elements. In these embodiments of the present application, the metal oxide semiconductors include any one of zinc oxide (ZnO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium titanium zinc oxide (ITZO), or indium tin oxide (ITO). In other embodiments of the present application, the Group IV elements include silicon, germanium, etc., and the silicon includes polysilicon, wherein the polysilicon includes, but is not limited to, low-temperature polysilicon (LTPS). In some embodiments of the present application, the material of the tunneling field active layer includes low-temperature polysilicon (LTPS).

[0131] In some embodiments of the present application, the first type of doping is N-type heavy doping, the second type of doping is P-type heavy doping, or the first type of doping is P-type heavy doping, and the second type of doping is N-type heavy doping. In these embodiments, the doping ions for N-type heavy doping include at least one of, but not limited to, phosphorus ions or arsenic ions. The doping ions for P-type heavy doping include at least one of, but not limited to, boron ions, gallium ions, or indium ions. The design method of the present application facilitates the realization of the reconfigurable characteristics of the field tunneling effect transistor, such as realizing P / N type switching by inputting a positive voltage or a negative voltage to the gate electrode. Therefore, the attributes of the transistor can be changed after the transistor is formed, thereby providing higher flexibility and adaptability, and this adaptability is crucial for the development of smaller and more energy-efficient circuits.

[0132] The present application Figure 8 gives the existing conventional field effect transistor rectifier switch circuit, Figure 7 and the present application designs a rectifier switch by forming a transistor unit composed of multiple tunneling field effect transistors, Figure 7 where Vg in Figure 8Vg1 and Vg2 in it are tunneling field effect transistors respectively. Vin is an external AC signal input electrode, Vout is a DC signal output electrode, and R is a load resistor. For an N-type tunneling field effect transistor, when a positive voltage is input to its gate electrode, Vin is a positive signal, Vout outputs normally, and the alternating current is converted into direct current. When the input of the positive voltage to the gate electrode stops, the tunneling stops and the Vout signal decreases to zero. For a P-type tunneling field effect transistor, when a negative voltage is input to its gate electrode, Vin is a positive signal, Vout outputs normally, and the alternating current is converted into direct current. When the input of the negative voltage to the gate electrode stops, the tunneling stops and the Vout signal decreases to zero. Combining with the present application Figure 7 it can be known that a positive voltage or a reverse voltage can be input to the gate electrode to achieve P / N type switching. Therefore, the present application obtains a reconfigurable tunneling field effect transistor. Using this transistor as a rectifying switch in a circuit, compared with the existing conventional field effect transistor rectifying switch, the transistor designed in the present application can improve the on-state current while reducing the number of transistors used in the circuit. Therefore, it has obvious advantages in circuit control.

[0133] The above focuses on a single tunneling field effect transistor and a transistor unit formed by parallel connection of multiple tunneling field effect transistors. The following will further explain in combination with the preparation method.

[0134] The present application provides a preparation method for a single tunneling field effect transistor. As Figure 9 shown, this preparation method includes the following preparation processes:

[0135] S100. Provide a substrate;

[0136] S200. Deposit and form a tunneling field active layer on one side surface of the substrate;

[0137] S300. Perform ion implantation on both sides of the tunneling field active layer in the first direction to form a first active layer with a first type of doping and a second active layer with a second type of doping, wherein the first type of doping is different from the second type of doping; the first active layer and the second active layer are arranged at intervals in the second direction, and a channel region is formed between the first active layer and the second active layer;

[0138] S400. Deposit and form an isolation layer on the side surface of the tunneling field active layer facing away from the substrate;

[0139] S500. Etch the isolation layer to form a first trench and a second trench;

[0140] S600. On the side of the isolation layer facing away from the substrate, a source electrode, a drain electrode, and a gate electrode are deposited and formed. The source electrode penetrates through the isolation layer to connect to the first active layer, and the drain electrode penetrates through the isolation layer to connect to the second active layer; the positive projection of the gate electrode on the substrate overlaps with the positive projection of the first active layer on the substrate by a first part; the positive projection of the gate electrode on the substrate overlaps with the positive projection of the second active layer on the substrate by a second part.

[0141] In some embodiments of the present application, it is also disclosed that before depositing and forming the isolation layer on the side of the tunneling field active layer facing away from the substrate, a first metal barrier layer is deposited and formed on the side of the first active layer facing away from the substrate, and a second metal barrier layer is deposited and formed on the side of the first active layer facing away from the substrate. Among them, the positive projection of the first metal barrier layer on the substrate is located within the positive projection of the first active layer on the substrate, and the positive projection of the second metal barrier layer on the substrate is located within the positive projection of the second active layer on the substrate. In these embodiments of the present application, it is also disclosed that the first trench etching stops at the surface of the first metal barrier layer, and the second trench etching stops at the surface of the second metal barrier layer.

[0142] In some embodiments of the present application, it is also disclosed that a gate insulating layer is deposited and formed on the side of the isolation layer facing away from the substrate, and the gate insulating layer is disposed on the side of the gate electrode facing the substrate.

[0143] In some embodiments of the present application, it is also disclosed that a gate insulating layer is deposited and formed on the side of the isolation layer facing away from the substrate, wherein the gate insulating layer is disposed to cover the gate electrode.

[0144] In some embodiments of the present application, it is disclosed that Figure 2A The preparation method of the schematic tunneling field effect transistor, and the specific formation flow chart is as Figures 10 to 22 Schematic.

[0145] As Figure 10 Schematic, a substrate is provided. As described above, the material of the substrate includes using a glass substrate. The present application selects the glass substrate because of the tunneling principle of the TFET, so that the TFET has no such strict restrictions on the doping type of the substrate as the traditional MOSFET. The advantages of the present application in selecting the glass substrate are as described above.

[0146] As Figure 11 Schematic, a buffer layer is deposited and formed on one side surface of the glass substrate;

[0147] As Figure 12 Schematic, a tunneling field active layer is deposited and formed on the side surface of the buffer layer facing away from the glass substrate;

[0148] As Figure 13 Schematic, the tunneling field active layer is patterned and etched to form a patterned tunneling field active layer;

[0149] AsFigure 14 As shown, along the second direction, processes such as ion implantation and annealing are respectively performed on both sides of the patterned tunneling field active layer to form a first active layer with a first type of doping and a second active layer with a second type of doping, where the doping types of the first type of doping and the second type of doping are different, and the specific doping types are as described above. And a channel region is formed between the first active layer and the second active layer.

[0150] As Figure 15 As shown, a first metal barrier layer is deposited and formed on the surface of the first active layer facing away from the substrate, and a second metal barrier layer is deposited and formed on the surface of the first active layer facing away from the substrate, where the orthographic projection of the first metal barrier layer on the substrate is within the orthographic projection range of the first active layer on the substrate, and the orthographic projection of the second metal barrier layer on the substrate is within the orthographic projection range of the second active layer on the substrate.

[0151] As Figure 16 As shown, along the first direction, an isolation layer is deposited and formed above the tunneling field active layer, and the isolation layer covers the first metal barrier layer, the second metal barrier layer, and the tunneling field active layer.

[0152] As Figure 17 As shown, the isolation layer is patterned and etched so that along the second direction, the heights of both sides of the isolation layer are lower than the height of the middle part. At the same time, a first trench and a second trench are etched in the middle part of the isolation layer, and the first trench is etched until the first metal barrier layer, and the second trench is etched until the second metal barrier layer.

[0153] As Figure 18 As shown, metal is continuously deposited on the surface of the isolation layer facing away from the substrate.

[0154] As Figure 19 As shown, the metal is patterned to form a source electrode and a drain electrode, where the source electrode penetrates the first trench to connect to the first active layer, and the drain electrode penetrates the second trench to connect to the second active layer.

[0155] As Figure 20 As shown, metal is deposited above the source electrode and the drain electrode to form a gate insulating layer.

[0156] As Figure 21 As shown, the gate insulating layer is patterned to form a patterned gate insulating layer.

[0157] As Figure 22 As shown, metal is continuously deposited on the surface of the patterned gate insulating layer facing away from the substrate, and the metal is patterned to form a gate electrode.

[0158] Experimental Example 1

[0159] This application provides a Figure 2BSchematic N-type tunneling field-effect transistor, wherein the width L of the first overlapping part 11 is equal to the width L of the second overlapping part 12 both being 1 μm. The material of the tunneling field active layer is polysilicon, and the gate insulating layer is a stack formed by Al2O3 / Si 1-x N x with each layer having a thickness of 5 nm.

[0160] Along the second direction, the distance between the first active layer and the second active layer is L = 4 μm, and the length w of the channel region along the third direction is 4 μm.

[0161] The transfer characteristic curve of this single N-type tunneling field-effect transistor is as Figure 23 schematic, and its SS is calculated to be 37.5 mV / dec.

[0162] Experimental Example 2

[0163] The difference from Experimental Example 1 is that it is a P-type tunneling field-effect transistor. The transfer characteristic curve of this single N-type tunneling field-effect transistor is as Figure 24 schematic, and its SS is calculated to be 20 mV / dec.

[0164] Thus, it can be seen that the transistor provided in this application is beneficial to improving the gate control efficiency and reaching the on state faster. At the same time, it can also achieve the technical effect of reducing power consumption.

[0165] Based on the proposed reconfigurable tunneling transistor and its low-power consumption characteristics, it is expected to be used in the signal processing unit of a photonic chip to achieve the function of free switching on a single transistor device. Therefore, it can reduce the effective line width of the device, streamline the circuit structure, reduce the circuit power consumption, and improve the integration of the system. Therefore, the tunneling field-effect transistor provided in this application has relatively good application prospects in optical communication devices.

[0166] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" as used herein may also include the plural. The terms "comprising", "including", "containing" and "having" are inclusive and thus specify the presence of stated features, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an execution order is explicitly stated. It should also be understood that additional or alternative steps may be used. As described above, these are only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A tunneling field effect transistor, characterized in that, Comprising: A substrate, a gate electrode, a tunneling field active layer, a source electrode, and a drain electrode stacked in a first direction; The tunneling field active layer includes a first active layer and a second active layer spaced apart in a second direction; A channel region is provided between the first active layer and the second active layer; the second direction is different from the first direction; The first active layer has a first type of doping, the second active layer has a second type of doping, and the first type of doping is different from the second type of doping; The first active layer is connected to the source electrode, and the second active layer is connected to the drain electrode; The positive projection of the gate electrode on the substrate has a first partial overlap with the positive projection of the first active layer on the substrate; The positive projection of the gate electrode on the substrate has a second partial overlap with the positive projection of the second active layer on the substrate.

2. The tunneling field effect transistor according to claim 1, wherein The first type of doping is N-type heavy doping, and the second type of doping is P-type heavy doping; Or, the first type of doping is P-type heavy doping, and the second type of doping is N-type heavy doping.

3. The tunneling field effect transistor according to claim 1, wherein A first metal barrier layer is provided between the first active layer and the source electrode, and the positive projection of the first metal barrier layer on the substrate is located within the positive projection of the first active layer on the substrate; A second metal barrier layer is provided between the second active layer and the drain electrode, and the positive projection of the second metal barrier layer on the substrate is located within the positive projection of the second active layer on the substrate.

4. The tunneling field effect transistor according to any one of claims 1 to 3, characterized in that, It further includes an isolation layer, and the isolation layer is provided to cover the tunneling field active layer; A first trench and a second trench are provided on the isolation layer, and the source electrode penetrates through the first trench to connect to the first active layer; the drain electrode penetrates through the second trench to connect to the second active layer.

5. The tunneling field effect transistor according to claim 4, characterized in that, It further includes a gate insulating layer, wherein the gate insulating layer is provided to cover the gate electrode; Or, the gate insulating layer is provided on the side of the gate electrode facing the substrate.

6. The tunneling field effect transistor according to claim 1 or 2 or 3 or 5, characterized in that, It includes a plurality of tunneling field effect transistors, and each of the tunneling field effect transistors is spaced apart and distributed in the second direction on the same substrate; It further includes a common gate, a common source, and a common drain, and the common gate, the common source, and the common drain are provided above the substrate in the first direction; The gate electrodes of each of the tunneling field effect transistors are respectively connected to the common gate; The source electrodes of each of the tunneling field effect transistors are respectively connected to the common source; The drain electrodes of each of the tunneling field effect transistors are respectively connected to the common drain.

7. The tunneling field effect transistor according to claim 1 or 2 or 3 or 5, characterized in that, The first direction is perpendicular to the second direction.

8. The tunneling field effect transistor according to claim 1 or 2 or 3 or 5, characterized in that, The material of the gate insulating layer includes a stack formed by any one or more of silicon oxide, silicon nitride, silicon oxynitride, and other high-K materials; the thickness of the gate insulating layer is 10 nm to 100 nm.

9. The tunneling field effect transistor according to claim 1 or 2 or 3 or 5, characterized in that, The substrate is a glass substrate.

10. The tunneling field effect transistor according to claim 1 or 2 or 3 or 5, characterized in that, The material of the tunneling field active layer includes metal oxide semiconductor or group IV elements.

11. The tunneling field effect transistor according to claim 10, wherein The metal oxide semiconductor includes any one of zinc oxide, indium oxide, titanium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium titanium zinc oxide, or indium tin oxide; The group IV elements include one or two of silicon and germanium.

12. A photon chip, characterized in that: The tunneling field effect transistor described in any one of claims 1 to 11 is used as a rectifying switch.

13. An optical communication device, characterized in that: The photon chip described in claim 12 is included.

14. A preparation method of a tunneling field effect transistor, characterized in that, The following preparation process is included: A substrate is provided; A tunneling field active layer is deposited and formed on one side surface of the substrate; Ion implantation is respectively performed on both sides of the tunneling field active layer in a first direction to form a first active layer with a first type of doping and a second active layer with a second type of doping, wherein the first type of doping is different from the second type of doping; the first active layer and the second active layer are arranged at intervals in a second direction, and a channel region is formed between the first active layer and the second active layer; An isolation layer is deposited and formed on the side surface of the tunneling field active layer facing away from the substrate; A first trench and a second trench are etched in the isolation layer; A source electrode, a drain electrode and a gate electrode are deposited and formed on the side surface of the isolation layer facing away from the substrate, the source electrode penetrates through the isolation layer to connect to the first active layer, and the drain electrode penetrates through the isolation layer to connect to the second active layer; the positive projection of the gate electrode on the substrate partially overlaps with the positive projection of the first active layer on the substrate; the positive projection of the gate electrode on the substrate partially overlaps with the positive projection of the second active layer on the substrate.

15. The preparation method according to claim 14, wherein, The preparation method further includes: before depositing and forming the isolation layer on the side surface of the tunneling field active layer facing away from the substrate, a first metal barrier layer is deposited and formed on the side surface of the first active layer facing away from the substrate, and a second metal barrier layer is deposited and formed on the side surface of the first active layer facing away from the substrate, wherein the positive projection of the first metal barrier layer on the substrate is within the positive projection range of the first active layer on the substrate, and the positive projection of the second metal barrier layer on the substrate is within the positive projection range of the second active layer on the substrate.

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