Tensor processing system based on reconfigurable computing, working method thereof, and FPGA development board

Abstract

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

Description

Technical Field

[0001] The present invention belongs to the field of computer processing technology, and in particular relates to a tensor processing system based on reconfigurable computing, a working method thereof, and an FPGA development board. Background Art

[0002] With the rapid development of artificial intelligence, high-performance computing, and edge computing technologies, tensors, as the core representation of multidimensional data, have become the core computing unit in fields such as deep learning, scientific computing, and image processing. The design goal of the tensor processing architecture is to improve computing power density and energy efficiency through efficient parallel computing and storage optimization.

[0003] Traditional general-purpose architectures, such as CPUs and GPUs, have limited computing energy efficiency and struggle to meet computational demands. Dedicated tensor processors (such as TPUs and NPUs) overcome the computing power limitations of general-purpose architectures, achieving highly energy-efficient computing through fixed-function units (such as systolic arrays and matrix multipliers). However, the rigid nature of algorithms in these architectures makes them applicable only to specific model structures and unable to adapt to the iterations of emerging algorithms (such as dynamic sparsification and mixed-precision computing). Heterogeneous computing architectures (such as CPU+GPU / FPGA / DSA) enhance flexibility by combining different computing units. For example, FPGAs leverage programmable logic resources to achieve partial dynamic reconfiguration, but their high development threshold and long compilation cycles make them difficult to meet real-time requirements. Meanwhile, reconfigurable computing technologies (such as CGRA and dynamic dataflow architectures) achieve a balance between energy efficiency and flexibility through dynamic configuration of hardware resources, becoming a research hotspot for the next generation of tensor processors.

[0004] Reconfigurable computing, a technological paradigm situated between general-purpose processors (such as CPUs / GPUs) and application-specific integrated circuits (ASICs), offers unique advantages in the field of high-performance computing. It achieves a flexible mapping of algorithms and computing engines through dynamic hardware resource reconfiguration, demonstrating unique advantages in high-performance computing. Reconfigurable computing enables spatial mapping of algorithms to computing engines and maintains customizable computing organization even after being fabricated into integrated circuits. A key characteristic of reconfigurable computing systems is the separation of algorithm control flow and data flow. Reconfigurable datapaths (RCDs) manage data flow, while reconfigurable control paths (RCCs) execute control flow and reconfigure the reconfigurable datapaths. Reconfigurable datapaths typically utilize arrays of basic data processing units. Compared to traditional von Neumann architectures, reconfigurable computing addresses the issues of a low proportion of computational instructions and the time-consuming analysis of information such as function and data access. Furthermore, compared to application-specific integrated circuits, reconfigurable computing offers the advantages of greater scalability and flexibility.

[0005] In recent years, reconfigurable architectures have achieved breakthroughs in deep learning acceleration. Reconfigurable arrays enable operator-level reconfiguration through microcode to address the diverse nature of tensor computations (such as Winograd convolution and sparse matrix multiplication). For example, FPGA accelerators based on the Winograd algorithm can dynamically configure processing modules to support different convolution kernel sizes, increasing inference speed by more than three times compared to fixed architectures.

[0006] However, the existing tensor computing architecture has the following defects:

[0007] (1) The rigidity of computing types and parallel granularity leads to poor reusability. Many dedicated tensor processors rely on fixed functional units, such as Google's systolic array, which only supports 128*128-dimensional matrix calculations. When processing dynamic sparse matrices or mixed-precision calculations, hardware resource utilization drops sharply to below 30%. At the same time, the parallel dimension of the calculation (such as the GPU's Warp scheduling granularity and the PE array size used by many coarse-grained reconfigurable processors) must be determined during the hardware design phase and cannot be dynamically adjusted according to algorithm requirements;

[0008] (2) Traditional reconfigurable computing suffers from low configuration efficiency. When configuring large-scale reconfigurable hardware, the reconfigured configuration needs to cover the entire array, resulting in low configuration efficiency. For example, FPGA configuration takes tens to hundreds of milliseconds and does not support dynamic partial reconfiguration.

[0009] (3) The existing tensor processing architecture has low computational versatility and low resource coordination efficiency. The different hardware components of the existing tensor processing architecture can only perform specialized computing tasks, and the task configuration granularity is large. There is a lack of hardware-level support for irregular computing such as sparse tensors and dynamic graphs, and software preprocessing is required, resulting in low utilization efficiency of computing resources. Summary of the Invention

[0010] In view of the problems existing in the above background technology, the purpose of the present invention is to provide a tensor processing system based on reconfigurable computing, a working method thereof, and an FPGA development board.

[0011] In order to achieve the above object, the present invention adopts the following technical solutions:

[0012] A tensor processing system based on reconfigurable computing, including:

[0013] QSFP interface: multiple QSFP interfaces are provided for loading external microcode and data into the DDR storage module. The microcode includes reconfigurable computing microcode and matrix computing microcode.

[0014] DDR memory module: used to store microcode and data;

[0015] Memory access control module: used to receive memory access requests sent by the on-chip shared memory module and obtain microcode and data from the DDR memory module; at the same time, when the on-chip shared memory module needs to release a certain amount of memory, the memory access control module writes the data to reduce the pressure on the on-chip cache;

[0016] Microcode control module: used to manage matrix computing microcode and reconfigurable computing microcode; by accessing the on-chip shared storage module, read the data corresponding to the microcode address, cache it in the microcode control module, and transmit the microcode and data to a matrix module or directly to the reconfigurable computing interface module according to the microcode type;

[0017] Matrix module: Set up a multi-way matrix module to calculate the type of microcode according to the loaded microcode and data, independently complete the analysis of matrix instructions in parallel, compress and decompress the sparse matrix, and generate the calculation type provided by the reconfigurable calculation interface module. It continuously initiates calculation requests to the reconfigurable calculation interface module, disassembles the matrix calculation task into the reconfigurable calculation microcode and integrates the data; after the calculation is completed, it sends a calculation completion signal to the microcode control module and applies to the on-chip shared storage module for data storage;

[0018] On-chip shared memory module: shared by the CPU, microcode control module and result return network, used to send memory access requests to the memory access control module and cache the loaded data;

[0019] Control network: used to convert the extended instructions issued by the CPU into microcode, and perform storage conflict detection on the microcode. After the detection is completed, the result address is generated and further microcode information and routing information / control signals are generated. The generated microcode information and routing information / control signals are transmitted to the microcode control module through the microcode send Fifo. After the microcode is executed, the error information is saved and the CPU is interrupted.

[0020] RISC-V processor: a CPU based on the RISC-V architecture, used to control the overall calculation under the CPU control method, and transmit the generated microcode to the microcode control module through the control network;

[0021] Reconfigurable computing interface module: used for the parallel entry of multiple computing requests, generates a dedicated address for reconfigurable computing, generates a response to the outside world after the address is generated, and starts receiving data. When the received data is ready, it submits the microcode to the reconfigurable configuration module;

[0022] Reconfigurable computing module: Contains four sub-arrays, and can simultaneously compute multiple microcodes through partial reconfiguration. It sends a computation completion signal to the result return network and submits the computation results to the result return network.

[0023] Reconfigurable configuration module: used for operator configuration and controls the entire computational process of the operator subarray;

[0024] Result return network: used to store the results of the calculation completed by the reconfigurable configuration module. If it is a reconfigurable calculation microcode issued by the matrix module, the calculation result will be returned to the corresponding matrix module; if it is a reconfigurable calculation microcode issued by the microcode control module, the calculated data will be stored in the on-chip shared storage module, and a calculation completion signal will be sent to the microcode control module at the same time.

[0025] Furthermore, the microcode control module includes:

[0026] Microcode request module: used to obtain microcode information from the on-chip shared storage module and send the unexecuted microcode to the microcode cache module;

[0027] Microcode receiving module: used to receive the calculation microcode from the CPU and send it to the microcode cache module;

[0028] Microcode cache module: used to temporarily store microcode that has not yet been executed;

[0029] Microcode memory access channel: used to submit the request for loading data from the microcode cache module to the on-chip shared memory module;

[0030] Data cache module: used to load data from the on-chip shared storage module after the microcode memory access channel issues a request to load microcode corresponding data, and send the reconfigurable computing microcode and data to the reconfigurable computing interface module through the reconfigurable microcode channel;

[0031] Address detection module: used to perform address detection on the matrix calculation microcode and matrix data and then send them to the matrix selection arbitration module;

[0032] Matrix selection arbitration module: used to select the on-chip matrix module according to the storage address range of the matrix calculation microcode, and then send the matrix data to be calculated and the matrix calculation microcode to a certain matrix channel;

[0033] Matrix channel: used to transmit matrix calculation microcode and matrix data to the corresponding matrix module according to the routing.

[0034] Furthermore, after the control network receives the extended instructions for matrix calculation and reconfigurable calculation from the RISC-V processor, it performs a storage conflict detection on the current extended instruction and the previously unfinished microcode; after the detection is completed and it is confirmed that there is no conflict, it checks the storage status in the on-chip shared storage module, allocates the result address for the current extended instruction from the on-chip shared storage module, further generates complete microcode information and routing information / control signals, and enters the microcode send Fifo to prepare for sending to the microcode control module; after the microcode calculation is completed, it returns to the control network, triggering a CPU interrupt, and when a calculation error occurs in the matrix module and the reconfigurable calculation module during the calculation process, the error information is registered in the error register. In addition, the control instructions for the peripherals are also issued through the control network. All inputs are routed inputs, and all outputs are arbitrated outputs.

[0035] Furthermore, the on-chip shared storage module includes:

[0036] Internal read / write control module: used to arbitrate read / write requests from the microcode control module, RISC-V processor, matrix module, result return network, and DDR storage module, distribute them to the read interface module and write interface module, and read or write data;

[0037] Read interface module: used to distribute the read requests submitted by the internal read / write control module to the read / write request queue of a certain bank according to the requested storage address range;

[0038] Write interface module: used to distribute the write requests submitted by the internal read / write control module to the read / write request queue of a certain bank according to the requested storage address range;

[0039] Read and write request queue module: used to cache a certain number of read and write requests. For a single bank, if a read request and a write request arrive at the same time, the write request is processed first. If the incoming requests are both read and write, or all are write requests, they can only be processed sequentially. If the requests arriving at the same bank are two read requests, they enter the bank for reading in parallel.

[0040] Distributed storage Bank0 to Bank11: Set up 12 banks, each bank has a row length of 256 bits and a depth of 32K. The storage size of a single bank is 1MB, and the total storage size of the 12 banks is 12MB.

[0041] Furthermore, the matrix module includes a memory access module, a control module, a compression module, a decompression module, a vector operation module and a matrix operation module. The control module is used to check whether the current microcode belongs to a matrix operation or a vector operation, and whether it is a sparse matrix calculation; if it is a sparse matrix calculation, the decompression module is called to decompress the data, and the reconfigurable computing interface module is called through the matrix operation module to complete the calculation, and the overall result is compressed through the compression module, and the compressed data is written to the on-chip shared storage module through the memory access module; if it is a dense matrix operation and vector operation, the matrix operation module and the vector operation module are entered respectively, and the operation unit organizes the operation form and sends it to the reconfigurable computing interface module for calculation, and writes it to the on-chip shared storage module after the calculation is completed.

[0042] Furthermore, in the reconfigurable computing interface module, after multiple computing requests enter in parallel, each computing request enters the buffer pool after passing through the microcode request arbitration module, and at the same time, a dedicated address for reconfigurable computing is generated in the address generation module; after the address is generated, the corresponding computing task request end is responded to, and data is started to be received and saved in the reconfigurable storage module; after the reconfigurable storage module receives the data, a notification is sent to inform the buffer pool that the microcode is allowed to be submitted to the reconfigurable configuration module.

[0043] Furthermore, the reconfigurable configuration module includes:

[0044] Configuration parsing module: used to parse configuration word information according to microcode;

[0045] Configuration word storage module: used to query detailed computing configuration information based on configuration word information and send computing configuration information unrelated to the array to the current array configuration module; if there is an available array configuration in the current array, it directly enters the array control module; if there is no available array configuration, it enters the array search module.

[0046] Array search module: used to search the array according to the calculated pattern to find available operator subarrays and lock the area of ​​available operator subarrays; after the operator search is completed, the found operator information is sent to the array control module;

[0047] Array control module: used to control the operator subarray to perform single-round or multi-round calculations based on operator information.

[0048] Furthermore, in the reconfigurable computing module, four PE subarrays can be reconfigured, including three floating-point arrays and one integer array. Every four PEs in the PE subarray form a subnet, the PE at the top of the subnet is a super PE, and data is transmitted layer by layer within the PE subnet.

[0049] The working method of the tensor processing system based on reconfigurable computing includes:

[0050] (1)CPU control method:

[0051] When used for single-chip computing, the CPU controls the global computing; it starts by the CPU, requesting instructions and data from the on-chip shared storage module, and the on-chip shared storage module determines whether the request issued by the CPU is hit. If not, the memory access control module issues a memory access request and reads the instructions and data of the corresponding address from the DDR storage module. If it is hit, the instructions and data required by the CPU are directly taken out; the CPU starts to fetch instructions, and when the CPU decodes and parses into ordinary CPU instructions, it executes normally and continues a new round of instruction fetch and memory access. When it parses instructions that need to be executed by the matrix module and the reconfigurable computing module, the microcode is transmitted to the microcode control module through the control network. When the CPU decodes, it has determined that only the matrix computing microcode and the reconfigurable computing microcode are sent to the microcode control module; after receiving the microcode, the microcode control module accesses the on-chip shared storage module, reads the data of the corresponding address of the microcode, and according to the type of microcode Send microcode; if it is a matrix calculation microcode, allocate the corresponding matrix module and transmit it to the matrix module. The matrix module generates reconfigurable calculation microcode inside and sends it to the reconfigurable calculation interface module. If it is not a matrix calculation microcode, it is a reconfigurable calculation microcode, which is directly sent to the reconfigurable calculation interface module; the reconfigurable calculation interface module responds and receives the data to be calculated, configures and calculates it, and then sends the result to the return network to complete the calculation; judge the source of the calculation task. If it is not a calculation task sent by the matrix module, it is directly submitted to the microcode control module, and the microcode control module interrupts the CPU; if it is a reconfigurable calculation microcode provided by the matrix module, it is returned to the corresponding matrix module, and it is judged whether the calculation is completed. If not, the reconfigurable calculation microcode continues to be generated. If completed, an end signal is sent to the microcode control module. The microcode control module interrupts the CPU and applies to the on-chip shared storage module for data storage;

[0052] (2) Cluster computing method:

[0053] A board for carrying a tensor processing system based on reconfigurable computing, the board is connected to the host computer through a QSFP interface. After loading external microcode and data, the microcode control module is started, and the microcode control module controls the overall calculation, and requests microcode and data from the on-chip shared storage module. The on-chip shared storage module determines whether the request sent by the microcode control module is hit. If it is hit, the microcode and data are directly sent to the microcode control module. If it is not hit, a memory access request is sent to the memory access control module to read the microcode and data of the corresponding address from the DDR storage module. The microcode and data in the DDR storage module are read from the low The storage format from address to high address is: ① location segment configuration of microcode and data, ② microcode sequence, ③ data; the microcode control module presets the lowest address to read, finds the microcode and data location, starts reading the data at the address corresponding to the microcode, and sends and executes the microcode; the microcode calculation process is consistent with the CPU control method, and finally the microcode control module determines whether the microcode is fully calculated. If not, the uncalculated microcode and data are obtained and sent to the microcode control module. If the calculation is fully completed, the microcode control module directly sends an end signal to the host computer, interrupts the host computer, and at the same time applies to the on-chip shared storage module for data storage.

[0054] The present invention further provides an FPGA development board for implementing the above-mentioned tensor processing system based on reconfigurable computing, which uses Virtex UltraScale+VU13P as the main logic implementation platform. The FPGA development board is integrated with multiple QSFP28 cage slots, each QSFP28 cage slot supports up to 4 channels of high-speed serial data transmission; the FPGA development board is equipped with four DIMM slots as DDR storage modules, each DIMM is connected to the core logic of the FPGA via a 72-bit wide parallel bus; the FPGA development board is equipped with a SlimSAS interface and a Utility Connection interface, and the SlimSAS interface can be extended to connect to external storage devices or high-speed interconnection systems to meet the needs of large-scale data handling and distributed system expansion; the Utility Connection interface allows Gigabit Ethernet (1GbE), PPS (Pulse Per Second) and USB interfaces to achieve system remote control, time synchronization and device communication. The FPGA development board also integrates a BMC (Board Management Controller) management chip, a USB Hub module, a JTAG interface and a FLASH memory.

[0055] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0056] 1. The present invention's reconfigurable computing-based tensor processing system, through dynamic granularity configuration of on-chip microcode, can implement matrix operations, vector operations, special function operations, and customized operation modes. When the underlying reconfigurable operators perform calculations, parallel computing of all scales below 32 dimensions can be achieved. Therefore, the number of operators can be dynamically configured according to actual scale requirements, improving hardware utilization.

[0057] 2. The hardware design of the present invention adopts a dynamic partial reconstruction strategy, which can reconfigure some hardware areas for different tasks. It implements a multi-configuration strategy in the hardware and can quickly find different configurations for different microcodes.

[0058] 3. This invention utilizes a unified, large-scale on-chip computing array to achieve high parallel computing capabilities. A multi-path matrix operation module is designed to independently process matrix partitioning and merging of different sizes. A unified, reconfigurable computational microcode is then sent to the computing array via an interface for independent computation. The microcode is designed for fine-grained parallel computing and supports direct read / write access to configuration words, resulting in high versatility and the ability to implement a wide range of computations. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Schematic diagram of the overall architecture of a tensor processing system based on reconfigurable computing provided by an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of the PCB structure of the FPGA development board provided by an embodiment of the present invention;

[0061] Figure 3 This is a flowchart of the CPU control method provided by an embodiment of the present invention;

[0062] Figure 4 This is a workflow diagram of the cluster computing method provided by an embodiment of the present invention;

[0063] Figure 5 1 is a schematic diagram of the microcode control module architecture provided by an embodiment of the present invention;

[0064] Figure 6 is a schematic diagram of a control network architecture provided by an embodiment of the present invention;

[0065] Figure 7 Schematic diagram of an on-chip shared storage module provided by an embodiment of the present invention;

[0066] Figure 8 Schematic diagram of the matrix module architecture provided by an embodiment of the present invention;

[0067] Figure 9 Schematic diagram of the reconfigurable interface module architecture provided by an embodiment of the present invention;

[0068] Figure 10 Schematic diagram of a reconfigurable configuration module architecture provided by an embodiment of the present invention;

[0069] Figure 11 Schematic diagram of a reconfigurable single sub-array architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0071] The tensor processing system based on reconfigurable computing provided by the present invention realizes parallel processing of multiple computing tasks through the idea of ​​dynamic partial reconstruction, designs reconfigurable computing microcode with fine computing granularity, and realizes various types of computing in different dimensions by configuring reconfigurable configuration words.

[0072] 1. Overall system

[0073] The overall architecture of the tensor processing system based on reconfigurable computing is as follows Figure 1 Shown, including:

[0074] QSFP interface: Four QSFP interfaces are provided for loading external microcode and data into the DDR memory module. The microcode is divided into reconfigurable computing microcode and matrix computing microcode.

[0075] DDR memory module: used to store microcode and data;

[0076] Memory access control module: used to receive memory access requests sent by the on-chip shared memory module and obtain microcode and data from the DDR memory module; at the same time, when the on-chip shared memory module needs to release a certain amount of memory, the memory access control module writes the data to reduce the pressure on the on-chip cache;

[0077] Microcode control module: used to manage matrix computing microcode and reconfigurable computing microcode; by accessing the on-chip shared storage module, read the data corresponding to the microcode address, cache it in the microcode control module, and transmit the microcode and data to a matrix module or directly to the reconfigurable computing interface module according to the microcode type;

[0078] Matrix module: Set up a four-way matrix module, according to the type of loaded microcode and data calculation microcode, parallelly and independently complete the parsing of matrix instructions, compression and decompression of sparse matrices, and generate the calculation type provided by the reconfigurable calculation interface module, continuously initiate calculation requests to the reconfigurable calculation interface module, disassemble the matrix calculation task into the reconfigurable calculation microcode and integrate the data; after the calculation is completed, send a calculation completion signal to the microcode control module and apply to the on-chip shared storage module for data storage;

[0079] On-chip shared memory module: shared by the CPU, microcode control module and result return network, used to send memory access requests to the memory access control module and cache the loaded data;

[0080] Control network: used to convert the extended instructions issued by the CPU into microcode, and perform storage conflict detection on the microcode. After the detection is completed, the result address is generated and further microcode information and routing information / control signals are generated. The generated microcode information and routing information / control signals are transmitted to the microcode control module through the microcode send Fifo. After the microcode is executed, the error information is saved and the CPU is interrupted.

[0081] RISC-V processor: a CPU based on the RISC-V architecture, used to control the overall calculation under the CPU control method, and transmit the generated microcode to the microcode control module through the control network;

[0082] Reconfigurable computing interface module: used for the parallel entry of multiple computing requests, generates a dedicated address for reconfigurable computing, generates a response to the outside world after the address is generated, and starts receiving data. When the received data is ready, it submits the microcode to the reconfigurable configuration module;

[0083] Reconfigurable computing module: Contains four sub-arrays, and can simultaneously compute multiple microcodes through partial reconfiguration. It sends a computation completion signal to the result return network and submits the computation results to the result return network.

[0084] Reconfigurable configuration module: used for operator configuration and controls the entire computational process of the operator subarray;

[0085] Result return network: used to store the results of the calculation completed by the reconfigurable configuration module. If it is a reconfigurable calculation microcode issued by the matrix module, the calculation result will be returned to the corresponding matrix module; if it is a reconfigurable calculation microcode issued by the microcode control module, the calculated data will be stored in the on-chip shared storage module, and a calculation completion signal will be sent to the microcode control module at the same time.

[0086] A custom FPGA development board is used to implement the above tensor processing system based on reconfigurable computing. The specific board PCB board structure diagram is as follows Figure 2As shown: The center of the PCB features a high-performance programmable logic device—the Virtex UltraScale+ VU13P FPGA (field-programmable gate array), serving as the core processing unit for the entire system. The left side of the PCB features four QSFP28 Cage high-speed optical module slots, each supporting up to four lanes (4x) of high-speed serial data transmission. The right side of the PCB features four 288-pin DIMM slots, which can accommodate DDR4×72 memory with Error-Correcting Code (ECC) for high-capacity data storage up to 128GB. Alternatively, they can be configured as dual-channel QDR (Quad Data Rate)×18 high-speed SRAM, providing up to 576Mb of low-latency, high-speed storage. Each DIMM module connects to the FPGA's core logic via a 72-bit parallel bus. Additionally, two SlimSAS interfaces are reserved on the right side of the PCB, each supporting x8 lanes of high-speed connectivity for connecting to external storage devices or high-speed interconnect systems, meeting the needs of large-scale data transfer and distributed system expansion. The top of the PCB features a utility connection port, allowing for Gigabit Ethernet (1GbE), Pulse Per Second (PPS), and USB interfaces for remote system control, time synchronization, and device communication. Above the FPGA, the BMC (Board Management Controller) chip, USB hub module, JTAG interface, and FLASH memory are integrated.

[0087] 2. Working methods and processes

[0088] The overall architecture operates in two ways: CPU control and cluster computing. The CPU control method uses the CPU to control global calculations and outputs for single-chip computing. The cluster computing method connects the host computer and the system's boards via optical ports. The microcode control module controls the overall calculation and returns the calculated data directly to the host computer, enabling multi-card cluster computing.

[0089] (1)CPU control method:

[0090] Workflow such as Figure 3As shown, the CPU starts to start and requests instructions and data from the on-chip shared storage module. The on-chip shared storage module determines whether the request issued by the CPU is hit. If not, the memory access control module issues a memory access request and reads the instructions and data of the corresponding address from the DDR storage module. If it is hit, the instructions and data required by the CPU are directly taken out; the CPU starts to fetch instructions. When the CPU decodes and parses into ordinary CPU instructions, it executes normally and continues a new round of instruction fetch and memory access. When it parses into instructions that need to be executed by the matrix module and the reconfigurable computing module, the microcode is transmitted to the microcode control module through the control network. When the CPU decodes, it has determined that only the matrix computing microcode and the reconfigurable computing microcode are sent to the microcode control module; after receiving the microcode, the microcode control module accesses the on-chip shared storage module, reads the data of the corresponding address of the microcode, and sends the microcode according to the type of microcode; if it is The matrix calculation microcode is assigned to the corresponding matrix module and transmitted to the matrix module. The matrix module generates reconfigurable calculation microcode internally and sends it to the reconfigurable calculation interface module. If it is not a matrix calculation microcode, it is a reconfigurable calculation microcode, which is directly sent to the reconfigurable calculation interface module; the reconfigurable calculation interface module responds and receives the data to be calculated, configures and calculates it, and then sends the result to the return network to complete the calculation; the source of the calculation task is determined. If it is not a calculation task sent by the matrix module, it is directly submitted to the microcode control module and the microcode control module interrupts the CPU; if it is a reconfigurable calculation microcode provided by the matrix module, it is returned to the corresponding matrix module and it is determined whether the calculation is completed. If not, the reconfigurable calculation microcode continues to be generated. If completed, an end signal is sent to the microcode control module. The microcode control module interrupts the CPU and applies to the on-chip shared storage module for data storage.

[0091] (2) Cluster computing method:

[0092] Workflow such as Figure 4As shown, a board for carrying a tensor processing system based on reconfigurable computing is connected to a host computer via a QSFP interface. After loading external microcode and data, the microcode control module is started, and the microcode control module controls the overall calculation and requests microcode and data from the on-chip shared storage module. The on-chip shared storage module determines whether the request issued by the microcode control module is hit. If it is hit, the microcode and data are directly sent to the microcode control module. If it is not hit, a memory access request is issued to the memory access control module to read the microcode and data of the corresponding address from the DDR storage module. The microcode and data in the DDR storage module are read from the DDR memory module. The storage format from low address to high address is: ① location segment configuration of microcode and data, ② microcode sequence, ③ data; the microcode control module presets the lowest address to read, finds the microcode and data location, starts reading the data at the address corresponding to the microcode, and sends and executes the microcode; the microcode calculation process is consistent with the CPU control method, and finally the microcode control module determines whether the microcode calculation is completed. If not, the uncalculated microcode and data are obtained and sent to the microcode control module. If the calculation is completed, the microcode control module directly sends an end signal to the host computer, interrupts the host computer, and at the same time applies to the on-chip shared storage module for data storage.

[0093] 3. Specific architecture description of each module

[0094] (1) Microcode control module

[0095] Mainly responsible for the acquisition, management and distribution of microcode, architecture such as Figure 5 As shown, it includes a microcode request module, a microcode receiving module, a microcode cache module, a data cache module 1, a data cache module 2, a microcode memory access channel 1, a microcode memory access channel 2, an address detection module 1, an address detection module 2, a matrix selection arbitration module, a matrix channel 1, a matrix channel 2, and a reconfigurable microcode channel.

[0096] In the cluster computing approach, the microcode request module retrieves a batch of microcode information from the on-chip shared memory module and sends any unexecuted microcode to the microcode cache module. The microcode cache module uses microcode access channel 1 and microcode access channel 2 to access the on-chip shared memory module in parallel. After data is loaded from the on-chip shared memory module, if the data being loaded is for reconfigurable computing microcode, it directly enters the reconfigurable microcode channel. For matrix computing tasks, the loaded data undergoes address checking. Data cache module 1 and data cache module 2 are used to load the data of the on-chip shared storage module after the microcode cache module issues a request to load the corresponding microcode data, and send the reconfigurable computing microcode to the reconfigurable computing interface module through the reconfigurable microcode channel, perform address detection on the matrix computing microcode and matrix data through the address detection module 1 and the address detection module 2, and provide the matrix module preferred to be used by the current address. Then, the matrix selection arbitration module selects the on-chip matrix module according to the actual availability of the matrix module, sends the data to be calculated and the matrix computing microcode to the matrix channel 1 or the matrix channel 2, and provides the routing information of the actually selected matrix module, and outputs it to the actual matrix module according to the routing information.

[0097] The microcode control module schedules the matrix using an algorithm based on address and module status, as described below:

[0098] The address space of the on-chip memory is divided into four areas according to the 10th bit of the address, so that the four areas are arranged in the form of {1,2,3,4,1,2,3,4...} in the memory, that is, 4KB is a cycle, and the address space is divided into appropriate granularity;

[0099] For loaded matrix calculations, determine in which address range the microcode data is located, and prioritize the processing of the microcode into the corresponding matrix module;

[0100] The matrix selection arbitration module will determine whether to provide the matrix module with the current matrix priority processing unit and the corresponding microcode calculation in the current matrix module. If the matrix module has the microcode type being calculated, it will access the currently idle matrix module in a polling manner and occupy the resource.

[0101] After selecting a module, the selected matrix module information is sent to the matrix channel, along with routing information for the selected matrix module. The microcode and data are then submitted to the matrix module. When the microcode execution is complete, a control signal enters the microcode control module, removing the microcode. When the microcode request module reads the stop microcode from the on-chip shared memory module, it ceases operation and waits for all subsequent calculations to complete before interrupting the host computer.

[0102] Under the CPU control method, the microcode receiving module obtains the calculation microcode from the CPU and sends it to the microcode cache module. When the CPU does not send the microcode, the module stops working.

[0103] The designed calculation microcode list is shown in Table 1:

[0104] Table 1 Calculation microcode list

[0105]

[0106] (2)RISC-V processor

[0107] A RISC-V processor, a CPU based on the RISC-V architecture, operates exclusively under CPU control and interacts with the outside world through a control network. The RISC-V processor requests processor instructions and data from the on-chip shared memory module, decodes the instructions to identify the extended instructions, and then translates the RISC-V extended instructions corresponding to the computational microcode list shown in Table 1. These instructions are then sent to the control network for further conversion into microcode.

[0108] (3) Control network

[0109] Control network architecture such as Figure 6 As shown, after receiving extended instructions for matrix and reconfigurable computing from the RISC-V processor, the control network performs a memory conflict check between the current extended instruction and the previously incomplete microcode. If a memory conflict exists, it indicates that the current extended instruction is dependent on the previous extended instruction and must wait until the corresponding instruction is executed before issuing it. In cluster computing, the default dependency issue is resolved by the host computer.

[0110] After the storage conflict detection is completed and confirmed to be free of conflict, the storage status in the on-chip shared storage module is checked, and the result address is allocated to the current extended instruction from the on-chip shared storage module. The complete microcode information and routing information are further generated. For the instructions of the peripherals, the control signals and microcode information of the peripherals are generated; then the microcode is sent to the Fifo and prepared to be sent to the microcode control module.

[0111] After the microcode completes the calculation, it returns to the control network, triggering an external interrupt to the RISC-V processor, which then processes the result. If errors occur during the calculation process in the matrix module or reconfigurable computation module, the error information is recorded in an error register. Furthermore, control instructions for peripherals are also issued through the control network. All inputs are routed, and all outputs are arbitrated.

[0112] (4) On-chip shared memory module

[0113] Responsible for loading data from the DDR memory module and caching it on the on-chip shared memory module, which facilitates the on-chip RISC-V processor, microcode control module, and result return network access. The on-chip shared memory module architecture is as follows Figure 7 As shown, the chip includes an internal read / write control module, a read interface module, a write interface module, distributed storage Banks 0-11, and corresponding read / write request queue modules. Each bank has a row length of 256 bits and a depth of 32KB. The storage capacity of a single bank is 1MB, and the total storage capacity of the 12 banks is 12MB. It supports three read interfaces and six write interfaces. The read interface modules include two microcode control module read data interfaces and one CPU read module interface, which distribute read requests submitted by the internal read / write control module to the read / write request queue of a specific bank based on the requested storage address range. The write interface modules include a result return network write, a four-way matrix write, and a CPU write, which distribute write requests submitted by the internal read / write control module to the read / write request queue of a specific bank based on the requested storage address range. When data in the on-chip shared storage module needs to be accessed, the internal read / write control module initiates the request. After arbitration between the read / write requests from the microcode control module, the RISC-V processor, the matrix module, the result return network, and the DDR storage module, the request is distributed to the read interface module and the write interface module, where the data is read or written.

[0114] The DDR memory module loads data into the on-chip shared memory module at a 1024-bit bit width, loading 512KB of data at a time. Due to the temporal and spatial locality of the program, the number of DDR memory module accesses can be reduced. The internal access bit width is 256 bits. Each time an internal access is made, the access request is sent to each bank based on the access address. The read and write request queue module is used to cache read and write requests. Each bank can queue and cache a certain number of read and write requests. For a bank, if a read request and a write request arrive at the same time, the write request is processed first. When the incoming requests are both read and write, or all are write, they can only be processed sequentially. When the requests arriving at the same bank are two read requests (read requests from different channels), they can enter the bank in parallel for reading, speeding up the process.

[0115] When the on-chip shared memory module needs to read data from the DDR memory module, it will start the internal read-write control module to read data from the memory access control module. When the on-chip shared memory module is full, it will also start the memory access control module to write data to clear part of the on-chip storage area, and use the LRU algorithm to store the least recently accessed data into the DDR memory module.

[0116] (5) Matrix module

[0117] The matrix module architecture is as follows Figure 8As shown, after receiving the matrix calculation microcode, the control module checks whether the current microcode belongs to matrix operation or vector operation, and whether it is sparse matrix calculation; if it is sparse matrix calculation, the decompression module is called to decompress the data, and the reconfigurable computing interface module is called through the matrix operation module to complete the calculation. After that, the overall result is compressed through the compression module, and the compressed data is written to the on-chip shared storage module through the memory access module; if it is a dense matrix operation and vector operation, it enters the matrix operation module and the vector operation module respectively, and the operation unit organizes the operation form and sends it to the reconfigurable computing interface module for calculation, and writes it to the on-chip shared storage module after the calculation is completed.

[0118] (6) Memory access control module

[0119] The memory access control module is responsible for receiving control from the on-chip shared memory module and obtaining data from the DDR memory module. At the same time, when the storage of the on-chip shared memory module is tight and some storage needs to be released, the memory access control module writes data to reduce the on-chip cache pressure.

[0120] (7) Reconfigurable computing interface module

[0121] Reconfigurable computing interface module architecture such as Figure 9 As shown, there are five computation requests (four from the matrix module and one from the microcode control module). After multiple computation requests enter in parallel, each one passes through the microcode request arbitration module and enters the buffer pool. Simultaneously, the address generation module generates a dedicated address for reconfigurable computation. After the address is generated, the corresponding computation task requester is responded to and data begins to be received and stored in the reconfigurable storage module. When the received data is ready, the reconfigurable storage module notifies the buffer pool and submits the corresponding microcode in the buffer pool to the reconfigurable configuration module.

[0122] (8) Reconfigurable configuration module

[0123] Reconfigurable configuration module architecture such as Figure 10 As shown, after the microcode enters the reconfigurable configuration module, the configuration parsing module parses the microcode configuration word information. The configuration word storage module queries the detailed calculation configuration information based on the configuration word information and sends the calculation configuration information unrelated to the array to the current array configuration module. If there is an available array configuration in the current array, it directly enters the array control module. If there is no available array configuration, it enters the array search module. The array search module searches for available operator subarrays and locks the area of ​​available operator subarrays. If the number of operators found is insufficient to complete the current calculation, it continues to loop in the array until sufficient operators are available. After the operator search is completed, the found operator information is sent to the array control module. The array control module controls the operator subarray to perform single or multiple rounds of calculations.

[0124] (9) Reconfigurable computing module

[0125] The reconfigurable computing module calculates multiple computing microcodes simultaneously by partial reconstruction; after the calculation is completed, it sends a calculation completion signal to the result return network and submits the calculation result to the result return network.

[0126] Reconfigurable including 4 PE sub-arrays, a single sub-array such as Figure 11 As shown, there are three floating-point arrays and one integer array. Every four PEs in the PE subarray form a subnet. The PE at the top of the subnet is a super PE. Data is transmitted layer by layer within the PE subnet.

[0127] (10) The results are returned to the network

[0128] After the computational array completes a calculation under the control of the array control module, the result is stored in the result return network. If the calculation is performed by a reconfigurable computation microcode issued by the matrix module, the calculation result is returned to the corresponding matrix module. If the calculation is performed by a reconfigurable computation microcode issued by the microcode control module, the calculated data is stored in the on-chip shared memory module and a calculation completion signal is sent to the microcode control module. This network is built using a CrossBar network to quickly store the calculated data in the on-chip shared memory module.

[0129] The proposed tensor processing system, based on reconfigurable computing, can deploy a wide variety of tensor computing tasks after simple software configuration, demonstrating enhanced versatility. Furthermore, it offers both CPU-controlled and microcode-controlled operating methods, enabling standalone computing on a single chip or cluster computing by inserting other boards and transferring data via PCIE.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A tensor processing system based on reconfigurable computing, characterized in that: include: QSFP interface: multiple QSFP interfaces are provided for loading external microcode and data into the DDR storage module. The microcode includes reconfigurable computing microcode and matrix computing microcode. DDR memory module: used to store microcode and data; Memory access control module: used to receive memory access requests sent by the on-chip shared memory module and obtain microcode and data from the DDR memory module; at the same time, when the on-chip shared memory module needs to release a certain amount of memory, the memory access control module writes the data; Microcode control module: used to manage matrix computing microcode and reconfigurable computing microcode; by accessing the on-chip shared storage module, read the data corresponding to the microcode address, cache it in the microcode control module, and transmit the microcode and data to a matrix module or directly to the reconfigurable computing interface module according to the microcode type; Matrix module: Set up a multi-way matrix module to calculate the type of microcode according to the loaded microcode and data, independently complete the analysis of matrix instructions in parallel, compress and decompress the sparse matrix, and generate the calculation type provided by the reconfigurable calculation interface module, continuously initiate calculation requests to the reconfigurable calculation interface module, and disassemble the matrix calculation task into the reconfigurable calculation microcode and integrate the data; After the calculation is completed, a calculation completion signal is sent to the microcode control module, and the on-chip shared storage module is requested to save the data; On-chip shared memory module: shared by the CPU, microcode control module and result return network, used to send memory access requests to the memory access control module and cache the loaded data; Control network: used to convert the extended instructions issued by the CPU into microcode, and perform storage conflict detection on the microcode. After the detection is completed, the result address is generated and further microcode information and routing information / control signals are generated. The generated microcode information and routing information / control signals are transmitted to the microcode control module through the microcode send Fifo. After the microcode is executed, the error information is saved and the CPU is interrupted. RISC-V processor: a CPU based on the RISC-V architecture, used to control the overall calculation under the CPU control method, and transmit the generated microcode to the microcode control module through the control network; Reconfigurable computing interface module: used for the parallel entry of multiple computing requests, generates a dedicated address for reconfigurable computing, generates a response to the outside world after the address is generated, and starts receiving data. When the received data is ready, it submits the microcode to the reconfigurable configuration module; Reconfigurable computing module: Contains four sub-arrays, and can simultaneously compute multiple microcodes through partial reconfiguration. It sends a computation completion signal to the result return network and submits the computation results to the result return network. Reconfigurable configuration module: used for operator configuration and controls the entire computational process of the operator subarray; Result return network: used to store the calculation results of the reconfigurable configuration module. If it is the reconfigurable calculation microcode issued by the matrix module, the calculation results will be returned to the corresponding matrix module. If it is a reconfigurable calculation microcode issued by the microcode control module, the calculated data will be stored in the on-chip shared storage module, and a calculation completion signal will be sent to the microcode control module at the same time.

2. The tensor processing system based on reconfigurable computing according to claim 1, wherein: The microcode control module includes: Microcode request module: used to obtain microcode information from the on-chip shared storage module and send the unexecuted microcode to the microcode cache module; Microcode receiving module: used to receive the calculation microcode from the CPU and send it to the microcode cache module; Microcode cache module: used to temporarily store microcode that has not yet been executed; Microcode memory access channel: used to submit the request for loading data from the microcode cache module to the on-chip shared memory module; Data cache module: used to load data from the on-chip shared storage module after the microcode memory access channel issues a request to load microcode corresponding data, and send the reconfigurable computing microcode and data to the reconfigurable computing interface module through the reconfigurable microcode channel; Address detection module: used to perform address detection on the matrix calculation microcode and matrix data and then send them to the matrix selection arbitration module; Matrix selection arbitration module: used to select the on-chip matrix module according to the storage address range of the matrix calculation microcode, and then send the matrix data to be calculated and the matrix calculation microcode to a certain matrix channel; Matrix channel: used to transmit matrix calculation microcode and matrix data to the corresponding matrix module according to the routing.

3. The tensor processing system based on reconfigurable computing according to claim 1, wherein: After receiving the extended instructions for matrix calculation and reconfigurable calculation from the RISC-V processor, the control network performs a storage conflict detection on the current extended instruction and the previously unfinished microcode; after confirming that there is no conflict, the control network checks the storage status in the on-chip shared storage module, allocates a result address for the current extended instruction from the on-chip shared storage module, further generates complete microcode information and routing information / control signals, and enters the microcode send Fifo to prepare for sending to the microcode control module; After the microcode calculation is completed, it returns to the control network, triggering a CPU interrupt. When a calculation error occurs in the matrix module and the reconfigurable computing module during the calculation process, the error information is registered in the error register. In addition, the control instructions for the peripherals are also issued through the control network. All inputs use the routing input method, and all outputs use the arbitration output method.

4. The tensor processing system based on reconfigurable computing according to claim 1, wherein: The on-chip shared storage module includes: Internal read / write control module: used to arbitrate read / write requests from the microcode control module, RISC-V processor, matrix module, result return network, and DDR storage module, distribute them to the read interface module and write interface module, and read or write data; Read interface module: used to distribute the read requests submitted by the internal read / write control module to the read / write request queue of a certain bank according to the requested storage address range; Write interface module: used to distribute the write requests submitted by the internal read / write control module to the read / write request queue of a certain bank according to the requested storage address range; Read and write request queue module: used to cache a certain number of read and write requests; Distributed storage Bank0 to Bank11: 12 banks are set, each bank has a row length of 256 bits and a depth of 32K, and the storage size of a single bank is 1MB.

5. The tensor processing system based on reconfigurable computing according to claim 1, wherein: The matrix module includes a memory access module, a control module, a compression module, a decompression module, a vector operation module and a matrix operation module. The control module is used to check whether the current microcode belongs to a matrix operation or a vector operation, and whether it is a sparse matrix calculation; If it is a sparse matrix calculation, the decompression module is called to decompress the data, and the reconfigurable computing interface module is called through the matrix operation module to complete the calculation. The overall result is compressed through the compression module, and the compressed data is written to the on-chip shared storage module through the memory access module; if it is a dense matrix operation and vector operation, it enters the matrix operation module and the vector operation module respectively, and the operation form is organized by the operation unit and sent to the reconfigurable computing interface module for calculation, and written to the on-chip shared storage module after the calculation is completed.

6. The tensor processing system based on reconfigurable computing according to claim 1, wherein: In the reconfigurable computing interface module, after multiple computing requests enter in parallel, each computing request enters the buffer pool after passing through the microcode request arbitration module, and at the same time, a dedicated address for reconfigurable computing is generated in the address generation module; After generating the address, it responds to the corresponding computing task requester and starts receiving data and saving it to the reconfigurable storage module; After receiving the data, the reconfigurable storage module sends a notification to inform the buffer pool to allow the microcode to be submitted to the reconfigurable configuration module.

7. The tensor processing system based on reconfigurable computing according to claim 1, wherein: The reconfigurable configuration module includes: Configuration parsing module: used to parse configuration word information according to microcode; Configuration word storage module: used to query detailed computing configuration information based on configuration word information and send computing configuration information unrelated to the array to the current array configuration module; if there is an available array configuration in the current array, it directly enters the array control module; if there is no available array configuration, it enters the array search module; Array search module: used to search the array according to the calculated pattern to find available operator subarrays and lock the area of ​​available operator subarrays; after the operator search is completed, the found operator information is sent to the array control module; Array control module: used to control the operator subarray to perform single-round or multi-round calculations based on operator information.

8. The tensor processing system based on reconfigurable computing according to claim 1, wherein: In the reconfigurable computing module, the reconfigurable PE subarrays include three floating-point arrays and one integer array. Every four PEs in the PE subarray form a subnet, the PE at the top of the subnet is a super PE, and data is transmitted layer by layer within the PE subnet.

9. A method for operating a tensor processing system based on reconfigurable computing according to any one of claims 1 to 8, characterized in that: include: (1)CPU control method: When used for single-chip computing, the CPU controls the global computing. It starts by the CPU, requesting instructions and data from the on-chip shared storage module. The on-chip shared storage module determines whether the request issued by the CPU is hit. If not, the memory access control module issues a memory access request to read the instructions and data of the corresponding address from the DDR storage module. If it is hit, the instructions and data required by the CPU are directly taken out. The CPU starts to fetch instructions. When the CPU decodes and resolves to ordinary CPU instructions, it executes normally and continues a new round of instruction fetch and memory access. When it resolves to instructions that need to be executed by the matrix module and the reconfigurable computing module, the microcode is transmitted to the microcode control module through the control network. When the CPU decodes, it has determined that only the matrix computing microcode and the reconfigurable computing microcode are sent to the microcode control module. After receiving the microcode, the microcode control module accesses the on-chip shared storage module, reads the data of the address corresponding to the microcode, and sends the microcode according to the type of microcode. If it is a matrix calculation microcode, the corresponding matrix module is allocated and transmitted to the matrix module. The matrix module generates a reconfigurable calculation microcode inside and sends it to the reconfigurable calculation interface module. If it is not a matrix calculation microcode, it is a reconfigurable calculation microcode and is directly sent to the reconfigurable calculation interface module. The reconfigurable computing interface module responds and receives the data to be calculated, configures and calculates it, and then sends the result to the return network to complete the calculation. It determines the source of the calculation task. If it is not a calculation task sent by the matrix module, it is directly submitted to the microcode control module, which then interrupts the CPU. If it is a reconfigurable calculation microcode provided by the matrix module, it is returned to the corresponding matrix module and determines whether the calculation is completed. If not, it continues to generate reconfigurable calculation microcode. If completed, it sends an end signal to the microcode control module. The microcode control module interrupts the CPU and applies to the on-chip shared storage module for data preservation. (2) Cluster computing method: A board for carrying a tensor processing system based on reconfigurable computing, the board is connected to the host computer through a QSFP interface. After loading external microcode and data, the microcode control module is started, and the microcode control module controls the overall calculation, and requests microcode and data from the on-chip shared storage module. The on-chip shared storage module determines whether the request sent by the microcode control module is hit. If it is hit, the microcode and data are directly sent to the microcode control module. If it is not hit, a memory access request is sent to the memory access control module to read the microcode and data of the corresponding address from the DDR storage module. The microcode and data in the DDR storage module are read from the low The storage format from address to high address is: ① location segment configuration of microcode and data, ② microcode sequence, ③ data; the microcode control module presets the lowest address to read, finds the microcode and data location, starts reading the data at the address corresponding to the microcode, and sends and executes the microcode; the microcode calculation process is consistent with the CPU control method, and finally the microcode control module determines whether the microcode is fully calculated. If not, the uncalculated microcode and data are obtained and sent to the microcode control module. If the calculation is fully completed, the microcode control module directly sends an end signal to the host computer, interrupts the host computer, and at the same time applies to the on-chip shared storage module for data storage.

10. An FPGA development board for implementing the tensor processing system based on reconfigurable computing according to any one of claims 1 to 8, characterized in that: The FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The FPGA development board is integrated with multiple QSFP28 cage slots, each of which supports up to 4 channels of high-speed serial data transmission. The FPGA development board is equipped with four DIMM slots as DDR storage modules, and each DIMM is connected to the core logic of the FPGA through a 72-bit wide parallel bus. The FPGA development board is equipped with a SlimSAS interface and a UtilityConnection interface. The FPGA development board also integrates a BMC management chip, a USB Hub module, a JTAG interface, and a FLASH memory.

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