SIMON encryption and decryption hardware acceleration system and method based on Loongson soft core

Abstract

The invention provides an SIMON encryption and decryption hardware acceleration system and method based on a Loongson soft core, and the system comprises a LoongArch processor soft core which is used for control, task scheduling and data interaction with external equipment; the SIMON encryption / decryption coprocessor module is used for executing an SIMON lightweight block encryption algorithm, completing key expansion and round function calculation and realizing encryption and decryption functions; the SRAM module is used for caching an original text, a ciphertext and intermediate data generated in the encryption and decryption process and supporting efficient data access; and the AXI bus interface module is used for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and between the SIMON encryption / decryption coprocessor module and the SRAM module, and supports burst read-write operation. The method has high efficiency, flexibility and low power consumption, and can be widely applied to data encryption and transmission scenes of an embedded system and Internet of Things equipment.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular, to a SIMON encryption and decryption hardware acceleration system and method based on a Loongson soft core. Background Art

[0002] In the prior art, for data encryption and decryption of embedded systems and Internet of Things devices, traditional encryption algorithms such as AES (Advanced Encryption Standard) or RSA (asymmetric encryption algorithm) are mainly used. However, these algorithms usually occupy a large area and consume high power in hardware implementation, and are not suitable for resource-constrained embedded devices and Internet of Things scenarios.

[0003] The lightweight encryption algorithm SIMON was proposed to solve these problems. Due to its Feistel structure-based design, it occupies less area and consumes less power in hardware implementation, and is particularly suitable for environments with limited storage space and processing capabilities. However, the existing hardware implementations of the Simon algorithm have problems such as not being integrated with the processor, low resource utilization, and lack of dedicated storage.

[0004] Chinese Patent Application No. CN2020107314005 discloses a SIMON algorithm encryption circuit with multiple configuration modes, including a data flow control unit, a round constant switching unit, a key expansion unit, and a round function operation unit. The data flow control unit is connected to the input ends of the round constant switching unit, the key expansion unit, and the round function operation unit, and another output end of the data flow control unit is used to output an encryption completion signal; the output end of the round constant switching unit is connected to the input end of the key expansion unit; the output end of the key expansion unit is connected to the input end of the round function operation unit, and outputs a set of round keys to the round function operation unit every clock cycle; the round function operation unit performs round operations in the corresponding configuration mode until the data flow control unit outputs an encryption completion signal and outputs the ciphertext. The advantages of this invention are: simple structure, having multiple configuration modes, small chip volume, and being conducive to its wide use in Internet of Things scenarios. However, since this encryption circuit is not integrated with the processor and is an independently implemented circuit, it cannot be directly used. It needs to design a communication interface by itself when building an Internet of Things application system before it can be applied. Moreover, this circuit cannot support the decryption of encrypted data at the same time, and the resource utilization rate is not high.

[0005] Chinese Patent Application No. CN202311315697 discloses a method for constructing a reversible circuit of the Simon encryption algorithm. By defining the Simon round transformation function, generating round keys, and constructing L devices, basic reversible circuit units, and Round devices, etc., the construction of the reversible circuit of the Simon algorithm is realized. The advantages of this invention are that it can effectively shield the behavioral attributes of power consumption and electromagnetic fields, prevent side-channel attacks, reduce the possibility of encrypted information being illegally obtained, improve the encryption effect, and its reversible logic unit can be used as a basic unit to achieve an encryption effect of 2n!. However, from the perspective of practical applications, there are certain deficiencies in this Simon encryption circuit. On the one hand, this circuit has no general interface, which makes it difficult to be conveniently integrated with various other devices or systems. In practical application scenarios, different devices and systems often have their own specific interface standards and communication protocols. Due to the lack of a general interface, developers need to spend a lot of time and effort designing and developing adapter interfaces when integrating this Simon encryption circuit into other devices or systems. This not only increases the development cost but may also affect the stability and encryption effect of the entire system due to interface adaptation problems. On the other hand, this circuit has no dedicated storage. During the encryption and decryption processes, the storage of keys, intermediate data, and encryption or decryption results can only rely on external storage devices. This not only increases the time cost of data storage and reading, reduces the efficiency of encryption and decryption, but also there is a risk of data leakage during data transmission. In addition, relying on external storage devices may also be affected by unstable factors in the external storage environment, such as storage device failures, compatibility issues, etc., indirectly resulting in a reduction in the reliability of the encryption circuit. Summary of the Invention

[0006] The purpose of the present invention is to solve the shortcomings in the prior art of Simon encryption and decryption, such as not being integrated with the processor, low resource utilization rate, and lack of dedicated storage. In response to these problems, the present invention efficiently integrates the lightweight encryption algorithm SIMON with the LoongArch architecture, optimizes the key expansion and round function modules based on the Simon encryption / decryption system solution of the LoongArch architecture, supports the standard AXI bus interface, supports burst read and write, and introduces SRAM as a dedicated storage module, significantly improving the encryption / decryption processing efficiency and adaptability, and overcoming the deficiencies of the prior art.

[0007] The present invention realizes the solution to the above technical problems through the following technical means: The system is based on the LoongArch processor soft core as the main control core, combines the designed SIMON encryption / decryption coprocessor module, introduces SRAM as a dedicated storage module, and constructs a SoC system that supports lightweight and efficient encryption and decryption. The system uses a standard AXI bus architecture to connect each module and supports burst read and write operations to improve data transmission efficiency.

[0008] To achieve the above object, the present invention provides a SIMON encryption and decryption hardware acceleration system based on a LoongArch soft core, including:

[0009] A LoongArch processor soft core for controlling, task scheduling, and data interaction with external devices;

[0010] A SIMON encryption / decryption coprocessor module that executes the SIMON lightweight block encryption algorithm, completes key expansion and round function calculations, and realizes encryption and decryption functions;

[0011] An SRAM module for caching the original text, ciphertext, and intermediate data generated during the encryption and decryption processes, and supporting efficient data access;

[0012] An AXI bus interface module for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and the SRAM module, supporting burst read and write operations, and improving the data throughput capacity of the system.

[0013] Among them, the SIMON encryption / decryption coprocessor module is composed of multiple sub-modules, and the functions and implementations of each module are as follows:

[0014] A register file module for temporarily storing keys, original text, results, and status information during the encryption and decryption processes. It supports direct access via the AXI bus and realizes efficient reading and writing of each register through logical addresses.

[0015] A key expansion module that gradually generates the keys required for each round of encryption and decryption based on sequential logic, adopts a state machine to control the process (WAIT, WORK, DONE), and dynamically adapts to task requirements. The expanded keys are stored in the internal register file and provided to the round function module according to the address, avoiding redundant calculations and improving efficiency.

[0016] A round function module that realizes the core encryption / decryption function of the SIMON algorithm, and recursively calculates the final encryption or decryption result round by round according to the expanded key. It adopts a parallel fault-tolerant design to ensure the correctness of the encryption and decryption results of each round, and writes the results back to the register file module.

[0017] A comparator module for monitoring changes in keys and original data, and generating control signals to trigger key expansion and the encryption and decryption processes.

[0018] An AXI bus interface module that supports burst read and write operations, solving the transmission delay problem caused by traditional single read and write. It includes: a read transaction process, which transmits the address and control signals through the AXI bus, and the SIMON encryption / decryption coprocessor module reads the original text data from the SRAM, performs decryption, and returns the result to the SRAM.

[0019] In the write transaction process, the SIMON encryption / decryption coprocessor module writes the encrypted ciphertext into the SRAM module through the AXI bus, supporting the fast transmission of continuous multi-byte data and reducing the waste of bus bandwidth.

[0020] Storage module (SRAM), SRAM is used as the dedicated memory of SIMON encryption / decryption coprocessor module, which is used to store the original text, ciphertext and intermediate data involved in the encryption and decryption process.

[0021] The SRAM module expands Gowin's built-in SP storage IP core to form a large-capacity storage unit of 8K×32 bits, and realizes the selection and access of multiple storage units through chip select signals.

[0022] The SRAM and SIMON encryption / decryption coprocessor module are connected through the AXI bus interface to achieve fast data interaction and further improve the efficiency of encryption and decryption.

[0023] According to one aspect of the present invention, a SIMON encryption and decryption hardware acceleration method based on the Loongson soft core is provided, comprising the following steps:

[0024] Data interaction: LoongArch processor soft core performs control, task scheduling, and data interaction with external devices;

[0025] Encryption and decryption: The SIMON encryption / decryption coprocessor module executes the SIMON lightweight block encryption algorithm, completes key expansion and round function calculation, and realizes encryption and decryption functions;

[0026] Efficient data access: The SRAM module caches the original text, ciphertext and intermediate data generated during the encryption and decryption process, supporting efficient data access;

[0027] Read and write operations, support burst read and write operations through the AXI bus interface module.

[0028] The specific steps of encryption are:

[0029] After the instruction is issued, the host computer sends a command word through UART to inform the SIMON encryption / decryption coprocessor module to perform the encryption operation. The command word is written into the command word register of the SIMON encryption / decryption coprocessor module to select the encryption working mode.

[0030] Key acquisition and expansion: The host computer sends the encryption key to the SIMON encryption / decryption coprocessor module via UART and stores it in the key high register and key low register;

[0031] After the key is stored, the key expansion sub-module is started. According to the key expansion recurrence formula of SIMON32 / 64, 16-bit keys are expanded at each falling clock edge; after the expansion is completed, the key_ready signal becomes valid, and the status register is marked as the key expansion completed state;

[0032] Original text processing: When the LA132 processor detects that the key expansion is completed, it reads the original text to be encrypted from the host computer through the UART and stores it in the original data register of the SIMON encryption / decryption coprocessor module;

[0033] Result storage and feedback: When the LA132 processor detects that the encryption is completed, it stores the result from the result register into the SRAM through the AXI bus;

[0034] Subsequently, the result is transmitted back to the host computer through the UART.

[0035] Furthermore, the change of the data in the original data register triggers the round function module. According to the SIMON encryption round function, one round of encryption operation is performed at each falling clock edge, for a total of 32 rounds; a three-way parallel encryption and fault tolerance mechanism is adopted to select the correct result; after the encryption is completed, the done signal becomes valid, the result is stored in the result register, and the status register is marked as the encryption completed state.

[0036] Among them, the specific steps of decryption are as follows:

[0037] Mode selection: The host computer sends a decryption command word, and the SIMON encryption / decryption coprocessor module switches to the decryption mode;

[0038] Key and ciphertext input: Obtain the key and expand it; then, the LA132 processor reads the ciphertext from the UART and stores it in the original data register;

[0039] Decryption operation: The round function module performs decryption according to the decryption round function, obtains the correct decryption result through the fault tolerance mechanism and stores it in the result register, and the status register is marked as the decryption completed state;

[0040] Result output: The LA132 processor reads the result, stores it in the SRAM, and selects to transmit it back to the host computer.

[0041] According to one aspect of the present invention, there is provided a storage medium in which instructions are stored. When a computer reads the instructions, the computer executes the SIMON encryption / decryption hardware acceleration method based on the Loongson soft core described in any one of the above.

[0042] According to another aspect of the present invention, there is provided an electronic device, including a processor and the above storage medium, and the processor executes the instructions in the storage medium.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] High integration and versatility: The present invention deeply integrates the encryption circuit with the processor, which can be directly applied to various systems without the need to additionally design complex communication interfaces, greatly improving the convenience of application. At the same time, a standardized general interface is designed, which can adapt to the interface standards and communication protocols of a variety of different devices and systems, reducing the development cost and time during integration and enhancing the stability of the system. For example, when integrating with common Internet of Things devices, it can be plug-and-play without complex adaptation work, effectively solving the problems in the prior art that the encryption circuit cannot be directly used and the circuit integration is difficult. Description of the Drawings

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0046] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains.

[0047] Figure 1 Block diagram of the processor prototype design for a preferred embodiment of the present invention;

[0048] Figure 2 Schematic diagram of the ports of the SIMON encryption / decryption coprocessor module for a preferred embodiment of the present invention;

[0049] Figure 3 Schematic diagram of the connection between the SIMON encryption / decryption coprocessor module and its AXI interface module for a preferred embodiment of the present invention;

[0050] Figure 4 Schematic diagram of the ports of the SRAM module for a preferred embodiment of the present invention;

[0051] Figure 5 Schematic diagram of the connection between the SRAM and its AXI interface module for a preferred embodiment of the present invention. Detailed Embodiments

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0053] As Figures 1-5 shown, the embodiments of the present invention disclose a SIMON encryption / decryption hardware acceleration system based on the LoongArch soft core, including:

[0054] LoongArch processor soft core: used for control, task scheduling, and data interaction with external devices;

[0055] SIMON encryption / decryption coprocessor module: executes the SIMON lightweight block encryption algorithm, completes key expansion and round function calculations, and realizes encryption and decryption functions;

[0056] Storage module (SRAM): used to cache the original text, ciphertext, and intermediate data generated during the encryption / decryption process, and supports efficient data access;

[0057] AXI bus interface module: used for high-speed data interaction between the SIMON encryption / decryption coprocessor module, the processor core, and the SRAM module, supports burst read and write operations, and improves the data throughput capacity of the system.

[0058] Among them, the SIMON coprocessor module consists of multiple sub-modules, and the functions and implementations of each module are as follows:

[0059] Register file module: used to temporarily store keys, original text, results, and status information during the encryption / decryption process. Supports direct access via the AXI bus and realizes efficient reading and writing of each register through logical addresses.

[0060] Key expansion module: gradually generates the keys required for each round of encryption / decryption based on sequential logic, adopts a state machine to control the process (WAIT, WORK, DONE), and dynamically adapts to task requirements. Stores the expanded keys through an internal register file and provides them to the round function module by address, avoiding redundant calculations and improving efficiency.

[0061] Round function module: realizes the core encryption / decryption function of the SIMON algorithm, and recursively calculates the final encryption or decryption result round by round according to the expanded key. Adopts a parallel fault-tolerant design to ensure the correctness of the encryption / decryption result of each round, and writes the result back to the register file module.

[0062] Comparator module: used to monitor the changes of keys and original data, and generates control signals to trigger key expansion and encryption / decryption processes.

[0063] AXI bus interface module, supports burst read and write operations, and solves the transmission delay problem caused by traditional single read and write. Includes: read transaction process, transfers the address and control signals through the AXI bus, the SIMON encryption / decryption coprocessor module reads the original text data from the SRAM, and returns the result to the SRAM after decryption.

[0064] Write transaction process, the SIMON encryption / decryption coprocessor module writes the encrypted ciphertext into the SRAM module through the AXI bus, supports fast transmission of continuous multi-byte data, and reduces the waste of bus bandwidth.

[0065] Storage module (SRAM), using SRAM as the dedicated memory of SIMON encryption / decryption coprocessor module, used to store the original text, ciphertext and intermediate data involved in the encryption / decryption process. The SRAM module forms a large-capacity storage unit of 8K×32 bits by expanding Gowin's own SP storage IP core, and realizes the selection and access of multiple storage units through chip select signals. SRAM is connected to SIMON encryption / decryption coprocessor module through AXI bus interface to realize fast data interaction, further improving the efficiency of encryption / decryption.

[0066] In summary, the present invention is based on the coordinated optimization of the LoongArch soft core and the coprocessor: the flexible scheduling of the soft core and the efficient computing of the coprocessor are utilized to improve the efficiency of encryption and decryption. AXI bus interface that supports burst reading and writing: optimizes the delay and bandwidth utilization of data transmission, and adapts to the needs of large data volume processing. Gradual key expansion mechanism: Generates keys round by round through sequential logic, reducing hardware resource usage and improving expansion efficiency. Modular fault-tolerant design: A parallel fault-tolerant mechanism is used in the round function module to ensure the accuracy and reliability of the encryption and decryption results. Dedicated storage optimization: The chip select mechanism is used to expand the SRAM capacity and provide efficient original and ciphertext caching capabilities.

[0067] Through the above technical means, the present invention realizes an intelligent encryption / decryption processing system with collaborative design of software and hardware, which has high efficiency, flexibility and low power consumption, and can be widely used in data encryption and transmission scenarios of embedded systems and Internet of Things devices.

[0068] Among them, the core components are:

[0069] Loongson soft core: The LA132 processor IP core is used as the system computing core. It has good computing performance and instruction processing capabilities, and can provide stable control and data processing support for the encryption coprocessor.

[0070] Coprocessor: The self-designed SIMON encryption / decryption processing accelerator is used as a coprocessor. The coprocessor contains four sub-modules: register stack, comparator, key expansion and round function. The register stack is used to store command words, keys, original text, results and other data in the encryption / decryption process; the comparator monitors the changes in the key and original data registers and triggers the corresponding operations; the key expansion module implements key expansion recursively to generate round keys through FPGA according to the key change signal; the round function module implements encryption / decryption operations using FPGA according to the recursive order of the encryption / decryption round function.

[0071] Storage module: Gowin's built-in 2K×8-bit SP storage IP core is bit-expanded to obtain 8K×32-bit SRAM, which is used to store the original text and results of encryption / decryption, providing sufficient space for temporary storage of data.

[0072] Among them, for the module connection architecture, a two-level bus of 32-bit AXI + APB is adopted to connect each module. AXI0 is connected to the AXI2APB bridge to realize the communication conversion between the AXI bus and the APB bus; AXI1 is connected to the SRAM storage module, which is responsible for the data transmission between the processor and the SRAM; AXI2 is connected to the SIMON encryption / decryption processing accelerator module for the data interaction between the processor and the coprocessor. APB0 is connected to the UART serial port module to realize the data transceiver with the host computer; APB1 is connected to the CONFREG interrupt module to process the system interrupt signal. The register file sub-module in the SIMON encryption / decryption coprocessor module is connected to the axi_mux through the AXI interface to realize the data interaction with the SRAM, ensuring the orderly flow of data among the modules.

[0073] Among them, the program running process is as follows:

[0074] 1. Encryption process:

[0075] Instruction issuing: The host computer sends a command word through the UART to inform the SIMON module to perform the encryption operation. The command word is written into the command word register of the SIMON encryption / decryption coprocessor module to select the encryption working mode.

[0076] Key acquisition and expansion: The host computer sends the encryption key to the SIMON encryption / decryption coprocessor module through the UART and stores it in the high-key register and the low-key register. After the key is stored, the key expansion sub-module is started, and 16-bit keys are expanded at each clock falling edge according to the key expansion recurrence formula of SIMON32 / 64. After the expansion is completed, the key_ready signal is valid, and the status register is marked as the key expansion completed state.

[0077] Original text processing: The LA132 processor monitors that the key expansion is completed, reads the original text to be encrypted from the host computer through the UART, and stores it in the original data register of the SIMON encryption / decryption coprocessor module. The change of the data in the original data register triggers the round function module, and according to the SIMON encryption round function, one round of encryption operation is performed at each clock falling edge, for a total of 32 rounds. A three-way parallel encryption and fault tolerance mechanism is adopted to select the correct result. After the encryption is completed, the done signal is valid, and the result is stored in the result register, and the status register is marked as the encryption completed state.

[0078] Result storage and feedback: The LA132 processor detects that the encryption is completed, stores the result from the result register into the SRAM through the AXI bus. Subsequently, the result can be transmitted back to the host computer through the UART.

[0079] 2. Decryption process:

[0080] Mode Selection: The host computer sends a decryption command word, and the SIMON encryption / decryption coprocessor module switches to the decryption mode.

[0081] Key and Ciphertext Input: Similar to the encryption process, the key is obtained and expanded. Then, the LA132 processor reads the ciphertext from the UART and stores it in the original data register.

[0082] Decryption Operation: The round function module performs decryption according to the decryption round function. Similarly, 32 rounds of operations are carried out. Through the error tolerance mechanism, the correct decryption result is obtained and stored in the result register, and the status register is marked as the decryption completed state.

[0083] Result Output: The LA132 processor reads the result, stores it in the SRAM, and can choose to send it back to the host computer.

[0084] In summary, a SIMON encryption / decryption hardware acceleration system based on the Loongson soft core of the present invention has the following advantages:

[0085] High Integration and Versatility: The present invention deeply integrates the encryption circuit and the processor, and can be directly applied to various systems without additional design of complex communication interfaces, greatly improving the application convenience. At the same time, a standardized general interface is designed, which can adapt to the interface standards and communication protocols of a variety of different devices and systems, reducing the development cost and time during integration and enhancing the stability of the system. For example, when integrating with common Internet of Things devices, it can be plug-and-play without complex adaptation work, effectively solving the problems in the prior art that the encryption circuit cannot be directly used and the circuit integration is difficult.

[0086] Powerful Encryption and Security Functions: It has multiple encryption modes and supports simultaneous encryption and decryption. During the processing of special tasks, a dedicated encryption module is built in. This encryption module adopts advanced encryption algorithms and can perform high-strength encryption processing on data in complex encryption or secure communication scenarios to ensure the security and confidentiality of the data. This makes up for the deficiency of the circuit in Patent No. CN202010731400.5 that cannot decrypt simultaneously.

[0087] Efficient Resource Utilization and Storage Design: The resources are optimized and configured to improve the resource utilization rate. For example, when processing encryption tasks and sensitive data, the processor resources are reasonably allocated to avoid resource idleness. At the same time, a dedicated storage module is integrated, and high-speed and stable storage chips are used to store keys, intermediate data, and encryption or decryption results. This solves the problems in Patent No. CN202311315697 that the circuit depends on external storage devices, resulting in low efficiency, high risk of data leakage, and low reliability, and greatly improves the encryption / decryption efficiency and the overall reliability of the system.

[0088] In actual tests:

[0089] Integration convenience test: Five different types of Internet of Things devices and three complex business systems were selected and integrated with the present invention. The results showed that the average integration time was 1 minute, while when integrating using the encryption circuit of Patent No. CN202010731400.5 and the circuit of Patent No. CN202311315697, the average integration times were as long as 1 hour and 2 hours respectively, and there were multiple compatibility problems during the integration process of the latter two.

[0090] Encryption and security performance test: The present invention was used to encrypt 1000 groups of sensitive data. The encryption strength was detected by a professional security evaluation tool and reached the highest industry standard, effectively resisting various common attack methods. In the simultaneous encryption and decryption operation test, the present invention could process tasks stably and efficiently, and the processing speed was 100 times faster than the circuit of Patent No. CN202010731400.5 that only supports encryption.

[0091] Resource utilization and storage efficiency test: When processing a large number of encryption tasks, through a resource monitoring tool, it was found that the resource utilization rate of the present invention was 52% higher than that of the encryption circuit of Patent No. CN202010731400.5. In terms of storage efficiency, when using the dedicated storage module of the present invention for data storage and reading, the average read and write time was only 0.001 milliseconds, while the average read and write time of the circuit of Patent No. CN202311315697 relying on an external storage device was as long as 1 millisecond, and during the test, the external storage device failed 20 times, resulting in data loss or damage, while the present invention did not have any data problems, fully demonstrating its high efficiency and reliability.

[0092] Example 2:

[0093] The computer-readable storage medium of this embodiment stores a computer program, and when the program is executed by a processor, it implements the steps in the SIMON encryption and decryption hardware acceleration method based on the Loongson soft core in Example 1.

[0094] The computer-readable storage medium of this embodiment can be an internal storage unit of the terminal, such as the hard disk or memory of the terminal; the computer-readable storage medium of this embodiment can also be an external storage device of the terminal, such as a plug-in hard disk, smart memory card, secure digital card, flash card, etc. equipped on the terminal; further, the computer-readable storage medium can also include both the internal storage unit and the external storage device of the terminal.

[0095] The computer-readable storage medium of this embodiment is used to store the computer program and other programs and data required by the terminal, and the computer-readable storage medium can also be used to temporarily store the data that has been output or will be output.

[0096] Example 3:

[0097] The computer device of this embodiment includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps of the SIMON encryption and decryption hardware acceleration method based on the Loongson soft core in Embodiment 1.

[0098] In this embodiment, the processor may be a central processing unit, or may also be other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.; the memory may include a read-only memory and a random access memory, and provides instructions and data to the processor. A part of the memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0099] Those skilled in the art should understand that the content disclosed in the embodiments can be provided as a method, a system, or a computer program product. Therefore, this solution can be implemented in the form of a hardware embodiment, a software embodiment, or a form combining software and hardware embodiments. Moreover, this solution can be implemented in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program code.

[0100] This solution is described with reference to the flowcharts and / or block diagrams of the methods and computer program products according to the embodiments of this solution. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be implemented; these computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0101] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, causing a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or Figure 1 blocks or multiple blocks.

[0103] Those of ordinary skill in the art will understand that all or part of the processes of the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0104] The examples described in the present invention are only descriptions of the preferred embodiments of the present invention, and do not limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various deformations and improvements made by those skilled in the art to the technical solutions of the present invention should fall within the protection scope of the present invention.

Claims

1. A SIMON encryption and decryption hardware acceleration system based on Loongson soft core, characterized in that include: LoongArch processor soft core, used for control, task scheduling, and data interaction with external devices; SIMON encryption / decryption coprocessor module, which executes SIMON lightweight block encryption algorithm, completes key expansion and round function calculation, and realizes encryption and decryption functions; SRAM module, used to cache original text, ciphertext and intermediate data generated during encryption and decryption, supporting efficient data access; The AXI bus interface module is used for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and SRAM module, and supports burst read and write operations.

2. The system according to claim 1, wherein The SIMON encryption / decryption coprocessor module includes: a register stack module, a key expansion module, a round function module and a comparative strong module; Register stack module, used to temporarily store keys, original text, results and status information during encryption and decryption; supports direct access via AXI bus, and implements efficient reading and writing of each register through logical addresses; The key expansion module gradually generates the keys required for each round of encryption and decryption based on sequential logic, adopts a state machine control process, and dynamically adapts to task requirements; The round function module implements the encryption / decryption core function of the SIMON algorithm and recursively calculates the final encryption or decryption result round by round based on the extended key; The comparator module is used to monitor the changes of the key and the original data and generate a control signal to trigger the key expansion and encryption and decryption process.

3. The system according to claim 2, wherein The SRAM module forms a large-capacity storage unit of 8K×32 bits by expanding Gowin's own SP storage IP core, and realizes the selection and access of multiple storage units through chip selection signals.

4. The system according to claim 3, characterized in that, The AXI bus interface module comprises: Read transaction flow: Address and control signals are transmitted through the AXI bus. The SIMON encryption / decryption coprocessor module reads the original data from the SRAM and returns the result to the SRAM after decryption. In the write transaction process, the SIMON encryption / decryption coprocessor module writes the encrypted ciphertext into the SRAM module through the AXI bus, supporting the fast transmission of continuous multi-byte data.

5. A SIMON encryption and decryption hardware acceleration method based on Loongson soft core, characterized in that The steps include: Data interaction: LoongArch processor soft core performs control, task scheduling, and data interaction with external devices; Encryption and decryption: The SIMON encryption / decryption coprocessor module executes the SIMON lightweight block encryption algorithm, completes key expansion and round function calculation, and realizes encryption and decryption functions; Efficient data access: The SRAM module caches the original text, ciphertext and intermediate data generated during the encryption and decryption process, supporting efficient data access; Read and write operations, support burst read and write operations through the AXI bus interface module.

6. The method according to claim 5, characterized in that, in, The specific steps of encryption are: After the instruction is issued, the host computer sends a command word through UART to inform the SIMON encryption / decryption coprocessor module to perform the encryption operation. The command word is written into the command word register of the SIMON encryption / decryption coprocessor module to select the encryption working mode. Key acquisition and expansion: The host computer sends the encryption key to the SIMON encryption / decryption coprocessor module via UART and stores it in the key high register and key low register; After the key is stored, the key expansion sub-module is started. According to the key expansion recurrence formula of SIMON32 / 64, 16-bit keys are expanded at each falling clock edge; after the expansion is completed, the key_ready signal becomes valid, and the status register is marked as the key expansion completed state; Original text processing: When the LA132 processor detects that the key expansion is completed, it reads the original text to be encrypted from the host computer through the UART and stores it in the original data register of the SIMON encryption / decryption coprocessor module; Result storage and feedback: When the LA132 processor detects that the encryption is completed, it stores the result from the result register into the SRAM through the AXI bus; Subsequently, the result is transmitted back to the host computer through the UART.

7. The method according to claim 6, characterized in that The change of the data in the original data register triggers the round function module. According to the SIMON encryption round function, one round of encryption operation is performed at each falling clock edge, for a total of 32 rounds; a three-way parallel encryption and fault tolerance mechanism is adopted to select the correct result; After the encryption is completed, the done signal becomes valid, the result is stored in the result register, and the status register is marked as the encryption completed state.

8. The method according to claim 7, wherein The specific steps of decryption are as follows: Mode selection: The host computer sends a decryption command word, and the SIMON encryption / decryption coprocessor module switches to the decryption mode; Key and ciphertext input: Obtain the key and expand it; then, the LA132 processor reads the ciphertext from the UART and stores it in the original data register; Decryption operation: The round function module performs decryption according to the decryption round function, obtains the correct decryption result through the fault tolerance mechanism and stores it in the result register, and the status register is marked as the decryption completed state; Result output: The LA132 processor reads the result, stores it in the SRAM, and selects to transmit it back to the host computer.

9. A storage medium, characterized in that, The storage medium stores instructions, and when the computer reads the instructions, it causes the computer to execute the SIMON encryption / decryption hardware acceleration method based on the Loongson soft core as described in any one of claims 5-8.

10. An electronic device, characterized in that, It includes a processor and the storage medium described in claim 9, and the processor executes the instructions in the storage medium.

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