Preparation method of doped polycrystalline silicon layer and preparation method and application of TBC battery

Abstract

The invention provides a preparation method of a doped polycrystalline silicon layer and a preparation method and application of a TBC battery, and relates to the technical field of solar cells, and the preparation method comprises the following steps: depositing the doped polycrystalline silicon layer on a tunneling oxide layer, and then annealing; wherein deposition of the doped polycrystalline silicon layer and annealing serve as one procedure, the process of preparing the doped polycrystalline silicon layer comprises at least two procedures, the annealing temperature in each procedure is lower than the deposition temperature, and the deposition temperatures in the adjacent procedures are decreased progressively. And the cell conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a doped polysilicon layer, a method for preparing a TBC cell, and an application thereof. Background Art

[0002] The preparation process of the N-Poly in the N region on the back of the TBC cell is LPCVD + phosphorus diffusion. The Poly-Si thin film is grown by the LPCVD method. The grains have a (110) preferred orientation, and their morphology is "V"-shaped, containing a high density of micro-twins, and the grain size is small, and the carrier mobility is not large enough. At the same time, the Poly-Si thin film grown at a high temperature (above 600 °C) has a large thermal stress, which causes an increase in the warpage of the silicon wafer, resulting in difficult doping during phosphorus diffusion, high sheet resistance, low FF, and reduced battery conversion efficiency.

[0003] In view of this, the present invention is particularly proposed. Summary of the Invention

[0004] One of the purposes of the present invention is to provide a method for preparing a doped polysilicon layer to solve at least one of the technical problems existing in the prior art. The present invention improves the warpage, improves the sheet resistance uniformity, and improves the battery conversion efficiency by adopting a multi-step deposition combined with an intermittent annealing process.

[0005] The second purpose of the present invention is to provide an application of the method for preparing a doped polysilicon layer in the preparation of a TBC cell.

[0006] The third purpose of the present invention is to provide a method for preparing a TBC cell.

[0007] In order to achieve the above purposes of the present invention, the following technical solutions are specifically adopted:

[0008] In the first aspect, the present invention provides a method for preparing a doped polysilicon layer, including the following steps: depositing a doped polysilicon layer on a tunneling oxide layer, and then annealing;

[0009] Wherein, taking the deposition of the doped polysilicon layer and annealing as one process, the process of preparing the doped polysilicon layer includes at least two such processes, the annealing temperature in each process is lower than the deposition temperature, and the deposition temperature in adjacent processes decreases.

[0010] Further, the process of preparing the doped polysilicon layer includes four such processes, and the four processes include the first deposition, the first annealing, the second deposition, the second annealing, the third deposition, the third annealing, the fourth deposition, and the fourth annealing;

[0011] Preferably, the doped polysilicon layer is deposited by the PECVD method;

[0012] Preferably, the temperature for the first deposition is 500 - 550 °C, the time is 100 - 200 s, the temperature for the first annealing is 450 - 500 °C, and the time is 10 - 20 min;

[0013] Preferably, the temperature for the second deposition is 450 - 500 °C, the time is 100 - 200 s, the temperature for the second annealing is 400 - 450 °C, and the time is 10 - 20 min;

[0014] Preferably, the temperature for the third deposition is 400 - 450 °C, the time is 400 - 600 s, the temperature for the third annealing is 350 - 400 °C, and the time is 30 - 40 min;

[0015] Preferably, the temperature for the fourth deposition is 350 - 400 °C, the time is 600 - 800 s, the temperature for the fourth annealing is 300 - 350 °C, and the time is 50 - 60 min;

[0016] Preferably, a mixed gas of SiH4, H2, and PH3 is introduced into the PECVD equipment to prepare a doped polysilicon layer, and the flow ratio of SiH4, H2, and PH3 is 1:(1 - 3):(0.2 - 0.5).

[0017] In a second aspect, the present invention provides an application of a method for preparing a doped polysilicon layer in the preparation of a TBC battery.

[0018] In a third aspect, the present invention provides a method for preparing a TBC battery, comprising the following steps:

[0019] (a) A first tunneling oxide layer, a P - Poly layer, and a BSG layer are sequentially prepared on the back surface of the silicon substrate;

[0020] (b) The back surface of the silicon substrate is patterned once to remove the BSG layer in the preset negative electrode region and the Gap region, forming a patterned groove, and then the P - Poly layer and the first tunneling oxide layer in the patterned groove region are removed;

[0021] (c) A second tunneling oxide layer, a doped polysilicon layer prepared by the method for preparing a doped polysilicon layer, and a PSG layer are sequentially prepared on the back surface of the silicon substrate;

[0022] (d) The back surface of the silicon substrate is patterned twice to remove the PSG layer in the preset positive electrode region and the Gap region;

[0023] (e) The N - Poly layer, the second tunneling oxide layer, and the BSG layer in the preset positive electrode region are removed, and the PSG layer in the preset negative electrode region and the N - Poly layer and the second tunneling oxide layer in the Gap region are removed;

[0024] (f) Passivate both sides of the cell, and then print electrodes to fabricate a TBC cell.

[0025] Further, in step (a), the thickness of the first tunneling oxide layer is 0.8 - 2.0 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 6 - 20 min;

[0026] Preferably, the first tunneling oxide layer is prepared by LPCVD method;

[0027] Preferably, the preparation process of the P-Poly layer and the BSG layer includes: depositing an i-PolySi layer on the first tunneling oxide layer, and then performing boron diffusion to form the BSG layer while preparing the i-PolySi layer into the P-Poly layer;

[0028] Preferably, the thickness of the BSG layer is 30 - 80 nm;

[0029] Preferably, the i-PolySi layer is prepared by LPCVD method;

[0030] Preferably, the thickness of the i-PolySi layer is 100 - 300 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 15 - 30 min;

[0031] Preferably, the boron diffusion process includes: introducing a mixed gas of BCl3, O2 and N2 to deposit the BSG layer, the flow rate of BCl3 is 200 - 400 sccm, the flow rate of O2 is 700 - 1000 sccm, the flow rate of N2 is 2500 - 3000 sccm, the deposition temperature is 800 - 1000 °C, the deposition time is 1 - 2 h, and the sheet resistance is 100 - 200 Ω.

[0032] Further, in step (b), the depth of the patterned groove is 30 - 80 nm, and the width of the patterned groove is 400 - 600 μm;

[0033] Preferably, the primary patterning is performed by laser;

[0034] Preferably, the P-Poly layer, the first tunneling oxide layer and a part of the silicon substrate in the patterned groove area are removed by the slot polishing method, and the depth of the patterned groove is increased to 2 - 3 μm.

[0035] Further, in step (c), the second tunneling oxide layer, the doped polysilicon layer and the PSG layer are prepared by PECVD method, wherein the doped polysilicon layer includes an N-Poly layer;

[0036] Preferably, the thickness of the second tunneling oxide layer is 0.8 - 2.0 nm, the deposition temperature is 300 - 350 °C, the deposition time is 80 - 150 s, the N2O flow rate is 5 - 10 slm, and the power is 6 - 9 kw;

[0037] Preferably, a mixed gas of SiH4 and N2O is introduced into the PECVD equipment to form a PSG layer, and the flow ratio of SiH4 to N2O is 1:(4 - 5);

[0038] Preferably, during the preparation of the N-Poly layer and the PSG layer, the equipment power is 12 - 15 kW, and the pressure inside the furnace tube is 2 - 5 torr;

[0039] Preferably, after depositing the PSG layer, annealing is carried out, the annealing temperature is 800 - 950 °C, and the annealing time is 0.5 - 2 h.

[0040] Furthermore, in step (d), a laser is used to remove the PSG layer in the preset positive electrode region and the Gap region.

[0041] Furthermore, in step (e), the N-Poly layer and the second tunneling oxide layer in the preset positive electrode region and the N-Poly layer and the second tunneling oxide layer in the Gap region are removed by the slot-type alkali texturing method, and then the BSG layer in the preset positive electrode region and the PSG layer in the preset negative electrode region are removed by the slot-type acid texturing method.

[0042] Furthermore, the passivation treatment includes: depositing an alumina passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back, and sequentially depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] In the method for preparing a doped polysilicon layer provided by the present invention, when preparing the doped polysilicon layer, depositing the doped polysilicon layer and annealing are taken as one process. In order to achieve gradient intermittent annealing, the process of preparing the doped polysilicon layer of the present invention includes at least two such processes, and the deposition temperature in adjacent processes is set to decrease. At the same time, the annealing temperature in each process is set to be lower than the deposition temperature, which can connect the next deposition, reduce the high-temperature time, and improve the warpage. The present invention adopts a multi-step deposition combined with intermittent annealing process to gradually release stress, and annealing is carried out after each deposition to promote lattice relaxation and improve the warpage. Description of the Drawings

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 Schematic diagram of a solar cell structure deposited with a first tunneling oxide layer, a P-PolySi layer, and a BSG layer provided by the present invention;

[0047] Figure 2 Schematic diagram of the solar cell structure after the first patterning;

[0048] Figure 3 Schematic diagram of the solar cell structure after removing the BSG layer and alkali polishing;

[0049] Figure 4 Schematic diagram of a solar cell structure deposited with a second tunneling oxide layer, an N-PolySi layer, and a PSG layer;

[0050] Figure 5 Schematic diagram of the solar cell structure after the second patterning;

[0051] Figure 6 Schematic diagram of the solar cell structure after removing the PSG layer and texturing;

[0052] Figure 7 Schematic diagram of the solar cell structure after passivation treatment and electrode printing.

[0053] Legend: 100 - silicon substrate; 200 - first tunneling oxide layer; 300 - P-PolySi layer; 400 - BSG layer; 500 - second tunneling oxide layer; 600 - N-PolySi layer; 700 - PSG layer; 800 - aluminum oxide passivation layer; 900 - silicon nitride passivation layer; 1000 - silicon oxide passivation layer; 1100 - P-region electrode; 1200 - N-region electrode. Specific Embodiments

[0054] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meanings and scopes of the terms should be clear. However, in any case of potential ambiguity, the definitions provided herein shall prevail over any dictionary or extrinsic definition. In this application, unless otherwise specified, the use of "or" means "and / or". In addition, the use of the term "comprising" and other forms is non-limiting.

[0055] The technical solution of the present invention will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative work belong to the protection scope of the present invention.

[0056] The first aspect of the present invention provides a method for preparing a doped polysilicon layer, including the following steps: depositing a doped polysilicon layer on a tunneling oxide layer and then annealing.

[0057] Wherein, taking the deposition of the doped polysilicon layer and annealing as one process, the process of preparing the doped polysilicon layer includes at least two such processes, the annealing temperature in each process is lower than the deposition temperature, and the deposition temperature decreases in adjacent processes.

[0058] In some preferred embodiments, the process of preparing the doped polysilicon layer includes four such processes, and the four processes include the first deposition, the first annealing, the second deposition, the second annealing, the third deposition, the third annealing, the fourth deposition and the fourth annealing.

[0059] Preferably, the doped polysilicon layer is deposited by PECVD method.

[0060] Preferably, the temperature of the first deposition is 500 - 550 °C, such as 500 °C, 510 °C, 520 °C, 530 °C, 540 °C, 550 °C, etc., and the time is 100 - 200 s, such as 100 s, 150 s, 200 s, etc.; the temperature of the first annealing is 450 - 500 °C, such as 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, etc., and the time is 10 - 20 min, such as 10 min, 15 min, 20 min, etc.

[0061] Preferably, the temperature of the second deposition is 450 - 500 °C, such as 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, etc., and the time is 100 - 200 s, such as 100 s, 150 s, 200 s, etc.; the temperature of the second annealing is 400 - 450 °C, such as 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, etc., and the time is 10 - 20 min, such as 10 min, 15 min, 20 min, etc.

[0062] Preferably, the temperature for the third deposition is 400 - 450 °C, such as 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, etc., the time is 400 - 600 s, such as 400 s, 500 s, 600 s, etc., the temperature for the third annealing is 350 - 400 °C, such as 350 °C, 360 °C, 370 °C, 380 °C, 390 °C, 400 °C, etc., and the time is 30 - 40 min, such as 30 min, 35 min, 40 min, etc.;

[0063] Preferably, the temperature for the fourth deposition is 350 - 400 °C, such as 350 °C, 360 °C, 370 °C, 380 °C, 390 °C, 400 °C, etc., the time is 600 - 800 s, such as 600 s, 700 s, 800 s, etc., the temperature for the fourth annealing is 300 - 350 °C, such as 300 °C, 310 °C, 320 °C, 330 °C, 340 °C, 350 °C, etc., and the time is 50 - 60 min, such as 50 min, 55 min, 60 min, etc.

[0064] The present invention improves the warpage, enhances the sheet resistance uniformity, and increases the cell conversion efficiency through low - temperature deposition by PECVD and the process of multi - step deposition combined with intermittent annealing. Specifically, (1) Low - temperature deposition can improve the accumulation of thermal stress and the intrinsic stress of the thin film to improve the warpage. Accumulation of thermal stress: The LPCVD process is usually carried out at a high temperature (600 - 800 °C). Due to the difference in the coefficient of thermal expansion (CTE) between the substrate (such as a silicon wafer) and the deposited Poly layer, thermal stress is generated during the cooling process. When the thickness of the Poly layer is large or the deposition rate is too fast, the stress accumulation is more significant. ② Intrinsic stress of the thin film: The Poly layer deposited by LPCVD itself has intrinsic stress (including tensile stress or compressive stress), which is closely related to the deposition conditions (such as gas ratio, pressure, temperature). For example, too high a deposition rate may lead to lattice defects and increase the internal stress. Therefore, low - temperature deposition can improve the accumulation of thermal stress and the intrinsic stress of the thin film to improve the warpage. (2) Segmented deposition and annealing: The process of multi - step deposition combined with intermittent annealing is adopted to gradually release the stress. For example, after depositing a certain thickness, a short - term annealing is carried out to promote lattice relaxation and improve the warpage.

[0065] The second aspect of the present invention provides an application of a method for preparing a doped polysilicon layer in the preparation of a TBC cell.

[0066] The third aspect of the present invention provides a method for preparing a TBC cell, including the following steps:

[0067] (a) Sequentially prepare a first tunneling oxide layer 200, a P - Poly layer, and a BSG layer 400 on the back surface of a silicon substrate 100;

[0068] (b) Pattern the back side of the silicon substrate 100 once to remove the BSG layer 400 in the preset negative electrode region (N region) and the Gap region, forming a patterned groove, and then remove the P-Poly layer and the first tunneling oxide layer 200 in the patterned groove region;

[0069] (c) Sequentially prepare a second tunneling oxide layer 500, a doped polysilicon layer prepared by a preparation method of a doped polysilicon layer, and a PSG layer 700 on the back side of the silicon substrate 100;

[0070] (d) Pattern the back side of the silicon substrate 100 twice to remove the PSG layer 700 in the preset positive electrode region and the Gap region;

[0071] (e) Remove the N-Poly layer, the second tunneling oxide layer 500, the BSG layer 400 in the preset positive electrode region (P region), and remove the PSG layer 700 in the preset negative electrode region and remove the N-Poly layer and the second tunneling oxide layer 500 in the Gap region;

[0072] (f) Perform passivation treatment on both sides of the cell, and then print electrodes to prepare a TBC cell.

[0073] Among them, the Gap region is the partition between the P region (preset positive electrode region) and the N region (preset negative electrode region).

[0074] In the present invention, the silicon substrate 100 is preferably an N-type crystalline silicon substrate 100.

[0075] In some preferred embodiments, in step (a), the thickness of the first tunneling oxide layer 200 is 0.8 - 2.0 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 6 - 20 min;

[0076] Among them, "0.8 - 2.0 nm" can be, for example, 0.8 nm, 1.0 nm, 1.5 nm, 2.0 nm, etc.;

[0077] "500 - 650 °C" can be, for example, 500 °C, 550 °C, 600 °C, 650 °C, etc.;

[0078] "6 - 20 min" can be, for example, 6 min, 10 min, 15 min, 20 min, etc.

[0079] Preferably, the first tunneling oxide layer 200 is prepared by the LPCVD method;

[0080] Preferably, the preparation process of the P-Poly layer and the BSG layer 400 includes: depositing an i-PolySi layer on the first tunneling oxide layer 200, and then performing boron diffusion to form the BSG layer 400, and at the same time preparing the i-PolySi layer into a P-Poly layer;

[0081] The thickness of the BSG layer is 30 to 80 nm, for example, it can be 30 nm, 50 nm, 80 nm, etc.;

[0082] Preferably, the i-PolySi layer is prepared by LPCVD method;

[0083] Preferably, the thickness of the i-PolySi layer is 100 to 300 nm, the deposition temperature is 500 to 650 °C, and the deposition time is 15 to 30 min;

[0084] Among them, "100 to 300 nm" can be, for example, 100 nm, 200 nm, 300 nm, etc.;

[0085] "500 to 650 °C" can be, for example, 500 °C, 550 °C, 600 °C, 650 °C, etc.;

[0086] "15 to 30 min" can be, for example, 15 min, 20 min, 25 min, 30 min, etc.

[0087] Preferably, the boron diffusion process includes: introducing a mixed gas of BCl3, O2 and N2 to deposit the BSG layer 400, the flow rate of BCl3 is 200 - 400 sccm, the flow rate of O2 is 700 - 1000 sccm, the flow rate of N2 is 2500 - 3000 sccm, the deposition temperature is 800 - 1000 °C, the deposition time is 1 - 2 h, and the sheet resistance is 100 - 200 Ω.

[0088] Among them, "200 - 400 sccm" can be, for example, 200 sccm, 300 sccm, 400 sccm, etc.;

[0089] "700 - 1000 sccm" can be, for example, 700 sccm, 800 sccm, 900 sccm, 1000 sccm, etc.;

[0090] "2500 - 3000 sccm" can be, for example, 2500 sccm, 2600 sccm, 2700 sccm, 2800 sccm, 2900 sccm, 3000 sccm, etc.;

[0091] "800 - 1000 °C" can be, for example, 800 °C, 900 °C, 1000 °C, etc.;

[0092] "1 - 2 h" can be, for example, 1 h, 1.5 h, 2 h, etc.;

[0093] "100 - 200 Ω" can be, for example, 100 Ω, 150 Ω, 200 Ω, etc.

[0094] In some preferred embodiments, in step (b), the depth of the patterned groove is 30 to 80 nm, and the width of the patterned groove is 400 to 600 μm;

[0095] Among them, "30 to 80 nm" can be, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc.;

[0096] "400 to 600 μm" can be, for example, 400 μm, 500 μm, 600 μm, etc.

[0097] Preferably, the first patterning is performed by laser;

[0098] Preferably, the P-Poly layer, the first tunneling oxide layer 200 and a part of the silicon substrate 100 in the patterned groove region are removed by a trench polishing method, and the depth of the patterned groove is increased to 2 to 3 μm.

[0099] In some preferred embodiments, in step (c), the second tunneling oxide layer 500, the doped polysilicon layer and the PSG layer 700 are prepared by PECVD. Among them, the doped polysilicon layer includes an N-Poly layer;

[0100] Preferably, the thickness of the second tunneling oxide layer 500 is 0.8 to 2.0 nm, the deposition temperature is 300 to 350 °C, the deposition time is 80 to 150 s, the N2O flow rate is 5 - 10 slm, and the power of the PECVD equipment is 6 - 9 kw;

[0101] Among them, "0.8 to 2.0 nm" can be, for example, 0.8 nm, 1.0 nm, 1.5 nm, 2.0 nm, etc.

[0102] Preferably, a mixed gas of SiH4, H2 and PH3 is introduced into the PECVD equipment to prepare the N-Poly layer, and the flow rate ratio of SiH4, H2 and PH3 is 1:(1 - 3):(0.2 - 0.5);

[0103] Among them, "1 - 3" can be, for example, 1, 2, 3, etc.;

[0104] "0.2 - 0.5" can be, for example, 0.2, 0.3, 0.4, 0.5, etc.

[0105] Preferably, a mixed gas of SiH4 and N2O is introduced into the PECVD equipment to form the PSG layer 700, and the flow rate ratio of SiH4 and N2O is 1:(4 - 5);

[0106] Among them, "4 - 5" can be, for example, 4, 4.5, 5, etc.

[0107] Preferably, during the preparation of the N-Poly layer and the PSG layer 700, the equipment power is 12 - 15 kW, and the pressure inside the furnace tube is 2 - 5 torr;

[0108] Among them, "12 - 15 kW" can be, for example, 12 kW, 13 kW, 14 kW, 15 kW, etc.;

[0109] "2 - 5 torr" can be, for example, 2 torr, 3 torr, 4 torr, 5 torr, etc.

[0110] Preferably, after depositing the PSG layer 700, annealing is carried out. The annealing temperature is 800 - 950 °C, and the annealing time is 0.5 - 2 h.

[0111] Among them, "800 - 950 °C" can be, for example, 800 °C, 850 °C, 900 °C, 950 °C, etc.;

[0112] "0.5 - 2 h" can be, for example, 0.5 h, 1 h, 1.5 h, 2 h, etc.

[0113] In some preferred embodiments, in step (d), the PSG layer 700 in the preset positive electrode region and the Gap region is removed by laser.

[0114] In some preferred embodiments, in step (e), the N-Poly layer and the second tunneling oxide layer 500 in the preset positive electrode region and the N-Poly layer and the second tunneling oxide layer 500 in the Gap region are removed by the trough alkaline texturing method, and then the BSG layer 400 in the preset positive electrode region and the PSG layer 700 in the preset negative electrode region are removed by the trough acidic texturing method.

[0115] In some preferred embodiments, the passivation treatment includes: depositing an alumina passivation layer 800 on both sides of the silicon substrate 100, depositing a silicon nitride passivation layer 900 on the back, and sequentially depositing a silicon nitride passivation layer 900 and a silicon oxide passivation layer 1000 on the front.

[0116] In the present invention, the i-Poly layer can also be written as the i-PolySi layer, and its Chinese name is the intrinsic polysilicon layer; the P-Poly layer can also be written as the P-PolySi layer 300, and its Chinese name is the p-type polysilicon layer, and the N-Poly layer can also be written as the N-PolySi layer 600, and its Chinese name is the n-type polysilicon layer.

[0117] In an alternative embodiment of the present invention, more preferably, the preparation method of the TBC battery specifically includes the following steps:

[0118] (1) Deposit on the back of the double-sided polished N-type crystalline silicon substrate 100 by LPCVD method to form a first tunneling oxide layer 200 and an i-PolySi layer in sequence; the thickness of the tunneling oxide layer is 0.8 - 2.0 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 6 - 20 min; the thickness of PolySi is 100 - 300 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 15 - 30 min;

[0119] (2) As Figure 1 shown, the cell processed in step (1) is subjected to boron diffusion to form a BSG layer, and at the same time, the i-PolySi layer is prepared into a P-Poly layer. A mixed gas of BCl3, O2, and N2 is introduced, the flow rate of BCl3 is 200 - 400 sccm, the flow rate of O2 is 700 - 1000 sccm, the flow rate of N2 is 2500 - 3000 sccm, the deposition temperature is 800 - 1000 °C, the deposition time is 1 - 2 h, and the sheet resistance is 100 - 200 Ω;

[0120] (3) The N-type crystalline silicon substrate 100 obtained in step (2) is successively subjected to primary patterning, removing BSG + alkali polishing, PECVD, annealing, secondary patterning, removing PSG + texturing, passivation treatment, and printing electrodes to obtain a TBC cell;

[0121] Among them, as Figure 2 shown, the specific steps of primary patterning are: removing a part of the BSG layer 400 on the back of the N-type crystalline silicon substrate 100 obtained in step (2) (i.e., the BSG layer 400 in the subsequent Gap area and N area) to form a patterned groove. The above removal step is carried out by picosecond laser. The depth of the patterned groove is 30 - 80 nm (i.e., the thickness of the BSG layer deposited in step 2), and the width of the patterned groove is 400 - 600 μm;

[0122] (4) As Figure 3 shown, the specific steps of removing the BSG layer 400 + alkali polishing are: removing the BSG overplating on the front by chain wet method, removing the overplated P-PolySi layer 300 and the first tunneling oxide layer 200 on the front by trough polishing, and the P-PolySi layer 300, the first tunneling oxide layer 200, and a part of the silicon substrate 100 in the back patterned groove area. The depth of the patterned groove is increased to 2 - 3 μm;

[0123] (5) As Figure 4As shown in the figure, the steps of the PECVD are specifically as follows: Deposition is carried out on the back of the silicon substrate 100 by the PECVD method to form a second tunneling oxide layer 500, an N-PolySi layer 600, and a PSG layer 700. The thickness of the second tunneling oxide layer 500 is 0.8 - 2.0 nm, the deposition temperature is 300 - 350 °C, the deposition time is 80 - 150 s, the N2O flow rate is 5 - 10 slm, and the power is 6 - 9 kw; The steps of depositing the N-PolySi layer 600 + PSG layer 700 are specifically as follows: A mixed gas of SiH4, H2, and PH3 is introduced to form the N-PolySi layer 600, and the flow rate ratio of SiH4, H2, and PH3 is 1:(1 - 3):(0.2 - 0.5); Subsequently, a mixed gas of SiH4 and N2O is introduced to form the PSG layer 700, and the flow rate ratio of SiH4 and N2O is 1:(4 - 5). The power for depositing the N-PolySi layer 600 and the PSG layer 700 is 12 - 15 kW, and the pressure in the furnace tube is 2 - 5 torr. Among them, a four-step deposition combined with an intermittent annealing process is used for depositing the N-PolySi layer 600. The deposition temperature of the first step is 500 - 550 °C, the time is 100 - 200 s, the annealing temperature of the first time is 450 - 500 °C, and the time is 10 - 20 min; The deposition temperature of the second step is 450 - 500 °C, the time is 100 - 200 s, the annealing temperature of the second time is 400 - 450 °C, and the time is 10 - 20 min; The deposition temperature of the third step is 400 - 450 °C, the time is 400 - 600 s, the annealing temperature of the third time is 350 - 400 °C, and the time is 30 - 40 min; The deposition temperature of the fourth step is 350 - 400 °C, the time is 600 - 800 s, the annealing temperature of the fourth time is 300 - 350 °C, and the time is 50 - 60 min;

[0124] (6) After depositing the PSG layer 700, annealing is carried out. The annealing temperature is 800 - 950 °C, and the annealing time is 0.5 - 2 h;

[0125] (7) As Figure 5 shown in the figure, the steps of the secondary patterning are specifically as follows: The PSG layer 700 in the preset positive region and the Gap region is removed by laser (that is, the PSG layer 700 on the back of the N region of the silicon substrate 100 is retained, and the PSG layer 700 in the remaining regions is removed); It is preferred to use picosecond laser for the above removal process;

[0126] (8) As Figure 6As shown in the figure, the steps of removing PSG + texturing are specifically as follows: The N-PolySi layer 600 and the second tunneling oxide layer 500 on the back N region are retained, the P-PolySi layer 300 and the first tunneling oxide layer 200 on the back P region are retained, and the rest of the front and back regions are textured. Specifically: First, the PSG layer 700 plated around the front is removed by the chain pickling method, and then the second tunneling oxide layer 500, the N-PolySi layer 600 plated around the front, the N-PolySi layer 600, the second tunneling oxide layer 500 in the back P region, and the N-PolySi layer 600, the second tunneling oxide layer 500 in the Gap region are removed by the tank alkaline texturing method. After that, the BSG layer 400 in the back P region and the PSG layer 700 in the N region are removed by the tank acid texturing;

[0127] (9) As Figure 7 shown, the steps of the passivation treatment sequentially include: depositing an alumina layer 800 on both sides of the silicon substrate 100, depositing a silicon nitride passivation layer 900 on the back, depositing a silicon nitride passivation layer 900 and a silicon oxide passivation layer 1000 on the front;

[0128] (10) Then, the P region electrode 1100 and the N region electrode 1200 are printed to obtain the TBC cell.

[0129] The present invention will be described below by way of examples. Unless otherwise specified, the materials in the examples are prepared according to existing methods or directly purchased from the market.

[0130] Example 1

[0131] This example provides a method for preparing a doped polysilicon layer, including the following steps:

[0132] When depositing the doped polysilicon layer N-PolySi layer, a four-step deposition combined with an intermittent annealing process is used. The deposition temperature of the first step is 525 °C, the time is 150 s, the first annealing temperature is 475 °C, and the time is 15 min; the deposition temperature of the second step is 475 °C, the time is 150 s, the second annealing temperature is 425 °C, and the time is 15 min; the deposition temperature of the third step is 425 °C, the time is 500 s, the third annealing temperature is 375 °C, and the time is 35 min; the deposition temperature of the fourth step is 375 °C, the time is 700 s, the fourth annealing temperature is 325 °C, and the time is 55 min;

[0133] Among them, the gas flow rate used in each step of deposition is: A mixed gas of SiH4, H2, and PH3 is introduced into the PECVD equipment to prepare the doped polysilicon layer, and the flow rate ratio of SiH4, H2, and PH3 is 1:2:0.4.

[0134] Example 2

[0135] This embodiment provides a method for preparing a doped polysilicon layer, comprising the following steps:

[0136] When depositing the doped polysilicon layer N-PolySi layer, a four-step deposition combined with an intermittent annealing process is adopted. The deposition temperature in the first step is 500 °C, the time is 200 s, the first annealing temperature is 450 °C, and the time is 20 min; the deposition temperature in the second step is 450 °C, the time is 200 s, the second annealing temperature is 400 °C, and the time is 20 min; the deposition temperature in the third step is 400 °C, the time is 600 s, the third annealing temperature is 350 °C, and the time is 40 min; the deposition temperature in the fourth step is 350 °C, the time is 800 s, the fourth annealing temperature is 300 °C, and the time is 60 min;

[0137] Among them, the gas flow rate used in each deposition step is as follows: A mixed gas of SiH4, H2, and PH3 is introduced into the PECVD equipment to prepare the doped polysilicon layer, and the flow rate ratio of SiH4, H2, and PH3 is 1:1:0.5.

[0138] Example 3

[0139] This embodiment provides a method for preparing a doped polysilicon layer, comprising the following steps:

[0140] When depositing the doped polysilicon layer N-PolySi layer, a four-step deposition combined with an intermittent annealing process is adopted. The deposition temperature in the first step is 550 °C, the time is 100 s, the first annealing temperature is 500 °C, and the time is 10 min; the deposition temperature in the second step is 500 °C, the time is 100 s, the second annealing temperature is 450 °C, and the time is 10 min; the deposition temperature in the third step is 450 °C, the time is 400 s, the third annealing temperature is 400 °C, and the time is 30 min; the deposition temperature in the fourth step is 400 °C, the time is 600 s, the fourth annealing temperature is 350 °C, and the time is 50 min;

[0141] Among them, the gas flow rate used in each deposition step is as follows: A mixed gas of SiH4, H2, and PH3 is introduced into the PECVD equipment to prepare the doped polysilicon layer, and the flow rate ratio of SiH4, H2, and PH3 is 1:3:0.2.

[0142] Example 4

[0143] This embodiment provides a method for preparing a doped polysilicon layer, comprising the following steps:

[0144] When depositing the doped polysilicon layer (N-PolySi layer), a two-step deposition combined with intermittent annealing process is adopted. The deposition temperature in the first step is 525 °C, and the time is 400 s. The annealing temperature in the first annealing is 475 °C, and the time is 40 min. The deposition temperature in the second step is 475 °C, and the time is 600 s. The annealing temperature in the second annealing is 425 °C, and the time is 60 min.

[0145] The gas flow rate used in each deposition step is the same as that in Example 1.

[0146] Example 5

[0147] This example provides a method for preparing a doped polysilicon layer, which includes the following steps:

[0148] When depositing the doped polysilicon layer (N-PolySi layer), a three-step deposition combined with intermittent annealing process is adopted. The deposition temperature in the first step is 525 °C, and the time is 200 s. The annealing temperature in the first annealing is 475 °C, and the time is 20 min. The deposition temperature in the second step is 475 °C, and the time is 300 s. The annealing temperature in the second annealing is 425 °C, and the time is 30 min. The deposition temperature in the third step is 425 °C, and the time is 500 s. The annealing temperature in the third annealing is 375 °C, and the time is 50 min.

[0149] The gas flow rate used in each deposition step is the same as that in Example 1.

[0150] Example 6

[0151] This example provides a method for preparing a doped polysilicon layer, which includes the following steps:

[0152] When depositing the doped polysilicon layer (N-PolySi layer), a five-step deposition combined with intermittent annealing process is adopted. The deposition temperature in the first step is 525 °C, and the time is 100 s. The annealing temperature in the first annealing is 475 °C, and the time is 10 min. The deposition temperature in the second step is 475 °C, and the time is 100 s. The annealing temperature in the second annealing is 425 °C, and the time is 10 min. The deposition temperature in the third step is 425 °C, and the time is 200 s. The annealing temperature in the third annealing is 375 °C, and the time is 20 min. The deposition temperature in the fourth step is 375 °C, and the time is 300 s. The annealing temperature in the fourth annealing is 325 °C, and the time is 30 min. The deposition temperature in the fifth step is 325 °C, and the time is 400 s. The annealing temperature in the fifth annealing is 275 °C, and the time is 40 min.

[0153] The gas flow rate used in each deposition step is the same as that in Example 1.

[0154] Example 7

[0155] This example provides a method for preparing a doped polysilicon layer. The difference from Example 1 is:

[0156] The deposition temperature in the first step is 600 °C, the time is 150 s, the first annealing temperature is 550 °C, and the time is 15 min; the deposition temperature in the second step is 550 °C, the time is 150 s, the second annealing temperature is 500 °C, and the time is 15 min; the deposition temperature in the third step is 500 °C, the time is 500 s, the third annealing temperature is 450 °C, and the time is 35 min; the deposition temperature in the fourth step is 450 °C, the time is 700 s, the fourth annealing temperature is 400 °C, and the time is 55 min;

[0157] The remaining gas flow parameters are the same as those in Example 1.

[0158] Example 8

[0159] This example provides a method for preparing a doped polysilicon layer, which is different from Example 1 in that:

[0160] The deposition temperature in the first step is 450 °C, the time is 150 s, the first annealing temperature is 400 °C, and the time is 15 min; the deposition temperature in the second step is 400 °C, the time is 150 s, the second annealing temperature is 350 °C, and the time is 15 min; the deposition temperature in the third step is 350 °C, the time is 500 s, the third annealing temperature is 300 °C, and the time is 35 min; the deposition temperature in the fourth step is 300 °C, the time is 700 s, the fourth annealing temperature is 250 °C, and the time is 55 min;

[0161] The remaining gas flow parameters are the same as those in Example 1.

[0162] Examples 9 - 16

[0163] Examples 9 - 16 provide a method for preparing a TBC battery, including the following steps:

[0164] (1) Use the LPCVD method to deposit on the back of a double-sided polished N-type crystalline silicon substrate to form a first tunneling oxide layer and an i-PolySi layer in sequence; the thickness of the tunneling oxide layer is 1.5 nm, the deposition temperature is 600 °C, and the deposition time is 13 min; the thickness of PolySi is 250 nm, the deposition temperature is 600 °C, and the deposition time is 18 min;

[0165] (2) Boron diffusion is carried out on the battery wafer processed in step (1) to form a BSG layer, and at the same time, the i-PolySi layer is prepared into a P-Poly layer. A mixed gas of BCl3, O2, and N2 is introduced, the flow rate of BCl3 is 300 sccm, the flow rate of O2 is 850 sccm, the flow rate of N2 is 2750 sccm, the deposition temperature is 900 °C, the deposition time is 1.5 h, and the sheet resistance is 160 Ω;

[0166] (3) Perform patterning, BSG removal + alkaline polishing, PECVD, annealing, secondary patterning, PSG removal + texturing, passivation treatment, and printing electrodes on the N-type crystalline silicon substrate obtained in step (2) in sequence to obtain a TBC cell;

[0167] Among them, the specific steps of the primary patterning are as follows: Remove a part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (i.e., the BSG layers in the subsequent Gap region and N region) to form a patterned groove. Use picosecond laser for the above removal step. The depth of the patterned groove is 50 nm, and the width of the patterned groove is 500 μm;

[0168] (4) The specific steps of BSG layer removal + alkaline polishing are as follows: Remove the BSG overplating on the front side by chain wet method (HF), remove the P-PolySi layer and the first tunneling oxide layer overplated on the front side by tank polishing (NaOH), and the P-PolySi layer, the first tunneling oxide layer, and part of the silicon substrate in the back-side patterned groove region. The depth of the patterned groove increases to 2.5 μm;

[0169] (5) The specific steps of the PECVD are as follows: Deposit on the back of the silicon substrate by PECVD method to form a second tunneling oxide layer, an N-PolySi layer, and a PSG layer.

[0170] Among them, in Examples 9 - 16, the N-PolySi layers prepared in Examples 1 - 8 are respectively used;

[0171] The thickness of the second tunneling oxide layer is 1.5 nm, the deposition temperature is 325 °C, the deposition time is 115 s, the N2O flow rate is 7.5 slm, and the power is 7.5 kw. The specific steps of depositing the N-PolySi layer + PSG layer are as follows: Introduce a mixed gas of SiH4, H2, and PH3 to form an N-PolySi layer; then introduce a mixed gas of SiH4 and N2O to form a PSG layer (with a thickness of 60 nm). The flow rate ratio of SiH4 to N2O is 1:4.5. The power for depositing the N-PolySi layer and the PSG layer is 13 kW, and the pressure in the furnace tube is 3.5 torr;

[0172] (6) After depositing the PSG layer, perform annealing. The annealing temperature is 900 °C, and the annealing time is 1.2 h;

[0173] (7) The specific steps of the secondary patterning are as follows: Use laser to remove the PSG layer in the preset positive electrode region and Gap region (i.e., retain the PSG layer in the N region on the back of the silicon substrate and remove the PSG layer in the remaining regions); use picosecond laser for the above removal process;

[0174] (8) The specific steps of removing PSG+ and texturing are as follows: retain the N-PolySi layer and the second tunneling oxide layer in the back N region, retain the P-PolySi layer and the first tunneling oxide layer in the back P region, and texture the remaining front and back regions. Specifically: first, use the chain pickling method (HF) to remove the PSG layer around the front surface, and then use the tank alkaline texturing method (NaOH) to remove the second tunneling oxide layer, N-PolySi layer on the front surface and the N-PolySi layer, second tunneling oxide layer in the back P region, and the N-PolySi layer, second tunneling oxide layer in the Gap region. After that, use the tank pickling method (HF) to remove the BSG layer in the back P region and the PSG layer in the N region;

[0175] (9) The passivation treatment steps sequentially include: depositing an alumina passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front;

[0176] (10) Then print the P region electrode and the N region electrode to obtain a TBC cell.

[0177] Example 17

[0178] This example provides a method for preparing a TBC cell, including the following steps:

[0179] (1) Use the LPCVD method to deposit on the back of a double-sided polished N-type crystalline silicon substrate, sequentially forming a first tunneling oxide layer and an i-PolySi layer; the thickness of the tunneling oxide layer is 0.8 nm, the deposition temperature is 500 °C, and the deposition time is 20 min; the thickness of the PolySi is 100 nm, the deposition temperature is 500 °C, and the deposition time is 30 min;

[0180] (2) Perform boron diffusion on the cell wafer processed in step (1) to form a BSG layer, and at the same time prepare the i-PolySi layer into a P-Poly layer. Introduce a mixed gas of BCl3, O2, and N2, the flow rate of BCl3 is 200 sccm, the flow rate of O2 is 700 sccm, the flow rate of N2 is 2500 sccm, the deposition temperature is 800 °C, the deposition time is 2 h, and the sheet resistance is 100 Ω;

[0181] (3) Perform patterning once, remove BSG+ and alkaline polishing, PECVD, annealing, patterning twice, remove PSG+ and texturing, passivation treatment, and print electrodes on the N-type crystalline silicon substrate obtained in step (2) to obtain a TBC cell;

[0182] Among them, the specific steps of the first patterning are as follows: Remove a part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (i.e., the BSG layer in the subsequent Gap region and N region) to form a patterned groove. The above removal step is carried out by using picosecond laser. The depth of the patterned groove is 30 nm, and the width of the patterned groove is 400 μm.

[0183] (4) The steps of removing the BSG layer + alkali polishing are specifically as follows: Chain wet etching (HF) is used to remove the BSG overplating on the front side, and trough polishing (NaOH) is used to remove the P-PolySi layer and the first tunneling oxide layer overplated on the front side, as well as the P-PolySi layer, the first tunneling oxide layer and part of the silicon substrate in the patterned groove region on the back side. The depth of the patterned groove is increased to 2 μm.

[0184] (5) The specific steps of the PECVD are as follows: Deposition is carried out on the back of the silicon substrate by using the PECVD method to form a second tunneling oxide layer, an N-PolySi layer and a PSG layer.

[0185] Among them, in Example 17, the N-PolySi layer prepared in Example 1 is used.

[0186] The thickness of the second tunneling oxide layer is 0.8 nm, the deposition temperature is 300 °C, the deposition time is 150 s, the N2O flow rate is 5 slm, and the power is 6 kw. The specific steps of depositing the N-PolySi layer + PSG layer are as follows: A mixed gas of SiH4, H2, and PH3 is introduced to form an N-PolySi layer; Subsequently, a mixed gas of SiH4 and N2O is introduced to form a PSG layer (with a thickness of 60 nm). The flow rate ratio of SiH4 to N2O is 1:4. The power for depositing the N-PolySi layer and the PSG layer is 12 kW, and the pressure in the furnace tube is 5 torr.

[0187] (6) After depositing the PSG layer, annealing is carried out. The annealing temperature is 800 °C, and the annealing time is 2 h.

[0188] (7) The specific steps of the second patterning are as follows: Use laser to remove the PSG layer in the preset positive electrode region and Gap region (i.e., retain the PSG layer in the N region on the back of the silicon substrate and remove the PSG layer in the remaining regions); The above removal process is carried out by using picosecond laser.

[0189] (8) The steps of removing PSG+ and texturing are as follows: retain the N-PolySi layer and the second tunneling oxide layer in the back N region, retain the P-PolySi layer and the first tunneling oxide layer in the back P region, and texture the remaining front and back regions. Specifically: first, use the chain pickling method (HF) to remove the deposited PSG layer on the front, and then use the tank alkali texturing method (NaOH) to remove the second tunneling oxide layer, N-PolySi layer on the front, and the N-PolySi layer, second tunneling oxide layer in the back P region, and the N-PolySi layer, second tunneling oxide layer in the Gap region. After that, use the tank pickling method (HF) to remove the BSG layer in the back P region and the PSG layer in the N region;

[0190] (9) The steps of passivation treatment include: depositing an aluminum oxide passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front;

[0191] (10) Then print the P-region electrode and the N-region electrode to obtain a TBC cell.

[0192] Example 18

[0193] This example provides a method for preparing a TBC cell, including the following steps:

[0194] (1) Use the LPCVD method to deposit on the back of a double-sided polished N-type crystalline silicon substrate, successively forming a first tunneling oxide layer and an i-PolySi layer; the thickness of the tunneling oxide layer is 2.0 nm, the deposition temperature is 650 °C, and the deposition time is 6 min; the thickness of PolySi is 300 nm, the deposition temperature is 650 °C, and the deposition time is 15 min;

[0195] (2) Perform boron diffusion on the cell wafer processed in step (1) to form a BSG layer, and at the same time prepare the i-PolySi layer into a P-Poly layer. Introduce a mixed gas of BCl3, O2, and N2, the flow rate of BCl3 is 400 sccm, the flow rate of O2 is 1000 sccm, the flow rate of N2 is 3000 sccm, the deposition temperature is 1000 °C, the deposition time is 1 h, and the sheet resistance is 200 Ω;

[0196] (3) Perform patterning, removing BSG+ and alkali polishing, PECVD, annealing, secondary patterning, removing PSG+ and texturing, passivation treatment, and printing electrodes on the N-type crystalline silicon substrate obtained in step (2) to obtain a TBC cell;

[0197] Among them, the steps of the first patterning are specifically as follows: removing a part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (i.e., the BSG layers in the subsequent Gap region and N region) to form a patterned groove. The above-mentioned removal step is carried out by using picosecond laser. The depth of the patterned groove is 80 nm, and the width of the patterned groove is 600 μm;

[0198] (4) The step of removing the BSG layer + is specifically as follows: removing the BSG overplating on the front by chain wet etching (HF), removing the overplated P-PolySi layer and the first tunneling oxide layer on the front by trough polishing (NaOH), and removing the P-PolySi layer, the first tunneling oxide layer and a part of the silicon substrate in the patterned groove area on the back. The depth of the patterned groove is increased to 3 μm;

[0199] (5) The step of the PECVD is specifically as follows: depositing on the back of the silicon substrate by the PECVD method to form a second tunneling oxide layer, an N-PolySi layer and a PSG layer.

[0200] Among them, in Example 18, the N-PolySi layer prepared in Example 1 is used;

[0201] The thickness of the second tunneling oxide layer is 2.0 nm, the deposition temperature is 350 °C, the deposition time is 80 s, the N2O flow rate is 10 slm, and the power is 9 kw; the steps of depositing the N-PolySi layer + PSG layer are specifically as follows: introducing a mixed gas of SiH4, H2, and PH3 to form an N-PolySi layer; then introducing a mixed gas of SiH4 and N2O to form a PSG layer (with a thickness of 60 nm). The flow rate ratio of SiH4 to N2O is 1:5. The power for depositing the N-PolySi layer and the PSG layer is 15 kW, and the pressure in the furnace tube is 2 torr.

[0202] (6) After depositing the PSG layer, annealing is carried out. The annealing temperature is 950 °C, and the annealing time is 0.5 h;

[0203] (7) The steps of the second patterning are specifically as follows: using laser to remove the PSG layer in the preset positive electrode region and Gap region (i.e., retaining the PSG layer in the N region on the back of the silicon substrate and removing the PSG layer in the remaining regions); preferably, the above-mentioned removal process is carried out by using picosecond laser;

[0204] (8) The specific steps of removing PSG + texturing are as follows: retain the N-PolySi layer and the second tunneling oxide layer in the back N region, retain the P-PolySi layer and the first tunneling oxide layer in the back P region, and texture the remaining front and back regions. Specifically: first, use the chain pickling method (HF) to remove the plated PSG layer on the front, and then use the trough alkaline texturing method (NaOH) to remove the second tunneling oxide layer, N-PolySi layer plated on the front, and the N-PolySi layer, second tunneling oxide layer in the back P region, and the N-PolySi layer, second tunneling oxide layer in the Gap region. After that, use the trough pickling method (HF) to remove the BSG layer in the back P region and the PSG layer in the N region;

[0205] (9) The steps of passivation treatment include, in sequence: depositing an alumina passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front;

[0206] (10) Then print the P-region electrode and the N-region electrode to obtain a TBC cell.

[0207] Comparative Example 1

[0208] This comparative example provides a method for preparing a doped polysilicon layer, including the following steps:

[0209] When depositing the doped polysilicon layer N-PolySi layer, a four-step deposition combined with intermittent annealing process is adopted. The deposition temperature of the first step is 375 °C, the time is 700 s, the first annealing temperature is 325 °C, and the time is 55 min; the deposition temperature of the second step is 425 °C, the time is 500 s, the second annealing temperature is 375 °C, and the time is 35 min; the deposition temperature of the third step is 475 °C, the time is 150 s, the third annealing temperature is 425 °C, and the time is 15 min; the deposition temperature of the fourth step is 525 °C, the time is 150 s, the fourth annealing temperature is 475 °C, and the time is 15 min;

[0210] The gas flow rate used in each deposition step is the same as that in Example 1.

[0211] Comparative Example 2

[0212] This comparative example provides a method for preparing a doped polysilicon layer, including the following steps:

[0213] When depositing the doped polysilicon layer (N-PolySi layer), a four-step deposition process combined with intermittent annealing is adopted. The deposition temperature in the first step is 525 °C, and the time is 150 s. The first annealing temperature is 575 °C, and the time is 15 min. The deposition temperature in the second step is 475 °C, and the time is 150 s. The second annealing temperature is 525 °C, and the time is 15 min. The deposition temperature in the third step is 425 °C, and the time is 500 s. The third annealing temperature is 475 °C, and the time is 35 min. The deposition temperature in the fourth step is 375 °C, and the time is 700 s. The fourth annealing temperature is 425 °C, and the time is 55 min.

[0214] The gas flow rate used for each deposition step is the same as that in Example 1.

[0215] Comparative Example 3

[0216] This comparative example provides a method for preparing a doped polysilicon layer, including the following steps:

[0217] When depositing the doped polysilicon layer (N-PolySi layer), a one-step deposition process combined with intermittent annealing is adopted. The deposition temperature is 550 °C, and the time is 800 s. The annealing temperature is 350 °C, and the time is 60 min.

[0218] The gas flow rate used for each deposition step is the same as that in Example 1.

[0219] Comparative Examples 4 - 6

[0220] Comparative Examples 4 - 6 provide a method for preparing a TBC cell. The N-PolySi layers prepared in Comparative Examples 1 - 3 are respectively used, and the remaining steps are the same as those in Example 9.

[0221] Test Example

[0222] Test samples: The TBC cells prepared in Examples 9 - 18 and the TBC cells prepared in Comparative Examples 4 - 6 are used as samples.

[0223] Test method:

[0224] The sheet resistance is measured by a four-probe method using a 5-point measurement method (i.e., measuring at a total of 5 positions at the four corners and the center of the cell). The sheet resistance values at 5 points of the test sample are measured, and the sheet resistance uniformity result data is calculated through the formula: (maximum value - minimum value) / (2 * average sheet resistance value). The smaller the sheet resistance uniformity value, the higher the in-sheet uniformity.

[0225] The conversion efficiency is measured by a Halm test system.

[0226] The test results are shown in Table 1.

[0227] Table 1

[0228]

[0229]

[0230] As can be seen from Table 1, through Examples 9 and Examples 12 - 14, Comparative Examples 4 - 6, it can be known that the product sheet resistance uniformity obtained by the four-step deposition combined with the intermittent annealing process in Example 9 is higher, and the conversion efficiency is higher. At the same time, through Examples 9 and Examples 15 - 16, it can be known that the product sheet resistance uniformity and conversion efficiency within the specific parameter range of the present invention are better.

[0231] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a doped polysilicon layer, characterized in that, It includes the following steps: Deposit a doped polysilicon layer on the tunneling oxide layer and then anneal it; Among them, taking the deposition of the doped polysilicon layer and annealing as one process, the process of preparing the doped polysilicon layer includes at least two such processes. The annealing temperature in each process is lower than the deposition temperature, and the deposition temperature in adjacent processes decreases.

2. The method for preparing a doped polysilicon layer according to claim 1, wherein, The process of preparing the doped polysilicon layer includes four such processes, and the four processes include the first deposition, the first annealing, the second deposition, the second annealing, the third deposition, the third annealing, the fourth deposition, and the fourth annealing; Preferably, the doped polysilicon layer is deposited by PECVD method; Preferably, the temperature of the first deposition is 500 - 550 °C, the time is 100 - 200 s, the temperature of the first annealing is 450 - 500 °C, and the time is 10 - 20 min; Preferably, the temperature of the second deposition is 450 - 500 °C, the time is 100 - 200 s, the temperature of the second annealing is 400 - 450 °C, and the time is 10 - 20 min; Preferably, the temperature of the third deposition is 400 - 450 °C, the time is 400 - 600 s, the temperature of the third annealing is 350 - 400 °C, and the time is 30 - 40 min; Preferably, the temperature of the fourth deposition is 350 - 400 °C, the time is 600 - 800 s, the temperature of the fourth annealing is 300 - 350 °C, and the time is 50 - 60 min; Preferably, a mixed gas of SiH4, H2, and PH3 is introduced into the PECVD equipment to prepare the doped polysilicon layer, and the flow ratio of SiH4, H2, and PH3 is 1:(1 - 3):(0.2 - 0.5).

3. Application of the method for preparing a doped polysilicon layer as described in claim 1 or 2 in the preparation of a TBC cell.

4. A method for preparing a TBC battery, characterized in that, It includes the following steps: (a) Sequentially prepare a first tunneling oxide layer, a P-Poly layer, and a BSG layer on the back of the silicon substrate; (b) Perform patterning on the back of the silicon substrate once to remove the BSG layer in the preset negative electrode area and the Gap area, form a patterned groove, and then remove the P-Poly layer and the first tunneling oxide layer in the patterned groove area; (c) Sequentially prepare a second tunneling oxide layer, a doped polysilicon layer prepared by the method for preparing a doped polysilicon layer as described in claim 1 or 2, and a PSG layer on the back of the silicon substrate; (d) Perform patterning on the back of the silicon substrate twice to remove the PSG layer in the preset positive electrode area and the Gap area; (e) Remove the N-Poly layer, the second tunneling oxide layer, and the BSG layer in the preset positive electrode area, and remove the PSG layer in the preset negative electrode area and remove the N-Poly layer and the second tunneling oxide layer in the Gap area; (f) Perform passivation treatment on both sides of the cell wafer, and then print electrodes to prepare a TBC cell.

5. The manufacturing method of the TBC battery according to claim 4, characterized in that, In step (a), the thickness of the first tunneling oxide layer is 0.8 - 2.0 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 6 - 20 min; Preferably, the first tunneling oxide layer is prepared by LPCVD method; Preferably, the preparation process of the P-Poly layer and the BSG layer includes: depositing an i-PolySi layer on the first tunneling oxide layer, followed by boron diffusion to form the BSG layer, and at the same time preparing the i-PolySi layer into the P-Poly layer; Preferably, the thickness of the BSG layer is 30 - 80 nm; Preferably, the i-PolySi layer is prepared by LPCVD method; Preferably, the thickness of the i-PolySi layer is 100 - 300 nm, the deposition temperature is 500 - 650 °C, and the deposition time is 15 - 30 min; Preferably, the boron diffusion process includes: introducing a mixed gas of BCl3, O2 and N2 to deposit the BSG layer, the flow rate of BCl3 is 200 - 400 sccm, the flow rate of O2 is 700 - 1000 sccm, the flow rate of N2 is 2500 - 3000 sccm, the deposition temperature is 800 - 1000 °C, the deposition time is 1 - 2 h, and the sheet resistance is 100 - 200 Ω.

6. The preparation method of the TBC battery according to claim 4, characterized in that, In step (b), the depth of the patterned groove is 30 - 80 nm, and the width of the patterned groove is 400 - 600 μm; Preferably, laser is used for the first patterning; Preferably, the P-Poly layer, the first tunneling oxide layer and part of the silicon substrate in the patterned groove area are removed by the trough polishing method, and the depth of the patterned groove is increased to 2 - 3 μm.

7. The manufacturing method of the TBC battery according to claim 4, wherein In step (c), the second tunneling oxide layer, the doped polysilicon layer and the PSG layer are prepared by PECVD method, wherein the doped polysilicon layer includes an N-Poly layer; Preferably, the thickness of the second tunneling oxide layer is 0.8 - 2.0 nm, the deposition temperature is 300 - 350 °C, the deposition time is 80 - 150 s, the N2O flow rate is 5 - 10 slm, and the power is 6 - 9 kw; Preferably, a mixed gas of SiH4 and N2O is introduced into the PECVD equipment to form the PSG layer, and the flow rate ratio of SiH4 to N2O is 1:(4 - 5); Preferably, during the preparation of the N-Poly layer and the PSG layer, the equipment power is 12 - 15 kW, and the pressure in the furnace tube is 2 - 5 torr; Preferably, after the PSG layer is deposited, annealing is carried out, the annealing temperature is 800 - 950 °C, and the annealing time is 0.5 - 2 h.

8. The manufacturing method of the TBC battery according to claim 4, characterized in that, In step (d), the PSG layer in the preset positive electrode area and the Gap area is removed by laser.

9. The preparation method of the TBC battery according to claim 4, characterized in that In step (e), the N-Poly layer and the second tunneling oxide layer in the preset positive electrode area and the N-Poly layer and the second tunneling oxide layer in the Gap area are removed by the trough alkaline texturing method, and then the BSG layer in the preset positive electrode area and the PSG layer in the preset negative electrode area are removed by the trough acidic texturing method.

10. The preparation method of the TBC battery according to claim 4, wherein, The passivation treatment includes: depositing an aluminum oxide passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back, and sequentially depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front.

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