Standard silicon wafer preparation method and calibration method for flatness measurement equipment

Abstract

This invention provides a method for preparing a standard silicon wafer and a method for calibrating a flatness measurement device. The method for preparing the standard silicon wafer includes: providing a substrate; depositing a polycrystalline silicon layer on the surface of the substrate; and, during the deposition of the polycrystalline silicon layer, controlling the deposition temperature and / or the flow rate of the reactive gas to distribute the different sizes of the polycrystalline silicon layer according to a set ratio, thereby ensuring that the surface roughness of the polycrystalline silicon layer is within a target range; wherein the process conditions for depositing the polycrystalline silicon layer include: using a silicon source gas as the reactive gas, a deposition temperature selectable in the range of 800~1080℃, and a silicon source gas flow rate selectable in the range of 5~30 SLM. The preparation method provided by this invention controls the grain size of the polycrystalline silicon layer by controlling the deposition temperature and / or the flow rate of the reactive gas, thus enabling the repeatable and controllable preparation of a standard wafer with specific roughness and excellent uniformity for calibration of a flatness measurement device.

Description

Technical Field

[0001] This invention relates to the field of measurement, and in particular to a method for preparing a standard silicon wafer and a calibration method for a flatness measurement device. Background Technology

[0002] During wafer fabrication, surface roughness needs to be measured. To ensure the accuracy and stability of surface flatness measurement, standard wafers are required, and the measuring equipment needs to be calibrated regularly.

[0003] However, current calibration practices face technical bottlenecks:

[0004] The existing calibration standards are not clean enough, with a large number of particulate contaminants and metallic impurities on their surface. They are only suitable for calibration of contact testing equipment such as atomic force microscopes. However, when using contact testing equipment such as atomic force microscopes for measurement, there are drawbacks such as long measurement time (generally, if only a single 10μm×10μm point in the center is measured, the measurement time is about 15 minutes, while if it is shipped as a product, 21 points need to be measured, and the measurement time is about five hours), small measurement range, and susceptibility to vibration.

[0005] In addition, existing technologies make it difficult to repeatedly and controllably prepare standard wafers with specific roughness and excellent uniformity at the wafer level for use in the calibration of flatness measurement equipment. Summary of the Invention

[0006] The purpose of this invention is to provide a standard silicon wafer preparation method and a calibration method for a flatness measurement device, so as to solve the problems of insufficient cleanliness of standard wafers, narrow applicability, and lack of controllable and uniform specific roughness in existing flatness measurement devices.

[0007] To address the above problems, this invention provides a method for preparing a standard silicon wafer, comprising:

[0008] Provide substrate;

[0009] A polycrystalline silicon layer is deposited on the surface of the substrate. During the deposition of the polycrystalline silicon layer, the deposition temperature and / or the flow rate of the reactive gas are controlled so that the different sizes of the polycrystalline silicon layer are distributed in a set ratio, thereby making the surface roughness of the polycrystalline silicon layer within the target range.

[0010] The process conditions for depositing the polycrystalline silicon layer include: using silicon source gas as the reaction gas, the deposition temperature can be selected in the range of 800~1080℃, and the silicon source gas flow rate can be selected in the range of 5~30SLM.

[0011] Optionally, in the method for preparing the standard silicon wafer, the distribution according to a set ratio includes: the proportion of large-size grains above 300nm is 5% to 40%; and the target range is 0.1 to 2nm.

[0012] Optionally, in the method for preparing the standard silicon wafer, when controlling the deposition temperature and / or the flow rate of the reactive gas to ensure that the surface roughness of the polycrystalline silicon layer is within the target range, the principle that the magnitude of the surface roughness is positively correlated with the magnitude of the deposition temperature and the magnitude of the reactive gas flow rate is followed.

[0013] Optionally, in the method for preparing the standard silicon wafer, the polycrystalline silicon layer is deposited by the pyrolysis reaction of the silicon source gas.

[0014] Optionally, in the method for preparing the standard silicon wafer, the polycrystalline silicon layer is deposited by a reduction reaction of the silicon source gas and hydrogen, wherein the flow rate of the hydrogen is 15~30 SLM.

[0015] Optionally, in the method for preparing the standard silicon wafer, after depositing a polycrystalline silicon layer on the substrate surface, the preparation method further includes:

[0016] The substrate on which the polycrystalline layer is deposited is subjected to thermal annealing to release the stress between the polycrystalline silicon layer and the substrate.

[0017] Optionally, in the method for preparing the standard silicon wafer, the thermal annealing temperature is 1000~1200℃.

[0018] Optionally, in the method for preparing the standard silicon wafer, the thermal annealing process is also performed in the deposition chamber where the polycrystalline silicon layer is deposited, or the thermal annealing process is performed in a rapid thermal processing furnace.

[0019] Optionally, in the method for preparing the standard silicon wafer, when the thermal annealing process is performed in the deposition chamber, the temperature inside the deposition chamber is raised to the thermal annealing temperature and then held at the thermal annealing temperature for 5 to 30 minutes; when the thermal annealing process is performed in the rapid thermal processing furnace, the temperature inside the rapid thermal processing furnace is raised to the thermal annealing temperature and then held at the thermal annealing temperature for 1 to 300 seconds.

[0020] The present invention also provides a calibration method for a flatness measuring device, characterized in that it includes:

[0021] Provide a standard silicon wafer prepared using the preparation method described in any of the preceding claims;

[0022] The surface of the standard silicon wafer is measured using the target measurement device to be calibrated, in order to obtain surface roughness measurement data; and,

[0023] The measurement error of the target measurement device is confirmed based on the measurement data.

[0024] In summary, this invention provides a method for preparing a standard silicon wafer and a method for calibrating a planarity measurement device. The method for preparing the standard silicon wafer includes: providing a substrate; depositing a polycrystalline silicon layer on the surface of the substrate; and, during the deposition of the polycrystalline silicon layer, controlling the deposition temperature and / or the flow rate of the reactive gas to ensure that the different sizes of the grains in the polycrystalline silicon layer are distributed in a set proportion, thereby ensuring that the surface roughness of the polycrystalline silicon layer is within a target range. The process conditions for depositing the polycrystalline silicon layer include: using a silicon source gas as the reactive gas; a deposition temperature selectable range of 800~1080℃; and a silicon source gas flow rate selectable range of 5~30 SLM. The preparation method provided by this invention controls the grain size of the polycrystalline silicon layer by controlling the deposition temperature and / or the flow rate of the reactive gas, thus enabling the repeatable and controllable preparation of standard wafers with specific roughness and excellent uniformity for calibration of planarity measurement devices. Attached Figure Description

[0025] Figure 1 A flowchart illustrating a method for preparing a standard silicon wafer according to an embodiment of the present invention;

[0026] Figure 2 The image shows the scanning electron microscope measurement results of three silicon wafers in Example 1 of this embodiment of the invention;

[0027] Figure 3 This is a diagram showing the size distribution of polycrystalline silicon grains on the surfaces of three silicon wafers in Example 1 of this embodiment of the invention;

[0028] Figure 4 The image shows the atomic force microscope measurement results of three silicon wafers in Example 1 of this embodiment of the invention.

[0029] Figure 5 This is a comparative schematic diagram of the root mean square roughness of three silicon wafer surfaces in Example 1 of the present invention;

[0030] Figure 6 The image shows the scanning electron microscope measurement results of three silicon wafers in Example 2 of this embodiment of the invention;

[0031] Figure 7 This is a diagram showing the size distribution of polycrystalline silicon grains on the surfaces of three silicon wafers in Example 2 of this embodiment of the invention.

[0032] Figure 8 The image shows the atomic force microscope measurement results of three silicon wafers in Example 2 of this embodiment of the invention;

[0033] Figure 9 This is a comparative schematic diagram of the root mean square roughness of three silicon wafer surfaces in Example 2 of this embodiment of the invention;

[0034] Figure 10 This is a comparative schematic diagram of the proportion of large-size grains in three silicon wafers in Example 3 of the present invention. Detailed Implementation

[0035] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the method for preparing a standard silicon wafer and the calibration method for a flatness measurement device provided by the present invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between various components, elements, steps, etc.

[0036] like Figure 1 As shown, this embodiment of the invention provides a method for preparing a standard silicon wafer, comprising the following steps:

[0037] S1 provides the substrate;

[0038] S2, depositing a polycrystalline silicon layer on the substrate surface, and during the deposition of the polycrystalline silicon layer, controlling the deposition temperature and / or the flow rate of the reactive gas to distribute the different sizes of the polycrystalline silicon layer according to a set ratio, thereby making the surface roughness of the polycrystalline silicon layer within the target range.

[0039] In step S2, the process conditions for depositing the polycrystalline silicon layer include: using silicon source gas as the reaction gas, the deposition temperature can be selected from 800~1080℃, and the silicon source gas flow rate can be selected from 5~30SLM.

[0040] The preparation method provided in this invention controls the proportion of polycrystalline silicon grain size by changing the polycrystalline silicon deposition temperature (800~1080℃) and the reactive gas flow rate (5~30 SLM). This allows the proportion of large-size grains (above 300nm) to vary from 5% to 40%, and the proportion of small-size grains (0~300nm) to vary from 60% to 95%, thus achieving different surface roughnesses on the silicon wafer. For example, a proportion of 5%~10% for large-size grains (above 300nm) can control the surface roughness range to 0.1~0.4nm; a proportion of 10%~30% can control the surface roughness range to 0.4~0.6nm; and further increasing the proportion of large-size grains can ultimately achieve a surface roughness of over 1nm. In this way, standard wafers with excellent uniformity and varying roughness within the range of 0.1~2nm can be repeatedly and controllably prepared, suitable for the calibration of flatness measurement equipment.

[0041] The following provides a more detailed description of each of the above steps.

[0042] In step S1, the substrate can be a single-crystal silicon wafer obtained by the Czochralski method or the zone melting method. Specifically, a single-crystal silicon ingot is first prepared by the Czochralski method or the zone melting method, and then a single-crystal silicon wafer is obtained through mid-to-late stage processes such as rolling, slicing, dicing, chamfering, and grinding. In other embodiments, the substrate can also be a polycrystalline silicon wafer, silicon-on-insulator, or other types of silicon-based wafers.

[0043] In step S2, the deposition of the polycrystalline silicon layer is carried out in a deposition chamber, specifically in an atmospheric pressure chemical vapor deposition (APCVD) chamber, so as to quickly deposit the polycrystalline silicon layer on the substrate surface.

[0044] Before depositing the polycrystalline silicon layer, it is preferable to first raise the temperature inside the deposition chamber to a set loading temperature, then load the substrate into the deposition chamber, and maintain it in an inert protective atmosphere for a set time.

[0045] The set loading temperature can be selected from 300℃ to 600℃, preferably 400℃ to 500℃, the inert protective atmosphere can be, for example, pure argon (Ar), and the set duration can be selected from 0.1 to 30 min, preferably 5 to 15 min.

[0046] Next, the polycrystalline silicon layer is deposited: under an inert protective atmosphere, the heating rate is maintained at 0.01~30℃ / min, preferably 1~10℃ / min, to raise the temperature inside the deposition chamber from the loading temperature to the deposition temperature. Then, the atmosphere inside the deposition chamber is switched to an atmosphere containing silicon source gas. The first heat treatment time is maintained at the deposition temperature and in the atmosphere containing silicon source gas.

[0047] In this embodiment, optionally, the polycrystalline silicon layer can be deposited through a pyrolysis reaction of the silicon source gas or through a reduction reaction of the silicon source gas and hydrogen. When depositing the polycrystalline silicon layer through a reduction reaction, the hydrogen flow rate is 15~30 slm. Optionally, after the temperature in the reaction chamber reaches the deposition temperature, it is maintained for 0.1~20 min, preferably 2~15 min. In addition to the reaction atmosphere, argon or nitrogen can also be used as a protective atmosphere for the deposition of the polycrystalline silicon layer.

[0048] The preparation method provided in this embodiment of the invention is used for the calibration of a planarity measurement device. Different planarity measurement devices have different requirements for the roughness of a standard silicon wafer. Therefore, the deposition temperature and reactive gas flow rate can be reasonably selected within a predetermined range to ensure that the surface roughness of the polycrystalline silicon layer is within the target range.

[0049] In step S2, when controlling the deposition temperature and / or the flow rate of the reactive gas to ensure that the surface roughness of the polysilicon layer is within the target range, the principle that the surface roughness is positively correlated with the deposition temperature and the flow rate of the reactive gas is followed. That is, within a predetermined selectable range, increasing the deposition temperature and / or increasing the flow rate of the reactive gas increases the surface roughness of the polysilicon layer; conversely, decreasing the deposition temperature and / or decreasing the flow rate of the reactive gas decreases the surface roughness of the polysilicon layer.

[0050] For example, when a larger surface roughness is required, a relatively high deposition temperature (e.g., 1000℃~1080℃) and / or a larger reactive gas flow rate (e.g., 20~30 SLM) are used; when a smaller surface roughness is required, a relatively low deposition temperature (e.g., 800℃~900℃) and / or a smaller reactive gas flow rate (e.g., 5~12 SLM) are used. By synergistically adjusting the deposition temperature and reactive gas flow rate, the surface roughness can be adjusted over a wider range to meet the requirements for different surface roughnesses of polycrystalline silicon layers.

[0051] In the specific implementation process, the target roughness range is first set, and then the process windows for deposition temperature and reactive gas flow rate are initially determined based on the aforementioned positive correlation principle. Subsequently, the parameters of both are fine-tuned through a small number of experiments until the actual measured surface roughness falls within the target range. This control method is simple, highly controllable, and can achieve precise control of the surface roughness of polycrystalline silicon layers without introducing additional surface treatment steps.

[0052] The following provides an exemplary description of the method for preparing the standard silicon wafer described in the embodiments of the present invention.

[0053] Example 1

[0054] Three initial state monocrystalline silicon wafers are provided, as shown in Table 1. One of the monocrystalline silicon wafers is not subjected to polycrystalline silicon deposition, while the other two monocrystalline silicon wafers are deposited at 850℃ for different times to obtain silicon wafer 1, silicon wafer 2, and silicon wafer 3.

[0055] Table 1

[0056]

[0057] The grain size of the three silicon wafers was characterized using scanning electron microscopy, and the results were as follows: Figure 2 The scanning electron microscope characterization comparison images shown are from... Figure 2 As can be seen, silicon wafers with a certain roughness can be obtained through polycrystalline silicon deposition.

[0058] Further analysis Figure 2 The measurement results shown can be analyzed using image processing software to obtain the grain size distribution of the polycrystalline silicon surface corresponding to different deposition times, as shown in the figure. Figure 3 , Figure 3 The horizontal axis represents grain size, and the vertical axis represents the percentage. From Figure 3 As can be seen, with the increase of deposition time, there is no significant difference in the proportion of large-sized grains (≥300nm) and small-sized grains (0~300nm).

[0059] Then, atomic force microscopy was used to characterize the surface roughness of each silicon wafer, and the atomic force microscopy measurement results are shown in the figure below. Figure 4 As shown in the figure, the brighter the area, the higher the surface level, and the larger the corresponding value; the darker the area, the lower the surface level, and the smaller the corresponding value.

[0060] Further calculations were performed on the root mean square roughness (AFM RMS) of each silicon wafer surface, yielding the following results: Figure 5 The comparison results are shown below. Root mean square roughness represents the root mean square value of the surface height, and its calculation formula is as follows:

[0061]

[0062] Where n represents the number of sampling points, 𝑍 𝑖 This represents the height of the i-th sampling point.

[0063] from Figure 4 as well as Figure 5 The comparison results show that depositing polycrystalline silicon can change the surface roughness of silicon wafers, but increasing the time does not significantly increase the roughness.

[0064] Example 2

[0065] Silicon wafer 2 and two other initial-state monocrystalline silicon wafers are provided. The two other initial-state monocrystalline silicon wafers are processed as shown in Table 2 to obtain silicon wafer 4 and silicon wafer 5. Compared with silicon wafer 2, silicon wafer 4 and silicon wafer 5 have the same other process conditions, except for the deposition temperature.

[0066] Table 2

[0067]

[0068] The grain size of the three silicon wafers was characterized using scanning electron microscopy, and the results were as follows: Figure 6 The scanning electron microscope characterization comparison images shown are from... Figure 6 As can be seen, with a fixed deposition time, increasing the deposition temperature can increase the grain size of polycrystalline silicon.

[0069] Further analysis Figure 6 The measurement results shown can be analyzed using image processing software to obtain the grain size distribution of the polycrystalline silicon surface corresponding to different deposition times, as shown in the figure. Figure 7 ,from Figure 7 As can be seen, with the increase of deposition temperature, the proportion of large-sized grains (≥300nm) increases significantly.

[0070] Then, atomic force microscopy was used to characterize the surface roughness of each silicon wafer, and the atomic force microscopy measurement results are shown in the figure below. Figure 8 As shown. Further calculation of the root mean square roughness (AFM RMS) of each silicon wafer surface yielded the following results: Figure 9 The comparison results are shown below. Figure 8 and Figure 9 The comparison results show that the higher the polycrystalline silicon deposition temperature, the greater the surface roughness of the silicon wafer.

[0071] Figure 10 This is a comparative diagram showing the proportion of large-size grains on three silicon wafers. Figure 10 In the image, the three values ​​from left to right represent the statistical results for silicon wafer 2, silicon wafer 4, and silicon wafer 5, respectively. Combined with... Figure 10 It can be seen that as the temperature increases, the proportion of large-sized polycrystalline silicon grains increases, which corresponds to a greater surface roughness of the silicon wafer.

[0072] Preferably, after performing step S2, the preparation method provided in this embodiment of the invention further includes the step of:

[0073] S3, perform thermal annealing on the substrate on which the polycrystalline layer is deposited to release the stress between the polycrystalline silicon layer and the substrate.

[0074] Preferably, the heat annealing temperature for the heat annealing treatment is 1000~1200℃.

[0075] Optionally, the thermal annealing process is also performed within the deposition chamber where the polycrystalline silicon layer is deposited, or the thermal annealing process is performed in a rapid thermal processing furnace.

[0076] When the thermal annealing process is performed in the deposition chamber, the temperature inside the deposition chamber is raised to the thermal annealing temperature and held at the thermal annealing temperature for 5 to 30 minutes. The specific steps are as follows: the temperature inside the deposition chamber is raised to 1000 to 1200°C and held at this temperature for 5 to 30 minutes, preferably for 10 to 20 minutes, and then the temperature is lowered. Optionally, the temperature is lowered to 300°C to 600°C, preferably to 400°C to 500°C, and the cooling rate can be selected as 0.01 to 30°C / min, preferably 1 to 10°C / min.

[0077] When the heat annealing process is carried out in the rapid heat treatment furnace, the temperature inside the rapid heat treatment furnace is raised to the heat annealing temperature and held at the heat annealing temperature for 1 to 300 seconds. The specific steps are as follows: first, the temperature inside the rapid heat treatment furnace is raised to 1000 to 1200°C and held at this temperature for 1 to 300 seconds, and then the temperature is lowered. Optionally, the temperature is lowered to 400°C to 800°C, preferably to 500°C, and the cooling rate can be selected as 5 to 40°C / s, preferably 20 to 35°C / s.

[0078] The rapid heat treatment involves heating and holding steps in an inert gas atmosphere and / or a reducing gas atmosphere, while the cooling step is performed in an inert gas atmosphere. The inert gas includes argon, and the reducing gas includes hydrogen. Optionally, the rapid heat treatment atmosphere can be pure argon, pure hydrogen, or a mixture of argon and hydrogen. When the rapid heat treatment enters the cooling phase, if the current atmosphere in the chamber is pure hydrogen or a mixture of argon and hydrogen, it is switched to an inert gas atmosphere (such as pure argon) until the cooling phase ends.

[0079] Annealing time and annealing temperature both significantly affect the warpage of substrates with deposited polycrystalline silicon layers. Therefore, the warpage of the substrate can be improved to varying degrees by changing the annealing time and temperature. Under the aforementioned rapid thermal processing conditions, the curvature and warpage of the standard silicon wafer can meet the calibration requirements of non-contact flatness measurement equipment such as surface light scattering meters.

[0080] As can be seen from the detailed description of each step above, the preparation method provided by the embodiments of the present invention is carried out in the same deposition chamber from loading, heating, polycrystalline silicon deposition to high-temperature annealing, or only the chamber is changed once, and each processing step is protected by inert gas or high-purity process gas, which minimizes the introduction of external particles and metal impurities. In this way, it can further ensure that the standard silicon wafers produced can be used for the calibration of equipment such as surface light scattering instruments with extremely high cleanliness requirements.

[0081] Furthermore, to further prevent the introduction of external particles and metal impurities, the preparation method provided in this embodiment may also include: cleaning the standard silicon wafer prepared through the above steps to remove metal or particulate contamination from the surface of the silicon wafer. The chemical reagents used for cleaning may include: SC~1 solution (volume ratio satisfying: NH4OH:H2O2:DIWater = 1:1:5, used for organic contamination and particle removal), SC~2 solution (volume ratio satisfying: HCl:H2O2:DIWater = 1:1:6, used for metal ion and oxide removal), the cleaning temperature is 20~40℃, and the cleaning time is 10~200s.

[0082] Furthermore, embodiments of the present invention also provide a calibration method for a flatness measuring device, comprising:

[0083] A standard silicon wafer prepared using the preparation method described in the embodiments of the present invention is provided;

[0084] The surface of the standard silicon wafer is measured using the target measurement device to be calibrated, in order to obtain surface roughness measurement data; and,

[0085] The measurement error of the target measurement device is confirmed based on the measurement data.

[0086] Optionally, the target measurement device can be a device that uses a non-contact optical measurement method to measure roughness, such as a localized light scattering (LLS) instrument, or a device that uses a contact or near-field scanning surface topography measurement method to measure roughness, such as an atomic force microscope or a scanning electron microscope. When the target measurement device is a surface light scattering instrument, its scattered light receiving channel can be DWN, DNN, DW1O, DW2O, or DNO.

[0087] Optionally, the measurement data of the target measuring device to be calibrated can be compared with known standard values ​​to confirm the measurement error of the target measuring device.

[0088] In summary, the standard silicon wafer preparation method and the planarity measurement equipment calibration method provided by the embodiments of the present invention include: providing a substrate; depositing a polycrystalline silicon layer on the surface of the substrate, and during the deposition of the polycrystalline silicon layer, controlling the deposition temperature and / or the flow rate of the reactive gas to distribute the different sizes of the polycrystalline silicon layer according to a set ratio, thereby ensuring that the surface roughness of the polycrystalline silicon layer is within a target range; wherein the process conditions for depositing the polycrystalline silicon layer include: using a silicon source gas as the reactive gas, the deposition temperature having a selectable range of 800~1080℃, and the silicon source gas flow rate having a selectable range of 5~30SLM. The preparation method provided by the present invention controls the grain size of the polycrystalline silicon layer by controlling the deposition temperature and / or the flow rate of the reactive gas, thus enabling the repeatable and controllable preparation of standard wafers with specific roughness and excellent uniformity for calibration of planarity measurement equipment.

[0089] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for preparing a standard silicon wafer, characterized in that, include: Provide substrate; A polycrystalline silicon layer is deposited on the surface of the substrate. During the deposition of the polycrystalline silicon layer, the deposition temperature and / or the flow rate of the reactive gas are controlled so that the different sizes of the polycrystalline silicon layer are distributed in a set ratio, thereby making the surface roughness of the polycrystalline silicon layer within the target range. The process conditions for depositing the polycrystalline silicon layer include: using silicon source gas as the reaction gas, the deposition temperature can be selected in the range of 800~1080℃, and the silicon source gas flow rate can be selected in the range of 5~30SLM.

2. The method for preparing a standard silicon wafer as described in claim 1, characterized in that, The distribution according to the set ratio includes: the proportion of large-size grains above 300nm is 5% to 40%; The target range is 0.1~2nm.

3. The method for preparing a standard silicon wafer as described in claim 1, characterized in that, When controlling the deposition temperature and / or the flow rate of the reactive gas to ensure that the surface roughness of the polycrystalline silicon layer is within the target range, the principle that the magnitude of the surface roughness is positively correlated with the magnitude of the deposition temperature and the magnitude of the reactive gas flow rate is followed.

4. The method for preparing a standard silicon wafer as described in claim 1, characterized in that, The polycrystalline silicon layer is deposited through the pyrolysis reaction of the silicon source gas.

5. The method for preparing a standard silicon wafer as described in claim 1, characterized in that, The polycrystalline silicon layer is deposited by a reduction reaction of the silicon source gas and hydrogen, wherein the hydrogen flow rate is 15~30 SLM.

6. The method for preparing a standard silicon wafer as described in claim 1, characterized in that, After depositing a polycrystalline silicon layer on the substrate surface, the fabrication method further includes: The substrate on which the polycrystalline layer is deposited is subjected to thermal annealing to release the stress between the polycrystalline silicon layer and the substrate.

7. The method for preparing a standard silicon wafer as described in claim 6, characterized in that, The heat annealing temperature for the heat annealing treatment is 1000~1200℃.

8. The method for preparing a standard silicon wafer as described in claim 7, characterized in that, The thermal annealing process is also performed in the deposition chamber where the polycrystalline silicon layer is deposited, or the thermal annealing process is performed in a rapid thermal processing furnace.

9. The method for preparing a standard silicon wafer as described in claim 8, characterized in that, When the hot annealing process is performed in the deposition chamber, the temperature inside the deposition chamber is raised to the hot annealing temperature and then held at the hot annealing temperature for 5 to 30 minutes; when the hot annealing process is performed in the rapid heat treatment furnace, the temperature inside the rapid heat treatment furnace is raised to the hot annealing temperature and then held at the hot annealing temperature for 1 to 300 seconds.

10. A calibration method for a leveling measurement device, characterized in that, include: Provide a standard silicon wafer prepared using the preparation method according to any one of claims 1 to 9; The surface of the standard silicon wafer is measured using the target measurement device to be calibrated, in order to obtain surface roughness measurement data; and, The measurement error of the target measurement device is confirmed based on the measurement data.

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