Ranging method and device based on non-equal sampling digital phase discriminator, and storage medium

Abstract

The invention relates to the technical field of space optical communication and distance measurement, in particular to a distance measurement method and device based on a non-equal sampling digital phase discriminator and a storage medium. A non-equal sampling method is used for carrying out sampling and phase discrimination on data bit clocks on two asynchronous clock domains for sending and receiving GTX, and hardware resources required for processing all use an FPGA internal digital logic block; the clock processing rate and the GTX sending and receiving clock rate are kept in a non-integer multiple relationship, so that the measurement precision of the phase difference between the two clock rates is improved, and the purpose of improving the laser ranging precision on the basis of simplifying the hardware design of a ranging system is achieved.

Description

Technical Field

[0001] The present invention relates to the technical fields of space optical communication and ranging, and particularly to a ranging method, device and storage medium based on a non-equal division sampling digital phase discriminator. Background Art

[0002] With the continuous development of space technology, traditional microwave communication methods are limited by frequency band resources and gradually become difficult to meet the future development needs in terms of rate, communication capacity, anti-interference and security. Laser communication has characteristics such as large capacity, strong anti-interference ability, low power consumption and small volume. Applying it to inter-satellite and satellite-ground communication can greatly improve the performance of the system. At the same time, the laser communication link can measure the distance and time difference between communication systems by measuring the time delay between the output and received signals.

[0003] Currently, the main method for high-precision space laser ranging is to use an incoherent bidirectional one-way or two-way ranging system. Its ranging accuracy is directly affected by the synchronization accuracy of the data symbol bits, that is, it is related to the measurement accuracy of the phase difference of the data bit clock. Therefore, choosing a suitable phase discrimination technology is also the key to obtaining high ranging accuracy. Existing space laser ranging systems generally use analog phase discrimination methods to accurately identify the phase of the data bit clock between the transmitted signal and the received signal through a dedicated phase discriminator chip. For example, in the principle prototype of a laser unified measurement and control system based on the OOK system proposed by Xing Qianglin et al., a processing architecture of a very large-scale FPGA + high-speed ADC is adopted. The problem brought by this method is that it significantly increases the software algorithm complexity and hardware design cost of the entire system. Therefore, further improving the space laser ranging method and breaking through the limitations of existing high-precision space laser ranging methods in terms of the volume, weight, power consumption, complexity, engineering, etc. of ranging equipment has become a new challenge.

[0004] In addition, with the continuous improvement of modern integrated circuit technology, FPGA devices integrated with GTX high-speed transceiver serializers with a transmission rate of up to more than a dozen Gbps have emerged. The method of using the high-speed serial transceiver of the FPGA in cooperation with the optoelectronic conversion module to implement the laser OOK direct modulation communication system is widely used in engineering practice. When the GTX OOK system is used for ranging, there is a problem that the data bit clocks at the GTX transmitter and receiver are not from the same source. Due to the metastable state effect caused by asynchronous clock sampling, it is impossible to directly sample and process the clock phase or data on one clock source on another clock source, and the difference between the GTX transmitter clock and the receiver clock cannot be effectively identified. Summary of the Invention

[0005] The present invention provides a ranging method, device, and storage medium based on a non-equal-sampling digital phase discriminator, aiming to solve the problem of measurement accuracy jitter caused by the inability to accurately estimate the change in clock phase under non-coherent direct ranging conditions through the design of the digital phase discriminator, and improve the spatial laser ranging accuracy in high code rate communications.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A ranging method based on a non-equal-sampling digital phase discriminator includes:

[0008] Step a: Generate a data frame containing a synchronization header under the transmission clock (clk_send), and record the value of the double-word sequence number counter when the synchronization header starts to be sent at the transmitting end ;

[0009] Step b: Convert the parallel data into a high-speed serial signal through the GTX transmission module of the FPGA, and send the laser signal at the line rate Vtr;

[0010] Step c: Receive the returned laser signal through the GTX receiving module, recover the receiving clock (clk_rev), and convert the serial data into a parallel data frame;

[0011] Step d: Synchronize the data frame under the receiving clock, capture the double-word sequence number and bit sequence number at the end of the synchronization header and calculate the number of offset bytes and bit offsets of the synchronization header ; and bit offsets ;

[0012] Step e: Perform non-equal sampling on the transmission clock and the receiving clock using a phase discriminator sampling clock (clk_sample) with a non-integer multiple relationship, multiply the complex conjugates of the two sampled clock signals, and perform arctangent phase discrimination through a phase-locked loop to obtain the phase difference ;

[0013] Step f: Perform 2 n times low-pass operation on the phase difference and input it into a second-order phase-locked loop, and set the bandwidth of the phase-locked loop to the order of 1 Hz and the damping coefficient 0.6 ≤ ξ ≤ 0.8;

[0014] Step g: Calculate the total time difference according to the formula:

[0015]

[0016] where is the parallel clock frequency, is the serial line rate;

[0017] The value of the phase difference term coefficient Cptc is the product of the transmission / reception clock division multiple and the parallel data bit width;

[0018] Step h, through Calculate the ranging value, where c is the speed of light.

[0019] Furthermore, the ratio of the phase discrimination sampling clock frequency to the transmission clock frequency and the reception clock frequency in step e is non-integer, specifically satisfying:

[0020]

[0021] Where and are the transmission clock and reception clock frequencies respectively, is the core sampling clock frequency of the digital phase discriminator.

[0022] Furthermore, the transfer function of the phase-locked loop in step f is:

[0023]

[0024] The loop bandwidth BL satisfies:

[0025]

[0026] Where , , and K is the loop gain.

[0027] Furthermore, the division multiple is 4, the parallel data bit width is 32 bits, and Cptc = 128.

[0028] Furthermore, in the 2 n times downsampling operation, n = 14.

[0029] A ranging device based on a non-equidistant sampling digital phase discriminator, comprising:

[0030] A laser emission unit, including an OOK transmission electro-optical conversion module and a GTX transmission module;

[0031] A laser reception unit, including an OOK reception optoelectronic conversion module and a GTX reception module;

[0032] A digital processing unit, including a frame synchronization module, a non-equidistant sampling phase discriminator, a second-order phase-locked loop, and a time difference calculation module integrated in the FPGA;

[0033] The frame synchronization module is used to implement double-word serial number counting and offset calculation;

[0034] The non-equidistant sampling phase discriminator samples the transmission and reception clocks at a non-integer multiple clock;

[0035] The bandwidth of the second-order phase-locked loop ≤ 1 Hz;

[0036] The total float calculation module performs the operation of total float;

[0037] When the device runs, it executes the ranging method based on the non-equidistant sampling digital phase discriminator.

[0038] A storage medium stores a computer program, and when the program is executed by a processor, it implements the spatial laser ranging method based on the digital phase discriminator described above.

[0039] The beneficial effects achieved by the present invention are as follows:

[0040] The ranging method, device and storage medium of the present invention based on the non-equidistant sampling digital phase discriminator replace the traditional analog phase discriminator. Using a digital phase discriminator can effectively reduce the design complexity and hardware cost of the system; adopting the non-equidistant sampling method, using the phase discriminator sampling clock that is in a non-integer multiple relationship with the receiving clock and the sending clock to sample the receiving clock and the sending clock respectively. While completing the phase discrimination of the receiving and sending clocks, the reliability of the phase discriminator is improved; in addition, the relevant design of the phase-locked loop is carried out to achieve precise tracking of the digital phase difference, reduce the jitter of the phase discrimination result, and improve the stability of the phase discriminator. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0042] Figure 1 It is a principle block diagram of spatial laser ranging based on a digital phase discriminator.

[0043] Figure 2 It is a principle block diagram based on a digital phase discriminator.

[0044] Figure 3 It is a simulation result diagram of non-equidistant sampling phase discrimination.

[0045] The realization, functional features and advantages of the object of the present invention will be further described in conjunction with the embodiments and with reference to the drawings. Detailed Embodiments

[0046] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0047] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, then such directional indications are only used to explain the relative positional relationship and movement conditions between components in a certain specific posture (as shown in the accompanying drawings). If this specific posture changes, then the directional indications will also change accordingly.

[0048] In addition, if there are descriptions such as "first", "second", etc. involved in the embodiments of the present invention, then such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text is that it includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or a solution where A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0049] The space laser ranging method based on a digital phase detector proposed by the present invention uses a non-uniform sampling method to sample and phase-detect the data bit clocks in two asynchronous clock domains of GTX transmission and reception. All the hardware resources required for processing are the internal digital logic blocks of the FPGA; the rate of the processing clock maintains a non-integer multiple relationship with the GTX transmission and reception clock rates, thereby improving the measurement accuracy of the phase difference between the two, achieving the purpose of improving the laser ranging accuracy on the basis of simplifying the hardware design of the ranging system.

[0050] A typical device functional structure of the space laser ranging method based on a digital phase detector is as Figure 1 shown. Among them, the OOK receiving optoelectronic conversion module is used to receive the laser signal and convert it into an electrical signal, and the OOK transmitting electro-optical conversion module is used to convert the electrical signal to be transmitted into a laser signal. This optoelectronic conversion module is directly connected to the GTX transceiver module: at the transmitting end, the parallel data stream is converted into a high-speed serial data stream by the GTX transmitting module and sent into the optical module; at the receiving end, the GTX receiving module converts the high-speed serial data stream transmitted by the optical module into a low-speed parallel data stream according to the protocol.

[0051] Spatial laser ranging method based on digital phase discriminator. The solution features mainly include: a non-equidistant sampling digital phase discriminator; setting a phase-locked loop to achieve precise tracking of the digital phase difference; and comprehensively calculating the time difference.

[0052] Based on a non-equidistant sampling digital phase discriminator. In a laser ranging system, the emitted laser is modulated into a signal with a specific frequency, such as a sine wave or a square wave. When the laser irradiates the target object and reflects back, the received signal will have a phase delay, which is proportional to the distance. Therefore, the key technical difficulty of optical ranging is to obtain the precise phase difference between the transmitting clock and the receiving clock, so as to calculate this delay time and then obtain the precise ranging value. Therefore, in order to further improve the ranging reliability, the present invention adopts a non-equidistant sampling digital phase discriminator, starting from improving the clock accuracy, and performing non-equidistant sampling on the GTX receiving clock clk_rev and the GTX transmitting clock clk_send through the phase discriminator sampling clock clk_sample, where the phase discriminator sampling clock and the GTX transceiver clock maintain a non-integer multiple relationship. The product of the sampled receiving clock and the complex conjugate of the sampled transmitting clock is sent to the phase-locked loop for arctangent phase discrimination. Through Figure 3 The simulation results can show the phase discrimination linearity of non-equidistant sampling. This design not only effectively reduces the system design complexity and equipment cost, but also effectively improves the reliability of the ranging system by using the non-equidistant sampling technology.

[0053] Setting a phase-locked loop to achieve precise tracking of the digital phase difference. To achieve precise tracking of the digital phase difference and improve the stability of the system, the phase-locked loop set by the present invention mainly adopts the following measures: First, perform high-magnification and low-sampling on the phase difference output by the digital phase discriminator to reduce the phase discrimination result jitter, reduce the loop update rate, and effectively reduce the system's calculation load and power consumption; Second, set the phase-locked loop bandwidth to a small value to reduce the tracking result jitter, effectively suppress high-frequency noise, and reduce the errors caused by environmental noise or circuit self-noise, thereby improving the ranging accuracy.

[0054] Comprehensively calculating the time difference. Laser ranging is achieved by measuring and calculating the time from the emission of the laser pulse to the reception of the returned laser. Therefore, the core influence of the time difference in ranging is directly related to the accuracy of distance calculation. The present invention comprehensively calculates the time difference by using the difference in the number of bits of the transceiver data and the phase difference of the data clock, and converts it into a specific time difference by using the method in step 7.

[0055] The hardware system architecture of the ranging device includes a laser transmitting unit, a laser receiving unit, and a digital processing unit. The laser transmitting unit includes an OOK transmitting electro-optic conversion module and an internal GTX transmitting module in the FPGA. The GTX transmitting module converts parallel data (156.25 MHz) into a 5 Gbps high-speed serial signal through serial-to-parallel conversion and drives the laser to emit a modulated optical signal.

[0056] The laser receiving unit includes an OOK receiving optoelectronic conversion module and an internal GTX receiving module in the FPGA. The optoelectronic conversion module converts the received optical signal into an electrical signal. The GTX receiving module completes serial-to-parallel conversion, outputs a 32-bit wide parallel data frame (156.25 MHz), and restores the received clock clk_rev.

[0057] The digital processing unit is integrated inside the FPGA and includes the following modules:

[0058] A frame synchronization module that detects the data frame synchronization header and calculates the offset; a non-equidistant sampling phase discriminator that performs non-integer multiple sampling on the transceiver clocks based on a 200 MHz sampling clock clk_sample; a second-order phase-locked loop with a bandwidth of 1 Hz and a damping factor of 0.7071 for phase difference tracking; a time difference calculation module that performs the calculation of the ranging value.

[0059] The spatial laser ranging method based on a digital phase discriminator of the present invention adopts a two-way ranging method. The transmitting unit sends a laser signal, and the receiving unit receives the returned laser signal. A non-equidistant sampling digital phase discriminator is used to discriminate the phase difference between the GTX transmitting clock and the GTX receiving clock. And the digital phase difference is sent into the phase-locked loop for precise tracking. Finally, based on the obtained clock phase difference and the synchronization header offset, an accurate time value is obtained to complete the ranging.

[0060] Taking the link transmission rate of 5 Gbps as an example, the present invention simulates and generates a GTX receiving clock clk_rev and a GTX transmitting clock clk_send with a frequency value of 156.25 MHz. Then, taking the local transmitting clock as the reference clock, a 200 MHz phase discrimination sampling clock clk_sample is generated, and this phase discrimination sampling clock has a non-integer multiple relationship with the transceiver clocks. Then, the arctangent phase discrimination processing is performed on the transceiver clock signals using this phase discrimination sampling clock. As shown in The specific parameters of this embodiment are as follows:

[0061] Step 1: Frame the transmitted data frame. Under the transmitting clock clk_send (156.25 MHz), a 1000-byte data frame including a 4-byte synchronization header, a packet identifier, and a data field is generated. Record the value of the double-word sequence counter DwT at the moment when the transmitting end starts to send the synchronization header and store it in the transmitting end DRAM.

[0062] The specific process is as follows: Under the clk_send clock, the value of the double-word sequence number counter at the moment when the sending end starts to send the synchronization header is stored in the DRAM of the sending end. At the same time, for the convenience of measurement, the data frame usually starts sending from byte 0. Additionally, considering that the GTX data interface is generally n (n is a positive integer) bytes, the frame length design should ensure that there are an integer number of data frames per second. Therefore, the encoded frame length is usually a multiple of 4 bytes. (n is a positive integer)bytes, the frame length design should ensure that there are an integer number of data frames per second. Therefore, the encoded frame length is usually a multiple of 4 bytes.

[0063] Step 2: GTX transmission module processing. Use the GTX transmission module inside the FPGA to convert the parallel data to be transmitted into a transmission signal according to the corresponding communication rate requirements through serial-to-parallel conversion, and obtain the GTX transmission clock clk_send of the transmitted data. In the present invention, taking the data line rate of the GTX serial transceiver as 5 Gbps as an example, at the sending end, with a parallel transmission line rate of 156.25 MHz, after serial-to-parallel conversion through the GTX core, it is transmitted at a transmission line rate Vtr of 5 Gbps.

[0064] Step 3: GTX reception module processing. Use the GTX reception module inside the FPGA to complete the reception of the laser signal data and perform serial-to-parallel conversion on the data, that is, at the receiving end, group the data according to a fixed 32-bit width to form a parallel data frame, ensuring that each group of data is exactly 32 bits. At the same time, the reception clock clk_rev is recovered. At the receiving end, the 5 Gbps transmission line rate is reduced to a parallel reception line rate of 156.25 MHz through serial-to-parallel conversion of the GTX core.

[0065] Step 4: Synchronization of the received data frame. Under the clk_rev clock, after receiving the parallel data, the received data processing part first performs data frame synchronization, searches for the double-word sequence number and the bit sequence number within the byte at the end of the received frame header, and parses the received frame format according to and . The specific process is as follows: Under the clk_rev clock, when the receiving end detects that the double-word data output by the current GTX receiving port contains the end flag of the synchronization header, the double-word sequence number counter is set to 0, and at the same time, the offset value of the bit sequence number corresponding to the synchronization header reception flag position within the double-word is stored in the DRAM of the receiving end; subsequently, each time 1 double-word is output by the GTX receiving port, is incremented by 1 until reaches the data frame length and then wraps back to 0. At the same time, synchronous update calculation:

[0066] The number of bytes of the synchronization header offset : The number of bits of offset of the synchronization header in the current byte :[[]]END]] Thus, the synchronization header offset is obtained.

[0067] Step 5: Unequally divided sampling digital phase detector. In the present invention, a GTX receive clock clk_rev and a GTX transmit clock clk_send with a frequency value of 156.25 MHz are simulated and generated, and each is divided by 4. Then, taking the local transmit clock as the reference clock, a 200 MHz phase detection sampling clock clk_sample is generated, and the clk_rev clock and the clk_send clock are unequally sampled. Then, the complex conjugate of the sampled receive clock and the sampled transmit clock are multiplied, and finally the product result is sent to the phase-locked loop to complete the arctangent phase detection of the phase difference between the transmit clock and the receive clock based on the unequally divided sampling digital phase detector in the clk_sample clock domain.

[0068] Step 6: Phase-locked loop design. In the present invention, relevant designs of the phase-locked loop are carried out to achieve precise tracking of the digital phase difference. The specific implementation steps are as follows:

[0069] Step 6.1 High-magnification and low-sampling operation on the digital phase difference to reduce the jitter of the phase detection result. Under the clock of clk_sample, the output phase difference result of the digital phase detector is subjected to a low-sampling operation of 16384 times, and then sent to the DDS through a low-pass filter LPF, reducing the loop update rate.

[0070] Step 6.2 The phase-locked loop bandwidth is set to a small value to reduce the jitter of the tracking result.

[0071] The present invention adopts an ideal second-order loop filter, and its transfer function of the filter is:

[0072] (1)

[0073] In the formula, and are circuit parameters, The corresponding system function is:

[0074] (2)

[0075] In the formula, K is the loop gain. The referred to as the characteristic frequency and the referred to as the damping coefficient are respectively defined as:

[0076] (3)

[0077] (4)

[0078] The above formula indicates that and these two loop parameters completely determine the performance of the second-order phase-locked loop.

[0079] From the system function , the loop bandwidth can be obtained as follows:

[0080] (5)

[0081] The loop bandwidth controls the amount of noise entering the loop. The narrower the noise bandwidth, the fewer frequency components of noise are allowed to enter the loop. Therefore, the filtering effect of the loop is better, and the loop tracks the signal more accurately. Therefore, in the present invention takes the value of 0.7071 to reduce the loop bandwidth and sets the bandwidth to the order of 1 Hz.

[0082] Step 7. Comprehensively calculate the total time difference. According to the phase difference between the transmitted clock and the received clock and the difference in the number of transmitted and received data bits obtained by the present invention, combined with the above steps, the total time difference is calculated as follows:

[0083] (6)

[0084] In the formula, represents the number of bytes of the synchronization header offset received at the receiving end; represents the number of bits of the synchronization header offset in the 32 bits of the current byte; represents the phase difference between the received clock and the transmitted clock; ; .

[0085] Step 8. Calculation of the ranging value. It is known that the distance value is equal to the speed value multiplied by the time value, and the propagation speed of light is constant. Therefore, the final ranging value can be obtained from the following formula as follows:

[0086] (7)

[0087] where is the speed of light, approximately ; is the total time difference from the transmission to the reception of the laser signal.

[0088] The above are only optional embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A ranging method based on a non-equidistant sampling digital phase discriminator, characterized in that, Including: Step a, generate a data frame containing a synchronization header under the transmission clock, and record the value of the double-word sequence counter when the transmitting end starts to transmit the synchronization header ; Step b: Convert parallel data into high-speed serial signals through the GTX transmission module of the FPGA, and transmit laser signals at a line rate of Vtr. Step c: Receive the returned laser signals through the GTX reception module, recover the reception clock, and convert the serial data into parallel data frames. Step d: Perform data frame synchronization under the receiving clock, capture the double-word sequence number at the end moment of the synchronization header and the bit sequence number , calculate the number of bytes offset by the synchronization header and the number of bits offset ; Step e: Non-equally sample the transmission clock and the reception clock using a phase discrimination sampling clock with a non-integer multiple relationship, multiply the complex conjugates of the two clock signals after sampling, and perform arctangent phase discrimination through a phase-locked loop to obtain the phase difference ; Step f: After performing a 2-fold low-pass operation on the phase difference, input it into a second-order phase-locked loop. The bandwidth of the phase-locked loop is set to the order of 1 Hz and the damping coefficient satisfies 0.6 ≤ ξ ≤ 0.8; n ​ Step g: Calculate the total float time according to the formula: wherein is the parallel clock frequency, is the serial line rate; The value of the phase difference term coefficient Cptc is the product of the transmission / reception clock division multiple and the parallel data bit width. Step h, by calculating a ranging value, where c is the speed of light.

2. The ranging method based on a non-equidistant sampling digital phase discriminator according to claim 1, wherein: In step e, the ratio of the phase discrimination sampling clock frequency to the transmission clock frequency and the reception clock frequency is non-integer, specifically satisfying: wherein and are the transmission clock frequency and the reception clock frequency respectively, is the core sampling clock frequency of the digital phase detector.

3. The ranging method based on a non-equidistant sampling digital phase discriminator according to claim 1, wherein In step f, the transfer function of the phase-locked loop is: The loop bandwidth BL satisfies: Among them , , where K is the loop gain.

4. The ranging method based on a non-uniform sampling digital phase discriminator according to claim 1, wherein The division multiple is 4, the parallel data bit width is 32 bits, and Cptc = 128.

5. The ranging method based on a non-uniform sampling digital phase discriminator according to claim 1, wherein The said 2 n In the double low-draw operation, n = 14.

6. A ranging device based on a non-equal-division sampling digital phase discriminator, characterized in that, Including: A laser emission unit, including an OOK transmission electro-optical conversion module and a GTX transmission module; A laser reception unit, including an OOK reception opto-electronic conversion module and a GTX reception module; A digital processing unit, including a frame synchronization module, a non-equal division sampling phase discriminator, a second-order phase-locked loop, and a float time calculation module integrated in the FPGA; The frame synchronization module is used to implement double-word sequence number counting and offset calculation; The non-equal division sampling phase discriminator samples the transmission and reception clocks at a non-integer multiple clock; The bandwidth of the second-order phase-locked loop ≤ 1 Hz; The float time calculation module performs the operation of the total float time; When the device runs, it executes the method described in any one of claims 1-5.

7. A storage medium, characterized in that, A computer program is stored, and when the computer program is executed by a processor, the processor is caused to execute the method described in any one of claims 1-5.

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