2.5 D substrate manufacturing method and packaging structure

Abstract

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular, to a method for manufacturing a 2.5D substrate and a packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, the chiplet technology adopts a new design method to package small chips with different functions together, thereby forming a heterogeneous integrated chip packaging structure. As the input and output density of chips is getting higher and higher, and the number of chips integrated in a single package increases significantly, at the same time, various 2.5D and 3D packaging technologies are used as multi-chip packaging solutions to connect adjacent chip pad lines within a single package. Therefore, the through-silicon via technology is proposed to form a heterogeneous integrated packaging structure, thereby realizing multi-chip integration and reducing the packaging volume and the number of wiring layers.

[0003] Currently, the through-silicon via technology (TSV) on the substrate can achieve vertical interconnection between chips. In conventional technologies, in the through-silicon via technology, etching or laser drilling technology is usually used to form through-holes on the substrate, then electroplating is used to deposit a metal layer to form metal pillars, and then etching is used to expose the conductive pillars. There is sidewall etching of the interposer in the etching process, resulting in delamination at the junction of the subsequent dielectric layer and the sidewall of the interposer, which affects the packaging quality. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a 2.5D substrate and a packaging structure, which can prevent the sidewalls of the interposer from being corroded, improve the bonding force between the interposer and the dielectric layer, and improve the packaging quality.

[0005] In a first aspect, the present invention provides a method for manufacturing a 2.5D substrate, including: Providing a first carrier mounted with metal components and an interposer; wherein, the interposer is located within the metal components; metal pillars are provided within the interposer; Forming a protective layer covering the metal components and the interposer on the first carrier; Forming a first groove on the metal components; Grinding the interposer and the protective layer so that the surfaces of the interposer and the protective layer are lower than the surface of the metal components; Forming a first dielectric layer with a first opening on the surfaces of the interposer and the protective layer; the first opening exposes the metal pillars; Forming a seed layer on the first dielectric layer; the seed layer extends to the surface of the metal components and fills the first groove; Forming a wiring layer on the seed layer; Remove the seed layer other than the first opening; Form a metal layer and bumps; wherein the metal layer is electrically connected to the wiring layer.

[0006] In an alternative embodiment, the thickness of the seed layer is equal to the depth of the first groove; and the first groove extends to the side of the metal component close to the interposer.

[0007] In an alternative embodiment, the steps of grinding the interposer and the protective layer include: Grind the interposer, the metal posts, and the protective layer to the same plane; Etch the interposer so that the surface of the interposer is respectively lower than the surface of the protective layer and the surface of the metal posts.

[0008] In an alternative embodiment, after the step of etching the interposer, further include: Form an insulating layer on the surface of the interposer; the surface of the insulating layer is flush with the surface of the protective layer and the surface of the metal posts respectively.

[0009] In an alternative embodiment, in the step of forming a protective layer on the first carrier to cover the metal component and the interposer: The protective layer is formed between the interposer and the metal component, and between adjacent metal components; In the step of forming a seed layer on the first dielectric layer: Deposit metal by sputtering to form the seed layer; the seed layer covers the entire surface of the first dielectric layer and the surface of the metal component.

[0010] In an alternative embodiment, the steps of forming a wiring layer on the seed layer include: Form a photoresist on the seed layer, cover the photoresist with a photomask, and form a second opening in the photoresist by exposure and development processes, and the second opening exposes part of the seed layer; Use electroplating process to electroplate metal in the second opening on the seed layer to form a wiring layer; wherein, the seed layer serves as an electroplating lead, and the metal component serves as a clamping part of the electroplating fixture; Remove the photoresist; Remove the seed layer that does not overlap with the wiring layer.

[0011] In an alternative embodiment, in the step of removing the seed layer that does not overlap with the wiring layer: In an alternative embodiment, after the step of forming the metal layer and the bumps, further include: Mount a chip on the bump; Plastically encapsulate the chip to form a second plastic encapsulation body; Cut and separate into single products; wherein, the cutting position is on the interposer or on the protective layer.

[0012] In a second aspect, the present invention provides a packaging structure prepared by using the 2.5D substrate manufacturing method described in any one of the foregoing embodiments; the packaging structure includes: An interposer provided with metal pillars; A dielectric layer, and a wiring layer electrically connected to the metal pillars is provided in the dielectric layer; A seed layer, and the seed layer is provided between the wiring layer and the dielectric layer; A bump, the bump protrudes from the dielectric layer, and the bump is electrically connected to the wiring layer.

[0013] The beneficial effects of the 2.5D substrate manufacturing method and the packaging structure provided by the embodiments of the present invention include: First form a protective layer covering the interposer, and then grind and etch the interposer, which can avoid the side wall of the interposer being etched during the etching process, and is beneficial to improving the bonding force between the interposer and the dielectric layer. And forming a first groove on the metal component can facilitate the subsequent formation of the seed layer, improve the bonding force between the wiring layer and the dielectric layer, and improve the packaging quality. Description of the Drawings

[0014] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0015] Figure 1 It is a process schematic diagram of the interposer provided by the embodiment of the present invention; Figure 2 It is one of the process schematic diagrams of the first 2.5D substrate manufacturing method provided by the embodiment of the present invention; Figure 3 It is Figure 2 A partial enlarged schematic diagram of part A in Figure 4 It is Figure 2 A partial enlarged schematic diagram of part B in Figure 5 It is the second of the process schematic diagrams of the first 2.5D substrate manufacturing method provided by the embodiment of the present invention; Figure 6 It is Figure 5 A partial enlarged schematic diagram of part C in Figure 7 Schematic diagram of forming a ground wiring by retaining a part of a seed layer in the process of removing the seed layer in the first 2.5D substrate manufacturing method provided by an embodiment of the present invention; Figure 8 The third process schematic diagram of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention; Figure 9 The fourth process schematic diagram of the first 2.5D substrate manufacturing method provided by an embodiment of the present invention; Figure 10 The first structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 11 The second structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 12 The third structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 13 A structural schematic diagram of the packaging structure provided by an embodiment of the present invention from a top view perspective; Figure 14 The fourth structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 15 The fifth structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 16 The first process schematic diagram of the interposer of the packaging structure provided by an embodiment of the present invention; Figure 17 The main process schematic diagram of the fifth structure of the packaging structure provided by an embodiment of the present invention; Figure 18 The sixth structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 19 The seventh structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 20 The second structural schematic diagram of the interposer of the packaging structure provided by an embodiment of the present invention; Figure 21 The main process schematic diagram of the seventh structure of the packaging structure provided by an embodiment of the present invention; Figure 22 The eighth structural schematic diagram of the packaging structure provided by an embodiment of the present invention; Figure 23 One of the main process schematic diagrams of the ninth structure of the packaging structure provided by an embodiment of the present invention; Figure 24 Two of the main process schematic diagrams of the ninth structure of the packaging structure provided by an embodiment of the present invention; Figure 25The tenth structural schematic diagram of the packaging structure provided by the embodiment of the present invention; Figure 26 The eleventh structural schematic diagram of the packaging structure provided by the embodiment of the present invention; Figure 27 The third structural schematic diagram of the interposer of the packaging structure provided by the embodiment of the present invention; Figure 28 One of the main process schematic diagrams of the eleventh structure of the packaging structure provided by the embodiment of the present invention; Figure 29 Two of the main process schematic diagrams of the eleventh structure of the packaging structure provided by the embodiment of the present invention; Figure 30 One of the main process schematic diagrams of the second method for manufacturing a 2.5D substrate provided by the embodiment of the present invention; Figure 31 Two of the main process schematic diagrams of the second method for manufacturing a 2.5D substrate provided by the embodiment of the present invention; Figure 32 The main process schematic diagram of the third method for manufacturing a 2.5D substrate provided by the embodiment of the present invention.

[0016] Icon: 101 - First carrier; 102 - Adhesive film; 110 - Interposer; 111 - Metal pillar; 112 - Active wiring layer; 113 - Protective glue; 114 - Copper pillar; 115 - Fourth opening; 116 - Redistribution layer; 117 - Electrical connection solder joint; 120 - Metal component; 121 - First groove; 130 - Protective layer; 140 - Insulating layer; 150 - First dielectric layer; 151 - First opening; 152 - Seed layer; 153 - Photoresist; 154 - Second opening; 155 - Wiring layer; 156 - Ground wiring; 160 - Second dielectric layer; 161 - Third opening; 162 - Metal layer; 163 - Bump; 103 - Second carrier; 170 - Chip; 171 - First underfill; 180 - Second encapsulant; 190 - Conductive layer; 201 - First wiring layer; 202 - Second wiring layer; 203 - Electrical connection post; 204 - Metal plating; 205 - Wiring bump; 206 - Second underfill; 210 - Protective film; 211 - Through groove; 212 - Third encapsulant; 213 - Electrical connection end. Detailed implementation manners

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0018] Accordingly, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0019] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0020] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0021] In addition, terms such as "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0022] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "arranged", "installed", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0024] A method for fabricating a 2.5D substrate proposed in an embodiment of the present invention is beneficial to preventing sidewall erosion of the interposer 110 caused by the etching process, improving the bonding strength between the interposer 110 and the dielectric layer, and improving the packaging quality and accuracy.

[0025] A method for manufacturing a 2.5D substrate provided by an embodiment of the present invention generally includes the following steps: Please refer to Figure 1 and Figure 2 , step S1: Provide a first carrier 101 mounted with a metal component 120 and an interposer 110; wherein, the interposer 110 is located within the metal component 120; and metal pillars 111 are provided within the interposer 110.

[0026] Optionally, take an interposer 110, the material of the interposer 110 can be a silicon-based or germanium-based substrate material, and can be prepared from silicon, germanium, gallium arsenide, indium phosphide, silicon carbide, etc. The thickness of the interposer 110 is 600um - 1500um.

[0027] Form conductive vias on the interposer 110 by dry etching. Among them, dry etching can use carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), hydrogen (H2), etc. to etch conductive vias on the interposer 110, or use a mixture of hydrofluoric acid (HF), buffered oxide etchant, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2), etc. to form conductive vias on the interposer 110 by chemical etching.

[0028] Deposit insulating materials on the pore walls of the conductive vias by vapor deposition in any one of PVCD, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The insulating materials can be at least one or more of silicon nitride, silicon oxynitride, and polyimide, etc.

[0029] Electroplate metal in the conductive vias by electroplating process to form metal pillars 111. Complete the production of the TSV interposer 110, and then cut the interposer 110 into single interposers 110 with TSVs by cutting.

[0030] Refer to Figures 2 to 4 , provide a first carrier 101, use a coater to spin-coat a liquid adhesive layer on the first carrier 101, and then perform soft baking (soft bake) shaping via a hot plate (Hot plate) to form an adhesive film 102. Mount the single interposer 110 and the metal component 120 onto the first carrier 101 respectively. By using the adhesiveness of the adhesive film 102 and after baking, the interposer 110 and the metal component 120 can be reliably fixed on the adhesive film 102. The first carrier 101 includes but is not limited to materials such as glass, silicon oxide, or metal, etc. The adhesive film 102 is a thermoplastic adhesive. The adhesive film 102 can be separated from the first carrier 101 after being irradiated with ultraviolet light. The material of the adhesive film 102 includes but is not limited to polymer composite materials such as epoxy resin and benzocyclobutene.

[0031] It can be understood that a plurality of metal components 120 and a plurality of interposers 110 are mounted on the first carrier 101, and each metal component 120 is disposed around the periphery of an interposer 110. The height of the metal component 120 is consistent with the height of the interposer 110. The metal component 120 can be block-shaped, column-shaped or ring-shaped.

[0032] Step S2: Form a protective layer 130 covering the metal component 120 and the intermediary layer 110 on the first carrier 101. The protective layer 130 can be formed on the first carrier 101 by a plastic encapsulation process. The plastic encapsulation process includes but is not limited to pressure injection molding or printing injection molding. In this embodiment, the protective layer 130 can be a first plastic encapsulation body. The first plastic encapsulation body is filled between multiple metal components 120, and between the metal component 120 and the intermediary layer 110. Optionally, the surface of the protective layer 130, the surface of the intermediary layer 110, and the surface of the metal component 120 are located in the same plane, and the end face of the metal column 111 is flush with the surface of the intermediary layer 110. It should be noted that the material of the protective layer 130 can be a plastic encapsulation body, such as epoxy resin. In some embodiments, the protective layer 130 can also be made of a sacrificial material, such as a photoresist.

[0033] Step S3: forming a first groove 121 on the side of the metal component 120 away from the first carrier 101. A chemical polishing process can be used to grind the surface of the metal component 120 under the pressure of a polishing pad and the action of centrifugal force to form the first groove 121. The depth of the first groove 121 is H1. The first groove 121 extends to the side of the metal component 120 close to the interposer 110.

[0034] Step S4: Grind the intermediary layer 110 and the protective layer 130 away from the side of the first carrier 101 so that the surfaces of the intermediary layer 110 and the protective layer 130 are lower than the surface of the metal component 120. Optionally, the protective layer 130, the intermediary layer 110 and the metal pillar 111 are ground using the same grinding process as step S3. After grinding, the upper surfaces of the protective layer 130, the intermediary layer 110 and the metal pillar 111 are located in the same plane. The vertical distance between the surface of the intermediary layer 110 after grinding and the bottom of the first groove 121 is H2.

[0035] Step S5: Etch the surface of the interlayer 110 to expose a part of the metal posts 111 from the surface of the interlayer 110. Optionally, a dry etching process is used on the upper surface of the interlayer 110 (the surface of the interlayer 110 away from the first carrier 101) to remove a part of the interlayer 110, so that the upper end surfaces of the metal posts 111 are exposed from the surface of the interlayer 110. The exposed height of the metal posts 111 is in the micron range. It should be noted that since the protective layer 130 covers the outer periphery of the interlayer 110, the outer peripheral wall of the interlayer 110 can be protected. In this etching process, the etching gas will only remove the material of the interlayer 110 and will not remove the material of the protective layer 130. Therefore, the side walls of the interlayer 110 can be prevented from being etched, thereby protecting the side walls of the interlayer 110 and improving the bonding property between the interlayer 110 and the dielectric layer in the subsequent process.

[0036] It should be noted that the etching gas can be selected as process gas and carrier gas according to actual needs. The process gas includes but is not limited to any one or more of SF6, CF4, and NF3. The carrier gas includes but is not limited to any one or more of nitrogen, helium, and argon. During the etching process, the process gas is decomposed and part of the gas is ionized to form plasma. The fluorine ions in the plasma react with the material to be etched, and at the same time, the surface of the material to be etched is bombarded by ions, which can knock out the atoms of the material to be etched, so as to achieve the purpose of etching by using physical energy. The surface material of the interlayer 110 is silicon and silicon dioxide. The addition of gases such as nitrogen can improve the etching efficiency. The main reactions occurring during the etching process are as follows: SiO2 + 4F = SiF4↑ + O2↑ The waste gas generated in this process is mainly unreacted fluorides and the fluorides generated by the reaction.

[0037] Therefore, after the protective layer 130 is provided, the material of the protective layer 130 is different from that of the interlayer 110, and the protective layer 130 will not be etched, effectively protecting the side walls of the interlayer 110.

[0038] In this embodiment, the etching depth of the surface of the interlayer 110 is H3, that is, the exposed height of the metal posts 111 is H3. After etching, the surface of the interlayer 110 is lower than the surfaces of the protective layer 130 and the metal posts 111 respectively.

[0039] Step S6: Form an insulating layer 140 on the surface of the interlayer 110. The surface of the insulating layer 140 is flush with the surfaces of the protective layer 130 and the metal posts 111 respectively.

[0040] Deposit an insulating layer 140 on the surface of the interlayer 110 by any one of the gas deposition methods such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD or PECVD. The thickness of the insulating layer 140 is H3. The material of the insulating layer 140 includes, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, polyimide, titanium nitride, etc.

[0041] Combine Figure 5 and Figure 6 , step S7: Form a first dielectric layer 150 with a first opening 151 on the surfaces of the interlayer 110 and the protective layer 130; the first opening 151 exposes the metal pillar 111.

[0042] Optionally, use a spin coating process, such as spin coating or spraying, to form the first dielectric layer 150 on the surfaces of the interlayer 110 and the protective layer 130. The material of the first dielectric layer 150 includes, but is not limited to, any one or more of organic materials such as polybenzoxazole (PBO), polyimide, and benzocyclobutene. Cover the first dielectric layer 150 with a photomask, and use an exposure and development process to form the first opening 151 on the first dielectric layer 150. The first opening 151 is the graphic layer opening corresponding to the shape of the wiring layer 155. Among them, the height of the first dielectric layer 150 is H2, and the surface of the first dielectric layer 150 is flush with the bottom of the first groove 121.

[0043] Step S8: Form a seed layer 152 on the first dielectric layer 150. The seed layer 152 extends to the surface of the metal component 120 and fills the first groove 121.

[0044] Optionally, use a metal sputtering method to form a layer of seed layer 152 in the first opening 151. The seed layer 152 is a metal conductive material, including, but not limited to, any one or more of copper, titanium, nickel, vanadium, chromium, gold, titanium, and tungsten. The seed layer 152 can be one or more layers of metal. In this embodiment, the thickness of the seed layer 152 is the depth H1 of the first groove 121, that is, the seed layer 152 fills the first groove 121 on the metal component 120. It is easy to understand that due to the use of the metal sputtering method, the seed layer 152 can be formed on the entire surfaces of the metal component 120 and the first dielectric layer 150. In other words, the seed layer 152 can cover the protective layer 130 and the metal component 120 between adjacent interlayers 110. The seed layer 152 in the first opening 151 is electrically connected to the metal pillar 111.

[0045] The seed layer 152 can improve the bonding property between the wiring layer 155 and the first dielectric layer 150 and avoid structural delamination. And the seed layer 152 can improve the bonding force between the wiring layer 155 and the metal pillar 111 and enhance the conductive performance. The first groove 121 can control the thickness of the seed layer 152 and improve the subsequent wiring accuracy.

[0046] Step S9: Optionally, after forming the seed layer 152, a photoresist 153 is coated on the surface of the seed layer 152 by a spin coating process. A photomask is covered on the photoresist 153, and a second opening 154 is formed on the photoresist 153 by an exposure and development process. The second opening 154 exposes a part of the seed layer 152. The shape of the second opening 154 is similar to that of the first opening 151 and is designed according to the required wiring layer 155.

[0047] By an electroplating process, a metal is electroplated in the second opening 154 on the seed layer 152 to form the wiring layer 155. Optionally, in the electroplating process, the metal component 120 can be used as the clamping part of the electroplating fixture. Among them, the clamping part is preferably the part of the metal component 120 other than the first groove 121 on the surface. Using the metal component 120 as the clamping part of the electroplating fixture will not damage the surface of the interposer 110. And the seed layer 152 can be used as an electroplating lead to ensure the uniformity of electroplating of all the wiring layers 155 in the second opening 154, with the thickness of the wiring layer 155 being uniform, improving the electroplating efficiency and electroplating quality of the wiring layer 155.

[0048] Step S10: Then, by a wet etching process, the photoresist 153 is removed using a developer, and then micro-etching is performed by a chemical etching method to remove the seed layer 152. The etching solution for the chemical etching can be a mixed solution of sulfuric acid and hydrogen peroxide.

[0049] It should be noted that in the process of removing the seed layer 152, the seed layer 152 that does not overlap with the wiring layer 155 is removed. In this way, it can be ensured that the seed layer 152 is retained between the wiring layer 155 and the first dielectric layer 150 to improve the bonding force between the first dielectric layer 150 and the wiring layer 155, as well as the conductivity and bonding force between the wiring layer 155 and the metal pillar 111.

[0050] Combined Figure 7 , optionally, in some embodiments, in the process of removing the seed layer 152, the seed layer 152 between adjacent first openings 151 can also be removed to prevent short-circuit connection of the wiring layer 155. At the same time, part or all of the seed layer 152 corresponding to the positions of the metal component 120 and the protective layer 130 is retained to form a ground wiring 156 or an equipotential wiring. It is easy to understand that only part of the seed layer 152 on the surface of the metal component 120 needs to be retained so that the wiring layer 155 can be electrically extended to the surface of the metal component 120. If the seed layer 152 on the metal component 120 is electrically connected to the grounded part of the wiring layer 155, the seed layer 152 on the surface of the metal component 120 forms a ground wiring 156, and electrostatic discharge can be achieved. Or, the seed layer 152 on the metal component 120 can also be electrically connected to the non-grounded part of the wiring layer 155, which is not specifically limited here.

[0051] Combination Figure 8 In step S11: Using a spin coating process, such as spin coating or spraying, a second dielectric layer 160 is formed on the surface of the first dielectric layer 150. The material of the second dielectric layer 160 includes, but is not limited to, any one or more of silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. A photomask is used to cover the second dielectric layer 160, and a third opening 161 is formed in the second dielectric layer 160 by an exposure and development process. The third opening 161 exposes the wiring layer 155. A metal is deposited in the third opening 161 to form a metal layer 162, and the metal layer 162 is electrically connected to the wiring layer 155. The metal layer 162 can be made of copper or other metal materials. The formation method of the metal layer 162 includes, but is not limited to, sputtering, electroless plating, electroplating, etc.

[0052] In step S12: A bump 163 is formed on the metal layer 162 by a ball mounting process. The ball mounting method can be electroplating or printing ball mounting, and the material of the bump 163 can be a conductive material such as Sn - Ag, Sn - Bi, or Sn - Ag - Cu.

[0053] Finally, through a debonding method by ultraviolet light irradiation, the first carrier 101 is separated from the interposer 110, and the first carrier 101 is removed. In this way, the production on one side of the interposer 110 is completed.

[0054] In some embodiments, if only the wiring on one side of the interposer 110 needs to be fabricated, the protective layer 130 can be removed by a chemical cleaning method to obtain an interposer 110 product with a wiring layer 155 on one side.

[0055] Combination Figure 9 It should be noted that in some embodiments, wiring also needs to be performed on the other side of the interposer 110, that is, double - sided wiring is included in a single interposer 110 product. Then, after removing the first carrier 101 as described above, the side of the interposer 110 with the bump 163 is mounted on the second carrier 103, and the processes from step S3 to step S12 are performed on the side of the interposer 110 away from the second carrier 103 to complete the wiring production on the other side, that is, the substrate production is completed.

[0056] Optionally, a chip 170 can also be mounted on the interposer 110. Taking the mounting of a flip - chip 170 as an example, the bumps of the chip 170 are welded to the bumps 163 of the interposer 110 to achieve electrical connection between the chip 170 and the interposer 110. Then, a first underfill 171 is filled in the gap between the chip 170 and the interposer 110.

[0057] Optionally, the chip 170 is encapsulated. A second encapsulation body 180 is formed on the interposer 110 to protect the welding structure of the chip 170 and the interposer 110. Optionally, the second encapsulation body 180 can be ground to be flush with the surface of the chip 170, that is, the second encapsulation body 180 exposes the surface of the chip 170. In this way, it is beneficial to improve the heat dissipation performance and reduce the package height.

[0058] Remove the second carrier 103, and cut and separate the interposer 110 to form single products. It should be understood that due to different cutting positions, single products including different structures can be formed. For example, if the cutting position is on the interposer 110, the metal component 120 and the protective layer 130 are cut and removed together, and the obtained single product is as Figure 10 shown. If the cutting position is on the protective layer 130, there are two cases: First, if the cutting position is on the protective layer 130 between the metal component 120 and the interposer 110, the metal component 120 is cut and removed, and part of the protective layer 130 is retained. The protective layer 130 protects the side wall of the interposer 110, and the structure of the single product is as Figure 11 shown.

[0059] Second, if the cutting position is on the protective layer 130 on the side of the metal component 120 away from the interposer 110, the metal component 120 is retained in the single product, which can relieve structural warping, improve the heat dissipation performance, and has greater structural strength and better peripheral support. The structure of the single product is as Figure 12 shown.

[0060] Combined with Figure 10 ,An embodiment of the present invention further provides a packaging structure, which is prepared by using the 2.5D substrate manufacturing method in any one of the foregoing embodiments. The packaging structure includes an interposer 110, an insulating layer 140, a dielectric layer, a seed layer 152, a wiring layer 155, and bumps 163. Among them, the interposer 110 is provided with metal posts 111, and both ends of the metal posts 111 expose from the surface of the interposer 110. The insulating layer 140 covers the surface of the interposer 110 and is flush with the surface of the metal posts 111. A wiring layer 155 electrically connected to the metal posts 111 is provided in the dielectric layer. A seed layer 152 is provided between the wiring layer 155 and the dielectric layer. The bumps 163 protrude from the dielectric layer, and the bumps 163 are electrically connected to the wiring layer 155.

[0061] Optionally, the dielectric layer includes a stacked first dielectric layer 150 and a second dielectric layer 160. The first dielectric layer 150 is located on the side of the insulating layer 140 away from the interposer 110, and the second dielectric layer 160 is located on the side of the first dielectric layer 150 away from the interposer 110. A wiring layer 155 is located within the first dielectric layer 150. The second dielectric layer 160 is provided with a metal layer 162 electrically connected to the wiring layer 155. A bump 163 protrudes from the second dielectric layer 160, and the bump 163 is electrically connected to the metal layer 162. The first dielectric layer 150 and the second dielectric layer 160 are made of the same material.

[0062] Combined Figure 11 , optionally, the outer periphery of the interposer 110 is coated with a protective layer 130, and the two surfaces of the protective layer 130 are flush with the two end faces of the metal pillar 111 respectively.

[0063] Combined Figure 12 and Figure 13 , optionally, the encapsulation structure further includes a metal component 120; the metal component 120 is located on the outer periphery of the interposer 110; the protective layer 130 is located between the metal component 120 and the interposer 110, and on the side of the metal component 120 away from the interposer 110; the two surfaces of the metal component 120 respectively protrude above the two end faces of the metal pillar 111; the surface of the metal component 120 extends into the dielectric layer.

[0064] Combined Figure 14 , optionally, the two surfaces of the metal component 120 are respectively provided with a first groove 121, and a conductive layer 190 is provided in the first groove 121. The conductive layer 190 is electrically connected to the wiring layer 155. It should be noted that the conductive layer 190 here is the seed layer 152 sputtered in the manufacturing process, and a part of the seed layer 152 remaining after removing the seed layer 152 forms the conductive layer 190. If the conductive layer 190 is electrically connected to the grounded part in the wiring layer 155, it becomes a ground wiring 156, which has functions such as electrostatic discharge.

[0065] In some embodiments, the conductive layer 190 can be electrically connected to the non-grounded part of the wiring layer 155, and the conductive layer 190 is provided on both sides of the metal component 120. In this way, an equipotential wiring can be formed, that is, the electric potentials on both sides of the metal component 120 are equal, which can prevent the generation of static electricity and avoid being interfered by static electricity.

[0066] Combined Figure 15, in some embodiments, the interposer 110 is a device such as an inductor, a voltage device, a resistor, a capacitor, a transistor, or a diode. An active wiring layer 112 is provided on the interposer 110. A first wiring layer 201 and a second wiring layer 202 are respectively formed on both sides of the interposer 110. The first wiring layer 201 or the second wiring layer 202 is electrically connected to the active wiring layer 112. Bumps 163 are respectively connected to the first wiring layer 201 and the second wiring layer. The chip 170 is disposed on at least one side of the interposer 110, and the chip 170 and the bumps 163 are soldered. A first underfill 171 is provided at the bottom of the chip 170 to protect the soldering structure. The chip 170 is encapsulated with a second molding compound 180. In this way, an integrated circuit (IC) package can be formed. The IC package includes a package substrate and one or more IC chips or other electronic modules mounted on the package substrate to provide electrical connections to the IC chips. For example, the IC chip in the IC package can be a system-on-chip (SoC). The IC chip is electrically coupled to other IC chips and / or other components in the IC package by being electrically coupled to the metal wires in the package substrate. The IC chip can also be electrically coupled to other circuits outside the IC package through the electrical connections of the external metal interconnections of the IC package. For example, one or more embedded capacitors can provide decoupling capacitance for the power distribution network (PDN) in the IC package to reduce the current resistance (IR) drop. Also, for example, the active wiring layer 112 of the embedded capacitor is disposed between the IC chip and the package substrate to minimize the distance between the embedded capacitor and the IC chip. This can reduce the parasitic inductance in the power distribution lines between the embedded capacitor and the IC chip to reduce the IR drop in the PDN and is also beneficial for reducing PDN noise.

[0067] Optionally, the first wiring layer 201 and the second wiring layer 202 are electrically connected by an electrical connection post 203. The first wiring layer 201 is directly connected to the active wiring layer 112. The first wiring layer 201 includes a redistribution layer 116. The active wiring layer 112 and the redistribution layer 116 are directly connected. With such a design, the integration degree is high, high-density packaging can be achieved, and the transmission path can be shortened, the transmission efficiency can be improved, and the transmission loss can be reduced. The seed layer 152 is electrically connected to the second wiring layer 202, and the seed layer 152 is located on the side of the second wiring layer 202 close to the interposer 110. The design of the seed layer 152 can improve the bonding force between the wiring layer 155 and the dielectric layer and can also enhance the electrical transmission performance of the wiring layer 155.

[0068] Figure 15 The manufacturing process of the structure shown is generally as follows: Combined with Figure 16 , an active wiring layer 112 is formed on the interposer 110; a protective glue 113 is provided on the side of the active wiring layer 112 away from the interposer 110. The protective glue 113 can be a photoresist. The interposer 110 is cut into single products.

[0069] Optionally, on the side of the grinding intermediate layer 110 away from the protective glue 113, the end face of the metal column 111 away from the protective glue 113 is flush with the surface of the intermediate layer 110.

[0070] Bond Figure 17 , mount the intermediate layer 110 and the metal component 120 on the first carrier 101; the protective glue 113 is flush with the metal component 120. The side of the intermediate layer 110 provided with the active wiring layer 112 faces away from the first carrier 101. Optionally, form the electrical connection posts 203 on the first carrier 101; the electrical connection posts 203 are located between the metal component 120 and the intermediate layer 110; the electrical connection posts 203 are flush with the metal component 120.

[0071] It can be understood that after mounting the electrical connection posts 203 on the first carrier 101 and mounting the metal component 120, the metal component 120 is located on the periphery of the electrical connection posts 203. In the subsequent encapsulation process, the metal component 120 can block the encapsulation mold flow and prevent the electrical connection posts 203 from being bent or broken by the encapsulation mold flow. Optionally, if the metal component 120 is a metal block, the mounting of the electrical connection posts 203 can also be omitted, and the electrical connection between the first wiring layer 201 and the second wiring layer 202 is realized through the metal component 120.

[0072] Form the protective layer 130 by encapsulation. Grind the protective layer 130 to expose the protective glue 113 on the intermediate layer 110. During this grinding process, the protective glue 113 plays a protective role for the active wiring layer 112, preventing metal ions generated during grinding from contaminating the active wiring layer 112.

[0073] Use the exposure and development method to form the fourth opening 115 in the protective glue 113; and form the redistribution layer 116 in the fourth opening 115; the redistribution layer 116 is electrically connected to the active wiring layer 112. Remove the protective glue 113. The protective glue 113 is a photoresist, and the fourth opening 115 can be directly formed, omitting a step of coating photoresist, which can simplify the process and improve the packaging efficiency.

[0074] Coat a dielectric layer on the redistribution layer 116, expose and develop to form a patterned opening, and form the first wiring layer 201 in the patterned opening. The first wiring layer 201 is electrically connected to the redistribution layer 116. After forming the first wiring layer 201, continue to coat the dielectric layer to form the metal layer 162 and the bumps 163, completing the preparation on one side of the dielectric layer. It should be noted that in this embodiment, the redistribution layer 116 can be regarded as a part of the first wiring layer 201, that is, the first wiring layer 201 has two layers. The number of layers of the first wiring layer 201 can be one layer or multiple layers, which is not specifically limited here. In this structure, the first wiring layer 201 is directly connected to the active wiring layer 112, with a short transmission path, high transmission efficiency, and high integration.

[0075] Flip the dielectric layer to complete the preparation of the other side. Refer to process steps S3 to S12 for the preparation of the other side. Steps S5 and S6 can be selectively omitted, that is, the insulating layer 140 may not be made.

[0076] Combined with Figure 18 , the encapsulation structure may not include the insulating layer 140. In the encapsulation structures of other embodiments, the insulating layer 140 is also an optional structure.

[0077] Combined with Figure 19 , in some embodiments, the first wiring layer 201 and the active wiring layer 112 are electrically connected through the copper pillar 114. Optionally, a protective glue 113 is provided between the first wiring layer 201 and the active wiring layer 112, and the copper pillar 114 is provided in the protective glue 113; the thickness of the protective glue 113 is greater than the height of the copper pillar 114; one end of the copper pillar 114 is electrically connected to the first wiring layer 201, and the other end is electrically connected to the active wiring layer 112. By using the copper pillar 114 for connection, compared with the direct connection between the first wiring layer 201 and the active wiring layer 112, the distance between the first wiring layer 201 and the active wiring layer 112 in the thickness direction can be increased, which is beneficial to reducing the parasitic capacitance effect.

[0078] Or, combined with Figure 20 , if the structure shown in Figure 19 is to be prepared, when preparing the interposer 110, the copper pillar 114 can be provided in the protective glue 113, and the copper pillar 114 is electrically connected to the active wiring layer 112. Optionally, the thickness of the protective glue 113 is greater than the height of the copper pillar 114. In this way, in the subsequent grinding process, the protective glue 113 can protect the copper pillar 114.

[0079] Combined with Figure 21 , the side of the interposer 110 provided with the copper pillar 114 is mounted face up on the first carrier 101. And the electrical connection pillar 203 and the metal component 120 are mounted on the first carrier 101. The electrical connection pillar 203 and the interposer 110 are both located within the metal component 120, and a protective layer 130 is formed on the first carrier 101. Referring to the above steps S11 and S12, a dielectric layer is coated on the protective glue 113 to form the first wiring layer 201, the metal layer 162, and the bump 163.

[0080] Optionally, after the protective layer 130 is formed, the aforementioned process step S3 can be adopted. First, a first groove 121 is formed in the metal component 120. Then, steps S7 to S12 are repeated, the dielectric layer is coated, the seed layer 152 is electroplated after exposure and development; the photoresist 153 is coated, the patterned opening is formed after exposure and development, and the first wiring layer 201 is formed; then the photoresist 153 and part of the seed layer 152 are removed. After that, the metal layer 162 and the bump 163 are prepared.

[0081] It should be noted that, in some embodiments, the step of mounting the electrical connection posts 203 on the first carrier 101 can also be omitted. Instead, after forming the bumps 163, the electrical connection between the first wiring layer 201 and the second wiring layer 202 is achieved by laser drilling holes in the first encapsulation body (protective layer 130) and then electroplating to fill with metal.

[0082] In some embodiments, the thickness of the protective glue 113 can also be flush with the surface of the copper pillar 114. As Figure 22 shown. In this way, when grinding the protective layer 130, the surface of the copper pillar 114 can be exposed. The protective glue 113 can also prevent metal ion contamination of the active wiring layer 112 during the grinding process.

[0083] Combined with Figure 23 and Figure 24 , in some embodiments, the first wiring layer 201 and the active wiring layer 112 are directly electrically connected. Its manufacturing process can be roughly as follows: The active wiring layer 112 is formed on the interposer 110. The number of layers of the active wiring layer 112 can be designed according to needs and can be one layer or multiple layers. When mounting the interposer 110 to the first carrier 101, the active wiring layer 112 faces the first carrier 101. On the side of the interposer 110 away from the first carrier 101, the above steps S3 to S12 are performed to form the second wiring layer 202 and the bumps 163. The interposer 110 is flipped, the first carrier 101 is removed, and the steps of S11 and S12 are performed on the side provided with the active wiring layer 112 to form the first wiring layer 201 and the bumps 163.

[0084] In other words, the process steps are relatively flexible. When mounting the interposer 110, the side provided with the active wiring layer 112 can face the first carrier 101, or the side provided with the active wiring layer 112 can face away from the first carrier 101, and no specific limitation is made here.

[0085] It can be understood that the electrical connection posts 203 can be mounted on the first carrier 101 when mounting the metal component 120. It can also be formed by drilling holes in the protective layer 130 and electroplating metal after forming the protective layer 130, or the electrical connection posts 203 can also be electroplated on the carrier, as Figure 28 , and no specific limitation is made here.

[0086] Figure 15 In the structure shown, the chip 170 is mounted on the side of the interposer 110 with the active wiring layer 112. With this setting, the transmission path is shorter, the transmission efficiency is higher, and the loss is lower.

[0087] Combined with Figure 25, the chip 170 can also be mounted on the side of the interposer 110 away from the active wiring layer 112. With this arrangement, the second wiring layer 202 is connected to the chip 170, and the first wiring layer 201 is connected to the active circuit layer. According to the capacitance calculation formula: C = εS / d; the distance d between the active wiring layer 112 and the second wiring layer 202 connected to the chip 170 is farther, which is beneficial to reducing the effects of parasitic current and parasitic capacitance, and the interference to the chip 170 is smaller.

[0088] Of course, in some embodiments, chips 170 can be mounted on both sides of the interposer 110 respectively, and no specific limitation is made here. The second encapsulation body 180 encapsulates the chip 170. The surface of the second encapsulation body 180 can be flush with the surface of the chip 170 or higher than the surface of the chip 170, that is, the chip 170 is completely covered.

[0089] Combined Figure 26 , an electrical connection solder point 117 connected to the active wiring layer 112 is provided on the interposer 110; a wiring bump 205 is provided on the first wiring layer 201 or the second wiring layer 202, and the electrical connection solder point 117 is connected to the wiring bump 205.

[0090] Optionally, the electrical connection solder point 117 on the interposer 110 is electrically connected to the first wiring layer 201, and a welding method can be used, and a second underfill 206 is scribed under the interposer 110 to protect the welding structure. The second wiring layer 202 is connected to the chip 170 through bumps 163, and a seed layer 152 is provided between the second wiring layer 202 and the dielectric layer. One end of the electrical connection post 203 is electrically connected to the first wiring layer 201, and the other end is electrically connected to the second wiring layer 202.

[0091] Combined Figures 27 to 29 , Figure 26 For the structure shown, its manufacturing method is generally as follows: Provide a first carrier 101 coated with a glue film 102, and form a metal coating 204 on the first carrier 101, which can be formed by processes such as electroplating, deposition, and sputtering. Electrical connection posts 203 and wiring bumps 205 are provided on the metal coating 204.

[0092] An active wiring layer 112 and an electrical connection solder point 117 are provided on the interposer 110. The active wiring layer 112 is electrically connected to the metal posts 111, and the electrical connection solder point 117 is electrically connected to the active wiring layer 112. Mount the metal component 120 and the interposer 110; wherein, the side of the interposer 110 with the electrical connection solder point 117 is mounted to the first carrier 101. And the electrical connection solder point 117 is welded to the corresponding wiring bump 205; a second underfill 206 is scribed under the interposer 110 to protect the welding structure.

[0093] Mount the electrical connection posts 203, and the electrical connection posts 203 are located between the interposer 110 and the metal component 120.

[0094] A protective layer 130 is formed on the first carrier 101. The above steps S3 to S12 are executed to complete the preparation of one side of the interposer 110.

[0095] The interposer 110 is flipped, the first carrier 101 is removed, and the metal plating layer 204 is removed by micro-etching to expose the wiring bumps 205. The above steps S3, S7 to S12 are executed to complete the fabrication of the other side of the interposer 110. Among them, steps S3, S7 to S10 can be selectively omitted.

[0096] Bond Figure 30 and Figure 31 , in some embodiments, after the steps of the metal layer 162 and the bumps 163 on one side of the interposer 110 are completed, it further includes: The first carrier 101 is removed, and the second carrier 103 is mounted on the side where the bumps 163 are provided; A protective film 210 is formed on the side where the first carrier 101 is removed, and the protective film 210 covers the interposer 110; the metal component 120 and the protective layer 130 are removed. The metal component 120 and the protective layer 130 can be removed in two processes, and the order of the two processes is not limited. To remove the metal component 120, an etching process can be used. To remove the protective layer 130, a photoresist stripping process can be used. It should be noted that in this embodiment, if a photoresist stripping process is required, the material of the protective layer 130 can be a sacrificial material such as photoresist.

[0097] Optionally, after removing the metal component 120 or removing the protective layer 130, the protective film 210 is removed by a debonding process. In this embodiment, the metal component 120, the protective film 210, and the protective layer 130 are removed in sequence. Of course, the protective film 210 can also be removed at the end, which is not specifically limited here.

[0098] The dielectric layer corresponding to the position of the metal component 120 is cut to form a through groove 211. A third encapsulant 212 covering the interposer is formed on the second carrier 103. The third encapsulant 212 fills the through groove 211; the through groove 211 can be used as a dicing lane to improve the dicing accuracy. The third encapsulant 212 is formed by an injection molding or printing process. It is easy to understand that during dicing, the second carrier 103 is removed, and dicing is performed along the third encapsulant 212 in the through groove 211, which can avoid damaging the interposer 110. The materials on the surface of the third encapsulant 212 and the interposer 110 are different, and the dicing machine can identify the different gray scales of the two materials, which is beneficial to improving the recognition rate of the dicing machine, and further improving the dicing accuracy and dicing efficiency.

[0099] It should be noted that in traditional reconstructed wafers, the product surface is completely covered by the plastic package and there is no scribe lane identification, so the cutting machine cannot accurately locate the scribe lane. However, in this embodiment, it is beneficial for the cutting machine to identify the scribe lane.

[0100] Combined with Figure 32 , optionally, the step of forming the wiring layer 155 on the seed layer 152 includes: Forming a first wiring layer 201 on the seed layer 152; the first wiring layer 201 includes an electrical connection end 213 extending outside the interposer 110. After the step of forming the through hole 211, an electrical connection pillar 203 is formed on the dielectric layer; the electrical connection pillar 203 is connected to the electrical connection end 213. The previously formed electrical connection end 213 can be used as the electroplating seed layer for the electrical connection pillar 203, which improves the electroplating efficiency and facilitates the formation of the electrical connection pillar 203. There is no need to additionally form a seed layer for electroplating the electrical connection pillar 203, the process is simpler, the process is simplified, and the efficiency is improved.

[0101] The third plastic package 212 covers the electrical connection pillar 203 and the interposer 110; a second wiring layer 202 is formed on the side of the interposer 110 away from the second carrier 103; the second wiring layer 202 is electrically connected to the electrical connection pillar 203. For the steps of forming the second wiring layer 202 and subsequent processes, reference can be made to the above steps S9 to S12. Among them, steps S3 to S8 can be selectively executed, and no specific limitation is made here.

[0102] Of course, the electrical connection pillar 203 can also be formed by laser grooving and filling with metal after the third plastic package 212 is formed, and no specific limitation is made here.

[0103] It should be noted that the electrical connection pillar 203 can be fabricated when forming one side of the first wiring layer 201, including but not limited to being formed by electroplating, mounting, or laser grooving and filling with metal, etc. That is, before removing the first carrier 101 and mounting the second carrier 103, the electrical connection pillar 203 has been formed on the interposer 110 product. In this way, when attaching the protective film 210, the protective film 210 covers the interposer 110 and the electrical connection pillar 203, and at the same time protects the interposer 110 and the electrical connection pillar 203, avoiding damage to the electrical connection pillar 203 and the interposer 110 during the process of removing the metal component 120.

[0104] The 2.5D substrate manufacturing method and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including: First, form a protective layer 130 that coats the intermediate layer 110, and then grind and etch the intermediate layer 110. This can prevent the sidewalls of the intermediate layer 110 from being etched during the etching process, which is beneficial to improving the bonding force between the intermediate layer 110 and the dielectric layer. In addition, forming a first groove 121 on the metal component 120 can facilitate the subsequent formation of the seed layer 152, improve the bonding force between the wiring layer 155 and the dielectric layer, and improve the packaging quality. In this embodiment, an active wiring layer 112 is provided on the intermediate layer 110, which can shorten the transmission path, improve the transmission efficiency, reduce the transmission loss, make the structure more compact, and achieve high-density integrated packaging.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; any modifications, equivalent replacements, improvements, etc. should be included in the protection scope of the present invention.

Claims

1. A method for fabricating a 2.5D substrate, characterized in that, Comprising: Providing a first carrier mounted with a metal component and an interposer; wherein, the interposer is located within the metal component; metal pillars are provided within the interposer; Forming a protective layer covering the metal component and the interposer on the first carrier; Forming a first groove in the metal component; Grinding the interposer and the protective layer so that the surfaces of the interposer and the protective layer are lower than the surface of the metal component; Forming a first dielectric layer having a first opening on the surfaces of the interposer and the protective layer; the first opening exposes the metal pillars; Forming a seed layer on the first dielectric layer; the seed layer extends to the surface of the metal component and fills the first groove; the thickness of the seed layer is equal to the depth of the first groove; Forming a wiring layer on the seed layer; Removing the seed layer except within the first opening; Forming a metal layer and bumps; wherein the metal layer and the wiring layer are electrically connected.

2. The 2.5D substrate manufacturing method according to claim 1, characterized in that The step of grinding the interposer and the protective layer includes: Grinding the interposer, the metal pillars and the protective layer to the same plane; Etching the interposer so that the surface of the interposer is lower than the surface of the protective layer and the surface of the metal pillars respectively.

3. The 2.5D substrate manufacturing method according to claim 2, wherein, After the step of etching the interposer, further included is: Forming an insulating layer on the surface of the interposer; the surface of the insulating layer is flush with the surface of the protective layer and the surface of the metal pillars respectively.

4. The 2.5D substrate manufacturing method according to claim 1, characterized in that, In the step of forming a protective layer covering the metal component and the interposer on the first carrier: The protective layer is formed between the interposer and the metal component, and between adjacent metal components; In the step of forming a seed layer on the first dielectric layer: Depositing metal by sputtering to form the seed layer; the seed layer covers the entire surface of the first dielectric layer and the surface of the metal component.

5. The 2.5D substrate manufacturing method according to claim 1, wherein The step of forming a wiring layer on the seed layer includes: Forming a photoresist on the seed layer, covering the photoresist with a photomask, and forming a second opening in the photoresist by an exposure and development process, the second opening exposing a part of the seed layer; Using an electroplating process to electroplate metal within the second opening on the seed layer to form a wiring layer; wherein, the seed layer serves as an electroplating lead, and the metal component serves as a clamping portion of the electroplating fixture; Removing the photoresist; Removing the seed layer that does not overlap with the wiring layer.

6. The method for fabricating a 2.5D substrate according to claim 1, wherein After the step of forming the metal layer and the bumps, further included is: Mounting a chip on the bumps; Encapsulating the chip to form a second encapsulation body; Cutting and separating into individual products; wherein, the cutting position is on the interposer or on the protective layer.

7. The method for manufacturing a 2.5D substrate according to claim 1, wherein In the step of providing a first carrier mounted with a metal component and an interposer: Forming an active wiring layer on the interposer; A protective adhesive is provided on a side of the active wiring layer away from the interposer; Mounting the interposer and the metal component on the first carrier; the protective adhesive is flush with the metal component.

8. The manufacturing method of the 2.5D substrate according to claim 7, characterized in that, The step of mounting the interposer and the metal component on the first carrier further includes: Form an electrical connection post on the first carrier; the electrical connection post is located between the metal component and the interposer; the electrical connection post is flush with the metal component; The side of the interposer provided with the active wiring layer faces away from the first carrier; The step of forming the first groove on the metal component further includes: Remove the first carrier and form the first groove on the side of the metal component facing away from the active wiring layer.

9. The method for manufacturing a 2.5D substrate according to claim 7, wherein After the step of mounting the interposer and the metal component on the first carrier, it further includes: Expose and develop on the protective glue to form a fourth opening; and form a redistribution layer in the fourth opening; the redistribution layer is electrically connected to the active wiring layer.

10. The method for fabricating a 2.5D substrate according to claim 7, wherein The step of providing a protective glue on the side of the active wiring layer away from the interposer further includes: Form copper pillars electrically connected to the active wiring layer on the side of the active wiring layer away from the interposer; The protective glue covers the copper pillars; Form a first wiring layer electrically connected to the copper pillars.

11. The method for fabricating a 2.5D substrate according to claim 1, wherein In the step of providing the first carrier mounted with the metal component and the interposer: Form an active wiring layer on the interposer; The side of the interposer provided with the active wiring layer is mounted to the first carrier; The step of forming the first groove on the metal component further includes: Form the first groove on the side of the metal component facing away from the first carrier.

12. The method for fabricating a 2.5D substrate according to claim 1, wherein, The step of providing the first carrier mounted with the metal component and the interposer includes: The first carrier is formed with a metal plating layer, and electrical connection posts and wiring bumps are provided on the metal plating layer; Mount the metal component and the interposer; wherein, the interposer is provided with an active wiring layer and electrical connection solder joints; the active wiring layer is electrically connected to the metal pillars, and the electrical connection solder joints are electrically connected to the active wiring layer; the electrical connection solder joints of the interposer are welded to the wiring bumps; the electrical connection posts are located between the interposer and the metal component; In the step of forming the first groove on the metal component: Form the first groove on the side of the metal component facing away from the first carrier.

13. The method for manufacturing a 2.5D substrate according to claim 1, wherein After the step of forming the metal layer and the bumps, it further includes: Remove the first carrier and mount the second carrier on the side provided with the bumps; Form a protective film on the side where the first carrier is removed, and the protective film covers the interposer; Remove the metal component and the protective layer; Remove the protective film; Cut the dielectric layer corresponding to the position of the metal component to form a through groove; Form a third encapsulation body covering the interposer on the second carrier; the third encapsulation body fills the through groove; the through groove serves as a cutting channel.

14. The method for manufacturing a 2.5D substrate according to claim 13, wherein The step of forming a wiring layer on the seed layer includes: Form a first wiring layer on the seed layer; the first wiring layer includes electrical connection ends extending outside the interposer; After the step of forming the through groove, it further includes: Form electrical connection posts on the dielectric layer; the electrical connection posts are connected to the electrical connection ends; The third encapsulation body covers the electrical connection posts; Form a second wiring layer on the side of the interposer away from the second carrier; the second wiring layer is electrically connected to the electrical connection posts.

15. An encapsulation structure, characterized in that, Prepared by using the 2.5D substrate manufacturing method according to any one of claims 1 to 14; the packaging structure includes: Interposer with metal posts; Dielectric layer, in which a wiring layer electrically connected to the metal posts is provided; Seed layer, which is provided between the wiring layer and the dielectric layer; Bump, which protrudes from the dielectric layer and is electrically connected to the wiring layer.

16. The encapsulation structure according to claim 15, wherein At least one end of the metal post exposes from the surface of the interposer; an insulating layer covers the surface of the interposer and is flush with the surface of the metal post.

17. The encapsulation structure according to claim 15, wherein A protective layer is coated on the outer periphery of the interposer, and the two surfaces of the protective layer are respectively flush with the two end surfaces of the metal post.

18. The encapsulation structure according to claim 15, wherein An active wiring layer electrically connected to the metal posts is provided on the interposer. The wiring layer includes a first wiring layer and a second wiring layer provided on both sides of the interposer. The first wiring layer is electrically connected to the active wiring layer, and the first wiring layer and the second wiring layer are respectively electrically connected to the bump; The seed layer is electrically connected to the second wiring layer, and the seed layer is located on the side of the second wiring layer close to the interposer.

19. The encapsulation structure according to claim 18, wherein A protective glue is provided between the first wiring layer and the active wiring layer, and copper posts are provided in the protective glue; one end of the copper post is electrically connected to the first wiring layer, and the other end is electrically connected to the active wiring layer; Alternatively, the first wiring layer includes a redistribution layer, and the redistribution layer is directly connected to the active wiring layer.

20. The encapsulation structure according to claim 18, wherein Also included is a chip; the bumps on at least one side of the interposer are electrically connected to the chip, and the chip is coated with a second encapsulant.

21. The encapsulation structure according to claim 18, wherein An electrical connection pad connected to the active wiring layer is provided on the interposer; a wiring bump is provided on the first wiring layer or the second wiring layer, and the electrical connection pad is connected to the wiring bump.

22. The encapsulation structure according to any one of claims 15 to 21, wherein Also included is an electrical connection column. The wiring layer includes a first wiring layer and a second wiring layer provided on both sides of the interposer. One end of the electrical connection column is electrically connected to the first wiring layer, and the other end is electrically connected to the second wiring layer.

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