Buffer, instruction processing method, processor and computer equipment

Abstract

The invention discloses a buffer, an instruction processing method, a processor and computer equipment, and relates to the technical field of chips. The buffer is an L2-level buffer in a processor and comprises a request distribution circuit and a buffer circuit, the request distribution circuit is connected with the cache circuit; the cache circuit comprises a cache unit and an operation unit; the operation unit is connected with the cache unit; the request distribution circuit is used for receiving the cache access request and sending the cache access request to the cache circuit; the cache unit is used for reading source data corresponding to the cache access request under the condition that the cache access request is a write request corresponding to the atomic operation, and inputting the read source data into the operation unit; and the arithmetic unit is used for executing atomic operation corresponding to the cache access request on the source data to obtain operation result data and writing the operation result data into the cache unit.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a buffer, an instruction processing method, a processor, and a computer device. Background Art

[0002] In a processor, when the processor receives a read / write request, the processor will access multiple levels of caches to read the request information.

[0003] In related technologies, multiple computing cores in a processor share a storage system, that is, the L2-level storage system. When receiving a read / write request, the computing cores in the processor will obtain data by interacting with the L2-level storage system.

[0004] However, in the above solution, due to the improvement of the computing power of the computing cores, there will be a situation where the required data loading bandwidth is getting larger and larger. And a large loading bandwidth will cause a relatively large parallel data access pressure on the L2-level storage system, resulting in a relatively large power consumption of the buffer. Summary of the Invention

[0005] Embodiments of this application provide a buffer, an instruction processing method, a processor, and a computer device, which can improve the efficiency of the processor in processing memory access instructions. The technical solutions are as follows.

[0006] On the one hand, a buffer is provided. The buffer is the L2-level cache in a processor, and the buffer includes: a request distribution circuit and a cache circuit;

[0007] The request distribution circuit is connected to the cache circuit;

[0008] The cache circuit includes cache units and an arithmetic unit; the arithmetic unit is connected to the cache units;

[0009] The request distribution circuit is configured to receive a cache access request and send the cache access request to the cache circuit;

[0010] The cache units are configured to, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and input the read source data into the arithmetic unit;

[0011] The arithmetic unit is configured to perform an atomic operation corresponding to the cache access request on the source data, obtain operation result data, and write the operation result data into the cache units.

[0012] On the other hand, an instruction processing method is provided. The method is executed by the buffer as described above, and the method includes:

[0013] Receive a cache access request through the request distribution circuit and send the cache access request to the cache circuit;

[0014] Through the cache unit, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and input the read source data into the arithmetic unit;

[0015] Through the arithmetic unit, perform an atomic operation corresponding to the cache access request on the source data to obtain operation result data, and write the operation result data into the cache unit.

[0016] In some embodiments, the cache circuit further includes: a first register, a multiplexer, and a second register;

[0017] Two input ends of the multiplexer are respectively connected to the first register and the arithmetic unit. The first register is also connected to the request distribution circuit and the arithmetic unit. The output end of the multiplexer is connected to the cache unit. The second register is respectively connected to the cache unit and the arithmetic unit;

[0018] The request distribution circuit is configured to write the cache access request into the first register;

[0019] The first register is configured to send the cache access request to the multiplexer and the arithmetic unit respectively;

[0020] The multiplexer is configured to send the cache access request to the cache unit when the arithmetic unit has no output;

[0021] The cache unit is configured to, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and write the read source data into the second register;

[0022] The second register is configured to send the source data to the arithmetic unit;

[0023] The arithmetic unit is configured to, when the cache access request is a write request corresponding to an atomic operation, perform an atomic operation corresponding to the cache access request on the source data to obtain operation result data, and send the operation result data to the multiplexer;

[0024] The multiplexer is configured to send the operation result data to the cache unit;

[0025] The cache unit is configured to cache the operation result data.

[0026] In some embodiments, the arithmetic unit includes: a first discriminator, an atomic data queue, an arithmetic unit, and a third register;

[0027] The first discriminator is respectively connected to the first register and the atomic data queue. Two input ends of the arithmetic unit are respectively connected to the atomic data queue and the second register. The third register is respectively connected to an output end of the arithmetic unit and an input end of the multiplexer;

[0028] The first discriminator is configured to discriminate the cache access request sent by the first register. When it is discriminated that the cache access request is a write request corresponding to an atomic operation, write the atomic operation data corresponding to the cache access request into the atomic data queue;

[0029] The arithmetic unit is configured to perform the atomic operation corresponding to the cache access request on the source data sent by the second register and the atomic operation data in the atomic data queue, obtain operation result data, and write the operation result data into the third register;

[0030] The third register is configured to send the operation result data to the multiplexer.

[0031] In some embodiments, the buffer further includes a check code generation circuit and a check circuit;

[0032] The check code generation circuit is respectively connected to an output end of the multiplexer and the cache unit. The second register is also connected to the check circuit.

[0033] In some embodiments, the cache unit is further configured to cache the data corresponding to the cache access request when the cache access request is a write request corresponding to a non-atomic operation.

[0034] In some embodiments, the buffer further includes a data output circuit, and the data output circuit is connected to the check circuit;

[0035] The cache unit is further configured to read the data corresponding to the cache access request and write the read data into the second register when the cache access request is a read request corresponding to a non-atomic operation;

[0036] The second register is further configured to send the data corresponding to the cache access request to the check circuit;

[0037] The check circuit is configured to send the data that passes the check to the data output circuit.

[0038] In some embodiments, the request distribution circuit includes: an interface circuit and an arbitration circuit;

[0039] The interface circuit is connected to the arbitration circuit, and the arbitration circuit is connected to the cache circuit;

[0040] The interface circuit is configured to send the cache access request to the arbitration circuit;

[0041] The arbitration circuit is configured to pause or block subsequent requests that conflict with the cache access request when the cache access request is a write request corresponding to an atomic operation.

[0042] In some embodiments, the arbitration circuit includes:

[0043] A shielding circuit, a request extraction circuit, a second discriminator, a delay circuit, an address management circuit, and a fourth register;

[0044] The shielding circuit is respectively connected to the request extraction circuit and the address management circuit. The request extraction circuit is also respectively connected to the second discriminator, the delay circuit, and the fourth register. The second discriminator is also respectively connected to the delay circuit and the address management circuit;

[0045] The shielding circuit is configured to receive the request sent by the interface circuit;

[0046] The request extraction circuit is configured to extract the cache access request from the shielding circuit and send the cache access request to the second discriminator and the fourth register respectively;

[0047] The fourth register is configured to send the cache access request to the cache circuit;

[0048] The second discriminator is configured to discriminate the cache access request sent by the request extraction circuit. When it is discriminated that the cache access request is a write request corresponding to an atomic operation, the cache access request is sent to the address management circuit and the delay circuit is started;

[0049] The delay circuit is configured to trigger the request extraction circuit to pause extracting new requests from the shielding circuit in the current clock cycle after delaying for N clock cycles; N is an integer greater than or equal to 2; the value of N is the difference between the first number of clock cycles and the second number of clock cycles. The first number of clock cycles is the number of clock cycles required for the processor to process a memory access operation during the processing of a write request corresponding to an atomic operation. The second number of clock cycles is the number of clock cycles required for the processor to process a memory access operation during the processing of a request corresponding to a non-atomic operation;

[0050] The address management circuit is configured to save the address of the cache access request within N - 1 clock cycles after receiving the cache access request;

[0051] The masking circuit is further configured to mask the request corresponding to the address saved by the address management circuit.

[0052] In some embodiments, the address management circuit includes: an update circuit and an atomic output table;

[0053] The update circuit is respectively connected to the atomic output table and the second discriminator, and the atomic output table is further connected to the masking circuit;

[0054] The atomic output table contains a plurality of entries, and each entry contains an address bit and a valid bit;

[0055] The update circuit is configured to, when receiving the cache access request sent by the second discriminator, write the address of the cache access request into an entry in the atomic output table, and set the valid bit in the entry where the address of the cache access request is written to N - 1;

[0056] The update circuit is further configured to, in each subsequent clock cycle, decrement the valid bit corresponding to the address of the cache access request by 1 until the valid bit corresponding to the address of the cache access request becomes 0, and remove the address of the cache access request from the atomic output table.

[0057] In some embodiments, the masking circuit includes: an address decoder, an address comparison circuit, and a gate circuit;

[0058] The interface circuit is respectively connected to the address decoder and the address comparison circuit. Two input terminals of the gate circuit are respectively connected to the address decoder and the address comparison circuit, an output terminal of the gate circuit is connected to the request extraction circuit, and the address comparison circuit is further connected to the address management circuit;

[0059] The address decoder is configured to, when the address of the request sent by the interface circuit is within a specified address segment, send the request sent by the interface circuit to the gate circuit;

[0060] The address comparison circuit is configured to compare the address of the request sent by the interface circuit with the address saved by the address management circuit, and send a first signal to the interface circuit when the address of the request sent by the interface circuit is different from the address saved by the address management circuit;

[0061] The gate circuit is used to send the request sent by the address decoder to the request extraction circuit when receiving the first signal sent by the interface circuit and receiving the request sent by the address decoder at the same time.

[0062] In some embodiments, the buffer includes M arbitration circuits and m buffer slices. Each buffer slice includes M buffer circuits, and each arbitration circuit corresponds to an address segment; m and M are integers greater than or equal to 2.

[0063] The M arbitration circuits correspond one-to-one with the M buffer circuits in each buffer slice.

[0064] In some embodiments, the interface circuit corresponds to p request output ports. The arbitration circuit includes p shielding circuits, and the p request output ports are connected to the p shielding circuits one-to-one. p is an integer greater than or equal to 2.

[0065] The request extraction circuit is used to poll and obtain the requests output by the p shielding circuits.

[0066] On the other hand, a processor is provided, and the processor includes at least one buffer as described above.

[0067] On the other hand, a computer device is provided. The computer device includes at least a processor and a memory, and the processor includes at least one buffer as described above.

[0068] The beneficial effects brought by the technical solution provided by the embodiments of the present application at least include:

[0069] A request distribution circuit and a buffer circuit are provided in the L2 cache of the processor. An arithmetic unit and a buffer unit are provided in the buffer circuit. When the request distribution circuit receives a cache access request, the above request is sent to the buffer circuit. The buffer unit reads the source data corresponding to the above request and inputs the above source data into the arithmetic unit. The arithmetic unit receives the above source data and the atomic operation corresponding to the above cache access request, obtains the operation result data, and writes the operation result data into the buffer unit. That is to say, in the above solution, during the operation of the processor on data, it is not necessary to transfer the output to the computing core. Only the source data corresponding to the request needs to be read in the L2 cache of the processor, and the atomic operation corresponding to the cache access request is completed in the arithmetic unit in the L2 cache, and the operation can be completed. This greatly improves the performance of the cache system, thereby reducing the power consumption of the entire processing system. Description of the Drawings

[0070] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0071] Figure 1 It is a schematic diagram of the memory structure of a multi-core processor;

[0072] Figure 2 It is a schematic diagram of the working interaction of an existing storage system structure;

[0073] Figure 3 It is a schematic diagram of the buffer structure provided by an exemplary embodiment of the present application;

[0074] Figure 4 It is a schematic diagram of the buffer structure provided by an exemplary embodiment of the present application;

[0075] Figure 5 It is a schematic diagram of the buffer structure provided by an exemplary embodiment of the present application;

[0076] Figure 6 It is a schematic diagram of the buffer structure provided by an exemplary embodiment of the present application;

[0077] Figure 7 It is a schematic diagram of the overall architecture related to the embodiments of the present application;

[0078] Figure 8 It is a schematic diagram of the read operation process related to the embodiments of the present application;

[0079] Figure 9 It is a schematic diagram of the write operation process related to the embodiments of the present application;

[0080] Figure 10 It is a schematic diagram of the atomic write operation process related to the embodiments of the present application;

[0081] Figure 11 It is a schematic diagram of the atomic operation pipeline related to the embodiments of the present application;

[0082] Figure 12 It is a schematic diagram of the timing relationship between an atomic operation and subsequent requests related to the embodiments of the present application;

[0083] Figure 13 It is a flowchart of the instruction processing method related to an exemplary embodiment of the present application. Detailed implementation manners

[0084] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0085] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various kinds of information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0086] First, some concepts related to this application are introduced below:

[0087] 1) Second-Level Cache (Level 2, L2): L2 is the second-level cache in the hierarchical storage structure. The L2 cache is located between the CPU and the main memory and is at a relatively high position in the storage hierarchy. Its function is to cache data from the main memory for faster provision to the CPU for use.

[0088] 2) Atomic: Atomic operation; An atomic operation refers to an operation that cannot be interrupted or divided during execution, either being completely executed successfully or not executed at all. In concurrent programming, atomic operations are an important concept for ensuring data consistency and correctness in a multi-threaded or multi-process environment. Atomic operations provide an effective way to achieve synchronized access to shared resources and avoid race conditions.

[0089] 3) Advanced eXtensible Interface (AXI): The AXI protocol defines a set of specifications, including aspects such as data transfer, register configuration, interrupt handling, and access protection. It provides a flexible and efficient interface that can support high-bandwidth and low-latency communication, enabling efficient data exchange between components such as multi-core processors, peripheral controllers, and memory controllers.

[0090] 4) Advanced Peripheral Bus (APB): APB is a common peripheral bus communication interface standard. The APB interface is typically used to connect the processor core and peripherals to achieve the transfer of data and control signals.

[0091] 5) Control Status Register (CSR): CSR is a special type of register used to store and control the control status information of the processor.

[0092] 6) Round-Robin (RR): An arbitrator design used to coordinate multiple devices to access shared resources. In this arbitration scheme, each device has the opportunity to obtain access to shared resources in one round, ensuring fairness and uniformity. The basic idea is to assign arbitration signals to each device in sequence, so that each device has the opportunity to obtain arbitration rights in one round. If a device does not obtain arbitration rights in the current round, it will wait for the next round.

[0093] 7) Atomic Outs Table: Atomic Outs Table is a data structure used to record the atomic operations being executed. It is used to ensure the atomicity of operations on shared resources in a concurrent environment. In concurrent programming, multiple threads or processes may compete for access to shared resources at the same time, and concurrent access may lead to inconsistent data or other unexpected results.

[0094] Figure 1 A schematic diagram of the memory structure of a multi-core processor is shown in FIG. Figure 1 As shown:

[0095] In the multi-core processor 110, multiple computing cores 101 ( Figure 1 3 are shown in the figure), multiple L caches ( Figure 1 3) and an L2 cache, computing core 0, computing core 1 and computing core 2 each include an L1 cache 102, and L1 cache 102 includes an L1 instruction cache and an L1 data cache. L2 cache 103 does not distinguish between instructions and data, and L2 cache 103 is shared by multiple computing cores.

[0096] Please refer to Figure 2 , which shows a schematic diagram of the working interaction of an existing storage system structure. Figure 2 As shown in the figure above, the existing solution is a two-level storage system structure. The computing core 0 and the computing core 1 are two artificial intelligence (AI) computing cores, each of which has an L1 cache. The two computing cores share an L2 cache for data exchange. If you want to operate on the data in the L2 cache, that is, after operating on the data in the L2 cache, write the result to the original storage location, in a possible solution, you can perform the following operations:

[0097] 1) The computing core initiates a data move request to load the data to be operated in the L2 cache into the L1 cache of the computing core;

[0098] 2) The computing core initiates a load request to transfer the data in the L1 cache to the register bank inside the computing core;

[0099] 3) The computing core completes the corresponding operation through computing instructions;

[0100] 4) The computing core initiates a store request to write the computing result into the L1 cache;

[0101] 5) The computing core initiates a data transfer request to transfer the computing result in the L1 cache to the L2 cache.

[0102] However, in the above solution, to complete an operation, the storage system needs to perform a large amount of data transfer. Specifically, the data needs to be repeatedly transferred between the L2 cache, the L1 cache, and the register bank, resulting in very low operation efficiency and thus low data operation performance of the processor.

[0103] In addition, the operation of transferring a large amount of data between memories is essentially a repeated read and write operation on the on-chip memory, and the power consumption of the read and write operation of the memory is very large, which makes the power consumption of the entire chip relatively high when processing the accumulation service.

[0104] Please refer to Figure 3 , which shows a schematic diagram of the cache structure provided by an exemplary embodiment of the present application. The cache is the L2 cache in the processor, and the cache includes: a request distribution circuit 301 and a cache circuit 302; the cache circuit 302 includes a cache unit 302a and an arithmetic unit 302b.

[0105] One or more output ports of the request distribution circuit 301 are connected to one or more input ports of the cache circuit 302, and the request information is transmitted from the above output ports of the request distribution circuit 301 to the above input ports of the cache circuit 302, so that the request information is input into the cache circuit 302.

[0106] One or more output ports of the cache unit 302a are connected to one or more input ports of the arithmetic unit 302b, and the source data read corresponding to the above request is transmitted from the above output ports of the cache unit 302a to the above input ports of the arithmetic unit 302b, so that the source data is input into the arithmetic unit 302b.

[0107] One or more output ports of the arithmetic unit 302b are connected to one or more input ports of the cache unit 302a, and the obtained operation result data is transmitted from the above output ports of the arithmetic unit 302b to the above input ports of the cache unit 302a, so that the operation result data is input into the cache unit 302a.

[0108] The request distribution circuit 301 is configured to receive a cache access request and send the cache access request to the cache circuit 302.

[0109] After receiving the cache access request, the request distribution circuit 301 sends the cache access request to the cache circuit 302. The cache access request may include, but is not limited to, a read request, a write request, and an atomic operation request, etc.

[0110] The cache unit 302a is configured to read the source data corresponding to the cache access request and input the read source data into the arithmetic unit 302b when the cache access request is a write request corresponding to an atomic operation. The cache unit 302a receives the cache access request transmitted by the request distribution circuit 301. When the cache access request is a write request corresponding to an atomic operation, the cache unit 302a reads the source data corresponding to the cache access request from the data already stored therein and inputs the read source data into the arithmetic unit 302b. In some embodiments, the above source data may be the actual data in the program.

[0111] The arithmetic unit 302b is configured to perform an atomic operation corresponding to the cache access request on the source data, obtain the operation result data, and write the operation result data into the cache unit 302a.

[0112] The operations in the arithmetic unit 302b may include, but are not limited to, logical operations and numerical operations on the source data. The logical operations may be, for example, AND operation, OR operation, NOT operation, and XOR operation, etc. The numerical operations may be addition operation, subtraction operation, multiplication operation, division operation, remainder operation, and power operation, etc.

[0113] The atomic operation may be an atomic operation of a specified type. For example, the atomic operation may be an atomic operation of the addition type.

[0114] In an embodiment of the present application, a request distribution circuit 301 and a cache circuit 302 are respectively arranged in the L2 cache of the processor. An arithmetic unit 302b and a cache unit 302a are arranged in the cache circuit 302. When the request distribution circuit 301 receives a cache access request, the above request is sent to the cache circuit 302. The cache unit 302a reads the source data corresponding to the above request and inputs the above source data into the arithmetic unit 302b. The arithmetic unit 302b receives the above source data and the atomic operation corresponding to the above cache access request, obtains the operation result data, and writes the operation result data into the cache unit 302a. That is to say, in the above solution, during the atomic operation of data by the processor, it is not necessary to transfer the output to the computing core. Only the source data corresponding to the request needs to be read in the L2 cache of the processor, and the atomic operation corresponding to the cache access request is completed in the arithmetic unit 302b in the L2 cache, and the arithmetic operation can be completed. This greatly improves the usage performance of the cache system, thereby reducing the power consumption of the entire processing system.

[0115] Based on Figure 3 the embodiment shown, please refer to Figure 4 , which shows a schematic diagram of the cache structure provided by an exemplary embodiment of the present application. This cache is the L2 cache in the processor, as Figure 4 shown. Figure 3 The cache circuit 302 in the embodiment shown further includes: a first register 3021, a multiplexer 3022, and a second register 3023.

[0116] Two input ends of the multiplexer 3022 are respectively connected to an output port of the first register 3021 and an output port of the arithmetic unit 302b. The cache access request is transferred from the above output port of the first register 3021 to the above input port of the multiplexer 3022, so that the cache access request is input into the multiplexer 3022.

[0117] In the case where the cache access request is a write request corresponding to an atomic operation, after the arithmetic unit 302b performs the atomic operation corresponding to the cache access request on the source data, the obtained operation result data is transferred from the above output port of the arithmetic unit 302b to the above other input port of the multiplexer 3022, so that the operation result data is input into the multiplexer 3022.

[0118] Another input port of the first register 3021 is also connected to an output port of the request distribution circuit 301. The cache access request is transferred from the above output port of the request distribution circuit 301 to the above input port of the first register 3021, so that the cache request access request is input into the first register 3021.

[0119] One output port of the first register 3021 is connected to one input port of the arithmetic unit 302b; the cache access request is transmitted from the above output port of the first register 3021 to the above input port of the arithmetic unit 302b, so that the cache request access request is input into the arithmetic unit 302b.

[0120] One output port of the multiplexer 3022 is connected to one input port of the cache unit 302a; when the arithmetic unit 302b has no output, the cache access request is transmitted from the above output port of the multiplexer 3022 to the above input port of the cache unit 302a, so that the cache access request enters the cache unit 302a.

[0121] Two output ports of the second register 3023 are respectively connected to one input port of the cache unit 302a and one input port of the arithmetic unit 302b; the source data is transmitted from the above output port of the second register 3023 to the above input port of the arithmetic unit 302b, so that the source data is input into the arithmetic unit 302b.

[0122] The request distribution circuit 301 is used to write the cache access request into the first register 3021; for example, after the request distribution circuit 301 receives the cache access request sent by the bus, it writes the above cache access request into the first register 3021.

[0123] The first register 3021 is used to send the cache access request to the multiplexer 3022 and the arithmetic unit 302b respectively; for example, after the first register 3021 receives the cache access request sent by the request distribution circuit 301, it can send the cache access request to the multiplexer 3022 and the arithmetic unit 302b at the same time.

[0124] The multiplexer 3022 is used to send the cache access request to the cache unit 302a when the arithmetic unit 302b has no output.

[0125] Among them, the situation where the arithmetic unit 302b has no output can be that neither the first register 3021 nor the second register 3023 sends a request / data to the arithmetic unit 302b, and the arithmetic unit 302b does not receive any data and cannot perform operations. At this time, the arithmetic unit 302b has no output.

[0126] The above multiplexer 3022, when the arithmetic unit 302b has no output, for example, when the multiplexer 3022 only receives the cache access request transmitted by the first register 3021, sends the cache access request to the cache unit 302a.

[0127] The cache unit 302a is configured to read the source data corresponding to the cache access request and write the read source data into the second register 3023 when the cache access request is a write request corresponding to an atomic operation; that is, when the cache access request is a write request corresponding to an atomic operation, the cache unit 302a can query the source data corresponding to the write request from the data cached in itself and write the read source data into the second register 3023.

[0128] The second register 3023 is configured to send the source data to the arithmetic unit 302b.

[0129] The arithmetic unit 302b is configured to perform an atomic operation corresponding to the cache access request on the source data, obtain the operation result data, and send the operation result data to the multiplexer 3022 when the cache access request is a write request corresponding to an atomic operation.

[0130] For example, the arithmetic unit 302b performs an atomic write operation on the source data, which is to write the source data into the cache and ensure that this write operation is uninterruptible.

[0131] In this embodiment, by using the atomic write operation, the arithmetic unit 302b can ensure that the source data will not be interrupted during the write operation, thereby avoiding other threads from reading inconsistent data during the write process, which helps to maintain the integrity and consistency of the data.

[0132] On the other hand, the specific operation content can be, but is not limited to, logical operations and numerical operations on the source data. The logical operations can be AND operation, OR operation, NOT operation, and XOR operation; the numerical operations can be addition operation, subtraction operation, multiplication operation, division operation, remainder operation, and power operation.

[0133] For example, the arithmetic unit 302b can perform an atomic write accumulation operation on the source data. When performing the accumulation calculation operation on the source data, ensure that this operation is uninterruptible. In this embodiment, the accumulation operation may involve multiple steps, and the atomic write ensures the integrity and reliability of the operation, thereby ensuring the consistency of the data.

[0134] The multiplexer 3022 is configured to send the operation result data to the cache unit 302a; for example, when the arithmetic unit 302b has an output (i.e., the above operation result data), the multiplexer 3022 preferentially writes the operation result data output by the arithmetic unit 302b into the cache unit 302a; that is, when the multiplexer 3022 receives both the cache access request and the operation result data output by the arithmetic unit 302b at the same time, it can preferentially write the operation result data into the cache unit 302a and delay sending the cache access request to the cache unit 302a.

[0135] A cache unit 302a for caching operation result data. After receiving the operation result data sent by the multiplexer, the cache unit 302a stores the above operation result data inside the cache unit 302a. The cache unit 302a may include one or more stacks for caching any received data.

[0136] In the embodiment of the present application, the cache circuit 302 further includes a first register 3021, a multiplexer 3022, and a second register 3023. The multiplexer 3022 preferentially outputs the result of the arithmetic unit 302b according to the data respectively input by the first register 3021 and the arithmetic unit 302b when the cache access request is a write request corresponding to an atomic operation, ensuring the execution of the atomic operation, thereby ensuring data consistency and reliability, avoiding data competition and errors, and improving the performance of the system.

[0137] Based on Figure 4 the cache, please refer to Figure 5 , which shows a schematic diagram of the cache structure provided by an exemplary embodiment of the present application. The arithmetic unit 302b includes: a first discriminator 302b1, an atomic data queue 302b2, an arithmetic unit 302b3, and a third register 302b4.

[0138] One input port of the first discriminator 302b1 is connected to one output port of the first register 3021. The cache access request is transmitted from the above output port of the first register 3021 to the above input port of the first discriminator 302b1, so that the cache access is input into the first discriminator 302b1.

[0139] One output port of the first discriminator 302b1 is connected to one input port of the atomic data queue 302b2. When it is determined that the cache access request is a write request corresponding to an atomic operation, the atomic operation data corresponding to the cache access request is transmitted from the above output port of the first discriminator 302b1 to the above input port of the atomic data queue 302b2, so that the atomic operation data corresponding to the cache access request is input into the first discriminator 302b1.

[0140] One input port of the arithmetic unit 302b3 is connected to one output port of the atomic data queue 302b2. The atomic operation data in the atomic data queue 302b2 is transmitted from the above output port of the atomic data queue 302b2 to the above input port of the arithmetic unit 302b3, so that the atomic operation data in the atomic data queue 302b2 is input into the arithmetic unit 302b3.

[0141] Another input port of the arithmetic unit 302b3 is connected to an output port of the second register 3023. The source data sent by the second register 3023 is transmitted from the above output port of the second register 3023 to the above input port of the arithmetic unit 302b3, so that the source data sent by the second register 3023 is input into the arithmetic unit 302b3.

[0142] The first discriminator 302b1 is configured to discriminate the cache access request sent by the first register 3021. When it is discriminated that the cache access request is a write request corresponding to an atomic operation, the atomic operation data corresponding to the cache access request is written into the atomic data queue 302b2.

[0143] Among them, the above cache access request carries a signal bit, which is used to indicate whether the cache access request is an atomic operation request. The first discriminator 302b1 receives the cache access request sent by the first register 3021, discriminates the signal bit in the above cache access request, and when it is discriminated that the cache access request is a write request corresponding to an atomic operation, the atomic operation data corresponding to the cache access request is written into the atomic data queue 302b2.

[0144] Exemplarily, the above signal bit can be a 1-bit signal bit. When the above signal bit is 1, it indicates that the cache access request is an atomic operation request. The first discriminator 302b1 recognizes that the signal bit in the cache access request is 1, indicating that the write request corresponds to an atomic operation request. The first discriminator 302b1 writes the atomic operation data corresponding to the request into the atomic data queue 302b2.

[0145] Or, when the above signal bit is 0, it indicates that the cache access request is an atomic operation request. The first discriminator 302b1 recognizes that the signal bit in the cache access request is 0, indicating that the write request corresponds to an atomic operation request. The first discriminator 302b1 writes the atomic operation data corresponding to the request into the atomic data queue 302b2. In this embodiment, the first discriminator 302b1 pre-judges the request type according to the signal bit in the cache access request, and then performs the write operation, pre-allocates resources, adopts a more effective cache management strategy to support the fast execution of atomic operations, and avoids unnecessary synchronization and communication overhead.

[0146] The arithmetic unit 302b3 is configured to perform the atomic operation corresponding to the cache access request on the source data sent by the second register 3023 and the atomic operation data in the atomic data queue 302b2, obtain the operation result data, and write the operation result data into the third register 302b4.

[0147] For example, the arithmetic unit 302b3 receives the source data sent by the second register 3023, which is a half-precision floating-point number, and receives the atomic operation data in the atomic data queue 302b2, which is another half-precision floating-point number. The operation requirement is to perform an addition operation on the two received data. At this time, the two floating-point numbers are input simultaneously, and then a parallel floating-point addition operation is performed. The arithmetic unit 302b3 outputs the sum of the two floating-point numbers, that is, a half-precision floating-point number.

[0148] In this embodiment, by processing the source data of the second register 3023 and the atomic operation data in the atomic data queue 302b2 in the arithmetic unit, parallel processing and asynchronous operations can be realized. While processing a cache access request, other operations can continue to execute, which helps to improve the performance, concurrency, and consistency of the system, thereby improving the overall efficiency of the system.

[0149] The third register 302b4 is used to send the operation result data to the multiplexer 3022.

[0150] In the embodiment of the present application, the first discriminator 302b1 in the arithmetic unit 302b receives the write request transmitted by the first register 3021. When it is determined that the cache access request is a write request corresponding to an atomic operation, the atomic operation data corresponding to the cache access request is transmitted from the atomic data queue 302b2 to the arithmetic unit 302b3. The arithmetic unit then executes the atomic operation corresponding to the request according to the atomic operation data and the source data sent by the second register 3023, and transmits the result to the third register 302b4. The components in the arithmetic unit 302b provide concurrent control, avoid race conditions, ensure the integrity of operations, and improve performance, improving the reliability and efficiency of executing atomic accumulation and other operations in a multi-threaded or multi-core environment.

[0151] Based on Figure 4 the buffer, please refer to Figure 6 , which shows a schematic diagram of the buffer structure provided by an exemplary embodiment of the present application.

[0152] The buffer further includes a check code generation circuit 3024 and a check circuit 3025;

[0153] An input port of the check code generation circuit 3024 is connected to an output port of the multiplexer 3022; the cache access request selected by the multiplexer 3022 is transmitted from the above output port of the multiplexer 3022 to the above input port of the check code generation circuit 3024, so that the above cache access request is input into the check code generation circuit 3024.

[0154] One output terminal of the check code generation circuit 3024 is connected to an input port of the buffer unit 302a; one output port of the second register 3023 is connected to an input port of the check circuit 3025; data is transmitted from the above output port of the second register 3023 to the above input port of the check circuit 3025, so that the data is input into the check circuit 3025.

[0155] The check code generation circuit 3024 processes the data to be sent using an algorithm for generating a check code related to the data, and the above check code may be a cyclic redundancy check, a longitudinal redundancy check, and a horizontal redundancy check.

[0156] The check circuit 3025 is used to process the received data and the attached check code to determine whether the data has been interfered with or damaged during transmission or storage. If the check circuit 3025 detects an error, it can locate and repair the error according to the type of the check code, or transmit the error information to the bus to notify the system that an error has occurred; for example, for a cyclic redundancy check, the check circuit 3025 can recalculate the check code using the same generating polynomial, compare the newly calculated check code with the received check code, and detect whether there is an error in the data.

[0157] In the embodiment of the present application, after detecting the correctness of the data through the check code generation circuit 3024 and the check circuit 3025, and promptly correcting or feeding back the error situation, the accuracy of the data can be ensured, thereby ensuring the reliability of data transmission and improving the reliability of the system. The buffer unit 302a is further configured to cache the data corresponding to the cache access request when the cache access request is a write request corresponding to a non-atomic operation.

[0158] In the embodiment of the present application, when the cache access request transmitted by the check code generation circuit 3024 received by the buffer unit 302a is a write request corresponding to a non-atomic operation, the data corresponding to the above cache access request is still cached, which ensures the effective execution of other types of cache access requests, expands the types of requests that the entire storage system can execute, and comprehensively improves the functionality of the storage system.

[0159] The buffer further includes a data output circuit 301c, and the data output circuit 301c is connected to the check circuit 3025; one or more input ports of the data output circuit 301c are connected to one or more output ports of the check circuit 3025, and the data corresponding to the cached access request after verification is transmitted from the above output port of the check circuit 3025 to the input port of the data output circuit 301c, so that the data corresponding to the cached access request after verification is input into the data output circuit 301c.

[0160] Among them, the above data output circuit 301c may be a neural network output layer circuit, and the above neural network output layer may be a Sigmoid output layer, a Softmax output layer, a linear output layer, a Tanh output layer, or other custom output layers.

[0161] The cache unit 302a is further configured to, when the cache access request is a read request corresponding to a non-atomic operation, read the data corresponding to the cache access request and write the read data into the second register 3023.

[0162] The second register 3023 is further configured to send the data corresponding to the cache access request to the verification circuit 3025.

[0163] The verification circuit 3025 is configured to send the data that passes the verification to the data output circuit 301c.

[0164] In the embodiment of the present application, when the cache access request is a read request corresponding to a non-atomic operation, the second register 3023 still transfers the data corresponding to the request, and the verification circuit 3025 transfers the data after verification to the data output circuit 301c to complete the read request corresponding to the non-atomic operation, ensuring the accuracy of the requested data. On the other hand, it also expands the types of cache access requests that the system can execute, ensuring the functionality of the system.

[0165] The request distribution circuit 301 includes: an interface circuit 301a and an arbitration circuit 301b.

[0166] One or more output ports of the interface circuit 301a are connected to one or more input ports of the arbitration circuit 301b. The cache access request is passed to one or more input ports of the arbitration circuit 301b through one or more output ports of the interface circuit 301a, so that the cache access request enters the arbitration circuit 301b.

[0167] One or more output ports of the arbitration circuit 301b are connected to one or more input ports of the cache circuit 302; the arbitration result is passed to the above input ports of the cache circuit 302 through the above output ports of the arbitration circuit 301b, so that the arbitration result enters the cache circuit 302; the above arbitration result may be a cache access request.

[0168] The interface circuit 301a is configured to send the cache access request to the arbitration circuit 301b.

[0169] The arbitration circuit 301b is configured to, when the cache access request is a write request corresponding to an atomic operation, pause or block subsequent requests that conflict with the cache access request.

[0170] In an embodiment of the present application, when the cache access request is a write request corresponding to an atomic operation, the arbitration circuit 301b pauses or masks subsequent requests that conflict with the cache access request, ensuring that the above cache access request will not be interfered with by other requests in terms of data integrity operations before it is executed completely, ensuring that the above cache access request can be effectively carried out, guaranteeing the atomic operation of the above write request, and contributing to ensuring the stability of the system.

[0171] The arbitration circuit 301b includes: a masking circuit 301b1, a request extraction circuit 301b2, a second discriminator 301b3, a delay circuit 301b4, an address management circuit 301b5, and a fourth register 301b6.

[0172] One or more output ports of the masking circuit 301b1 are connected to one or more input ports of the request extraction circuit 301b2; the cache access request is transmitted from the above output port of the masking circuit 301b1 to the above input port of the request extraction circuit 301b2, enabling the cache access request to be input into the request extraction circuit 301b2.

[0173] One or more input ports of the masking circuit 301b1 are connected to one or more output ports of the address management circuit 301b5; the address of the cache access request stored in the address management circuit 301b5 is transmitted from the above output port of the address management circuit 301b5 to the above input port of the masking circuit 301b1, enabling the above address to be input into the masking circuit 301b1.

[0174] One or more output ports of the request extraction circuit 301b2 are connected to one input port of the second discriminator 301b3; the address of the cache access request is transmitted from the above output port of the request extraction circuit 301b2 to the above input port of the second discriminator 301b3, enabling the address of the cache access request to be transmitted into the second discriminator 301b3.

[0175] One output port of the delay circuit 301b4 is connected to one input port of the request extraction circuit 301b2; the pause request is transmitted from the above output port of the delay circuit 301b4 to the above input port of the request extraction circuit 301b2, enabling the pause request to be input into the request extraction circuit 301b2, and the above pause request can trigger the request extraction circuit to pause extracting new requests from the masking circuit in the current clock cycle.

[0176] One output port of the request extraction circuit 301b2 is connected to one input port of the fourth register 301b6; the cache access request is transmitted from the above output port of the request extraction circuit 301b2 to the above input port of the fourth register 301b6, enabling the cache access request to be input into the fourth register 301b6.

[0177] One output port of the second discriminator 301b3 is connected to one input port of the delay circuit 301b4; for example, the start signal is transmitted from the above output port of the second discriminator 301b3 to the above input port of the delay circuit 301b4, enabling the start signal to enter the delay circuit 301b4; wherein, the above delay signal can be issued when the second discriminator 301b3 determines that the cache access request is a write request corresponding to an atomic operation, and is used to start the delay circuit 301b4.

[0178] One output port of the second discriminator 301b3 is connected to one input port of the address management circuit 301b5; for example, when the second discriminator 301b3 determines that the cache access request is a write request corresponding to an atomic operation, the cache access request is transmitted from the above output port of the second discriminator 301b3 to the above input port of the address management circuit 301b5, enabling the cache access request to enter the address management circuit 301b5.

[0179] The shielding circuit 301b1 is used to receive the requests sent by the interface circuit 301a.

[0180] The request extraction circuit 301b2 is used to extract the cache access request from the shielding circuit 301b1 and send the cache access request to the second discriminator 301b3 and the fourth register 301b6 respectively.

[0181] The fourth register 301b6 is used to send the cache access request to the cache circuit 302.

[0182] The second discriminator 301b3 is used to discriminate the cache access request sent by the request extraction circuit. When it determines that the cache access request is a write request corresponding to an atomic operation, it sends the cache access request to the address management circuit 301b5 and starts the delay circuit.

[0183] Wherein, the above cache access request can carry a signal bit, which is used to indicate whether the cache access request is a write request corresponding to an atomic operation. The second discriminator 301b3 receives the cache access request sent by the request extraction circuit 301b2, discriminates the signal bit in the above cache access request, and when it determines that the cache access request is a write request corresponding to an atomic operation, it sends the cache access request to the address management circuit 301b5.

[0184] Exemplarily, the above signal bit can be a 1-bit signal bit. When the above signal bit is 1, it indicates that the cache access request is an atomic operation request. When the second discriminator 301b3 recognizes that the signal bit in the cache access request is 1, indicating that the write request corresponds to an atomic operation request, the second discriminator 301b3 sends the cache access request to the address management circuit 301b5.

[0185] Alternatively, when the above signal bit is 0, indicating that the cache access request is an atomic operation request, the second discriminator 301b3 recognizes that the signal bit in the cache access request is 0, indicating that the write request corresponds to an atomic operation request, and the second discriminator 301b3 sends the cache access request to the address management circuit 301b5.

[0186] In this embodiment, the second discriminator 301b3 determines the request type in advance according to the signal bit in the cache access request, then performs the sending operation, and allocates resources in advance, adopting a more efficient cache management strategy to support the fast execution of atomic operations and avoid unnecessary synchronization and communication overhead.

[0187] The delay circuit 301b4 is used to trigger the request extraction circuit to pause extracting new requests from the shielding circuit in the current clock cycle after delaying for N clock cycles; N is an integer greater than or equal to 2; the value of N is the difference between the first clock cycle number and the second clock cycle number; the first clock cycle number is the number of clock cycles required for the processor to process the memory access operation during the processing of the write request corresponding to the atomic operation; the second clock cycle number is the number of clock cycles required for the processor to process the memory access operation during the processing of the request corresponding to the non-atomic operation.

[0188] Exemplarily, during the processing of the write request corresponding to the atomic operation by the processor, the number of clock cycles required for the processor to process the memory access operation is 7, and during the processing of the request corresponding to the non-atomic operation by the processor, the number of clock cycles required for the processor to process the memory access operation is 3. Then, the delay circuit 301b needs to delay for 4 clock cycles and then trigger the request extraction circuit to pause extracting new requests from the shielding circuit in the current clock cycle. The address management circuit 301b5 is used to save the address of the cache access request within N - 1 clock cycles after receiving the cache access request.

[0189] Exemplarily, the first clock cycle is 7, the second clock cycle is 4, the delay circuit 301b needs to delay for 4 clock cycles and then trigger the request extraction circuit to pause extracting new requests from the shielding circuit in the current clock cycle, and the address management circuit 301b5 saves the address of the cache access request within 3 clock cycles after receiving the cache access request.

[0190] The shielding circuit 301b1 is further used to shield the request corresponding to the address saved by the address management circuit 301b5;

[0191] Exemplarily, the first clock cycle is 7 and the second clock cycle is 4. After the delay circuit 301b needs to delay for 4 clock cycles, it triggers the request extraction circuit to pause extracting new requests from the shielding circuit within the current clock cycle. When receiving the cache access request at the 4th clock cycle, the shielding circuit 301b1 compares the address corresponding to the cache access request sent by the interface circuit 301a with the address stored in the address management circuit 301b5. If the above two addresses are exactly the same, the shielding circuit 301b1 shields the request.

[0192] In the embodiment of the present application, through each component in the arbitration circuit 301b, the requests received after the atomic operation are judged, and the requests conflicting with the atomic operation requests are shielded or paused, avoiding address conflicts, ensuring that the atomic operation requests can not be interfered by other data, and ensuring the stability of the system for executing atomic operations.

[0193] The address management circuit 301b5 includes: an update circuit 301b51 and an atomic output table 301b52.

[0194] One or more output ports of the update circuit 301b51 are connected to one or more input ports of the atomic output table 301b52.

[0195] One input port of the update circuit 301b51 is connected to one output port of the second discriminator 301b3. The discrimination result is transmitted from the above output port of the second discriminator 301b3 to the above input port of the update circuit 301b51, so that the discrimination result is input into the update circuit 301b51; the above discrimination result is the discrimination result of whether the cache access request is a write request corresponding to the atomic operation.

[0196] One or more output ports of the atomic output table 301b52 are connected to one or more input ports of the shielding circuit 301b1. One or more address entries are transmitted from the above output port of the atomic output table 301b52 to the above input port of the shielding circuit 301b1, so that one or more address entries are input into the shielding circuit 301b1.

[0197] The atomic output table 301b52 contains multiple entries, and each entry contains an address bit and a valid bit; wherein, the number of the above entries can be N, and N is an integer greater than or equal to 2; the value of N is the difference between the number of the first clock cycles and the number of the second clock cycles; the number of the first clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the write request corresponding to the atomic operation; the number of the second clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the request corresponding to the non-atomic operation.

[0198] Each of the above entries corresponds to the cache access request information historically received by the address management circuit 301b5, where the address bit stores the address corresponding to the cache access request; the valid bit can be a 1-bit signal bit, used to indicate whether the address is valid. When the valid bit is 0, it indicates invalid, and the rest are valid. Invalid means that the access request corresponding to the address cannot perform a cache access request, and the address of the cache access request needs to be removed from the atomic output table 301b52.

[0199] The update circuit 301b51 is used to, when receiving a cache access request sent by the second discriminator, write the address of the cache access request into an entry in the atomic output table 301b52, and set the valid bit in the entry where the address of the cache access request is written to N - 1.

[0200] The update circuit 301b51 is also used to, in each subsequent clock cycle, decrement the valid bit corresponding to the address of the cache access request by 1 until the valid bit corresponding to the address of the cache access request is 0, and remove the address of the cache access request from the atomic output table 301b52.

[0201] In the embodiment of the present application, the update circuit 301b51 updates the entry information in the atomic output table 301b52 in real time according to the clock cycle. When an invalid entry appears, the invalid entry is removed in time, ensuring that the information in the atomic output table 301b52 is all valid information, avoiding the problem that invalid data occupies memory and causes low execution efficiency of the entire cache access request, and improving the efficiency of system processing.

[0202] The masking circuit 301b1 includes an address decoder 301b11, an address comparison circuit 301b12, and a gate circuit 301b13.

[0203] One or more output ports of the interface circuit 301a are connected to one or more input ports of the address decoder 301b11; the cache access request is transmitted from the above output port of the interface circuit 301a to the address decoder 301b11, so that the cache access request is input into the address decoder 301b11.

[0204] One or more output ports of the interface circuit 301a are connected to one or more input ports of the address comparison circuit 301b12; the cache access request is transmitted from the above output port of the interface circuit 301a to the address comparison circuit 301b12, so that the cache access request is input into the address comparison circuit 301b12.

[0205] Two input terminals of the gate circuit 301b13 are respectively connected to an output port of the address decoder 301b11 and an output port of the address comparison circuit 301b12.

[0206] The determination result of the address comparison circuit 301b12 and the address decoder 301b11 are simultaneously transmitted to different input ports of the gate circuit 301b13 through different output ports respectively; wherein, the above determination result is used to indicate whether the address corresponding to the cache access request is consistent with the valid address in the address management circuit 301b5.

[0207] One or more output terminals of the gate circuit 301b13 are connected to one or more input ports of the request extraction circuit 301b2; one input port of the address comparison circuit 301b12 is connected to one output port of the address management circuit 301b5; the valid address in the address management circuit 301b5 is transmitted to the above input port of the address comparison circuit 301b12 through the above output port of the address management circuit 301b5 and enters the address comparison circuit 301b12.

[0208] The address decoder 301b11 is used to send the request sent by the interface circuit 301a to the gate circuit 301b13 when the address of the request sent by the interface circuit 301a is within the specified address segment.

[0209] Exemplarily, a complete address is 32 bits, and the address data of the request sent here is from the 8th to the 12th bit. According to this data segment, it can be judged which specified address segment this address belongs to.

[0210] The address comparison circuit 301b12 is used to compare the address of the request sent by the interface circuit 301a with the address saved in the address management circuit 301b5, and send a first signal to the interface circuit 301a when the address of the request sent by the interface circuit 301a is different from the address saved in the address management circuit 301b5.

[0211] In a possible implementation manner, the above first signal can be a 1-bit signal bit. When the first signal is 0, it indicates that the address of the request sent by the interface circuit 301a is the same as the address saved in the address management circuit 301b5; when the first signal is 1, it indicates that the address of the request sent by the interface circuit 301a is different from the address saved in the address management circuit 301b5.

[0212] In another possible implementation manner, the first signal can be in any form. Only when the address of the request sent by the interface circuit 301a is different from the address saved in the address management circuit 301b5, will the interface signal 301a receive the first signal.

[0213] The gate circuit 301b13 is used to send the request sent by the address decoder 301b11 to the request extraction circuit 301b2 when receiving the first signal sent by the interface circuit 301a and simultaneously receiving the request sent by the address decoder 301b11.

[0214] In a possible case, the gate circuit 301b13 receives a first signal and a request sent by the address decoder 301b11, where the first signal indicates that the address of the request sent by the interface circuit 301a is different from the address stored in the address management circuit 301b5. The gate circuit 301b13 sends the request sent by the address decoder 301b11 to the request extraction circuit 301b2.

[0215] In a possible case, the gate circuit 301b13 receives a first signal and a request sent by the address decoder 301b11, where the first signal indicates that the address of the request sent by the interface circuit 301a is the same as the address stored in the address management circuit 301b5. The request sent by the address decoder 301b11 will not be sent by the gate circuit 301b13 to the request extraction circuit 301b2.

[0216] In a possible case, the gate circuit 301b13 only receives the first signal and does not receive the request sent by the address decoder 301b11. The gate circuit 301b13 will not send a request.

[0217] In a possible case, the gate circuit 301b13 only receives the request sent by the address decoder 301b11 and does not receive the first signal. The gate circuit 301b13 will not send a request.

[0218] In the embodiment of the present application, the gate circuit 301b13 makes a combined determination on the data or signals sent by the address decoder 301b11 and the address comparison circuit 301b12, and then outputs. Among them, the address decoder 301b11 and the address comparison circuit 301b12 execute independently, reducing the coupling degree between the two parts, and making a determination and output in this part, processing the cache access request in advance, reducing the working pressure of subsequent components, and improving the overall performance of the system.

[0219] The buffer contains M arbitration circuits 301b and m buffer slices. Each buffer slice contains M buffer circuits. Each arbitration circuit 301b corresponds to an address segment; m and M are integers greater than or equal to 2; the M arbitration circuits 301b correspond one-to-one with the M buffer circuits in each buffer slice.

[0220] In the embodiment of the present application, the buffer contains multiple arbitration circuits 301b and multiple buffer slices, which can process multiple requests in parallel, improving the overall throughput and performance of the system.

[0221] The interface circuit 301a corresponds to p request output ports. The arbitration circuit 301b includes p masking circuits 301b1, and the p request output ports are connected to the p masking circuits 301b1 in a one-to-one correspondence. p is an integer greater than or equal to 2; The request extraction circuit 301b2 is used to poll and obtain the requests output by the p masking circuits 301b1.

[0222] In the embodiment of the present application, the request extraction circuit 301b2 polls and obtains the requests output by multiple masking circuits 301b1. Compared with continuously listening to the channel, polling can reduce the resource occupancy of the system and ensure that each request can be obtained.

[0223] Based on the above Figures 3 to 6 Any of the shown solutions, the present application can provide an L2 storage system design that supports vector atomic operations. Based on Figures 3 to 6 Any of the shown solutions, the detailed description of the technical solution of this embodiment is as follows:

[0224] In the field of processors, the L2 storage system is the core component of the entire AI processor chip. The L2 storage system design that supports vector atomic operations proposed in the embodiment of the present application has high performance and reduces the power consumption of the entire chip.

[0225] Please refer to Figure 7 , which shows a schematic diagram of an overall architecture involved in the embodiment of the present application.

[0226] The overall architecture is as shown in the above figure. There are a total of 5 interfaces in terms of interfaces. Among them, the input 1 interface is used to read the status information of the L2 storage system, the input 2 interface is the data interface at the soc level for the soc to access the L2 storage system, the input 3 interface is used for the system dma to access the L2, and the input 4 / 5 interface 1 is used for two AI computing cores to access the L2. Here, two AI computing cores are taken as an example for illustration, and the number of cores can be arbitrarily expanded according to their own needs.

[0227] Module 1 processes the interface signals of 5 AXI channels and splits the burst transmission. Among them, the splitting module 1 is the splitting module for the write channel, and the splitting module 2 is the splitting module for the read channel. After being replicated by the register, it is output to 8 polling arbitration modules. The polling arbitration module receives a total of 8 requests from 4 interfaces and adopts a polling scheduling strategy.

[0228] The polling arbitration module completes the scheduling between multiple input requests. If an Atomic request is scheduled, the request is stored in the atomic operation output table. This table has a total of 3 entries, each entry has 2 fields, one stores address information and the other stores signal information. The signal is automatically cleared after 3 clock cycles. The delay line is used to delay the Atomic instruction, and the polling arbitration device is shut down after 4 clock cycles.

[0229] Request a masking operation in the mask module. If the current request address is the same as an address in the atomic operation output table, mask the request. The address decoder module determines the module to which it belongs based on the address module field segment.

[0230] Divide the memory into 8 shards. The data read from the 8 modules passes through a selection network to select the read data for each interface, and the read data of the 8 shards is concatenated and written into queue 5.

[0231] Taking three typical operations as examples below, the data processing flow is explained.

[0232] Please refer to Figure 8 , which shows a schematic diagram of a read operation process involved in an embodiment of the present application.

[0233] 1) The read request enters queue 4.

[0234] 2) Queue 4 is not empty, pop the head request, and perform a split operation on the burst request.

[0235] 3) The read request passes through the address decoder and enters the polling arbiter of polling arbitration module 0.

[0236] 4) The read request is authorized by the arbiter, and the request enters the read ports of module 0 of the 8 shards to read data.

[0237] 5) Select the read data through the selection network, and concatenate the read data of the 8 shards.

[0238] 6) The concatenated read data is written back to queue 5.

[0239] 7) Pop the head data of queue 5 and return it to the bus.

[0240] Please refer to Figure 9 , which shows a schematic diagram of a write operation process involved in an embodiment of the present application.

[0241] 1a) The request on the aw (address write) channel enters queue 1.

[0242] 1b) The request on the w (write) channel enters queue 2.

[0243] 2) When both queue 1 and queue 2 are not empty, perform a split operation on the head request.

[0244] 3) The write request passes through the address decoder and enters the polling arbiter of polling arbitration module 0.

[0245] 4a) The write request is authorized by the arbiter, and the request enters the write ports of module 0 of the 8 shards to write data.

[0246] 4b) The write request is authorized by the arbiter, and the wid information passed along the path is returned to queue 3.

[0247] 5) The head data of queue 3 is popped and returned to the bus.

[0248] Please refer to Figure 10 , which shows a schematic flowchart of an Atomic write operation related to the embodiments of the present application.

[0249] 1a) The request on the aw channel enters queue 1.

[0250] 1b) The request on the w channel enters queue 2.

[0251] When both queue 1 and queue 2 are non-empty, the head requests are split.

[0252] 3) The Atomic request passes through the address decoder and enters the polling arbiter of polling arbiter module 0.

[0253] 4a) The Atomic request is authorized by the arbiter, and the request enters the read port of module 0 with 8 shards to read data.

[0254] 4b) The Atomic request is authorized by the arbiter, and a scheduler mediation signal after 4 clock cycles is generated through the delay line.

[0255] 4c) The Atomic request is authorized by the arbiter, the address information is updated to the atomic operation output table, and subsequent requests with the same address are masked.

[0256] 4d) The Atomic request is authorized by the arbiter, and the data enters the atomic operation data queue in each module for temporary storage.

[0257] 5a) Data is read from the buffer and sent to the source end of the adder.

[0258] 5b) The head data is read from the atomic operation data queue and sent to the source end of the adder.

[0259] 6a) The adder completes the calculation and writes the result into the buffer.

[0260] 6b) The wid information passed along the path is returned to queue 3.

[0261] The head data of queue 3 is popped and returned to the bus.

[0262] Please refer to Figure 11 , which shows a schematic pipeline diagram of an Atomic operation related to the embodiments of the present application.

[0263] The above pipeline isFigure 10 Refinement of the process, with each square representing a first-level pipeline. Next, the timing relationship between Atomic operations and subsequent requests will be introduced.

[0264] Please refer to Figure 12 , which shows a schematic diagram of the timing relationship between an Atomic operation and subsequent requests involved in an embodiment of the present application.

[0265] The schematic diagram of the Atomic operation and its subsequent request pipeline is as shown above. Instruction 0 is an Atomic request. The addresses of instructions 1 to 3 need to be compared with the address of instruction 0. If they are the same, mediation is required during the arbitration stage. If the addresses are different, normal execution can proceed. The memory access of instruction 4 will conflict with the memory access of instruction 0, and the scheduler for this loop needs to be mediated. Instruction 5 and subsequent instructions can be executed normally. Based on Figures 7 to 12 , in an embodiment of the present application, an accumulative atomic operation is proposed, that is, the accumulative operation is directly performed inside the L2 memory by reading first and then writing, without moving the data to the L1 cache and the register file, greatly improving the performance; the calculation process occurs at the L2 access level, without moving the data to the L1 cache, reducing a large number of memory read and write operations, and also greatly reducing the power consumption; the hardware automatically processes the address conflicts between atomic operations and other operations, which is not perceived at the software level, reducing the burden on programmers.

[0266] In summary, in the design of the L2 storage system supporting vector atomic operations proposed in the embodiment of the present application, the hardware automatically processes the accumulative operation at the L2 level, without importing the data into the core for processing. This L2 storage system has high performance and low power consumption.

[0267] Please refer to Figure 13 , which shows a flowchart of an instruction processing method involved in an exemplary embodiment of the present application. As Figure 13 shown, this method can be executed by a cache, and the cache can be any cache such as Figures 3 to 6 . As Figure 13 shown, this method may include the following steps:

[0268] An instruction processing method, which is executed by the above cache, and the method includes:

[0269] Step 1301: Receive a cache access request through a request distribution circuit and send the cache access request to the cache circuit.

[0270] Step 1302: Through the cache unit, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and input the read source data into the arithmetic unit.

[0271] Step 1303: Through the arithmetic unit, perform an atomic operation corresponding to the cache access request on the source data, obtain the operation result data, and write the operation result data into the cache unit.

[0272] In some embodiments, the cache circuit further includes: a first register, a multiplexer, and a second register;

[0273] Two input terminals of the multiplexer are respectively connected to the first register and the arithmetic unit. The first register is also connected to the request distribution circuit and the arithmetic unit. The output terminal of the multiplexer is connected to the cache unit. The second register is respectively connected to the cache unit and the arithmetic unit;

[0274] The request distribution circuit is configured to write the cache access request into the first register;

[0275] The first register is configured to send the cache access request to the multiplexer and the arithmetic unit respectively;

[0276] The multiplexer is configured to send the cache access request to the cache unit when the arithmetic unit has no output;

[0277] The cache unit is configured to, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and write the read source data into the second register;

[0278] The second register is configured to send the source data to the arithmetic unit;

[0279] The arithmetic unit is configured to, when the cache access request is a write request corresponding to an atomic operation, perform an atomic operation corresponding to the cache access request on the source data, obtain the operation result data, and send the operation result data to the multiplexer;

[0280] The multiplexer is configured to send the operation result data to the cache unit;

[0281] The cache unit is configured to cache the operation result data.

[0282] In some embodiments, the arithmetic unit includes: a first discriminator, an atomic data queue, an arithmetic unit, and a third register;

[0283] The first discriminator is respectively connected to the first register and the atomic data queue. Two input terminals of the arithmetic unit are respectively connected to the atomic data queue and the second register. The third register is respectively connected to the output terminal of the arithmetic unit and an input terminal of the multiplexer;

[0284] A first discriminator for discriminating a cache access request sent by a first register, and writing the atomic operation data corresponding to the cache access request into an atomic data queue when it is discriminated that the cache access request is a write request corresponding to an atomic operation;

[0285] An arithmetic unit for performing an atomic operation corresponding to the cache access request on the source data sent by a second register and the atomic operation data in the atomic data queue, obtaining operation result data, and writing the operation result data into a third register;

[0286] The third register is used to send the operation result data to a multiplexer.

[0287] In some embodiments, the cache further includes a check code generation circuit and a check circuit;

[0288] The check code generation circuit is respectively connected to the output end of the multiplexer and the cache unit, and the second register is also connected to the check circuit.

[0289] In some embodiments, the cache unit is further configured to read the data corresponding to the cache access request when the cache access request is a write request corresponding to a non-atomic operation.

[0290] In some embodiments, the cache further includes a data output circuit, and the data output circuit is connected to the check circuit;

[0291] The cache unit is further configured to read the data corresponding to the cache access request when the cache access request is a read request corresponding to a non-atomic operation, and write the read data into the second register;

[0292] The second register is further configured to send the data corresponding to the cache access request to the check circuit;

[0293] The check circuit is configured to send the data that passes the check to the data output circuit.

[0294] In some embodiments, the request distribution circuit includes: an interface circuit and an arbitration circuit;

[0295] The interface circuit is connected to the arbitration circuit, and the arbitration circuit is connected to the cache circuit;

[0296] The interface circuit is configured to send the cache access request to the arbitration circuit;

[0297] The arbitration circuit is configured to pause or block subsequent requests that conflict with the cache access request when the cache access request is a write request corresponding to an atomic operation.

[0298] In some embodiments, the arbitration circuit includes:

[0299] Shielding circuit, request extraction circuit, second discriminator, delay circuit, address management circuit, and fourth register;

[0300] The shielding circuit is respectively connected to the request extraction circuit and the address management circuit. The request extraction circuit is also respectively connected to the second discriminator, the delay circuit, and the fourth register. The second discriminator is also respectively connected to the delay circuit and the address management circuit;

[0301] The shielding circuit is used to receive requests sent by the interface circuit;

[0302] The request extraction circuit is used to extract cache access requests from the shielding circuit and send the cache access requests to the second discriminator and the fourth register respectively;

[0303] The fourth register is used to send cache access requests to the cache circuit;

[0304] The second discriminator is used to discriminate cache access requests sent by the request extraction circuit. When it is discriminated that the cache access request is a write request corresponding to an atomic operation, the cache access request is sent to the address management circuit and the delay circuit is started;

[0305] The delay circuit is used to trigger the request extraction circuit to pause extracting new requests from the shielding circuit in the current clock cycle after delaying for N clock cycles; N is an integer greater than or equal to 2; the value of N is the difference between the first number of clock cycles and the second number of clock cycles. The first number of clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the write request corresponding to the atomic operation. The second number of clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the request corresponding to the non-atomic operation;

[0306] The address management circuit is used to save the address of the cache access request within N - 1 clock cycles after receiving the cache access request;

[0307] The shielding circuit is also used to shield requests corresponding to the addresses saved by the address management circuit.

[0308] In some embodiments, the address management circuit includes: an update circuit and an atomic output table;

[0309] The update circuit is respectively connected to the atomic output table and the second discriminator. The atomic output table is also connected to the shielding circuit;

[0310] The atomic output table contains multiple entries, and each entry contains an address bit and a valid bit;

[0311] An update circuit, configured to, when receiving a cache access request sent by a second discriminator, write the address of the cache access request into an entry in an atomic output table, and set the valid bit in the entry where the address of the cache access request is written to N - 1;

[0312] The update circuit is further configured to, in each subsequent clock cycle, decrement the valid bit corresponding to the address of the cache access request by 1 until the valid bit corresponding to the address of the cache access request becomes 0, and then remove the address of the cache access request from the atomic output table.

[0313] In some embodiments, the shielding circuit includes: an address decoder, an address comparison circuit, and a gate circuit;

[0314] The interface circuit is respectively connected to the address decoder and the address comparison circuit. Two input terminals of the gate circuit are respectively connected to the address decoder and the address comparison circuit. The output terminal of the gate circuit is connected to the request extraction circuit, and the address comparison circuit is further connected to the address management circuit;

[0315] The address decoder is configured to, when the address of the request sent by the interface circuit is within a specified address segment, send the request sent by the interface circuit to the gate circuit;

[0316] The address comparison circuit is configured to compare the address of the request sent by the interface circuit with the address stored in the address management circuit, and send a first signal to the interface circuit when the address of the request sent by the interface circuit is different from the address stored in the address management circuit;

[0317] The gate circuit is configured to, when receiving the first signal sent by the interface circuit and simultaneously receiving the request sent by the address decoder, send the request sent by the address decoder to the request extraction circuit.

[0318] In some embodiments, the buffer includes M arbitration circuits and m buffer slices. Each buffer slice contains M buffer circuits, and each arbitration circuit corresponds to an address segment; m and M are integers greater than or equal to 2;

[0319] The M arbitration circuits correspond one-to-one with the M buffer circuits in each buffer slice.

[0320] In some embodiments, the interface circuit corresponds to p request output ports. The arbitration circuit includes p shielding circuits, and the p request output ports are connected to the p shielding circuits one-to-one. p is an integer greater than or equal to 2;

[0321] The request extraction circuit is configured to poll and obtain the requests output by the p shielding circuits.

[0322] A request distribution circuit and a cache circuit are set in the L2 cache in the processor. An arithmetic unit and a cache unit are set in the cache circuit. When the request distribution circuit receives a cache access request, it sends the above request to the cache circuit. The cache unit reads the source data corresponding to the above request and inputs the above source data into the arithmetic unit. The arithmetic unit receives the above source data and the atomic operation corresponding to the above cache access request, obtains the operation result data, and writes the operation result data into the cache unit. That is to say, in the above solution, during the process of the processor performing operations on data, it does not need to transfer the output to the computing core. It only needs to read the source data corresponding to the request in the L2 cache in the processor and complete the atomic operation corresponding to the cache access request in the arithmetic unit in the L2 cache to complete the operation. This greatly improves the usage performance of the cache system and thus reduces the power consumption of the entire processing system.

[0323] The solution shown in the above embodiments of the present application can be applied to a processor. Specifically, the present application further provides a processor, which includes at least one cache as shown in any of the above Figures 3 to 6 any one.

[0324] The present application further provides a computer device, which includes at least one processor, and the processor includes at least one cache as shown in any of the above Figures 3 to 6 any one.

[0325] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing related hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk, an optical disc, etc.

[0326] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A buffer, characterized in that, The buffer is the L2 cache in the processor, and the buffer includes: a request distribution circuit and a cache circuit; The request distribution circuit is connected to the cache circuit; The cache circuit includes a cache unit and an arithmetic unit; the arithmetic unit is connected to the cache unit; The request distribution circuit is configured to receive a cache access request and send the cache access request to the cache circuit; The cache unit is configured to, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and input the read source data into the arithmetic unit; The arithmetic unit is configured to perform an atomic operation corresponding to the cache access request on the source data, obtain operation result data, and write the operation result data into the cache unit.

2. The buffer according to claim 1, wherein The cache circuit further includes: a first register, a multiplexer, and a second register; Two input ends of the multiplexer are respectively connected to the first register and the arithmetic unit, the first register is further connected to the request distribution circuit and the arithmetic unit, an output end of the multiplexer is connected to the cache unit, and the second register is respectively connected to the cache unit and the arithmetic unit; The request distribution circuit is configured to write the cache access request into the first register; The first register is configured to send the cache access request to the multiplexer and the arithmetic unit respectively; The multiplexer is configured to send the cache access request to the cache unit when the arithmetic unit has no output; The cache unit is configured to, when the cache access request is a write request corresponding to an atomic operation, read the source data corresponding to the cache access request and write the read source data into the second register; The second register is configured to send the source data to the arithmetic unit; The arithmetic unit is configured to, when the cache access request is a write request corresponding to an atomic operation, perform an atomic operation corresponding to the cache access request on the source data, obtain operation result data, and send the operation result data to the multiplexer; The multiplexer is configured to send the operation result data to the cache unit; The cache unit is configured to cache the operation result data.

3. The buffer according to claim 2, wherein The arithmetic unit includes: a first discriminator, an atomic data queue, an arithmetic unit, and a third register; The first discriminator is respectively connected to the first register and the atomic data queue, two input ends of the arithmetic unit are respectively connected to the atomic data queue and the second register, and the third register is respectively connected to an output end of the arithmetic unit and an input end of the multiplexer; The first discriminator is configured to discriminate the cache access request sent by the first register, and when it is discriminated that the cache access request is a write request corresponding to an atomic operation, write the atomic operation data corresponding to the cache access request into the atomic data queue; The arithmetic unit is configured to perform an atomic operation corresponding to the cache access request on the source data sent by the second register and the atomic operation data in the atomic data queue, obtain operation result data, and write the operation result data into the third register; The third register is configured to send the operation result data to the multiplexer.

4. The buffer according to claim 2 or 3, characterized in that, The buffer further includes a check code generation circuit and a check circuit; The check code generation circuit is respectively connected to the output end of the multiplexer and the cache unit, and the second register is also connected to the check circuit.

5. The buffer according to claim 4, wherein The cache unit is further configured to cache the data corresponding to the cache access request when the cache access request is a write request corresponding to a non-atomic operation.

6. The buffer according to claim 4, wherein The buffer further includes a data output circuit, and the data output circuit is connected to the check circuit; The cache unit is further configured to read the data corresponding to the cache access request and write the read data into the second register when the cache access request is a read request corresponding to a non-atomic operation; The second register is further configured to send the data corresponding to the cache access request to the check circuit; The check circuit is configured to send the data that passes the check to the data output circuit.

7. The buffer according to any one of claims 1 to 6, characterized in that, The request distribution circuit includes: an interface circuit and an arbitration circuit; The interface circuit is connected to the arbitration circuit, and the arbitration circuit is connected to the cache circuit; The interface circuit is configured to send the cache access request to the arbitration circuit; The arbitration circuit is configured to pause or block subsequent requests that conflict with the cache access request when the cache access request is a write request corresponding to an atomic operation.

8. The buffer according to claim 7, wherein, The arbitration circuit includes: A shielding circuit, a request extraction circuit, a second discriminator, a delay circuit, an address management circuit, and a fourth register; The shielding circuit is respectively connected to the request extraction circuit and the address management circuit, the request extraction circuit is also respectively connected to the second discriminator, the delay circuit, and the fourth register, and the second discriminator is also respectively connected to the delay circuit and the address management circuit; The shielding circuit is configured to receive the request sent by the interface circuit; The request extraction circuit is configured to extract the cache access request from the shielding circuit and send the cache access request to the second discriminator and the fourth register respectively; The fourth register is configured to send the cache access request to the cache circuit; The second discriminator is configured to discriminate the cache access request sent by the request extraction circuit. When it is discriminated that the cache access request is a write request corresponding to an atomic operation, the cache access request is sent to the address management circuit and the delay circuit is started; The delay circuit is used to trigger the request extraction circuit to pause extracting new requests from the shielding circuit within the current clock cycle after delaying for N clock cycles; N is an integer greater than or equal to 2; the value of N is the difference between the first number of clock cycles and the second number of clock cycles; the first number of clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the write request corresponding to the atomic operation; the second number of clock cycles is the number of clock cycles required for the processor to process the memory access operation during the processing of the request corresponding to the non-atomic operation; The address management circuit is used to save the address of the cache access request within N - 1 clock cycles after receiving the cache access request; The shielding circuit is further used to shield the request corresponding to the address saved by the address management circuit.

9. The buffer according to claim 8, wherein The address management circuit includes: an update circuit and an atomic output table; The update circuit is respectively connected to the atomic output table and the second discriminator, and the atomic output table is also connected to the shielding circuit; The atomic output table contains multiple entries, and each entry contains an address bit and a valid bit; The update circuit is used to write the address of the cache access request into an entry in the atomic output table and set the valid bit in the entry where the address of the cache access request is written to N - 1 when receiving the cache access request sent by the second discriminator; The update circuit is further used to subtract 1 from the valid bit corresponding to the address of the cache access request in each subsequent clock cycle until the valid bit corresponding to the address of the cache access request is 0, and then remove the address of the cache access request from the atomic output table.

10. The buffer according to claim 8, characterized in that The shielding circuit includes: an address decoder, an address comparison circuit, and a gate circuit; The interface circuit is respectively connected to the address decoder and the address comparison circuit. Two input terminals of the gate circuit are respectively connected to the address decoder and the address comparison circuit, and the output terminal of the gate circuit is connected to the request extraction circuit. The address comparison circuit is also connected to the address management circuit; The address decoder is used to send the request sent by the interface circuit to the gate circuit when the address of the request sent by the interface circuit is within the specified address segment; The address comparison circuit is used to compare the address of the request sent by the interface circuit with the address saved by the address management circuit, and send a first signal to the interface circuit when the address of the request sent by the interface circuit is different from the address saved by the address management circuit; The gate circuit is used to send the request sent by the address decoder to the request extraction circuit when receiving the first signal sent by the interface circuit and the request sent by the address decoder at the same time.

11. The buffer according to claim 9, wherein The buffer contains M of the arbitration circuits and m cache slices. Each cache slice contains M of the cache circuits, and each arbitration circuit corresponds to an address segment; m and M are integers greater than or equal to 2; The M arbitration circuits correspond one-to-one with the M cache circuits in each of the cache slices.

12. The buffer according to claim 8, wherein The interface circuit corresponds to p request output ports. The arbitration circuit includes p shielding circuits, and the p request output ports are connected to the p shielding circuits one-to-one. p is an integer greater than or equal to 2; The request extraction circuit is configured to poll and obtain requests output by the p shielding circuits.

13. An instruction processing method, characterized in that, The method is executed by a cache, and the cache is the cache according to any one of claims 1 to 12. The method includes: Receiving a cache access request through the request distribution circuit and sending the cache access request to the cache circuit; Reading, through the cache unit, source data corresponding to the cache access request in the case where the cache access request is a write request corresponding to an atomic operation, and inputting the read source data into the operation unit; Performing, through the operation unit, an atomic operation corresponding to the cache access request on the source data to obtain operation result data, and writing the operation result data into the cache unit.

14. A processor, characterized in that, The processor includes: the cache according to any one of claims 1 to 12.

15. A computer device, characterized in that, The computer device includes a processor and a memory; the processor includes: the cache according to any one of claims 1 to 12.

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