Packaging structure of memory chip and preparation method thereof

Abstract

In order to overcome the problems of poor heat dissipation and stress caused by different volume expansion ratios among storage chips in the existing stacked chip packaging structure, the invention provides a packaging structure of a storage chip, which comprises a substrate, a control chip, a heat conduction layer, a storage chip, a heat conduction slurry layer and a packaging adhesive layer, the heat conduction layer is arranged on the surface, away from the substrate, of the control chip, a first step face and a second step face are formed on the two sides of the multiple storage chips respectively, and the control chip, the heat conduction layer and the storage chips are located in the packaging glue layer. The heat-conducting slurry layer comprises a first heat-conducting slurry layer and a second heat-conducting slurry layer, the first heat-conducting slurry layer covers the second step surface, and the second heat-conducting slurry layer covers the outer surface of the packaging adhesive layer. Meanwhile, the invention further discloses a preparation method of the packaging structure of the storage chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a packaging structure of a memory chip and a preparation method thereof. Background Art

[0002] In the stacked memory chip packaging structure, the control chip is usually stacked together with multiple memory chips. Due to the compact space, the heat dissipation channel is relatively narrow, and the control chip will generate a lot of heat when working, especially under high frequency and high load conditions. However, the design of the stacked package makes the air circulation poor and cannot form effective convection heat dissipation. At the same time, the thermal conductivity of the packaging material is limited and the heat generated by the control chip cannot be conducted away in time. This causes the temperature of the control chip to continue to rise, and being in a high temperature state for a long time will affect the service life of the control chip.

[0003] At the same time, in the stacked memory chip package, different memory chips will have different calorific values due to differences in operating frequency, storage capacity, read and write operations, and other factors. Memory chips with higher calorific values will generate more heat, resulting in a larger temperature increase. According to the principle of thermal expansion and contraction, the volume of the chip will expand when the temperature rises. The volume expansion of memory chips with lower calorific values is relatively small. In particular, the temperature of the memory chip in direct contact with the control chip is significantly higher than that of other memory chips. Since the memory chips are closely stacked, internal stress will be generated when their volume expansion degrees are different. This internal stress will gradually increase with the accumulation of time, and will have an adverse effect on the connection structure between the chips. The memory chips are electrically connected through leads to achieve data transmission and signal control. When the volume expansion of each memory chip is different due to different calorific values, the lead will be subjected to uneven tension and pressure. Under long-term stress, the metal material of the lead will be fatigued and damaged, eventually leading to lead breakage. Summary of the invention

[0004] In view of the problems of poor heat dissipation in the existing stacked chip packaging structure and stress caused by different volume expansion rates among memory chips, the present invention provides a packaging structure of a memory chip and a preparation method thereof.

[0005] The technical solution adopted by the present invention to solve the above technical problems is as follows: On the one hand, the present invention provides a packaging structure for a storage chip, which includes a substrate, a control chip, a heat-conducting layer, storage chips, a heat-conducting paste layer, and a packaging glue layer. The control chip is disposed on the surface of the substrate. The heat-conducting layer is disposed on the surface of the control chip facing away from the substrate and partially extends beyond the coverage of the control chip. The number of the storage chips is multiple, and the multiple storage chips are arranged in a stepped and staggered stacked manner on the surface of the heat-conducting layer facing away from the control chip, so that a first stepped surface and a second stepped surface are respectively formed on both sides of the multiple storage chips. The multiple storage chips are electrically connected to each other at the position of the first stepped surface. The storage chip is electrically connected to the control chip. The packaging glue layer is disposed on the substrate. The control chip, the heat-conducting layer, and the storage chips are located in the packaging glue layer, and at least part of the heat-conducting layer extends beyond the packaging glue layer. The heat-conducting paste layer includes a first heat-conducting paste layer and a second heat-conducting paste layer. The first heat-conducting paste layer covers the second stepped surface, and the second heat-conducting paste layer covers the outer surface of the packaging glue layer. The first heat-conducting paste layer and the second heat-conducting paste layer are connected to each other, and the heat-conducting layer is connected to the second heat-conducting paste layer.

[0006] Optionally, at least one first pad is disposed at the position of the first stepped surface of the storage chip, and the first pads between adjacent two storage chips are connected to each other by a first lead. At least one second pad is disposed on the control chip, and at least one second pad and at least one first pad are connected to each other by a second lead.

[0007] Optionally, the heat-conducting paste layer further includes a third heat-conducting paste layer and a fourth heat-conducting paste layer. The third heat-conducting paste layer covers the surface of the heat-conducting layer extending beyond the control chip, and the fourth heat-conducting paste layer covers the side surface of the control chip. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer, and the fourth heat-conducting paste layer are connected as a whole.

[0008] Optionally, a first silicone resin layer is disposed between adjacent storage chips, between the first heat-conducting paste layer and the storage chip, and between the fourth heat-conducting paste layer and the control chip; A second silicone resin layer is disposed on the side of the first heat-conducting paste layer facing away from the storage chip, on the side of the third heat-conducting paste layer facing away from the heat-conducting layer, and on the side of the fourth heat-conducting paste layer facing away from the control chip. The packaging glue layer is made of an epoxy resin material; Both the first silicone resin layer and the second silicone resin layer are obtained by curing a silicone paste. The silicone paste includes the following weight components: 40-60 parts of organic silicone resin, 3-10 parts of hydrogen-containing silicone oil, 0.05-1 part of catalyst, 10-20 parts of filler and 10-70 parts of solvent.

[0009] Optionally, the thermal conductive slurry layer is obtained by curing a thermal conductive slurry, and the thermal conductive slurry includes the following components by weight: 2-11 parts of graphene, 0.5-4 parts of tetraethyl orthosilicate and 81-93 parts of solvent.

[0010] Optionally, the thermal conductive layer includes a metal sheet, an upper insulating layer and a lower insulating layer, the upper insulating layer is located between the metal sheet and the storage chip, the lower insulating layer is located between the metal sheet and the control chip, the thickness of the lower insulating layer is less than the thickness of the upper insulating layer, and the end of the metal sheet extends out of the packaging glue layer and is bent to form a bent portion, and the bent portion adheres to the surface of the second thermal conductive paste layer.

[0011] Optionally, the thermally conductive paste layer further includes a fifth thermally conductive paste layer, which is located in the packaging glue layer, and one end of the fifth thermally conductive paste layer is connected to the first thermally conductive paste layer, and the other end of the fifth thermally conductive paste layer is connected to the second thermally conductive paste layer.

[0012] In another aspect, the present invention provides a method for preparing the packaging structure of the memory chip as described above, comprising the following steps: Performing staggered stacking of a plurality of memory chips to obtain a memory chip stack, wherein a first step surface and a second step surface are respectively formed on two sides of the memory chip stack; Fixing the control chip on the substrate, placing the heat-conducting layer and the memory chip stack in sequence on the side of the control chip away from the substrate and pre-fixing them, and making lead electrical connections between the memory chip and the control chip on the first step surface; The control chip, the heat-conducting layer and the memory chip stack are shielded on one side of the second step surface, and the control chip, the heat-conducting layer and the memory chip stack are pre-packaged on one side of the first step surface using packaging glue; removing the shielding of the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, applying a heat-conducting slurry to the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, and curing the slurry; The control chip, the heat-conducting layer and the memory chip stack are re-encapsulated on one side of the second step surface by using encapsulation glue, and an encapsulation glue layer is formed outside the control chip, the heat-conducting layer and the memory chip, and the heat-conducting layer at least partially extends out of the encapsulation glue layer; A thermal conductive paste is applied to the outside of the packaging adhesive layer and solidified to form a thermal conductive paste layer.

[0013] Optionally, before the stepped misaligned stacking of the memory chips: apply silicone paste to the bottom surface and one side surface of the memory chips, and cure; apply silicone paste to the top surface and one side surface of the control chips, and cure; to obtain the first silicone resin layer; After applying the thermal conductive paste and curing, and before re-encapsulation: apply silicone paste to one side of the second stepped surface of the control chip, the thermal conductive layer and the memory chip stack, and cure, to obtain the second silicone resin layer.

[0014] Optionally, after curing to form the thermal conductive paste layer, bend the part of the thermal conductive layer extending out of the encapsulating adhesive layer so that it adheres to the surface of the thermal conductive paste layer.

[0015] According to the encapsulation structure of the memory chip provided by the present invention, a first thermal conductive paste layer is provided on the second stepped surface of the memory chip, a thermal conductive layer is provided between the control chip and the memory chip, and a second thermal conductive paste layer is provided outside the encapsulating adhesive layer, so that the first thermal conductive paste layer, the thermal conductive layer and the second thermal conductive paste layer are connected. Among them, the first thermal conductive paste layer located on the second stepped surface can improve the temperature consistency between multiple memory chips, reduce the stress generated due to the different temperature and volume change rates of each memory chip, and is beneficial to improving the electrical connection stability of the leads; at the same time, through the heat conduction of the first thermal conductive paste layer, the thermal conductive layer and the second thermal conductive paste layer, the heat of the memory chip and the control chip can be directly conducted to the outer surface of the encapsulating adhesive layer, so as to effectively improve the heat dissipation efficiency of the encapsulation structure, and is also beneficial to heat dissipation through an external heat dissipation structure (such as a heat pipe), thereby reducing the temperature of the memory chip and the control chip and improving the service life. Description of the Drawings

[0016] Figure 1 is a schematic structural diagram of the encapsulation structure of the memory chip provided by the present invention; Figure 2 is a top view structural diagram of the encapsulation structure of the memory chip provided by the present invention; Figure 3 is a schematic structural diagram of the first intermediate of the encapsulation structure of the memory chip provided by the present invention; Figure 4 is a schematic structural diagram of the second intermediate of the encapsulation structure of the memory chip provided by the present invention; Figure 5 is a schematic structural diagram of the third intermediate of the encapsulation structure of the memory chip provided by the present invention.

[0017] The reference numerals in the accompanying drawings of the specification are as follows: 1. Substrate; 11. Welding structure; 2. Control chip; 21. Second pad; 3. Heat-conducting layer; 31. Upper insulating layer; 32. Metal sheet; 33. Lower insulating layer; 4. Memory chip; 41. First pad; 42. First lead; 43. Second lead; 5. Encapsulating glue layer; 6. First silicone resin layer; 7. Second silicone resin layer; 8. Heat-conducting paste layer; 81. First heat-conducting paste layer; 82. Second heat-conducting paste layer; 83. Third heat-conducting paste layer; 84. Fourth heat-conducting paste layer; 85. Fifth heat-conducting paste layer; 91. First stepped surface; 92. Second stepped surface. Detailed implementation manners

[0018] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] See Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a packaging structure for a memory chip, including a substrate 1, a control chip 2, a heat-conducting layer 3, a memory chip 4, a heat-conducting paste layer 8 and an encapsulating glue layer 5. The control chip 2 is disposed on the surface of the substrate 1. The heat-conducting layer 3 is disposed on the surface of the control chip 2 facing away from the substrate 1 and partially extends out of the coverage of the control chip 2. The number of the memory chips 4 is multiple, and the multiple memory chips 4 are arranged in a stepped and staggered manner on the surface of the heat-conducting layer 3 facing away from the control chip 2, so as to form a first stepped surface 91 and a second stepped surface 92 on both sides of the multiple memory chips 4 respectively. The multiple memory chips 4 are electrically connected to each other at the position of the first stepped surface 91. The memory chip 4 is electrically connected to the control chip 2. The encapsulating glue layer 5 is disposed on the substrate 1. The control chip 2, the heat-conducting layer 3 and the memory chip 4 are located in the encapsulating glue layer 5, and at least part of the heat-conducting layer 3 extends out of the encapsulating glue layer 5. The heat-conducting paste layer 8 includes a first heat-conducting paste layer 81 and a second heat-conducting paste layer 82. The first heat-conducting paste layer 81 covers the second stepped surface 92. The second heat-conducting paste layer 82 covers the outer surface of the encapsulating glue layer 5. The first heat-conducting paste layer 81 and the second heat-conducting paste layer 82 are connected to each other. The heat-conducting layer 3 is connected to the second heat-conducting paste layer 82.

[0020] The first thermal conductive paste layer 81 located on the second stepped surface 92 can improve the temperature consistency among multiple memory chips 4, reduce the stress generated due to the different temperature and volume change rates of each memory chip 4, and is beneficial to improving the electrical connection stability of the leads. At the same time, through the heat conduction of the first thermal conductive paste layer 81, the heat conduction layer 3, and the second thermal conductive paste layer 82, the heat of the memory chip 4 and the control chip 2 can be directly conducted to the outer surface of the encapsulation glue layer 5, thereby effectively improving the heat dissipation efficiency of the encapsulation structure, and is also beneficial to heat dissipation through an external heat dissipation structure (such as a heat pipe), further reducing the temperatures of the memory chip 4 and the control chip 2 and increasing the service life.

[0021] Furthermore, when the second thermal conductive paste layer 82 is made of graphene paste or metal paste, it has a good electromagnetic shielding effect. According to the principle of electromagnetics, due to the high conductivity of the graphene paste or metal paste, under the action of an external electromagnetic signal, the free electrons in the conductor will move directionally under the action of the electric field force. A charge distribution opposite to the external electric field will be induced on the outer surface of the cage, thereby generating an electromagnetic field opposite to the incident electromagnetic wave, reducing the intensity of the electromagnetic wave passing through the second thermal conductive paste layer 82, achieving the effect of signal shielding, reducing external electromagnetic interference, and enhancing the operating stability of the memory chip 4.

[0022] In an embodiment, at least one first pad 41 is provided at the position of the memory chip 4 on the first stepped surface 91. The first pads 41 between adjacent two memory chips 4 are connected to each other through a first lead 42. At least one second pad 21 is provided on the control chip 2. At least one second pad 21 and at least one first pad 41 are connected to each other through a second lead 43.

[0023] As Figure 2 shown, a plurality of first pads 41 are provided at the position of the memory chip 4 on the first stepped surface 91. Specifically, the first pads 41 are located on the surface of the first stepped surface 91 facing away from the substrate 1, and the first pads 41 of the plurality of memory chips 4 are arranged in one-to-one correspondence to form a matrix arrangement structure of multiple rows and multiple columns. The first pads 41 in the same column are welded and connected in sequence through the first lead 42. Correspondingly, a plurality of second pads 21 are provided on the control chip 2 at the arrangement extension positions corresponding to the plurality of first pads 41. The second pads 21 on the control chip 2 and the first pad 41 closest to the second pad 21 are welded and connected through the second lead 43. The control chip 2 is responsible for controlling and managing the read and write operations of the memory chip 4.

[0024] The layout of the above-mentioned first pad 41, second pad 21, first lead 42 and second lead 43 is conducive to reducing the electrical signal transmission distance, reducing signal attenuation and external interference, enabling the control chip 2 to effectively read, write, control and manage the storage chip 4, and ensuring the normal operation of the entire storage chip 4 system.

[0025] In some embodiments, the first lead 42 and the second lead 43 are metal wires. In other embodiments, the first lead 42 and the second lead 43 can also be replaced with other electrical connection structures.

[0026] In some embodiments, a welding structure 11 is provided on the side of the substrate 1 facing away from the control chip 2. The first welding structure 11 is used to achieve electrical connection and mechanical fixation between the substrate 1 and other external structures. In a specific embodiment, the welding structure 11 is a solder ball.

[0027] In some embodiments, an electrical connection structure is provided between the control chip 2 and the substrate 1. For example, electrical connection protrusions can be provided at the bottom of the control chip 2, and at the same time, an electrically conductive structure is provided in the substrate 1 to electrically connect the electrical connection protrusions and the welding structure 11. Another example is that a third pad can be provided on the control chip 2, a fourth pad can be provided on the substrate 1, a lead is provided between the third pad and the fourth pad for electrical connection, and the fourth pad and the welding structure 11 are electrically connected.

[0028] In some embodiments, leads and / or other connection structures can also be provided to achieve electrical connection between the storage chip 4 and the welding structure 11.

[0029] In some embodiments, the thermal paste layer 8 further includes a third thermal paste layer 83 and a fourth thermal paste layer 84. The third thermal paste layer 83 covers the surface of the heat conduction layer 3 extending out of the control chip 2, and the fourth thermal paste layer 84 covers the side surface of the control chip 2. The first thermal paste layer 81, the second thermal paste layer 82, the third thermal paste layer 83 and the fourth thermal paste layer 84 are connected as a whole.

[0030] The third thermal paste layer 83 can enhance the heat dissipation capacity of the extended part of the heat conduction layer 3, enabling the heat conduction layer 3 to conduct heat more efficiently; the fourth thermal paste layer 84 can increase the heat dissipation area on the side surface of the control chip 2, effectively improving the heat dissipation efficiency of the control chip 2. Each thermal paste layer 8 is connected as a whole to form a continuous heat conduction channel, further optimizing the heat conduction path, enabling the heat inside the packaging structure to be quickly conducted to the surface of the packaging structure, and improving the heat dissipation performance of the entire packaging structure.

[0031] In some embodiments, a first silicone resin layer 6 is provided between adjacent memory chips 4, between the first thermal conductive paste layer 81 and the memory chip 4, and between the fourth thermal conductive paste layer 84 and the control chip 2.

[0032] The first silicone resin layer 6, on the one hand, as an adhesive, can ensure the bonding and fixation between different memory chips 4; on the other hand, as an insulating layer, silicone resin has good insulation properties. In the present invention, the thermal conductive paste layer 8 has a certain electrical conductivity. By providing the first silicone resin layer 6, electrical short circuits between the memory chip 4, the thermal conductive paste layer 8, and the control chip 2 can be prevented, ensuring electrical safety; on the third hand, as a buffer layer, since the silicone resin layer has a certain deformation elasticity, it can better adapt to the stress generated by the volume change between the memory chips 4, ensure its adhesiveness, improve the stability of the connection between the memory chips 4, and avoid the generation of cracks due to stress.

[0033] In some embodiments, a second silicone resin layer 7 is provided on the side of the first thermal conductive paste layer 81 facing away from the memory chip 4, on the side of the third thermal conductive paste layer 83 facing away from the thermal conductive layer 3, and on the side of the fourth thermal conductive paste layer 84 facing away from the control chip 2. The encapsulation adhesive layer 5 is made of epoxy resin material.

[0034] The epoxy resin material as the encapsulation adhesive layer 5 has the advantages of high thermal stability, low water vapor transmission rate, and high curing hardness, and can better prevent the internal memory chip 4 and control chip 2 from being affected by the external environment. However, there is a shrinkage stress during the curing process of epoxy resin. In the traditional encapsulation structure, the influence of this shrinkage stress is small, but in the present invention, due to the provision of the thermal conductive paste layer 8, during the "re-encapsulation", due to the shrinkage stress between the epoxy resin and the memory chip 4, the thermal conductive layer 3, and the control chip 2, it is easy to cause the first thermal conductive paste layer 81, the third thermal conductive paste layer 83, and the fourth thermal conductive paste layer 84 to separate from the surfaces of the memory chip 4, the thermal conductive layer 3, and the control chip 2, forming a gap between the first thermal conductive paste layer 81, the third thermal conductive paste layer 83, the fourth thermal conductive paste layer 84 and the memory chip 4, the thermal conductive layer 3, and the control chip 2. This kind of gap will affect the heat conduction efficiency between the first thermal conductive paste layer 81, the third thermal conductive paste layer 83, the fourth thermal conductive paste layer 84 and the memory chip 4, the thermal conductive layer 3, and the control chip 2. To avoid this situation, the second silicone resin layer 7 is provided, and the deformation buffering effect of the silicone resin is used to reduce the direct action of the shrinkage stress generated by the curing of the epoxy resin on the first thermal conductive paste layer 81, the third thermal conductive paste layer 83, and the fourth thermal conductive paste layer 84, thereby effectively ensuring the contact between the first thermal conductive paste layer 81, the third thermal conductive paste layer 83, the fourth thermal conductive paste layer 84 and the memory chip 4, the thermal conductive layer 3, and the control chip 2, and improving the heat conduction efficiency.

[0035] In some embodiments, both the first silicone resin layer 6 and the second silicone resin layer 7 are obtained by curing a silicone paste, and the silicone paste comprises the following components by weight: 40 - 60 parts of silicone resin, 3 - 10 parts of hydrogen-containing silicone oil, 0.05 - 1 part of catalyst, 10 - 20 parts of filler, and 10 - 70 parts of solvent.

[0036] In some embodiments, the thermal conductive paste layer 8 is obtained by curing a thermal conductive paste, and the thermal conductive paste comprises the following components by weight: 2 - 11 parts of graphene, 0.5 - 4 parts of tetraethyl orthosilicate, and 81 - 93 parts of solvent.

[0037] By adding tetraethyl orthosilicate to the graphene paste, since tetraethyl orthosilicate has multiple siloxane structures, it can undergo hydrolysis and condensation reactions with the hydroxyl groups on the surface of graphene, and can also directly undergo hydrolysis and condensation with the silicone resin in the first silicone resin layer 6 and the second silicone resin layer 7. Furthermore, a connection structure is formed between the graphene and the silicone resin, improving the connection strength between the thermal conductive paste layer 8 and the first silicone resin layer 6 and the second silicone resin layer 7, and enhancing the heat conduction efficiency and structural stability.

[0038] In some embodiments, the thermal conductive layer 3 includes a metal sheet 32, an upper insulating layer 31, and a lower insulating layer 33. The upper insulating layer 31 is located between the metal sheet 32 and the storage chip 4, and the lower insulating layer 33 is located between the metal sheet 32 and the control chip 2. The thickness of the lower insulating layer 33 is less than the thickness of the upper insulating layer 31.

[0039] The upper insulating layer 31 and the lower insulating layer 33 can prevent electrical short circuits between the metal sheet 32 and the storage chip 4 and the control chip 2, ensuring electrical safety.

[0040] In some embodiments, the thickness of the lower insulating layer 33 is 1 - 10 μm, and the thickness of the upper insulating layer 31 is 15 - 1000 μm.

[0041] By setting the thickness of the lower insulating layer 33 to be less than the thickness of the upper insulating layer 31, on the one hand, the heat conduction efficiency between the metal sheet 32 and the control chip 2 can be improved, and on the other hand, it is used to reduce the heat conduction efficiency between the metal sheet 32 and the storage chip 4. While ensuring the heat dissipation effect for the control chip 2, excessive heat conduction to the storage chip 4 closest to the control chip 2 is avoided.

[0042] In some embodiments, the upper insulating layer 31 and the lower insulating layer 33 are selected from polyimide layers.

[0043] In some embodiments, an end portion of the metal sheet 32 extends out of the packaging glue layer 5 and is bent to form a bent portion, and the bent portion is in contact with the surface of the second thermal conductive paste layer 82 .

[0044] The provision of the bending portion is helpful to increase the heat conduction area between the heat conducting layer 3 and the second heat conducting paste layer 82 , thereby improving the heat dissipation effect.

[0045] In some embodiments, the thermal conductive paste layer 8 also includes a fifth thermal conductive paste layer 85, which is located in the packaging glue layer 5, and one end of the fifth thermal conductive paste layer 85 is connected to the first thermal conductive paste layer 81, and the other end of the fifth thermal conductive paste layer 85 is connected to the second thermal conductive paste layer 82.

[0046] The fifth thermally conductive paste layer 85 serves as a thermally conductive intermediate between the first thermally conductive paste layer 81 and the second thermally conductive paste layer 82 , and can improve the thermal conductivity of the first thermally conductive paste layer 81 and the second thermally conductive paste layer 82 , thereby improving the heat dissipation effect on the memory chip 4 .

[0047] Another embodiment of the present invention provides a method for preparing the packaging structure of the memory chip as described above, comprising the following steps: Performing staggered stacking of a plurality of memory chips to obtain a memory chip stack, wherein a first step surface and a second step surface are respectively formed on two sides of the memory chip stack; The control chip is fixed on the substrate, and the heat-conducting layer and the memory chip stack are sequentially placed on the side of the control chip away from the substrate and pre-fixed. The memory chip and the control chip are electrically connected by wires on the first step surface to obtain the following Figure 3 The first intermediate structure shown; The control chip, the heat-conducting layer and the memory chip stack are shielded on one side of the second step surface, and the control chip, the heat-conducting layer and the memory chip stack are pre-packaged on one side of the first step surface using a packaging glue to obtain a Figure 4 The second intermediate structure shown; removing the shielding of the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, applying a heat-conducting slurry to the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, and curing the slurry; The control chip, the heat-conducting layer and the memory chip stack are again packaged on one side of the second step surface using a packaging glue, and a packaging glue layer is formed outside the control chip, the heat-conducting layer and the memory chip, and the heat-conducting layer at least partially extends out of the packaging glue layer, so as to obtain Figure 5 The third intermediate structure shown; A thermal conductive paste is applied to the outside of the packaging adhesive layer and solidified to form a thermal conductive paste layer.

[0048] In the description of the present invention, the application method of the thermal conductive slurry and the silicone slurry can be selected from existing commonly used application methods, such as spraying, physical vapor deposition, etc.

[0049] In some embodiments, before performing the step-by-step staggered stacking of the memory chips: applying an organic silicon slurry to the bottom surface and one side surface of the memory chip and curing; applying an organic silicon slurry to the top surface and one side surface of the control chip and curing; obtaining a first organic silicon resin layer; After applying and curing the thermal conductive paste and before re-packaging: applying and curing the organic silicon paste on one side of the second step surface of the control chip, the thermal conductive layer and the memory chip stack to obtain a second organic silicon resin layer.

[0050] In some embodiments, after the thermal conductive paste layer is cured to form the thermal conductive paste layer, the portion of the thermal conductive layer extending out of the packaging adhesive layer is bent so as to be attached to the surface of the thermal conductive paste layer.

[0051] The present invention is further described below by way of examples.

[0052] Example 1 This embodiment is used to illustrate the method for preparing the packaging structure of the memory chip disclosed in the present invention, and includes the following steps: Applying organic silicon slurry to the bottom surface and one side surface of the memory chip and curing; applying organic silicon slurry to the top surface and one side surface of the control chip and curing; obtaining a first organic silicon resin layer; The organosilicon slurry comprises the following components by weight: 50 parts of organic silicone resin, 5 parts of hydrogen-containing silicone oil, 0.5 parts of triethylenediamine, 15 parts of fumed silica and 50 parts of toluene.

[0053] Performing staggered stacking of a plurality of memory chips to obtain a memory chip stack, wherein a first step surface and a second step surface are respectively formed on two sides of the memory chip stack; The control chip is fixed on the substrate, and the heat-conducting layer and the memory chip stack are sequentially placed on the side of the control chip away from the substrate and pre-fixed, and the memory chip and the control chip are electrically connected by wires on the first step surface; the heat-conducting layer includes a first polyimide layer, a metal sheet, and a second polyimide layer stacked in sequence, and the end of the metal sheet is exposed outside the control chip and the memory chip; The control chip, the heat-conducting layer and the memory chip stack are shielded on one side of the second step surface, and the control chip, the heat-conducting layer and the memory chip stack are pre-packaged on one side of the first step surface using packaging glue; Remove the shielding on one side of the stacked body of the control chip, heat-conducting layer and storage chip on the second stepped surface, apply heat-conducting paste to one side of the stacked body of the control chip, heat-conducting layer and storage chip on the second stepped surface, and cure it; Apply silicone paste to one side of the stacked body of the control chip, heat-conducting layer and storage chip on the second stepped surface, cure it, and obtain the second silicone resin layer; Use encapsulating glue to re-encapsulate one side of the stacked body of the control chip, heat-conducting layer and storage chip on the second stepped surface, form an encapsulating glue layer outside the control chip, the heat-conducting layer and the storage chip, and the end of the metal sheet extends out of the encapsulating glue layer; Apply heat-conducting paste to the outside of the encapsulating glue layer, cure it to form a heat-conducting paste layer; bend the part of the end of the metal sheet that extends out of the encapsulating glue layer so that it adheres to the surface of the heat-conducting paste layer.

[0054] The heat-conducting paste includes the following weight components: 5 parts of graphene, 2 parts of tetraethyl orthosilicate and 85 parts of water.

[0055] Example 2 This example is used to illustrate the preparation method of the encapsulation structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1, and the differences are as follows: The silicone paste includes the following weight components: 60 parts of silicone resin, 3 parts of hydrogen-containing silicone oil, 0.05 part of triethylenediamine, 20 parts of fumed silica and 40 parts of toluene.

[0056] Example 3 This example is used to illustrate the preparation method of the encapsulation structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1, and the differences are as follows: The heat-conducting paste includes the following weight components: 5 parts of graphene, 2 parts of polyacrylate and 85 parts of water.

[0057] Example 4 This example is used to illustrate the preparation method of the encapsulation structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1, and the differences are as follows: Do not perform the operation of applying the second silicone resin layer.

[0058] Example 5 This example is used to illustrate the preparation method of the encapsulation structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1, and the differences are as follows: Do not perform the bending operation of the heat-conducting layer.

[0059] Comparative Example 1 This comparative example is used to comparatively illustrate the preparation method of the packaging structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1. The difference is that: All operations of applying the thermal conductive paste are not carried out.

[0060] Comparative Example 2 This comparative example is used to comparatively illustrate the preparation method of the packaging structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1. The difference is that: The application of the thermal conductive paste inside the packaging structure is not carried out, and only the application of the thermal conductive paste outside the packaging structure is carried out.

[0061] Comparative Example 3 This comparative example is used to comparatively illustrate the preparation method of the packaging structure of the storage chip disclosed in the present invention, including most of the operation steps in Example 1. The difference is that: The thermal conductive layer is not provided, and the storage chip stack is directly laminated on the surface of the control chip.

[0062] Performance Test The following performance tests are carried out on the packaging structure of the storage chip prepared above: After the packaged packaging structure is placed in an oven at 100 °C for 2 h, the packaging structure is taken out and placed on the same glass substrate, and naturally cooled at room temperature of 25 °C. After 2 minutes and 4 minutes, the surface temperature is detected by a non-contact infrared temperature measuring device respectively, and the test results are filled in Table 1.

[0063] Table 1 It can be seen from the test results in Table 1 that by using the packaging structure provided by the present invention, the heat conduction efficiency between the internal chip and the outside can be effectively improved, thereby improving the cooling effect on the storage chip and the control chip, avoiding excessive internal temperature during operation, and being beneficial to extending the service life.

[0064] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A packaging structure of a storage chip, characterized in that It includes a substrate, a control chip, a heat-conducting layer, memory chips, a heat-conducting paste layer, and a packaging adhesive layer. The control chip is disposed on the surface of the substrate. The heat-conducting layer is disposed on the surface of the control chip facing away from the substrate and partially extends beyond the coverage of the control chip. The number of the memory chips is multiple, and the multiple memory chips are arranged in a stepped and offset stacked manner on the surface of the heat-conducting layer facing away from the control chip, so that a first stepped surface and a second stepped surface are respectively formed on both sides of the multiple memory chips. The multiple memory chips are electrically connected to each other at the position of the first stepped surface. The memory chips are electrically connected to the control chip. The packaging adhesive layer is disposed on the substrate. The control chip, the heat-conducting layer, and the memory chips are located in the packaging adhesive layer, and the heat-conducting layer at least partially extends out of the packaging adhesive layer. The heat-conducting paste layer includes a first heat-conducting paste layer and a second heat-conducting paste layer. The first heat-conducting paste layer covers the second stepped surface. The second heat-conducting paste layer covers the outer surface of the packaging adhesive layer. The first heat-conducting paste layer and the second heat-conducting paste layer are connected to each other. The heat-conducting layer is connected to the second heat-conducting paste layer.

2. The encapsulation structure of the storage chip according to claim 1, wherein At least one first pad is disposed at the position of the first stepped surface of the memory chips. A first lead is disposed between the first pads of two adjacent memory chips to connect them to each other. At least one second pad is disposed on the control chip. A second lead is disposed between at least one of the second pads and at least one of the first pads to connect them to each other.

3. The encapsulation structure of the storage chip according to claim 1, wherein The heat-conducting paste layer further includes a third heat-conducting paste layer and a fourth heat-conducting paste layer. The third heat-conducting paste layer covers the surface of the heat-conducting layer extending out of the control chip. The fourth heat-conducting paste layer covers the side surface of the control chip. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer, and the fourth heat-conducting paste layer are connected as a whole.

4. The encapsulation structure of the storage chip according to claim 3, wherein, A first silicone resin layer is disposed between adjacent memory chips, between the first heat-conducting paste layer and the memory chips, and between the fourth heat-conducting paste layer and the control chip; A second silicone resin layer is disposed on the side of the first heat-conducting paste layer facing away from the memory chips, on the side of the third heat-conducting paste layer facing away from the heat-conducting layer, and on the side of the fourth heat-conducting paste layer facing away from the control chip. The packaging adhesive layer is made of an epoxy resin material; Both the first silicone resin layer and the second silicone resin layer are obtained by curing a silicone paste. The silicone paste includes the following weight components: 40 - 60 parts of silicone resin, 3 - 10 parts of hydrogen-containing silicone oil, 0.05 - 1 part of catalyst, 10 - 20 parts of filler, and 10 - 70 parts of solvent.

5. The package structure of the storage chip according to claim 1, wherein The heat-conducting paste layer is obtained by curing a heat-conducting paste. The heat-conducting paste includes the following weight components: 2 - 11 parts of graphene, 0.5 - 4 parts of tetraethyl orthosilicate, and 81 - 93 parts of solvent.

6. The package structure of the memory chip according to claim 1, wherein The heat-conducting layer includes a metal sheet, an upper insulating layer and a lower insulating layer, the upper insulating layer is located between the metal sheet and the storage chip, the lower insulating layer is located between the metal sheet and the control chip, the thickness of the lower insulating layer is less than the thickness of the upper insulating layer, the end of the metal sheet extends out of the packaging glue layer and is bent to form a bent portion, and the bent portion is attached to the surface of the second heat-conducting paste layer.

7. The package structure of the storage chip according to claim 1, characterized in that, The thermal conductive paste layer further includes a fifth thermal conductive paste layer, which is located in the packaging glue layer, and one end of the fifth thermal conductive paste layer is connected to the first thermal conductive paste layer, and the other end of the fifth thermal conductive paste layer is connected to the second thermal conductive paste layer.

8. The preparation method of the packaging structure of the storage chip according to any one of claims 1 to 7, characterized in that, The steps are as follows: Performing staggered stacking of a plurality of memory chips to obtain a memory chip stack, wherein a first step surface and a second step surface are respectively formed on two sides of the memory chip stack; Fixing the control chip on the substrate, placing the heat-conducting layer and the memory chip stack in sequence on the side of the control chip away from the substrate and pre-fixing them, and making lead electrical connections between the memory chip and the control chip on the first step surface; The control chip, the heat-conducting layer and the memory chip stack are shielded on one side of the second step surface, and the control chip, the heat-conducting layer and the memory chip stack are pre-packaged on one side of the first step surface using packaging glue; removing the shielding of the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, applying a heat-conducting slurry to the control chip, the heat-conducting layer and the memory chip stack on one side of the second step surface, and curing the slurry; The control chip, the heat-conducting layer and the memory chip stack are re-encapsulated on one side of the second step surface by using encapsulation glue, and an encapsulation glue layer is formed outside the control chip, the heat-conducting layer and the memory chip, and the heat-conducting layer at least partially extends out of the encapsulation glue layer; A thermal conductive paste is applied to the outside of the packaging adhesive layer and solidified to form a thermal conductive paste layer.

9. The method for manufacturing the packaging structure of the memory chip according to claim 8, wherein, Before performing the step-by-step staggered stacking of the memory chips: applying and curing the bottom surface and one side surface of the memory chip with organic silicon slurry; applying and curing the top surface and one side surface of the control chip with organic silicon slurry; obtaining a first organosilicon resin layer; After applying and curing the thermal conductive paste and before re-packaging: applying and curing the organic silicon paste on one side of the second step surface of the control chip, the thermal conductive layer and the memory chip stack to obtain a second organic silicon resin layer.

10. The method for manufacturing the packaging structure of the storage chip according to claim 8, characterized in that, After the thermal conductive paste layer is solidified and formed, the portion of the thermal conductive layer extending out of the packaging adhesive layer is bent so as to be attached to the surface of the thermal conductive paste layer.

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