Photomask and alignment method

Abstract

The invention provides a photomask and an alignment method, and relates to the technical field of semiconductors. The photomask comprises N sub-photomasks, and exposure areas formed after the N sub-photomasks are sequentially exposed are adjacently arranged according to a preset mode; wherein two sub-photomasks in the N sub-photomasks are respectively a first sub-photomask and a second sub-photomask, an exposure area corresponding to the first sub-photomask is adjacent to an exposure area corresponding to the second sub-photomask, M first mask identifiers are arranged on the first sub-photomask, and M second mask identifiers are arranged on the second sub-photomask, the M first mask identifiers are in one-to-one correspondence with the M second mask identifiers, the corresponding first mask identifiers and second mask identifiers jointly form a complete identifier pattern, and the identifier pattern is located in a chip area of the photomask. According to the invention, the alignment deviation between two times of exposure can be captured through the pattern formed after exposure of the first mask mark on the first sub-photomask and the second mask mark on the second sub-photomask, so that the alignment precision is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a photomask and an alignment method. Background Art

[0002] A photomask plays a crucial role in the lithography process in the semiconductor field. It is one of the key components for transferring the pattern of microelectronic devices onto a wafer. Its main function is to serve as a "template" for the pattern during the lithography process, and form an accurate micro-structure pattern on the wafer surface through light irradiation.

[0003] In the related art, the alignment marks on the photomask can only provide an alignment reference for single exposure, and cannot effectively reflect the relative error between two exposures. Therefore, the alignment deviation between each exposure cannot be captured in real time and dynamically, resulting in low overall alignment accuracy.

[0004] How to improve the alignment accuracy is an urgent problem to be solved.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The present disclosure provides a photomask and an alignment method, which can improve the alignment accuracy to at least a certain extent.

[0007] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, there is provided a photomask, including: N sub-photomasks, the exposure areas formed after sequential exposure of the N sub-photomasks are arranged adjacent to each other in a predetermined manner, where N is an integer greater than or equal to 2; wherein, two of the N sub-photomasks are a first sub-photomask and a second sub-photomask respectively, the exposure area corresponding to the first sub-photomask is adjacent to the exposure area corresponding to the second sub-photomask, M first mask identifiers are provided on the first sub-photomask, M second mask identifiers are provided on the second sub-photomask, the M first mask identifiers and the M second mask identifiers are in one-to-one correspondence, and the corresponding first mask identifier and second mask identifier together form a complete identifier pattern, and the identifier pattern is located in the chip area of the photomask, where M is an integer greater than or equal to 1.

[0009] In an exemplary embodiment of the present disclosure, the first mask identifier and the second mask identifier form a mirror-symmetric pattern.

[0010] In an exemplary embodiment of the present disclosure, the identification pattern includes a closed pattern.

[0011] In an exemplary embodiment of the present disclosure, the pattern of the first mask identification is Z-shaped or E-shaped.

[0012] In an exemplary embodiment of the present disclosure, the identification pattern includes an overlapping pattern.

[0013] In an exemplary embodiment of the present disclosure, both the first sub-mask and the second sub-mask include a splicing area. The patterns of the first mask identification and the second mask identification are both W-shaped. A part of the first mask identification is located in the splicing area of the first sub-mask, and a part of the second mask identification is located in the splicing area of the second sub-mask. The part of the second mask identification located in the splicing area overlaps with a part of the first mask identification located in the chip area, and the part of the first mask identification located in the splicing area overlaps with a part of the second mask identification located in the chip area.

[0014] In an exemplary embodiment of the present disclosure, N is 2. The exposure area corresponding to the first sub-mask and the exposure area corresponding to the second sub-mask are arranged along a first direction, and the first direction is the length direction of the chip area.

[0015] In an exemplary embodiment of the present disclosure, M is 2. The two first mask identifications on the first sub-mask are distributed along a second direction, and the second direction is the width direction of the chip area.

[0016] According to another aspect of the present disclosure, an alignment method is provided, including: performing a lithography process on a wafer using the mask described in any one of the above; the wafer is formed with a first identification pattern and a second identification pattern, the first identification pattern is the pattern corresponding to the exposure of the first mask identification, and the second identification pattern is the pattern corresponding to the exposure of the second mask identification; using any exposure area having a matching first identification pattern and second identification pattern as a measurement unit to obtain the alignment offset of the second identification pattern relative to the first identification pattern; feeding back the alignment offset to the lithography machine control unit so that the lithography machine control unit adjusts the offset of the wafer stage and / or the offset angle of the mask according to the alignment offset.

[0017] In an exemplary embodiment of the present disclosure, the first mask identifier and the second mask identifier form a mirror-symmetric pattern, and the corresponding first mask identifier and second mask identifier together form a complete identifier pattern, and the identifier pattern includes a closed pattern; when the identifier pattern is a closed pattern, the alignment offset includes a first offset and a second offset, the first offset is the distance between the first identifier pattern and the second identifier pattern in a first direction, the first direction is the length direction of the chip area of the reticle, and the second offset is the distance between the first identifier pattern and the second identifier pattern in a second direction, the second direction is the width direction of the chip area.

[0018] In an exemplary embodiment of the present disclosure, the first mask identifier and the second mask identifier form a mirror-symmetric pattern, and the corresponding first mask identifier and second mask identifier together form a complete identifier pattern, and the identifier pattern includes an overlapping pattern; both the first sub-reticle and the second sub-reticle include a splicing area, a part of the first mask identifier is located in the splicing area of the first sub-reticle, a part of the second mask identifier is located in the splicing area of the second sub-reticle, the second mask identifier located in the splicing area overlaps with a part of the first mask identifier located in the chip area, and the first mask identifier located in the splicing area overlaps with a part of the second mask identifier located in the chip area; when the identifier pattern is an overlapping pattern, the alignment offset includes a first offset and a second offset, the first offset is the distance between the first identifier pattern corresponding to the first mask identifier located in the chip area and the second identifier pattern corresponding to the second mask identifier located in the chip area in a first direction, the first direction is the length direction of the chip area of the reticle, and the second offset is the distance between the first identifier pattern corresponding to the first mask identifier located in the chip area and the second identifier pattern corresponding to the second mask identifier located in the chip area in a second direction, the second direction is the width direction of the chip area.

[0019] In an exemplary embodiment of the present disclosure, adjusting the offset of the wafer stage and / or the offset angle of the reticle according to the alignment offset includes: inputting the alignment offset into a pre-trained machine learning model, and outputting a first compensation value for adjusting the offset of the wafer stage and / or a second compensation value for adjusting the offset angle of the reticle.

[0020] The photomask provided by the present disclosure includes N sub-photomasks. The exposure areas formed after the N sub-photomasks are exposed in sequence are arranged adjacent to each other in a predetermined manner, where N is an integer greater than or equal to 2. Among them, two of the N sub-photomasks are the first sub-photomask and the second sub-photomask respectively. The exposure area corresponding to the first sub-photomask is adjacent to the exposure area corresponding to the second sub-photomask. There are M first mask identifiers provided on the first sub-photomask, and M second mask identifiers provided on the second sub-photomask. The M first mask identifiers and the M second mask identifiers correspond to each other one by one, and the corresponding first mask identifier and second mask identifier together form a complete identification pattern. The identification pattern is located in the chip area of the photomask, where M is an integer greater than or equal to 1. The present disclosure can capture the alignment deviation between two exposures through the patterns (the first identification pattern and the second identification pattern in the following) formed by the first mask identifier on the first sub-photomask and the second mask identifier on the second sub-photomask after exposure, thereby improving the alignment accuracy. In addition, the first mask identifier and the second mask identifier can be spliced into a complete identification pattern, and the identification pattern is located in the chip area, which can save the wafer area and reduce the production cost. That is to say, the pattern formed after the identification pattern is exposed is embedded in the process area and does not occupy additional wafer area, thereby saving the wafer area.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 The schematic structural diagram of the photomask in an embodiment of the present disclosure is shown.

[0024] Figure 2 The schematic structural diagram of the photomask in another embodiment of the present disclosure is shown.

[0025] Figure 3 The schematic diagram of a part of the wafer in an embodiment of the present disclosure is shown.

[0026] Figure 4 The schematic diagram after the current layer of a part of the wafer is exposed is shown.

[0027] Figure 5 The schematic diagram after the current layer of a part of the wafer is exposed is shown.

[0028] Figure 6Schematic diagram showing the first sub-photomask and the second sub-photomask spliced together in an embodiment of the present disclosure.

[0029] Figure 7 Schematic diagram showing the first sub-photomask and the second sub-photomask spliced together in another embodiment of the present disclosure.

[0030] Figure 8 Schematic diagram showing the first sub-photomask and the second sub-photomask spliced together in yet another embodiment of the present disclosure.

[0031] Figure 9 Schematic diagram showing the splicing of the first sub-photomask and the second sub-photomask in an embodiment of the present disclosure.

[0032] Figure 10 Flowchart of an alignment method in an embodiment of the present disclosure.

[0033] Figure 11 Schematic diagram showing the structures of the first identification pattern and the second identification pattern in an embodiment of the present disclosure.

[0034] Figure 12 Schematic diagram showing the structures of the first identification pattern and the second identification pattern in another embodiment of the present disclosure.

[0035] Figure 13 Schematic diagram showing the structures of the first sub-photomask and the second sub-photomask after exposure in an embodiment of the present disclosure.

[0036] Figure 14 Schematic diagram showing the structures of the first identification pattern and the second identification pattern in yet another embodiment of the present disclosure. Detailed implementation manners

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0038] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0039] It should be understood that the various steps described in the method embodiments of the present disclosure can be executed in different orders and / or executed in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this regard.

[0040] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependent relationships.

[0041] It should be noted that the modifications of "one" and "plural" mentioned in the present disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly stated otherwise in the context, it should be understood as "one or more".

[0042] In the related art, the alignment marks on the photomask can only provide the alignment reference for single exposure and cannot effectively reflect the relative error between two exposures. Therefore, the alignment deviation between each exposure cannot be captured in real time and dynamically, which results in low overall alignment accuracy. In addition, the alignment accuracy is detected by independent alignment marks, and the detection accuracy of the independent marks is affected by the resolution of the lithography equipment and the interference of the measurement equipment, making it difficult to meet the nano-level alignment requirements.

[0043] Based on at least one of the above problems, the embodiments of the present disclosure provide a photomask and an alignment method, which can be applied to the lithography process of semiconductors. Exemplarily, a double photomask process can be applied. According to the technical solution provided by the embodiments of the present disclosure, the photomask provided by the present disclosure includes N sub-photomasks, and the exposure areas formed after the N sub-photomasks are exposed in sequence are arranged adjacent to each other in a predetermined manner, where N is an integer greater than or equal to 2; among them, two of the N sub-photomasks are respectively the first sub-photomask and the second sub-photomask, the exposure area corresponding to the first sub-photomask is adjacent to the exposure area corresponding to the second sub-photomask, M first mask identifiers are provided on the first sub-photomask, M second mask identifiers are provided on the second sub-photomask, the M first mask identifiers and the M second mask identifiers correspond to each other one by one, and the corresponding first mask identifier and second mask identifier jointly form a complete identifier pattern, and the identifier pattern is located in the chip area of the photomask, where M is an integer greater than or equal to 1. The present disclosure can capture the alignment deviation between two exposures through the patterns formed by the first mask identifiers on the first sub-photomask and the second mask identifiers on the second sub-photomask, thereby improving the alignment accuracy. In addition, the first mask identifier and the second mask identifier can be spliced into a complete identifier pattern, and the identifier pattern is located in the chip area, which can save the wafer area and reduce the production cost.

[0044] The following will describe this exemplary embodiment in detail with reference to the drawings and embodiments.

[0045] In an embodiment of the present disclosure, a photomask is provided. The photomask may include: N sub-photomasks, and the exposure regions formed after the N sub-photomasks are sequentially exposed are arranged adjacent to each other in a predetermined manner, where N is an integer greater than or equal to 2; among them, two of the N sub-photomasks are respectively a first sub-photomask and a second sub-photomask, the exposure region corresponding to the first sub-photomask is adjacent to the exposure region corresponding to the second sub-photomask, M first mask identifiers are provided on the first sub-photomask, M second mask identifiers are provided on the second sub-photomask, the M first mask identifiers and the M second mask identifiers correspond one by one, and the corresponding first mask identifier and second mask identifier together form a complete identification pattern, and the identification pattern is located in the chip area of the photomask, where M is an integer greater than or equal to 1.

[0046] In an embodiment of the present disclosure, each of the N sub-photomasks forms an exposure region after exposure. Regarding the arrangement manner of the N exposure regions corresponding to the N sub-photomasks, the embodiment of the present disclosure does not make a specific limitation, and the predetermined manner can be set according to specific application scenarios and actual application experience. For example, the N exposure regions are arranged along a first direction, and the first direction is the length direction (X direction) of the chip area. For another example, the N exposure regions are arranged along a second direction, and the second direction is the width direction (Y direction) of the chip area. For still another example, the N exposure regions are arranged in a rectangle.

[0047] It should be noted that, as Figure 1 shown, the photomask 10 includes a chip area 11 and a peripheral area 12. The chip area 11 is the area where the chip is formed after the photomask is exposed, and the peripheral area 12 is the peripheral area of the photomask, which is not used for exposing to form a chip, but is used to provide an optical boundary and ensure the uniformity of exposure.

[0048] Exemplarily, as Figure 1 shown, the photomask 10 includes 3 sub-photomasks, the 3 sub-photomasks are arranged along the X direction, two of the 3 sub-photomasks are respectively a first sub-photomask 13 and a second sub-photomask 14, the exposure region corresponding to the first sub-photomask 13 is adjacent to the exposure region corresponding to the second sub-photomask 14, 2 first mask identifiers 15 are provided on the first sub-photomask 13, 2 second mask identifiers 16 are provided on the second sub-photomask, the 2 first mask identifiers 15 and the 2 second mask identifiers 16 correspond one by one, and the corresponding first mask identifier 15 and second mask identifier 16 together form a complete identification pattern. It should be noted that when the exposure region corresponding to a sub-photomask is located between two exposure regions, other mask identifiers may also be included on this sub-photomask. For example, Figure 1 the mask identifier on the right side of the second sub-photomask 14 in

[0049] Exemplarily, as Figure 2As shown, the photomask 10 includes nine sub-photomasks, which are distributed in a rectangular array. The sub-photomasks corresponding to two adjacent exposure regions are the first sub-photomask 13 and the second sub-photomask 14 respectively. The first sub-photomask 13 includes two first mask identifiers 15, and the second sub-photomask includes two second mask identifiers 16. The two first mask identifiers 15 correspond to the two second mask identifiers 16 one by one, and the corresponding first mask identifier 15 and second mask identifier 16 together form a complete identification pattern.

[0050] It should be noted that the photomask of the present disclosure is exposed N times to complete the exposure of a chip region to be formed on the wafer. That is to say, the region formed by splicing the N exposure regions together is the region of the chip to be formed.

[0051] Exemplarily, as Figure 3 shown, the wafer may include multiple chip regions 31 to be formed. The region between two adjacent chip regions 31 to be formed is a cutting channel (Cutting Line). After using the photomask of the present disclosure (such as Figure 1 the photomask in Figure 4 to sequentially expose all the chip regions 31 to be formed, and after development, etching, and photoresist removal processes, a pattern 41 corresponding to the exposed identification pattern is formed. The pattern 41 is located in the chip region 31 to be formed on the wafer, as

[0052] shown. The pattern 41 formed after the exposure of the identification pattern is embedded in the process region and does not occupy additional wafer area, thereby saving wafer area.

[0052] The embodiments of the present disclosure can further save wafer area. Since the first mask identifier and the second mask identifier are located in the chip region of the photomask, the alignment identifier can be set in the chip region. The first sub-photomask is aligned with the alignment identifier of the previous layer, and the second sub-photomask is aligned with the first sub-photomask. That is to say, the alignment of the photomask can be achieved without setting an identifier on the cutting channel. The present disclosure can reduce the width of the cutting channel, thereby further increasing the area for manufacturing chips. That is to say, more chips can be manufactured on the same wafer using the photomask of the present disclosure, thereby reducing the production cost. The schematic diagram of the wafer after exposure with a reduced cutting channel is as Figure 5 shown, and the pattern 41 is located in the chip region to be formed on the wafer. Figure 5 and Figure 4 can manufacture the same number of chips, but Figure 5 the wafer area used is smaller. That is to say, for wafers of the same area, using the photomask of the present disclosure for lithography can reduce the width of the cutting channel, thereby manufacturing more chips.

[0053] In the embodiments of the present disclosure, the alignment deviation between two exposures can be captured by the first mask identification on the first sub-mask and the second mask identification on the second sub-mask to form a pattern after exposure, thereby improving the alignment accuracy. In addition, the first mask identification and the second mask identification can be spliced into a complete identification pattern, and the identification pattern is located in the chip area, which can save the wafer area and reduce the production cost. That is to say, the pattern formed after the identification pattern is exposed is embedded in the process area and does not occupy additional wafer area, thereby saving the wafer area.

[0054] The following describes the present disclosure through several exemplary embodiments.

[0055] In an exemplary embodiment, the first mask identification and the second mask identification form a mirror-symmetrical pattern.

[0056] In the embodiments of the present disclosure, the first identification pattern and the second identification pattern formed after the first mask identification and the second mask identification that are mirror-symmetrical are also mirror-symmetrical patterns, and the axis of symmetry is the junction of the two exposure areas, that is to say, the junction of the exposure areas formed by the two exposures.

[0057] In the embodiments of the present disclosure, the first mask identification and the second mask identification form a mirror-symmetrical pattern, which is convenient for judging whether there is an alignment error, thereby improving the alignment error detection accuracy to the nanometer level.

[0058] Exemplarily, if the first identification pattern and the second identification pattern are completely symmetrical, the alignment error is 0. If the first identification pattern and the second identification pattern are misaligned, there is an error, and the alignment error is calculated by measuring the offset between the first identification pattern and the second identification pattern.

[0059] Regarding how to measure the offset between the first identification pattern and the second identification pattern, the embodiments of the present disclosure do not make specific limitations. For example, the offset between the first identification pattern and the second identification pattern is measured by electron beam detection or an optical microscope (such as a scanning electron microscope (SEM)).

[0060] In order to further improve the detection accuracy, the following embodiments are provided by the present disclosure.

[0061] In one embodiment, the identification pattern may include a closed pattern.

[0062] In the embodiments of the present disclosure, the boundary of the closed pattern is closed, and the embodiments of the present disclosure can determine the alignment error according to the closing degree of the identification pattern after exposure.

[0063] In the embodiments of the present disclosure, the shape of the first mask identifier is not specifically limited, as long as it can make the identifier pattern include a closed pattern. Exemplarily, the shape of the first mask identifier is C-shaped, X-shaped, Z-shaped or E-shaped.

[0064] For example, as Figure 6 shown, a first mask identifier 15 is provided on the first sub-mask 13, and the shape of the first mask identifier 15 is E-shaped. A second mask identifier 16 is provided on the second sub-mask 14, and the shape of the second mask identifier 16 is symmetrical to the shape of the first mask identifier 15. The corresponding first mask identifier 15 and second mask identifier 16 together form a complete identifier pattern 17.

[0065] For another example, as Figure 7 shown, a first mask identifier 15 is provided on the first sub-mask 13, and the shape of the first mask identifier 15 is Z-shaped. A second mask identifier 16 is provided on the second sub-mask 14, and the shape of the second mask identifier 16 is symmetrical to the shape of the first mask identifier 15. The corresponding first mask identifier 15 and second mask identifier 16 together form a complete identifier pattern 17.

[0066] In the embodiments of the present disclosure, the first mask identifier and the second mask identifier together form a closed pattern, and an interlocking structure is formed after the first mask identifier and the second mask identifier are exposed, which is convenient for detecting the alignment error and can improve the alignment error detection accuracy to the nanometer level.

[0067] In another embodiment, the identifier pattern may include an overlapping pattern.

[0068] In the embodiments of the present disclosure, the first mask identifier and the second mask identifier partially overlap to form an overlapping pattern. In the embodiments of the present disclosure, the alignment error can be determined according to the overlapping degree of the identifier pattern after exposure.

[0069] In the embodiments of the present disclosure, the shape of the first mask identifier is not specifically limited, as long as it can make the identifier pattern include an overlapping pattern. Exemplarily, the identifier pattern is an overlapping pattern.

[0070] For example, as Figure 8As shown, the first sub-mask 13 and the second sub-mask 14 both include a splicing area 18. The patterns of the first mask identifier 15 and the second mask identifier 16 are both in the shape of a "W". Part of the first mask identifier 15 is located in the splicing area 18 of the first sub-mask 13, and part of the second mask identifier 16 is located in the splicing area 18 of the second sub-mask 14. The second mask identifier 16 located in the splicing area 18 overlaps with part of the first mask identifier 15 located in the chip area, and the first mask identifier 15 located in the splicing area 18 overlaps with part of the second mask identifier 16 located in the chip area. It should be noted that a part of the first mask identifier 15 is located in the chip area, and the other part is located in the splicing area 18 of the first sub-mask 13. A part of the second mask identifier 16 is located in the chip area, and the other part is located in the splicing area 18 of the second sub-mask 14. During the exposure process, the first sub-mask 13 is aligned with the alignment mark of the previous layer for exposure. After that, the splicing area 18 of the second sub-mask 14 overlaps with the splicing area 18 of the first sub-mask 13 for exposure. The first identification pattern corresponding to the first mask identifier 15 and the second identification pattern corresponding to the second mask identifier 16 overlap.

[0071] In the embodiment of the present disclosure, the first mask identifier and the second mask identifier jointly form an overlapping pattern. After the first mask identifier and the second mask identifier are exposed, an overlapping structure is formed, which is convenient for detecting the alignment error and can improve the alignment error detection accuracy to the nanometer level.

[0072] In the embodiment of the present disclosure, the alignment offset can be determined by detecting the symmetry degree between the first identification pattern and the second identification pattern in real time. The alignment offset can reflect the alignment deviation between each exposure, so as to adjust the offset of the wafer stage (Stage) and / or the offset angle of the mask according to the alignment offset, thereby reducing the alignment error and improving the alignment accuracy.

[0073] The present disclosure will be described below through an application scenario of two exposures, but the present disclosure is not limited to the application scenario of two exposures.

[0074] In one embodiment, N = 2, and the exposure area corresponding to the first sub-mask and the exposure area corresponding to the second sub-mask are arranged along the first direction, and the first direction is the length direction of the chip area.

[0075] As Figure 9 shown, the exposure area corresponding to the first sub-mask and the exposure area corresponding to the second sub-mask are arranged along the first direction (X direction). The alignment offset is determined by detecting the symmetry degree between the first identification pattern and the second identification pattern in real time.

[0076] It should be noted that in the lithography process, the double-mask technology decomposes complex patterns into two sub-patterns through two exposures to break through the resolution and field-of-view limitations of single exposure. However, the alignment accuracy of the double-mask process directly affects the integrity of the final pattern. If the alignment error exceeds the allowable range, it will lead to defects such as line width deviation, bridging, or disconnection, greatly reducing the chip yield.

[0077] In related technologies, the alignment accuracy is usually detected through independent alignment marks (such as cross-shaped or circular marks pre-etched on the silicon wafer). However, static detection has certain limitations and also has defects in terms of detection accuracy authorization.

[0078] Independent alignment marks can only provide the alignment reference for single exposure and cannot directly reflect the relative error between two exposures; in addition, the detection accuracy of independent alignment marks is affected by the resolution of lithography equipment and the interference of measurement equipment, making it difficult to meet the nano-level alignment requirements.

[0079] Using the mask in the embodiments of the present disclosure can solve the above problems. Based on the first identification pattern corresponding to the first mask identification and the second identification pattern corresponding to the second mask identification, the relative error between two exposures can be directly reflected, facilitating subsequent adjustment according to the relative error to improve the alignment accuracy. In addition, according to the characteristics of the first identification pattern and the second mask identification (such as the closed characteristic and the overlapping characteristic), the detection accuracy of the alignment error can be improved to the nano-level.

[0080] In another embodiment, in order to further improve the accuracy of detecting the alignment error, multiple mask identifications are provided on each sub-mask.

[0081] Exemplarily, as Figure 7 shown, M is 2, and the two first mask identifications 15 on the first sub-mask 13 are distributed along the second direction, and the second direction is the width direction (Y direction) of the chip area.

[0082] In the embodiments of the present disclosure, after the first mask identification is exposed, a first identification pattern is formed, and after the second mask identification is exposed, a second identification pattern is formed. By calculating the alignment error between two sets of matching first identification patterns and second identification patterns, the alignment offset amount when the first sub-mask and the second sub-mask are exposed can be obtained, which can improve the accuracy of detecting the alignment error, thereby realizing more precise adjustment of the lithography equipment and improving the alignment accuracy.

[0083] Using the mask in the embodiments of the present disclosure for lithography can realize real-time detection and compensation of the alignment error, reduce the impact of the alignment error on the final lithography pattern, reduce rework or scrapping caused by the alignment error, and improve the production yield.

[0084] Based on the same inventive concept, an alignment method is also provided in the embodiments of the present disclosure, as described in the following embodiments. Since this alignment method uses the above-mentioned photomask to solve the problem, the implementation of the embodiments of this alignment method can refer to the implementation of the above-mentioned photomask embodiments, and the repeated parts will not be elaborated.

[0085] An alignment method is provided in the embodiments of the present disclosure, and this method can be executed by any electronic device or control system with computing and lithography capabilities.

[0086] Figure 10 The flowchart of an alignment method in the embodiments of the present disclosure is shown, as Figure 10 shown, this alignment method includes the following S1001 to S1003.

[0087] S1001, perform a lithography process on the wafer using the aforementioned photomask. The wafer is formed with a first identification pattern and a second identification pattern. The first identification pattern is the pattern corresponding to the exposure of the first mask identification, and the second identification pattern is the pattern corresponding to the exposure of the second mask identification.

[0088] In the embodiments of the present disclosure, the lithography machine performs a lithography process on the wafer using the above-mentioned photomask. The photomask includes a first sub-photomask and a second sub-photomask. The exposure area corresponding to the first sub-photomask is adjacent to the exposure area corresponding to the second sub-photomask. The first sub-photomask includes a plurality of first mask identifications, and the second sub-photomask includes a plurality of second mask identifications. The plurality of first mask identifications and the plurality of second mask identifications correspond one by one, and the corresponding first mask identification and second mask identification together form a complete identification pattern.

[0089] Exemplarily, the first sub-photomask is aligned with the alignment identification of the previous layer, and the first sub-photomask is used for exposure to form a first identification pattern corresponding to the first mask identification on the wafer. The second mask identification on the second sub-photomask is aligned with the first identification pattern, and the second sub-photomask is used for exposure to form a second identification pattern corresponding to the first mask identification on the wafer. In the embodiments of the present disclosure, during the lithography process, using the second mask identification on the second sub-photomask to align with the first identification pattern can improve the alignment accuracy.

[0090] Exemplarily, the first sub-photomask is aligned with the alignment identification of the previous layer, and the first sub-photomask is used for the first exposure to form a first identification pattern corresponding to the first mask identification on the wafer. The lithography machine configures the second sub-photomask to the corresponding position for the second exposure according to the preset position parameters of the second sub-photomask, and forms a second identification pattern corresponding to the first mask identification on the wafer.

[0091] S1002, use any exposure area with a matching first identification pattern and second identification pattern as a measurement unit to obtain the alignment offset of the second identification pattern relative to the first identification pattern.

[0092] In the embodiments of the present disclosure, the alignment offset of the second identification pattern relative to the first identification pattern can be obtained by one measurement unit. It can also be obtained by multiple measurement units.

[0093] Exemplarily, the exposure area of the first sub-mask is called the first exposure area, and the exposure area of the second sub-mask is called the second exposure area. The first identification pattern is located on one side of the first exposure area close to the second exposure area, and the second identification pattern is located on one side of the second exposure area close to the first exposure area. That is to say, multiple first identification patterns and multiple second identification patterns correspond one by one and are distributed on both sides of the junction of the first exposure area and the second exposure area. Suppose there are 5 first identification patterns in the first exposure area, then there are 5 groups of matching first identification patterns and second identification patterns in total. The alignment offset of the second identification pattern relative to the first identification pattern can be obtained by selecting the group with the largest error from the 5 groups. The alignment offset of 5 groups of second identification patterns relative to the first identification pattern can also be obtained.

[0094] In the embodiments of the present disclosure, the device for measuring the alignment offset is not specifically limited. For example, the offset between the second identification pattern and the first identification pattern is measured by electron beam detection or optical microscopy.

[0095] S1003, feedback the alignment offset to the lithography machine control unit so that the lithography machine control unit adjusts the offset of the wafer stage and / or the offset angle of the mask according to the alignment offset.

[0096] In the embodiments of the present disclosure, the lithography machine control unit is the core control system in the lithography machine, which is used to coordinate and manage various operations in the lithography process. It is responsible for controlling various components of the lithography machine, such as the exposure light source, the mask stage, the wafer stage (also known as the wafer carrier), the lens system, etc., to ensure the precise execution of the lithography process.

[0097] In the embodiments of the present disclosure, feeding back the alignment offset to the lithography machine control unit means feeding back the alignment error to the lithography machine, which is convenient for the lithography machine to adjust the wafer position and / or the offset angle of the mask according to the alignment offset, thereby improving the alignment accuracy.

[0098] Based on the matching first mask identification and second mask identification, the embodiments of the present disclosure realize the monitoring of the alignment accuracy, and realize the real-time detection and feedback compensation of the alignment error of the patterns on the double masks during the exposure process, which can significantly improve the alignment accuracy and reduce the process defect rate.

[0099] The following describes the present disclosure through several exemplary embodiments.

[0100] In an exemplary embodiment, the first mask identification and the second mask identification form a mirror-symmetric pattern. The corresponding first mask identification and second mask identification together form a complete identification pattern, and the identification pattern includes a closed pattern. When the identification pattern is a closed pattern, the alignment offset includes a first offset and a second offset. The first offset is the distance between the first identification pattern and the second identification pattern in a first direction, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance between the first identification pattern and the second identification pattern in a second direction, and the second direction is the width direction of the chip area.

[0101] In the embodiments of the present disclosure, the identification pattern includes a closed pattern. That is to say, the first identification pattern and the second identification pattern are an interlocking structure. According to the interlocking structure, it is convenient to determine whether the alignment error is 0. If the first identification pattern and the second identification pattern form a complete closed structure, there is no error. If the first identification pattern and the second identification pattern cannot form a complete closed structure, there is an error.

[0102] In one embodiment, complementary Mark patterns (the first mask identification and the second mask identification) are designed on a double photomask (the first sub-photomask and the second sub-photomask). After the first mask identification and the second mask identification are exposed, the first identification pattern and the second identification pattern are formed. As Figure 11 shown, A is the first identification pattern and B is the second identification pattern. The first mask identification is an "E"-shaped structure with an opening, and the second mask identification is an "E"-shaped structure complementary to the first mask identification. The two can be spliced into a closed rectangle during alignment. It should be noted that the size of the first mask identification should match the process node (such as the alignment mark) and be embedded near the splicing position of the two patterns.

[0103] Exemplarily, the shape of the first mask identification is an "E" shape, the opening width is 25 nm (nanometers) - 75 nm, and the length is 100 nm - 300 nm. For example, the opening width is 50 nm and the length is 200 nm. It should be noted that when the first sub-photomask is exposed, the center of the "E" shape is aligned with the alignment reference point of the process critical area.

[0104] The double photomask is exposed twice respectively to form complementary Mark patterns (the first identification pattern and the second identification pattern). After the two exposures, the actual morphology of the interlocking Mark patterns is observed through an optical microscope or an electron beam detection.

[0105] If the alignment error is zero, the interlocking Mark patterns will form a complete closed structure. If there is an error, the closed structure will be misaligned, and the alignment offset ΔX / ΔY is calculated by measuring the offset.

[0106] As Figure 11 or Figure 12As shown, the alignment offset includes a first offset and a second offset. The first offset is the distance between the first identification pattern and the second identification pattern in the first direction, i.e., ΔX, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance between the first identification pattern and the second identification pattern in the second direction, i.e., ΔY, and the second direction is the width direction of the chip area.

[0107] In one embodiment, combining the geometric parameters (such as the opening width, period, etc.) of the Mark pattern, the physical error can be converted into an alignment offset.

[0108] In one embodiment, after exposure, the complementary Mark notch is observed by SEM, and the alignment deviation is calculated by measuring the notch. The alignment deviation is fed back to the lithography machine to adjust the position of the wafer stage, and re-exposure is performed after compensating for the error.

[0109] The embodiments of the present disclosure feed the detected alignment offset back to the lithography machine control unit, and realize closed-loop compensation by adjusting the offset of the wafer stage or the deflection angle of the photomask during exposure, thereby improving the alignment accuracy of exposure.

[0110] It should be noted that the embodiments of the present disclosure support dynamically adjusting the exposure sequence or the photomask stitching strategy to adapt to the error changes under different process conditions.

[0111] The first mask identification and the second mask identification in the embodiments of the present disclosure jointly form a closed pattern. After the first mask identification and the second mask identification are exposed, an interlocking structure is formed, which is convenient for detecting the alignment error and can improve the alignment error detection accuracy to the nanometer level. In addition, the alignment offset is fed back to the lithography machine control unit, and closed-loop compensation is realized by adjusting the offset of the wafer stage or the deflection angle of the photomask during exposure.

[0112] In another exemplary embodiment, the first mask identification and the second mask identification form a mirror-symmetric pattern. The corresponding first mask identification and the second mask identification jointly form a complete identification pattern, and the identification pattern includes an overlapping pattern. Both the first sub-photomask and the second sub-photomask include a stitching area. A part of the first mask identification is located in the stitching area of the first sub-photomask, and a part of the second mask identification is located in the stitching area of the second sub-photomask. The second mask identification located in the stitching area overlaps with a part of the first mask identification located in the chip area, and the first mask identification located in the stitching area overlaps with a part of the second mask identification located in the chip area.

[0113] In the case where the identification pattern is an overlapping pattern, the alignment offset includes a first offset and a second offset. The first offset is the distance between the first identification pattern corresponding to the first mask identification in the chip area and the second identification pattern corresponding to the second mask identification in the chip area in the first direction, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance between the first identification pattern corresponding to the first mask identification in the chip area and the second identification pattern corresponding to the second mask identification in the chip area in the second direction, and the second direction is the width direction of the chip area.

[0114] In the embodiments of the present disclosure, the identification pattern includes an overlapping pattern, and it is convenient to judge whether the alignment error is 0 according to the overlapping characteristics. If the first identification pattern and the second identification pattern form an overlapping structure, there is no error. If the first identification pattern and the second identification pattern cannot form an overlapping structure, there is an error.

[0115] In one embodiment, as Figure 13 shown, both the first sub-photomask 13 and the second sub-photomask 14 include a splicing area 18. A part of the first mask identification 15 is located in the splicing area 18 of the first sub-photomask 13, and a part of the second mask identification 16 is located in the splicing area 18 of the second sub-photomask 14. The second mask identification 16 located in the splicing area 18 overlaps with a part of the first mask identification 15 located in the chip area, and the first mask identification 15 located in the splicing area 18 overlaps with a part of the second mask identification 16 located in the chip area. That is to say, the splicing area 18 of the second sub-photomask 14 is located in the chip area to be formed corresponding to the exposure area of the first sub-photomask 13 during exposure, and a part of the chip area to be formed overlaps with the splicing area 18 of the second sub-photomask 14, so that a part of the first identification pattern formed after the first mask identification 15 located in the splicing area 18 is exposed overlaps with a part of the second identification pattern formed after the second mask identification 16 located in the chip area is exposed.

[0116] As Figure 14 shown, A is the first identification pattern and B is the second identification pattern. The alignment offset includes a first offset and a second offset. The first offset is the distance ΔX in the first direction between the first identification pattern corresponding to the first mask identification in the chip area and the second identification pattern corresponding to the second mask identification in the chip area, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance ΔY in the second direction between the first identification pattern corresponding to the first mask identification in the chip area and the second identification pattern corresponding to the second mask identification in the chip area, and the second direction is the width direction of the chip area.

[0117] It should be noted that if there is an alignment error, the first identification pattern and the second identification pattern will be offset at the splicing point, and the error is calculated by measuring the offset.

[0118] In the embodiments of the present disclosure, the first mask identifier and the second mask identifier together form an overlapping pattern. After the first mask identifier and the second mask identifier are exposed, an overlapping structure is formed, which is convenient for detecting alignment errors and can improve the detection accuracy of alignment errors to the nanometer level. In addition, the alignment offset is fed back to the lithography machine control unit, and the closed-loop compensation is realized by adjusting the offset of the wafer stage or the deflection angle of the reticle during exposure.

[0119] In yet another exemplary embodiment, in an alignment method provided by the present disclosure, adjusting the offset of the wafer stage and / or the offset angle of the reticle according to the alignment offset may include: inputting the alignment offset into a pre-trained machine learning model, and outputting a first compensation value for adjusting the offset of the wafer stage and / or a second compensation value for adjusting the offset angle of the reticle.

[0120] In the embodiments of the present disclosure, the present disclosure embodiments do not limit what specific model the machine learning model is. For example, the machine learning model may be a combination of one or more of a reinforcement learning model, a deep learning model, and a supervised learning model.

[0121] Exemplarily, the machine learning model is trained with historical data as a training set. When the machine learning model meets the required accuracy requirements, it is used as a pre-trained machine learning model. For example, the historical data includes historical alignment offsets, target wafer stage offsets, and target reticle offset angles. The historical alignment offset is input into the machine learning model, and a verified wafer stage offset and a verified reticle offset angle are output. The difference between the target wafer stage offset and the verified wafer stage offset is calculated to obtain a first difference. The difference between the target reticle offset angle and the verified reticle offset angle is calculated to obtain a second difference. The parameters of the machine learning model are adjusted according to the first difference and the second difference until the first difference and the second difference meet a preset value. For example, the preset value is any value in the range of 0 - 0.1.

[0122] For another example, the historical data includes historical alignment offsets and target wafer stage offsets. The historical alignment offset is input into the machine learning model, and a verified wafer stage offset is output. The difference between the target wafer stage offset and the verified wafer stage offset is calculated to obtain a first difference. The parameters of the machine learning model are adjusted according to the first difference until the first difference meets a preset value.

[0123] In the embodiments of the present disclosure, the first compensation value for calculating the offset of the wafer stage and / or the second compensation value for adjusting the offset angle of the reticle by using the machine learning model can improve the dynamic response speed.

[0124] In the embodiments of the present disclosure, by calculating the first compensation value of the wafer stage offset and the second compensation value of the mask offset angle using a machine learning model, the dynamic response speed of the system can be effectively improved, the adjustment time can be reduced, and the overall accuracy and efficiency can be enhanced. This method realizes faster and more accurate process optimization through an intelligent compensation mechanism, further enhancing the automation and stability of the production line.

[0125] Using the mask in the embodiments of the present disclosure for lithography can achieve real-time detection and compensation of alignment errors, reduce the impact of alignment errors on the final lithography pattern, reduce rework or scrap caused by alignment errors, and improve the production yield.

[0126] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be an intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, specify the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0127] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0128] In addition, the specification of this application describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

[0129] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope of the present disclosure is indicated by the appended claims.

Claims

1. A photomask, characterized in that, Including: N sub-photomasks, the exposed areas formed after sequential exposure of the N sub-photomasks are arranged adjacent to each other in a predetermined manner, where N is an integer greater than or equal to 2; Among them, two of the N sub-photomasks are a first sub-photomask and a second sub-photomask respectively. The exposed area corresponding to the first sub-photomask is adjacent to the exposed area corresponding to the second sub-photomask. M first mask identifiers are provided on the first sub-photomask, and M second mask identifiers are provided on the second sub-photomask. The M first mask identifiers and the M second mask identifiers are in one-to-one correspondence, and the corresponding first mask identifier and second mask identifier together form a complete identification pattern. The identification pattern is located in the chip area of the photomask, and M is an integer greater than or equal to 1.

2. The photomask according to claim 1, wherein The first mask identifier and the second mask identifier form a mirror-symmetric pattern.

3. The photomask according to claim 2, wherein, The identification pattern includes a closed pattern.

4. The photomask according to claim 3, characterized in that, The shape of the first mask identifier is Z-shaped or E-shaped.

5. The photomask according to claim 2, characterized in that, The identification pattern includes an overlapping pattern.

6. The photomask according to claim 5, wherein Both the first sub-photomask and the second sub-photomask include a splicing area. The shapes of the first mask identifier and the second mask identifier are both W-shaped. A part of the first mask identifier is located in the splicing area of the first sub-photomask, and a part of the second mask identifier is located in the splicing area of the second sub-photomask. The second mask identifier located in the splicing area overlaps with a part of the first mask identifier located in the chip area, and the first mask identifier located in the splicing area overlaps with a part of the second mask identifier located in the chip area.

7. The photomask according to claim 1, characterized in that, N is 2. The exposed area corresponding to the first sub-photomask and the exposed area corresponding to the second sub-photomask are arranged along a first direction, and the first direction is the length direction of the chip area.

8. The photomask according to claim 1, characterized in that, M is 2. The 2 first mask identifiers on the first sub-photomask are distributed along a second direction, and the second direction is the width direction of the chip area.

9. An alignment method, characterized in that, Including: Performing a lithography process on a wafer using the photomask according to any one of claims 1 to 8. The wafer is formed with a first identification pattern and a second identification pattern. The first identification pattern is the pattern corresponding to the exposure of the first mask identifier, and the second identification pattern is the pattern corresponding to the exposure of the second mask identifier; Taking any exposed area with a matching first identification pattern and second identification pattern as a measurement unit to obtain the alignment offset of the second identification pattern relative to the first identification pattern; Feeding back the alignment offset to a lithography machine control unit so that the lithography machine control unit adjusts the offset of the wafer stage and / or the offset angle of the photomask according to the alignment offset.

10. The alignment method according to claim 9, wherein The first mask identifier and the second mask identifier form a mirror-symmetric pattern. The corresponding first mask identifier and second mask identifier together form a complete identification pattern, and the identification pattern includes a closed pattern; When the identification pattern is a closed pattern, the alignment offset includes a first offset and a second offset. The first offset is the distance between the first identification pattern and the second identification pattern in a first direction, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance between the first identification pattern and the second identification pattern in a second direction, and the second direction is the width direction of the chip area.

11. The alignment method according to claim 9, wherein The first mask identification and the second mask identification form a mirror-symmetric pattern, and the corresponding first mask identification and second mask identification together form a complete identification pattern, and the identification pattern includes an overlapping pattern; Both the first sub-photomask and the second sub-photomask include a splicing area. A part of the first mask identification is located in the splicing area of the first sub-photomask, and a part of the second mask identification is located in the splicing area of the second sub-photomask. The part of the second mask identification located in the splicing area overlaps with a part of the first mask identification located in the chip area, and the part of the first mask identification located in the splicing area overlaps with a part of the second mask identification located in the chip area; When the identification pattern is an overlapping pattern, the alignment offset includes a first offset and a second offset. The first offset is the distance between the first identification pattern corresponding to the first mask identification located in the chip area and the second identification pattern corresponding to the second mask identification located in the chip area in a first direction, and the first direction is the length direction of the chip area of the photomask. The second offset is the distance between the first identification pattern corresponding to the first mask identification located in the chip area and the second identification pattern corresponding to the second mask identification located in the chip area in a second direction, and the second direction is the width direction of the chip area.

12. The alignment method according to claim 9, wherein Adjusting the offset of the wafer stage and / or the offset angle of the photomask according to the alignment offset includes: Inputting the alignment offset into a pre-trained machine learning model to output a first compensation value for adjusting the offset of the wafer stage and / or a second compensation value for adjusting the offset angle of the photomask.

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