Capacity adjusting method of cache space and computer equipment

Abstract

The invention relates to the field of computer storage, and provides a cache space capacity adjusting method and computer device.The method comprises the steps that cache access information of a processor executing cache access operation is obtained; performing feature extraction on the cache access information to obtain data feature information corresponding to the cache access information; predicting the space size of a data cache space required by a processor according to the data feature information to obtain the predicted capacity of the cache space; determining an adjustment strategy for adjusting the space size of the data cache space based on the cache space prediction capacity; and adjusting the space size of the data cache space according to the adjustment strategy. Due to the fact that the size of the cache space needed by the equipment is predicted, and the space size of the cache space is adjusted according to the prediction result, the size of the cache space can adapt to the requirements of the equipment, the flexibility of the size of the cache space is improved, and the utilization rate of hardware is improved.

Description

Technical Field

[0001] The present application relates to the field of computer storage, and particularly to a method for adjusting the capacity of a cache space and a computer device. Background Art

[0002] Cache is a storage technology that uses high-speed storage components in a computer system to store frequently accessed data, so as to reduce the number of accesses by the processor to low-speed storage components (such as hard disks), thereby improving the response speed of the computer system. Existing computer components usually use at least a part of the storage space in the memory (RAM) as the cache space. For example, a storage space of a preset size in the memory is used as the cache space. This method results in that during the operation of the computer system, the cache space is either over-occupied, causing resource waste, or the cache frequently fails due to insufficient space, reducing the system performance. How to more flexibly manage the cache space has become an urgent problem to be solved. Summary of the Invention

[0003] The main purpose of the present application is to provide a method for adjusting the capacity of a cache space and a computer device, aiming to improve the flexibility of the cache space size.

[0004] In a first aspect, the present application provides a method for adjusting the capacity of a cache space, and the method for adjusting the capacity of the cache space includes the following steps:

[0005] Obtain cache access information of the processor executing a cache access operation;

[0006] Extract features from the cache access information to obtain data feature information corresponding to the cache access information;

[0007] Predict the space size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity;

[0008] Based on the predicted cache space capacity, determine an adjustment strategy for adjusting the space size of the data cache space;

[0009] Adjust the space size of the data cache space according to the adjustment strategy.

[0010] In a second aspect, the present application further provides a computer device, which includes a processor, a memory, and a computer program stored on the memory and executable by the processor. When the computer program is executed by the processor, the method for adjusting the capacity of the cache space as described above is implemented.

[0011] The present application provides a method and device for adjusting the capacity of a cache space. The present application obtains cache access information of a processor performing a cache access operation; extracts features from the cache access information to obtain data feature information corresponding to the cache access information; predicts the space size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity; determines an adjustment strategy for adjusting the space size of the data cache space based on the predicted cache space capacity; and adjusts the space size of the data cache space according to the adjustment strategy. Since the size of the cache space required by the device is predicted and the size of the cache space is adjusted according to the prediction result, the size of the cache space can adapt to the needs of the device, improving the flexibility of the cache space size and thus improving the utilization rate of the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a flowchart showing the method for adjusting the capacity of a cache space provided by an embodiment of the present application;

[0014] Figure 2 It is a flowchart showing the sub-steps of the method for adjusting the capacity of a cache space provided by an embodiment of the present application;

[0015] Figure 3 It is a schematic diagram showing the first predicted space capacity and the second predicted space capacity provided by an embodiment of the present application;

[0016] Figure 4 It is a schematic block diagram showing the structure of a computer device involved in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0018] The flowcharts shown in the accompanying drawings are only illustrative examples, not necessarily including all the content and operations / steps, nor necessarily executed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged, so the actual execution order may change according to the actual situation.

[0019] An embodiment of the present application provides a method for adjusting the capacity of a cache space and a computer device.

[0020] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0021] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a method for adjusting the capacity of a cache space provided by an embodiment of the present application. This method for adjusting the capacity of the cache space can be used in a terminal or a server to adjust the size of the cache space of the terminal or the server. Among them, the terminal can be an electronic device such as a mobile phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device; the server can be an independent server, a server cluster, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, Content Delivery Network (CDN), and big data and artificial intelligence platforms.

[0022] Please refer to Figure 2 , Figure 2 which is a usage scenario diagram provided by an embodiment of the present application. As shown in Figure 2 , the target screenshot obtained during the execution of the operation script can be obtained by the server from the terminal device, and the test report can be stored in the server or the terminal device, which is not limited here.

[0023] As shown in Figure 1 , this method for adjusting the capacity of the cache space includes steps S101 to S105.

[0024] Step S101: Obtain cache access information of the processor executing cache access operations.

[0025] Exemplarily, the cache access information is the relevant information of operations performed on the cache space captured at various key nodes of the computer system. For example, the relevant information of the data transfer request between the processor and the memory captured at the front-side bus interface of the processor, the relevant information of the memory read and write operations captured at the control channel of the memory controller, and the relevant information collected by the data acquisition module deployed at the storage device interface. Specifically, at the interfaces of relevant devices of the computer system, such as the Serial ATA (SATA) interface and the Non-Volatile Memory Express (NVMe) interface, based on the hardware interrupt mechanism, a response can be made at the first time when a data access event occurs to ensure the timeliness and integrity of the collected cache access information.

[0026] Exemplarily, the cache access information includes, but is not limited to, one or more of access time information, access address information, operation type information, and associated process information, so as to determine the characteristics of the cache access operation based on the diversified cache access information.

[0027] Among them, the access time information is used to reflect the time when the cache access operation occurs, and can be a timestamp recorded by a high-precision hardware clock. For example, a timestamp accurate to the nanosecond level recorded by a clock source based on a crystal oscillator is used to ensure that the time accuracy meets the requirements of subsequent complex data analysis. The access address information is used to reflect the storage address of the cache data targeted by the cache access operation, and can be the physical address and virtual address of the accessed data obtained based on the address mapping information of the Memory Management Unit (MMU). The operation type information is used to reflect the control signal corresponding to the cache access operation. For example, it can be a read signal (RD), a write signal (WR), a modify signal (MOD), etc. The associated process information is used to reflect the application program or process that initiates the cache access operation, and the process identifier (PID) of the application program that initiates the cache access operation can be obtained based on the process management mechanism of the operating system to determine the associated process information.

[0028] Exemplarily, during the operation of a computer system, a large amount of cache access information may be generated. To save the space required for storing cache access information, a columnar storage database such as ClickHouse can be used. Based on vectorized computing and data compression technologies, it can efficiently store large-scale cache access information. To improve the retrieval efficiency of cache access information, the cache access information can be stored in sub-tables, divided according to time dimensions (such as daily, weekly) and associated process information, and multi-level indexes can be established. For example, a balanced tree (abbreviated as B-tree) index based on access time information and a hash index based on access address information can be used to achieve multi-dimensional and fast data retrieval.

[0029] Step S102: Extract features from the cache access information to obtain data feature information corresponding to the cache access information.

[0030] Exemplarily, before feature extraction, the cache access information can be first subjected to data cleaning. Among them, data cleaning includes the rationality check of access time information, the validity verification of access address information, and noise data processing.

[0031] Specifically, a reasonable range of access time information can be set, for example, between the computer system startup time and the current time, to check whether the access time information is within this reasonable range, and the access time information outside this reasonable range can be excluded or repaired. The time interval between adjacent access time information can also be checked to exclude data records with time reversal between adjacent access time information.

[0032] Specifically, according to the memory address space range of the computer system and the logical address range of the storage device, the validity of the access address information can be verified, and illegal addresses can be excluded or corrected, such as access address information that exceeds the memory address space range or the logical address range of the storage device.

[0033] Specifically, based on statistical analysis methods such as the 3σ principle, noise points in the cache access information can be identified. For cache access information that significantly deviates from the normal range, such as abnormally high or low data access frequencies, further verification can be carried out. For incorrect data, according to the source and characteristics of the data, attempts can be made to repair or discard it.

[0034] Exemplarily, the data feature information includes at least one of the following: access frequency information, access interval information, access pattern information, and process type information.

[0035] In some embodiments, the extracting features from the cache access information to obtain data feature information corresponding to the cache access information includes:

[0036] Determine the data block corresponding to the cache access operation according to the access address information in the cache access information;

[0037] Determine the access frequency information and access interval information of each data block according to the access time information in the cache access information.

[0038] Exemplarily, the cache space is composed of multiple data blocks. Since the address corresponding to each data block is determined, the data block to which the cache access operation belongs can be determined according to the access address information in the cache access information, and thus the access frequency information and access interval information of the data block can be determined according to the access time information.

[0039] Exemplarily, the access frequency information can be the access frequency for a specific data block in the data cache space within a preset time window, and the access time interval can be the interval between two cache access operations for a specific data block. Among them, the preset time window can be time windows of different sizes, such as 1 minute, 5 minutes, 1 hour. The sliding window algorithm is used to count the access times of each data block within different time windows to obtain the access frequency information of each data block within different time windows, and capture the short-term and long-term trends of the cache access operations for each data block. The access time interval can be obtained by maintaining the cache access information of each data block. When each cache access operation occurs, record the interval from the previous access time, and use statistical features such as the mean, variance, maximum value, and minimum value of the access time interval as the access interval information describing data access.

[0040] In some embodiments, the extracting features from the cache access information to obtain the data feature information corresponding to the cache access information includes:

[0041] Determine a cache access sequence according to the cache access information, and the position of the cache access information in the cache access sequence is determined by the access time information;

[0042] Perform pattern recognition on the cache access sequence to obtain the access pattern information corresponding to each cache access information in the cache access sequence; [[ID= nineteen]]

[0043] Among them, the access pattern information includes: sequential access pattern, random access pattern, periodic access pattern.

[0044] Exemplarily, the cache access sequence can be determined in sequence according to the access time information of the cache access information, and the sequence pattern mining algorithm in machine learning, such as the PrefixSpan algorithm, etc., can be used to perform pattern recognition on the cache access sequence to determine the data access pattern, such as sequential access pattern, random access pattern, periodic access pattern, so as to better understand the data access rule and provide a more accurate basis for predicting the space size of the data cache space.

[0045] Among them, the sequential access pattern means that specific cache access operations always occur in a certain order. For example, operation A is always followed immediately by operation B and operation C, presenting an order of "operation A - operation B - operation C"; the periodic access pattern means that cache access operations have a certain periodicity in terms of the time of occurrence. For example, operation D or "operation A - operation B - operation C" appears approximately every hour; the random access pattern means that the cache access information neither belongs to the sequential access pattern nor the periodic access pattern.

[0046] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the sub-step process of the cache space capacity adjustment method provided by an embodiment of this application.

[0047] In some embodiments, the pattern recognition of the cache access sequence to obtain the access pattern information corresponding to each cache access information in the cache access sequence includes:

[0048] Step S1021: Determine a first subsequence in the cache access sequence whose repetition times are greater than a first preset number, and the first subsequence includes at least two cache access information;

[0049] Step S1022: Determine a candidate subsequence according to the first subsequence, the length of the candidate subsequence is greater than that of the first subsequence, and determine the candidate subsequence with the most repetition times as the second subsequence;

[0050] Step S1023: When the repetition times of the second subsequence are greater than a second preset number, determine a candidate subsequence according to the second subsequence, and determine the candidate subsequence with the most repetition times as the third subsequence;

[0051] Step S1024: When the repetition times of the third subsequence are less than or equal to the second preset number, determine the second subsequence as the target subsequence, and determine the access pattern information of the cache access information in the target subsequence as the sequential access pattern.

[0052] Exemplarily, the target subsequence is a subsequence in the cache access sequence that has an ordered access pattern, and the target subsequence is determined in the target subsequence in ascending order of length. For example, a subsequence containing two cache access messages and having a repetition count greater than a first preset count can be first determined as the first subsequence. Assume that the first preset count is 50, and the subsequence "Operation A - Operation B" appears in the cache access sequence more than 50 times, then "Operation A - Operation B" is determined as the first subsequence; then a subsequence that is longer than the first subsequence "Operation A - Operation B" and contains the first subsequence "Operation A - Operation B" is determined as a candidate subsequence. For example, by increasing one length unit each time, the candidate subsequences can include "Operation A - Operation B - Operation C", "Operation A - Operation B - Operation X", "Operation A - Operation B - Operation Y"; the candidate subsequence with the most repetition count is determined as the third subsequence. For example, the repetition count of "Operation A - Operation B - Operation C" is 30 times, the repetition count of "Operation A - Operation B - Operation X" is 10 times, and the repetition count of "Operation A - Operation B - Operation Y" is 10 times, then "Operation A - Operation B - Operation C" is determined as the third subsequence; when the repetition count of the third subsequence is greater than a second preset count, the third subsequence is used as the new second subsequence, and the above steps are repeated to determine candidate subsequences again based on the new second subsequence. For example, "Operation A - Operation B - Operation C - Operation D" and "Operation A - Operation B - Operation C - Operation Z", until the repetition count of the third subsequence is less than the second preset count, and the old second subsequence is determined as the target subsequence, so as to obtain the target subsequence in the cache access sequence that has an ordered access pattern, and the access pattern information of the cache access messages in the target subsequence is determined as the ordered access pattern.

[0053] Exemplarily, the data feature information may further include process type information. Specifically, the type of the application corresponding to the cache access operation is determined according to the associated process information in the cache access message, such as database applications, multimedia applications, office software, etc. The process type information can be judged according to information such as the file extension, process name, and system call mode of the application indicated by the associated process information. The process type information may further include the running state of the application (foreground running, background running), resource occupancy (including CPU usage rate, memory occupancy, etc.), which is not limited herein.

[0054] Step S103: Predict the spatial size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity.

[0055] Exemplarily, a deep learning model is used to predict the spatial size of the data cache space according to the data feature information. For example, a deep learning model can be constructed based on a Long Short-Term Memory (LSTM) network.

[0056] In some embodiments, predicting the spatial size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity includes:

[0057] Converting the data feature information into a data feature tensor and inputting it into a preset cache space prediction model;

[0058] Inputting the data feature tensor into at least one Long Short-Term Memory network to obtain the hidden states of each Long Short-Term Memory network;

[0059] Inputting the hidden state into a fully connected layer to obtain the cache space prediction capacity output by the fully connected layer.

[0060] Exemplarily, the data feature information can be normalized. For example, the access frequency information, access interval information, etc. are normalized and mapped to the [0,1] interval based on the following formula: \(x_{norm}=\frac{x - x_{min}}{x_{max}-x_{min}}\), where \(x\) is the original data feature information, \(x_{min}\) and \(x_{max}\) are respectively the minimum and maximum values of the data feature information in the training dataset, and \(x_{norm}\) is the normalized data feature information. For some features with special distributions, such as access pattern information, methods such as One-Hot Encoding can be used for processing. The data feature information is processed into a tensor format through the above methods to make it suitable for model input.

[0061] Exemplarily, the hidden layer of the cache space prediction model includes multiple LSTM units. The LSTM units process the data feature tensor through a gating mechanism (input gate, forget gate, output gate), and can effectively capture the long-term dependencies in the data to obtain the hidden states output by multiple LSTM units.

[0062] Exemplarily, the output layer of the cache space prediction model uses a fully connected layer to map the hidden state output by the LSTM unit to a scalar, that is, the size of the predicted capacity. Since the size of the predicted capacity is a continuous value, the activation function of the output layer can use a linear function.

[0063] In some embodiments, the method further includes:

[0064] Converting the preset sample feature information into a sample feature tensor and inputting it into the prediction model to be trained;

[0065] Input the sample feature tensor into at least one long short-term memory network to be trained, and obtain the sample hidden states of each of the long short-term memory networks to be trained;

[0066] Randomly discard the sample hidden states, and input the remaining sample hidden states into the fully connected layer to be trained, and obtain the sample prediction information output by the fully connected layer to be trained;

[0067] Adjust the prediction model to be trained according to the sample prediction information and the preset capacity information corresponding to the sample feature information until the cache space prediction model is obtained.

[0068] Exemplarily, train the prediction model to be trained through the preset sample feature information and the preset capacity information corresponding to the sample feature information to obtain the cache space prediction model. Among them, the prediction model to be trained also includes an input layer for converting feature information into a tensor, a hidden layer composed of multiple LSTM units, and an output layer composed of fully connected layers. The process of training the prediction model to be trained can refer to the working process of the cache space prediction model provided in the embodiments of the present application, which will not be elaborated here.

[0069] It can be understood that a Dropout layer is added after multiple LSTM units to randomly discard the sample hidden states output by the LSTM units, reduce the complex co-adaptation relationship between the LSTM units, improve the generalization ability of the model, and prevent the model from overfitting.

[0070] Exemplarily, the loss function of the prediction model to be trained can be the mean square error function,

[0071]

[0072] where n is the number of samples, is the sample prediction information predicted from the i-th sample feature information, y i is the preset capacity information corresponding to the i-th sample feature information.

[0073] Step S104: Based on the cache space prediction capacity, determine an adjustment strategy for adjusting the space size of the data cache space.

[0074] Exemplarily, when the cache space prediction capacity is greater than the current cache space capacity, increase the capacity of the data cache space in the storage device; conversely, when the cache space prediction capacity is less than the current cache space capacity, increase the capacity of the data cache space in the storage device, so that the size of the cache space can adapt to the needs of the device, improve the flexibility of the cache space size, and thus improve the utilization rate of the storage device.

[0075] In some embodiments, the adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the predicted capacity of the cache space includes:

[0076] When the predicted capacity of the cache space is greater than the current capacity of the cache space, obtain a preset unit capacity;

[0077] Based on the preset unit capacity, adjust the current capacity of the cache space to the predicted capacity of the cache space.

[0078] Exemplarily, when it is necessary to increase the capacity of the data cache space in the storage device, the capacity of the data cache space in the storage device can be gradually increased. For example, the preset unit capacity can be used as the step size for each increase. The preset unit capacity can be, for example, 1MB, 4MB, etc.

[0079] Exemplarily, when increasing the data cache space, it is necessary to ensure the compatibility of the newly added data blocks with the existing cache structure. Through data migration and cache coherence protocols, ensure the consistency of data between the old and new data blocks. For example, adopt the MESI (Modified, Exclusive, Shared, Invalid) cache coherence protocol to ensure the cache data consistency in a multi-processor environment.

[0080] In some embodiments, the adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the predicted capacity of the cache space further includes:

[0081] When the predicted capacity of the cache space is less than the current capacity of the cache space, determine the preset reduction space in the data cache space according to the access frequency information in the data feature information;

[0082] After the processor finishes accessing the preset reduction space, eliminate the preset reduction space from the data cache space, so that the current capacity of the cache space is adjusted to the predicted capacity of the cache space.

[0083] Exemplarily, when it is necessary to reduce the capacity of the data cache space in the storage device, recycle the data blocks in the storage space, and preferentially eliminate the data blocks with low access frequency by the processor. The access frequency of the data blocks can be determined according to the access frequency information in the data feature information in step S102. For example, assume that it is necessary to reduce the cache space capacity by 8MB, then preferentially reduce the 8MB with the lowest access frequency in the cache space. Among them, the preset reduction space can be continuous data blocks or fragmented multiple data blocks, which is not limited here.

[0084] In some embodiments, the spatial prediction capacity includes a first spatial prediction capacity and a second spatial prediction capacity. The first spatial prediction capacity corresponds to a first prediction duration, and the second spatial prediction capacity corresponds to a second prediction duration, and the second prediction duration is greater than the first prediction duration. The adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the cache spatial prediction capacity includes:

[0085] When the second spatial prediction capacity is greater than or equal to the first spatial prediction capacity, the spatial size of the data cache space is not adjusted within a preset duration.

[0086] Exemplarily, the spatial prediction capacity can correspond to different time spans. For example, the first spatial prediction capacity is the prediction of the cache space capacity for the next 5 minutes, and the second spatial prediction capacity is the prediction of the cache space capacity for the next 10 minutes. To avoid repeatedly increasing and decreasing the cache space capacity in a short time, the adjustment strategy for adjusting the spatial size of the data cache space can be jointly determined based on the prediction results of different time spans.

[0087] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the first spatial prediction capacity and the second spatial prediction capacity provided by an embodiment of the present application.

[0088] As Figure 3 shown, when the second spatial prediction capacity is greater than or equal to the first spatial prediction capacity and the first spatial prediction capacity is less than the current capacity of the cache space, in order to avoid increasing the cache space again shortly after reducing the cache space, resulting in repeated adjustment of the size of the cache space in a short time, the control system does not adjust the spatial size of the data cache space within a preset duration until a new prediction is made after the preset duration, and then the adjustment strategy is determined again according to the prediction result.

[0089] Step S105: Adjust the spatial size of the data cache space according to the adjustment strategy.

[0090] Exemplarily, the spatial size of the data cache space is adjusted according to the adjustment strategy determined in step S104, so as to improve the flexibility of the cache space and the utilization rate of the storage device.

[0091] The cache space capacity adjustment method provided in the present application obtains cache access information of a processor performing a cache access operation; performs feature extraction on the cache access information to obtain data feature information corresponding to the cache access information; predicts the size of the data cache space required by the processor based on the data feature information to obtain a predicted cache space capacity; determines an adjustment strategy for adjusting the size of the data cache space based on the predicted cache space capacity; and adjusts the size of the data cache space according to the adjustment strategy. Since the cache space size required by the device is predicted and the cache space size is adjusted based on the predicted result, the size of the cache space can be adapted to the needs of the device, thereby improving the flexibility of the cache space size and thus improving the utilization of the hardware.

[0092] For example, the above method can be implemented in the form of a computer program. Figure 4 Runs on the computer equipment shown.

[0093] See also Figure 4 , Figure 4 This is a schematic block diagram of the structure of a computer device provided in an embodiment of the present application. The computer device can be a server or a terminal.

[0094] like Figure 4 As shown, the computer device includes a processor, a memory, and a network interface connected via a system bus, wherein the memory may include a storage medium and an internal memory.

[0095] The storage medium can store an operating system and a computer program. The computer program includes program instructions, and when the program instructions are executed, the processor can execute any one of the cache space capacity adjustment methods.

[0096] The processor is used to provide computing and control capabilities and support the operation of the entire computer equipment.

[0097] The internal memory provides an environment for the operation of the computer program in the storage medium. When the computer program is executed by the processor, the processor can execute any one of the cache space capacity adjustment methods.

[0098] The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0099] It should be understood that the processor can be a Central Processing Unit (CPU), and the processor can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0100] Among them, in one embodiment, the processor is used to run a computer program stored in a memory to implement the following steps:

[0101] Obtain cache access information for the processor to perform cache access operations;

[0102] Extract features from the cache access information to obtain data feature information corresponding to the cache access information;

[0103] Predict the size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity;

[0104] Based on the predicted cache space capacity, determine an adjustment strategy for adjusting the size of the data cache space;

[0105] Adjust the size of the data cache space according to the adjustment strategy.

[0106] It should be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0107] It should also be understood that the term "and / or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, in this context, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or system comprising the element.

[0108] The serial numbers of the embodiments of the present application above are for description only and do not represent the superiority or inferiority of the embodiments. The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for adjusting the capacity of a cache space, characterized in that The method includes: Obtaining cache access information of a processor performing a cache access operation; Performing feature extraction on the cache access information to obtain data feature information corresponding to the cache access information; Predicting the spatial size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity; Based on the predicted cache space capacity, determining an adjustment strategy for adjusting the spatial size of the data cache space; Adjusting the spatial size of the data cache space according to the adjustment strategy.

2. The method for adjusting the capacity of the cache space according to claim 1, characterized in that The cache access information at least includes: access time information, access address information, and the data feature information at least includes: access frequency information, access interval information. The performing feature extraction on the cache access information to obtain data feature information corresponding to the cache access information includes: Determining a data block corresponding to the cache access operation according to the access address information in the cache access information; Determining the access frequency information and access interval information of each data block according to the access time information in the cache access information.

3. The method for adjusting the capacity of the cache space according to claim 2, wherein the data characteristic information further includes: Access pattern information, wherein the performing feature extraction on the cache access information to obtain data feature information corresponding to the cache access information includes: Determining a cache access sequence according to the cache access information, and the position of the cache access information in the cache access sequence is determined by the access time information; Performing pattern recognition on the cache access sequence to obtain access pattern information corresponding to each cache access information in the cache access sequence; Wherein, the access pattern information includes: sequential access pattern, random access pattern, periodic access pattern.

4. The method for adjusting the capacity of the cache space according to claim 3, wherein The performing pattern recognition on the cache access sequence to obtain access pattern information corresponding to each cache access information in the cache access sequence includes: Determining a first subsequence in the cache access sequence whose repetition times are greater than a first preset number, and the first subsequence includes at least two pieces of cache access information; Determining a candidate subsequence according to the first subsequence, the length of the candidate subsequence is greater than that of the first subsequence, and determining the candidate subsequence with the most repetition times as the second subsequence; When the repetition times of the second subsequence are greater than a second preset number, determining a candidate subsequence according to the second subsequence, and determining the candidate subsequence with the most repetition times as the third subsequence; When the repetition times of the third subsequence are less than or equal to the second preset number, determining the second subsequence as the target subsequence, and determining the access pattern information of the cache access information in the target subsequence as the sequential access pattern.

5. The method for adjusting the capacity of the cache space according to claim 1, characterized in that The predicting the spatial size of the data cache space required by the processor according to the data feature information to obtain a predicted cache space capacity includes: Converting the data feature information into a data feature tensor and inputting it into a preset cache space prediction model; Inputting the data feature tensor into at least one long short-term memory network to obtain the hidden states of each long short-term memory network; Input the hidden state into the fully-connected layer to obtain the predicted capacity of the cache space output by the fully-connected layer.

6. The method for adjusting the capacity of the cache space according to claim 5, wherein The method further includes: Convert the preset sample feature information into a sample feature tensor and input it into the prediction model to be trained; Input the sample feature tensor into at least one long short-term memory network to be trained to obtain the sample hidden states of the long short-term memory networks to be trained; Randomly discard the sample hidden states, and input the remaining sample hidden states into the fully-connected layer to be trained to obtain the sample prediction information output by the fully-connected layer to be trained; Adjust the prediction model to be trained according to the sample prediction information and the preset capacity information corresponding to the sample feature information until the cache space prediction model is obtained.

7. The method for adjusting the capacity of the cache space according to any one of claims 1-6, characterized in that, The adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the predicted cache space capacity includes: When the predicted cache space capacity is greater than the current cache space capacity, obtain the preset unit capacity; Based on the preset unit capacity, adjust the current cache space capacity to the predicted cache space capacity.

8. The method for adjusting the capacity of the cache space according to any one of claims 1-6, characterized in that, The adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the predicted cache space capacity further includes: When the predicted cache space capacity is less than the current cache space capacity, determine the preset reduction space in the data cache space according to the access frequency information in the data feature information; After the processor finishes accessing the preset reduction space, eliminate the preset reduction space from the data cache space so that the current cache space capacity is adjusted to the predicted cache space capacity.

9. The method for adjusting the capacity of the cache space according to claim 1, wherein The predicted space capacity includes: a first predicted space capacity and a second predicted space capacity. The first predicted space capacity corresponds to a first prediction duration, and the second predicted space capacity corresponds to a second prediction duration, and the second prediction duration is greater than the first prediction duration; the adjustment strategy for determining the adjustment of the spatial size of the data cache space based on the predicted cache space capacity includes: When the second predicted space capacity is greater than or equal to the first predicted space capacity and the first predicted space capacity is less than the current cache space capacity, do not adjust the spatial size of the data cache space within a preset duration.

10. A computer device, characterized in that, The computer device includes a processor, a memory, and a computer program stored on the memory and executable by the processor. When the computer program is executed by the processor, the steps of the method for adjusting the capacity of the cache space according to any one of claims 1 to 9 are implemented.

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