ARINC664 terminal system for detecting and reporting network faults in real time

Abstract

The invention discloses an ARINC664 terminal system for detecting and reporting network faults in real time, which comprises an ARINC664 terminal and a fault information acquisition upper computer module, the ARINC664 terminal comprises a power supply module, a power supply voltage monitoring module, a power supply temperature monitoring module, a reset circuit module, an AFDX network connection module, an MCU microcontroller subsystem, an FPGA programmable gate array subsystem, a display module, an application program interface module and a high-speed data memory module. According to the invention, power supply voltage monitoring, main control chip monitoring, power supply temperature monitoring, network data packet protocol and data fault detection, fault information summarizing, and real-time display and reporting are carried out. The method can be applied to multiple scenes such as fault monitoring of an avionics system, real-time state monitoring of an airborne network, aircraft ground maintenance and fault node positioning and the like, has high safety, real-time performance, reliability and flexibility, is high in fault monitoring coverage rate, and improves the safety of the avionics system.

Description

Technical Field

[0001] The present invention belongs to the field of avionics systems and airborne network health management, and particularly relates to an ARINC664 terminal system for real-time detection and reporting of network faults. It is applicable to various scenario tasks such as fault monitoring of avionics systems, real-time status monitoring of airborne networks, and positioning of faulty nodes during aircraft ground maintenance. Background Art

[0002] With the evolution of avionics systems towards an integrated modular avionics architecture, AFDX (Avionics Full Duplex Switched Ethernet) based on the ARINC664 standard has become the core protocol of the new generation of civil aircraft avionics networks. Compared with traditional buses such as ARINC 429, AFDX significantly improves bandwidth and deterministic transmission capabilities through virtual link scheduling and dual redundancy switching. However, it also introduces complex network fault modes, including protocol faults such as incorrect virtual link bandwidth allocation and overrun of bandwidth allocation intervals, which may lead to real-time violations of critical data streams, data faults such as single-event upsets and multiple-bit upsets of ARINC664 end-system chips caused by the harsh airborne environment, and hardware fault risks such as power supply faults or overheating of the terminal system. For avionics systems with high safety and high real-time requirements, it is of great significance to adopt an ARINC664 terminal system with the ability to monitor network faults in real time and report them. Summary of the Invention

[0003] The object of the present invention is to provide an ARINC664 terminal system for real-time detection and reporting of network faults. Through circuit design, power supply voltage and temperature fault detection of the terminal system at the hardware level, as well as abnormal temperature detection of the main control chip, are realized to detect network faults at the physical layer; through FPGA logic processing, protocol faults and data faults are detected to detect network faults at the data link layer, network layer and transport layer; through MCU program control, the network fault information of the ARINC664 terminal is displayed on the display module and reported to the upper computer module for collecting fault information; through the upper computer module, the fault information of all ARINC664 terminals in the AFDX network is summarized and processed. The present invention realizes an ARINC664 terminal system with the ability to detect network faults in real time and report them, and has the advantages of high safety, high real-time performance, high reliability, flexible application, and high fault monitoring coverage rate.

[0004] The specific technical solution for achieving the object of the present invention is as follows: An ARINC664 terminal system for real-time detection and reporting of network faults, which includes an ARINC664 terminal and a fault information collection host computer module. The ARINC664 terminal includes a power supply module, a power supply voltage monitoring module, a power supply temperature monitoring module, a reset circuit module, an AFDX network connection module, an MCU microcontroller subsystem, an FPGA programmable gate array subsystem, a display module, an application program interface module, and a high-speed data memory module; The power supply voltage monitoring module is connected to the power supply module and the MCU microcontroller subsystem for monitoring the power supply voltage; The power supply temperature monitoring module is connected to the power supply module and the MCU microcontroller subsystem for monitoring the power supply temperature; The reset circuit module is connected to the power supply module, the MCU microcontroller subsystem, and the FPGA programmable gate array subsystem for controlling the reset of the ARINC664 terminal when a reporting failure occurs; The AFDX network connection module is connected to the power supply module and the FPGA programmable gate array subsystem for accessing the physical layer of the AFDX avionics network to send and receive data; The MCU microcontroller subsystem is connected to the power supply module, the power supply voltage monitoring module, the power supply temperature monitoring module, the reset circuit module, the FPGA programmable gate array subsystem, the display module, and the fault information collection host computer module to summarize the power supply voltage anomalies, power supply temperature anomalies, protocol faults, data faults, MCU chip temperature anomalies, and FPGA chip temperature anomalies of the ARINC664 terminal, display the fault information on the display module, and transmit it to the fault information collection host computer module; The FPGA programmable gate array subsystem is connected to the power supply module, the reset circuit module, the AFDX network connection module, the MCU microcontroller subsystem, the application program interface module, and the high-speed data memory module to realize data interaction with the upper-layer application program of the ARINC664 terminal, encapsulate the application program data sent by the application program interface module into network data packets conforming to the ARINC664 standard protocol, and send the data packets to the AFDX network connection module, unload the ARINC664 protocol from the data packets received from the AFDX network connection module to obtain the application program data and send it to the application program interface module, perform data caching through the high-speed data memory module during data sending and receiving, detect protocol faults, data faults occurring during network data processing, and FPGA chip temperature anomalies of the ARINC664 terminal system, and transmit the fault information to the MCU microcontroller subsystem; The display module is connected to the power supply module and the MCU microcontroller subsystem for locally displaying fault information on the ARINC664 terminal; The application programming interface module is connected to the FPGA (Field Programmable Gate Array) subsystem to implement the upper-layer application program of the ARINC664 terminal; The high-speed data memory module is connected to the power supply module and the FPGA subsystem, and is implemented by the cache resources inside the FPGA chip and the off-chip high-speed memory DDR4 chip, providing high-speed caching for the data processing of the ARINC664 terminal; The upper computer module for collecting fault information is connected to the MCU (Microcontroller Unit) subsystem inside the ARINC664 terminal. The upper computer module for collecting fault information can be connected to multiple ARINC664 terminals through independent links to achieve the summary and processing of the fault information of all ARINC664 terminals in the AFDX network.

[0005] The power supply module includes a fault detection circuit power supply module and an ARINC664 terminal power supply module; The fault detection circuit power supply module is connected to the power supply voltage monitoring module, the power supply temperature monitoring module, the reset circuit module, the MCU subsystem, and the display module, and is powered independently to improve the power supply safety of the power supply voltage monitoring module, the power supply temperature monitoring module, the reset circuit module, the MCU subsystem, and the display module used to implement fault monitoring and reporting; The ARINC664 terminal power supply module is connected to the AFDX network connection module, the FPGA subsystem, and the high-speed data memory module, and is used to provide power for the AFDX network connection module, the FPGA subsystem, and the high-speed data memory module required to implement the ARINC664 protocol.

[0006] The MCU subsystem includes an MCU chip temperature detection module, a watchdog timer module, an ARINC664 terminal fault information summary module, an MCU-FPGA communication module, an interface display module, and a fault reporting module; The MCU chip temperature detection module is connected to the ARINC664 terminal fault information summary module, and uses the temperature sensor built in the MCU chip and the ADC of the MCU to perform temperature measurement and calculation to achieve the detection of the MCU chip temperature; The watchdog timer module is connected to the reset circuit module, and uses the hardware watchdog timer built in the MCU to perform timeout detection to achieve the detection of MCU program faults; The ARINC664 terminal fault information summary module is connected to the power supply voltage monitoring module, power supply temperature monitoring module, MCU chip temperature detection module, MCU_FPGA communication module, interface display module, and fault reporting module, and realizes the summary and processing of power supply voltage anomalies, power supply temperature anomalies, MCU chip temperature anomalies, protocol faults, data faults, and FPGA chip temperature anomaly fault information from the MCU_FPGA communication module. The fault information is sent to the interface display module for display on the fault interface, and the fault information is sent to the fault reporting module for reporting of the fault information; The MCU_FPGA communication module is connected to the FPGA programmable gate array subsystem and is used for bus communication with the FPGA programmable gate array subsystem to receive protocol faults, data faults, and FPGA chip temperature anomaly fault information transmitted by the FPGA programmable gate array subsystem; The interface display module is connected to the ARINC664 terminal fault information summary module and the display module to realize the driving and drawing of the ARINC664 terminal display interface; The fault reporting module is connected to the ARINC664 terminal fault information summary module and the fault information acquisition host computer module, and realizes the integration of power supply voltage anomalies, power supply temperature anomalies, protocol faults, data faults, MCU chip temperature anomalies, and FPGA chip temperature anomaly fault information into data packets in a specific format and reports them to the fault information acquisition host computer module through an independent transmission link.

[0007] The FPGA programmable gate array subsystem includes an FPGA chip temperature detection module, an ARINC664 data sending module, an ARINC664 data receiving module, an FPGA_MCU communication module, a protocol and data processing fault information summary module, an ARINC664 protocol fault detection module, an ARINC664 data communication module, a logic internal and external cache data storage verification module, and an ARINC664 data packet processing module; The FPGA chip temperature detection module is connected to the protocol and data processing fault information summary module, and uses the temperature sensor and ADC built into the FPGA chip for temperature measurement and calculation to realize the detection of the internal temperature of the FPGA chip; The ARINC664 data sending module is connected to the AFDX network connection module and the ARINC664 protocol fault detection module, and realizes the virtual link sending logic and dual-redundant link sending logic. The data packet after the ARINC664 protocol fault detection module completes the protocol error detection is encapsulated into a MAC frame and sent to the physical layer AFDX network connection module to complete the network data sending function of the ARINC664 terminal; The ARINC664 data receiving module is connected to the AFDX network connection module and the ARINC664 protocol fault detection module, implementing virtual link receiving logic and dual-redundant link receiving logic. It receives physical layer data packets from the AFDX network connection module, unloads the MAC frame protocol, and then sends them to the ARINC664 protocol fault detection module for protocol detection, completing the network data receiving function of the ARINC664 terminal; The FPGA_MCU communication module is connected to the MCU microcontroller subsystem and the protocol and data processing fault information summarization module, implementing the organization of protocol faults, data faults, and FPGA chip temperature anomaly fault information summarized by the protocol and data processing fault information summarization module into a specific data format and transmitting it to the MCU microcontroller subsystem through the communication bus; The protocol and data processing fault information summarization module is connected to the FPGA chip temperature detection module, the FPGA_MCU communication module, the ARINC664 protocol fault detection module, and the logical internal and external cache data storage verification module, implementing the summarization and processing of protocol fault information from the ARINC664 protocol fault detection module, data fault information from the logical internal and external cache data storage verification module, and FPGA chip temperature anomaly fault information from the FPGA chip temperature detection module, and sending the fault information to the FPGA_MCU communication module; The ARINC664 protocol fault detection module is connected to the ARINC664 data sending module, the ARINC664 data receiving module, the protocol and data processing fault information summarization module, and the ARINC664 data packet processing module. Through FPGA logic code, it implements virtual link identifier legality verification logic, virtual link bandwidth allocation legality verification logic, bandwidth allocation gap BAG legality verification logic, scheduler scheduling result verification logic, frame format error detection logic, frame length anomaly detection logic, ARINC664 protocol stack error detection logic, redundancy management fault detection logic, end-to-end delay overrun detection logic, traffic detection logic, and EDE integrity check logic, completing the protocol fault detection function. It performs protocol fault detection on data packets from the ARINC664 data packet processing module, and the data packets after protocol fault detection are sent to the ARINC664 data sending module. It performs protocol fault detection on data packets from the ARINC664 data receiving module, and the data packets after protocol fault detection are sent to the ARINC664 data packet processing module, and sends the protocol fault information to the protocol and data processing fault information summarization module; The ARINC664 data communication module is connected to the logical internal and external cache data storage and verification module and the application program interface module, and uses the PCIe bus for communication. It is used to send and receive application data with the ARINC664 terminal application program interface module. For the application data sent by the application program interface module, the ARINC664 data communication module forwards the application data to the logical internal and external cache data storage and verification module. For the data sent by the logical internal and external cache data storage and verification module, the ARINC664 data communication module forwards this data to the application program interface module; The logical internal and external cache data storage and verification module is connected to the protocol and data processing fault information summary module, the ARINC664 data communication module, the ARINC664 data packet processing module, and the high-speed data memory module. When receiving data sent by the ARINC664 data communication module, the logical internal and external cache data storage and verification module caches these data in the high-speed data memory module and forwards them to the ARINC664 data packet processing module. When receiving data from the ARINC664 data packet processing module, the logical internal and external cache data storage and verification module caches these data in the high-speed data memory module and forwards them to the ARINC664 data communication module. During the above caching and forwarding process, CRC verification is used to achieve data integrity check, and the ECC verification algorithm is used to verify the data, so as to detect and correct the single-event upset data faults that occur during the data caching and processing process, as well as detect multiple-bit flip errors, complete data fault detection, and send the data fault information to the protocol and data processing fault information summary module; The ARINC664 data packet processing module is connected to the ARINC664 protocol fault detection module and the logical internal and external cache data storage and verification module, and realizes virtual link scheduling and bandwidth allocation logic, bandwidth interval allocation logic, and traffic shaping logic. For the data from the ARINC664 protocol fault detection module, the ARINC664 data packet processing module unloads the ARINC664 protocol from these data and sends the data after protocol unloading to the logical internal and external cache data storage and verification module. For the data from the logical internal and external cache data storage and verification module, the ARINC664 data packet processing module encapsulates these data into ARINC664 protocol frames and sends the ARINC664 protocol frames to the ARINC664 protocol fault detection module, realizing network data processing and the ARINC664 protocol.

[0008] The beneficial effects of the present invention are: a The present invention can detect and report protocol faults, data faults, and hardware faults for ARINC664 terminals. The fault detection includes network faults in the physical layer, data link layer, network layer, and transport layer, and the system fault detection coverage rate is high.

[0009] b The present invention uses FPGA logic to detect ARINC664 protocol faults and data faults, and can achieve a fault detection speed at the nanosecond level, with high real-time performance.

[0010] c The present invention separates the power supply of the ARINC664 terminal system from the power supply of the detection module. For faults in the detection core FPGA logic and the program of the reporting core MCU, hardware-level reset processing is adopted, and the fault reporting uses an independent communication link, so the reliability and security of the system fault detection and reporting functions are high.

[0011] d The application program interface module in the present invention can adapt to different ARINC664 terminal applications, the system FPGA programmable gate array can be redeveloped, and the system application flexibility is high.

[0012] e The present invention is based on a self-designed high-speed printed circuit board. The FPGA program and the C language program are both developed by the inventor team without using any finished modules. The hardware system ensures signal integrity and power integrity, with good performance and stable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is the architecture diagram of the present invention; Figure 2 is the block diagram of the ARINC664 terminal structure of the present invention; Figure 3 is the schematic diagram of the working data flow of the present invention; Figure 4 is the connection schematic diagram of the present invention when the AFDX network has multiple ARINC664 terminals. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The present invention will be described in detail below with reference to the drawings and embodiments. Embodiment

[0015] Refer to Figure 1 and Figure 2, the present invention includes an ARINC664 terminal and a fault information acquisition host computer module 13; the ARINC664 terminal includes a power supply module 1, a power supply voltage monitoring module 2, a power supply temperature monitoring module 3, a reset circuit module 4, an AFDX network connection module 5, an MCU microcontroller subsystem 6, an FPGA programmable gate array subsystem 7, a display module 8, an application program interface module 9, and a high-speed data memory module 10; the power supply voltage monitoring module 2 is connected to the power supply module 1 and the MCU microcontroller subsystem 6, and a hardware circuit is built using a voltage comparison chip MAX16062ATG and a logic gate chip SN74LVC86ARGYR, and logical calculations are performed through the comparison result of the actual voltage value and the set threshold to obtain a power supply voltage abnormal signal for monitoring the power supply voltage; the power supply temperature monitoring module 3 is connected to the power supply module 1 and the MCU microcontroller subsystem 6, and an AD590 temperature sensor is used to measure the temperature of the power supply module with higher heat generation for monitoring the power supply temperature; the reset circuit module 4 is connected to the power supply module 1, the MCU microcontroller subsystem 6, and the FPGA programmable gate array subsystem 7, and a voltage monitor chip MAX811R is used to monitor the timeout error signal of the watchdog timer for controlling the ARINC664 terminal to reset when a failure is reported; the AFDX network connection module 5 is connected to the power supply module 1 and the FPGA programmable gate array subsystem 7, and a hardware circuit is built using an Ethernet PHY chip DP83867ERGZR, a network port transformer chip HX1260NL, and an RJ45 Ethernet connector for accessing the physical layer of the AFDX avionics network to send and receive data; the MCU microcontroller subsystem 6 is connected to the power supply module 1, the power supply voltage monitoring module 2, the power supply temperature monitoring module 3, the reset circuit module 4, the FPGA programmable gate array subsystem 7, the display module 8, and the fault information acquisition host computer module 13 to summarize the fault information of the power supply voltage abnormality, power supply temperature abnormality, protocol fault, data fault, MCU chip temperature abnormality, and FPGA chip temperature abnormality of the ARINC664 terminal, display the fault information on the display module 8, and transmit it to the fault information acquisition host computer module 13;The FPGA programmable gate array subsystem 7 is connected to the power supply module 1, the reset circuit module 4, the AFDX network connection module 5, the MCU microcontroller subsystem 6, the application program interface module 9, and the high-speed data memory module 10 to realize data interaction with the upper-layer application program of the ARINC664 terminal. It encapsulates the application program data sent by the application program interface module 9 into network data packets conforming to the ARINC664 standard protocol and sends the data packets to the AFDX network connection module 5. It unloads the ARINC664 protocol from the data packets received from the AFDX network connection module 5 to obtain the application program data and sends it to the application program interface module 9. During the data sending and receiving process, data caching is performed through the high-speed data memory module 10, and protocol faults of the ARINC664 terminal system, data faults occurring during network data processing, and abnormal faults of the FPGA chip temperature are detected, and the fault information is transmitted to the MCU microcontroller subsystem 6; the display module 8 is connected to the power supply module 1 and the MCU microcontroller subsystem 6, and the display screen model used is ATK-MD0700R, which is used to locally display fault information on the ARINC664 terminal; the application program interface module 9 is connected to the FPGA programmable gate array subsystem 7, develops the PCIe bus driver using the WinDriver development tool, transmits application data to the FPGA programmable gate array subsystem through the PCIe3.0 bus, and develops the upper-layer application program of the ARINC664 terminal using Qt; the high-speed data memory module 10 is connected to the power supply module 1 and the FPGA programmable gate array subsystem 7, and is implemented by the RAM resources inside the FPGA chip and the off-chip high-speed memory DDR4 chip MT40A512M16HA_075E, providing high-speed caching for ARINC664 terminal data processing; the fault information acquisition host computer module 13 is connected to the MCU microcontroller subsystem 6 inside the ARINC664 terminal. The fault information acquisition host computer module 13 can be connected to multiple ARINC664 terminals using independent links. Each link uses the RS485 protocol for communication, and uses Qt to develop the fault information summary and processing program interface to realize the summary and processing of the fault information of all ARINC664 terminals in the AFDX network.;

[0016] Refer to Figure 2, the power supply module 1 includes a fault detection circuit power supply module 11 and an ARINC664 terminal power supply module 12, which are built by a DC-DC power chip LTM4650, a PMIC power management chip TPS51200, a DC-DC power chip TPS62130 and peripheral circuits; the fault detection circuit power supply module 11 is connected to a power supply voltage monitoring module 2, a power supply temperature monitoring module 3, a reset circuit module 4, an MCU microcontroller subsystem 6 and a display module 8, and is powered by an independent power supply to improve the power supply safety of the power supply voltage monitoring module, the power supply temperature monitoring module, the reset circuit module, the MCU microcontroller subsystem and the display module used to implement fault monitoring and reporting; the ARINC664 terminal power supply module 12 is connected to an AFDX network connection module 5, an FPGA programmable gate array subsystem 7 and a high-speed data storage module 10, and is used to provide power for the AFDX network connection module, the FPGA programmable gate array subsystem and the high-speed data storage module required to implement the ARINC664 protocol.

[0017] Refer to Figure 2, the MCU microcontroller subsystem 6 includes an MCU chip temperature detection module 61, a watchdog timing module 62, an ARINC664 terminal fault information aggregation module 63, an MCU_FPGA communication module 64, an interface display module 65, and a fault reporting module 66. The used MCU microcontroller chip is STM32H743XIH6; the MCU chip temperature detection module 61 is connected to the ARINC664 terminal fault information aggregation module 63, uses the built-in temperature sensor of the chip for temperature measurement, and samples using the corresponding ADC channel of the MCU to calculate the temperature data, realizing the detection of the MCU chip temperature; the watchdog timing module 62 is connected to the reset circuit module 4, uses the built-in hardware watchdog timer of the MCU for timeout detection. When a program fault occurs in the MCU, the watchdog timer times out and sends a timeout error signal to the reset circuit module to realize the detection of the MCU program fault; the ARINC664 terminal fault information aggregation module 63 is connected to the power supply voltage monitoring module 2, the power supply temperature monitoring module 3, the MCU chip temperature detection module 61, the MCU_FPGA communication module 64, the interface display module 65, and the fault reporting module 66, realizing the aggregation and processing of fault information such as power supply voltage abnormality, power supply temperature abnormality, MCU chip temperature abnormality, protocol fault, data fault, and FPGA chip temperature abnormality from the MCU_FPGA communication module 64, sending the fault information to the interface display module 65 for fault interface display, and sending the fault information to the fault reporting module 66 for fault information reporting; the MCU_FPGA communication module 64 is connected to the FPGA programmable gate array subsystem 7, used for bus communication with the FPGA programmable gate array subsystem, and receiving protocol fault, data fault, and FPGA chip temperature abnormality fault information transmitted from the FPGA programmable gate array subsystem through the SPI bus; the interface display module 65 is connected to the ARINC664 terminal fault information aggregation module 63 and the display module 8, uses the LVGL graphics library to draw the ARINC664 terminal system error information display interface, and drives the display module using the LTDC interface to display the interface, realizing the driving and drawing of the ARINC664 terminal display interface; the fault reporting module 66 is connected to the ARINC664 terminal fault information aggregation module 63 and the fault information acquisition host computer module 13, realizing CRC check calculation for fault information such as power supply voltage abnormality, power supply temperature abnormality, protocol fault, data fault, MCU chip temperature abnormality, and FPGA chip temperature abnormality, integrating the fault information and the CRC check code into a data packet in a specific format, and reporting it to the fault information acquisition host computer module 13 through an independent RS485 transmission link.

[0018] Refer to Figure 2, the FPGA programmable gate array subsystem 7 includes an FPGA chip temperature detection module 71, an ARINC664 data sending module 72, an ARINC664 data receiving module 73, an FPGA_MCU communication module 74, a protocol and data processing fault information summarization module 75, an ARINC664 protocol fault detection module 76, an ARINC664 data communication module 77, a logic internal and external cache data storage verification module 78, and an ARINC664 data packet processing module 79. The used FPGA programmable gate array chip is XCVU125-2FLVA2104; the FPGA chip temperature detection module 71 is connected to the protocol and data processing fault information summarization module 75, and uses the built-in temperature sensor and XADC of the FPGA chip to perform temperature measurement and calculation to realize the detection of the internal temperature of the FPGA chip; the ARINC664 data sending module 72 is connected to the AFDX network connection module 5 and the ARINC664 protocol fault detection module 76, realizes the virtual link sending logic and the dual-redundancy link sending logic, encapsulates the data packet after the ARINC664 protocol fault detection module 76 completes the protocol error detection into a MAC frame and sends it to the physical layer AFDX network connection module 5 to complete the network data sending function of the ARINC664 terminal; the ARINC664 data receiving module 73 is connected to the AFDX network connection module 5 and the ARINC664 protocol fault detection module 76, realizes the virtual link receiving logic and the dual-redundancy link receiving logic, receives the physical layer data packet from the AFDX network connection module 5, unloads the MAC frame protocol and sends it to the ARINC664 protocol fault detection module 76 for protocol detection to complete the network data receiving function of the ARINC664 terminal; the FPGA_MCU communication module 74 is connected to the MCU microcontroller subsystem 6 and the protocol and data processing fault information summarization module 75, realizes sorting the protocol faults, data faults, and FPGA chip temperature anomaly fault information summarized by the protocol and data processing fault information summarization module 75 into a specific data format, and transmitting it to the MCU microcontroller subsystem 6 through the communication bus; the protocol and data processing fault information summarization module 75 is connected to the FPGA chip temperature detection module 71, the FPGA_MCU communication module 74, the ARINC664 protocol fault detection module 76, and the logic internal and external cache data storage verification module 78, realizes the summarization and processing of the protocol fault information of the ARINC664 protocol fault detection module 76, the data fault information of the logic internal and external cache data storage verification module 78, and the FPGA chip temperature anomaly fault information of the FPGA chip temperature detection module 71, and sends the fault information to the FPGA_MCU communication module 74;The ARINC664 protocol fault detection module 76 is connected to the ARINC664 data sending module 72, the ARINC664 data receiving module 73, the protocol and data processing fault information summarization module 75, and the ARINC664 data packet processing module 79. It implements the virtual link identifier compliance verification logic, virtual link bandwidth allocation compliance verification logic, bandwidth allocation interval BAG compliance verification logic, scheduler scheduling result verification logic, frame format error detection logic, frame length anomaly detection logic, ARINC664 protocol stack error detection logic, redundancy management fault detection logic, end-to-end delay overrun detection logic, traffic detection logic, and EDE integrity check logic through FPGA logic code to complete the protocol fault detection function. It performs protocol fault detection on the data packets from the ARINC664 data packet processing module 79, and the data packets after protocol fault detection are sent to the ARINC664 data sending module 72. It also performs protocol fault detection on the data packets from the ARINC664 data receiving module 73, and the data packets after protocol fault detection are sent to the ARINC664 data packet processing module 79, and the protocol fault information is sent to the protocol and data processing fault information summarization module 75. The ARINC664 data communication module 77 is connected to the logic internal and external cache data storage verification module 78 and the application program interface module 9. It uses PCIe3.0 bus communication to send and receive application data with the ARINC664 terminal application program interface module. For the application data sent by the application program interface module 9, the ARINC664 data communication module 77 forwards the application data to the logic internal and external cache data storage verification module 78. For the data sent by the logic internal and external cache data storage verification module 78, the ARINC664 data communication module forwards these data to the application program interface module 9;The internal and external cache data storage verification module 78 is connected to the protocol and data processing fault information summary module 75, the ARINC664 data communication module 77, the ARINC664 data packet processing module 79, and the high-speed data memory module 10. When receiving data sent by the ARINC664 data communication module 77, the internal and external cache data storage verification module 78 caches the data in the high-speed data memory module 10 and forwards it to the ARINC664 data packet processing module 79. When receiving data from the ARINC664 data packet processing module 79, the internal and external cache data storage verification module 78 caches the data in the high-speed data memory module 10 and forwards it to the ARINC664 data communication module 77. During the above caching and forwarding process, CRC verification is used to implement data integrity checking, and the ECC verification algorithm is used to verify the data, realizing the detection and correction of single-event upset data faults and the detection of multi-bit flip errors that occur during the data caching and processing process, completing data fault detection, and sending the data fault information to the protocol and data processing fault information summary module 75; the ARINC664 data packet processing module 79 is connected to the ARINC664 protocol fault detection module 76 and the internal and external cache data storage verification module 78, realizing virtual link scheduling and bandwidth allocation logic, bandwidth interval allocation logic, and traffic shaping logic. For the data from the ARINC664 protocol fault detection module 76, the ARINC664 data packet processing module 79 unloads the ARINC664 protocol from the data and sends the data after protocol unloading to the internal and external cache data storage verification module 78. For the data from the internal and external cache data storage verification module 78, the ARINC664 data packet processing module 79 encapsulates the data into ARINC664 protocol frames and sends the ARINC664 protocol frames to the ARINC664 protocol fault detection module 76, realizing network data processing and the ARINC664 protocol.;

[0019] Refer to Figure 3, during the operation of the present invention, the application programming interface module generates application data, and transmits the data to the FPGA programmable gate array subsystem through the PCIe3.0 bus. After the ARINC664 data communication module of the FPGA programmable gate array subsystem receives the application data, the application data is sent to the internal and external cache data storage and verification module through the ARINC664 data communication module to implement data caching, forwarding, and data fault detection, and obtain correct data. The correct data is sent to the ARINC664 packet processing module for ARINC664 protocol frame encapsulation. The processed ARINC664 data frame is sent to the ARINC664 protocol error detection module for protocol fault detection. The ARINC664 data frame that has passed the protocol fault detection is sent to the A664 data sending module. After being encapsulated into a MAC frame, the virtual link and redundancy processing at the sending end are completed, and the ARINC664 packet is sent to the AFDX network connection module to complete the data transmission to the network physical layer connection. Similarly, after the AFDX network connection module receives the ARINC664 packet sent by the network physical layer connection, it sends the packet to the A664 data receiving module to complete the virtual link and redundancy processing at the receiving end, unload the MAC frame protocol, and send the obtained ARINC664 data frame to the ARINC664 protocol error detection module for protocol fault detection. The ARINC664 data frame that has passed the protocol fault detection is sent to the ARINC664 packet processing module for ARINC664 protocol unloading. The unloaded data is forwarded to the internal and external cache data storage and verification module to implement data caching, forwarding, and data fault detection, and obtain correct data. The correct data is sent to the ARINC664 data communication module, and the data transmission from the FPGA programmable gate array subsystem to the application programming interface module is completed through the PCIe3.0 bus. The application programming interface module uses the received application data to implement application functions.

[0020] Refer to Figure 3, during the operation of the present invention, the protocol and data processing fault information summarization module in the FPGA (Field-Programmable Gate Array) subsystem will summarize and statistically analyze the protocol fault information generated by the ARINC664 protocol error detection module, the data fault information generated by the internal and external cache data storage verification module of the logic, and the FPGA chip temperature abnormal fault information generated by the FPGA chip temperature detection module. The protocol and data processing fault information summarization module will send the protocol fault, data fault, and FPGA chip temperature fault information to the FPGA_MCU communication module. The FPGA_MCU communication module will organize the protocol fault, data fault, and FPGA chip temperature fault information into a specific data format and use the SPI (Serial Peripheral Interface) communication bus to send the above three types of fault information to the MCU (Microcontroller Unit) subsystem; the MCU subsystem obtains the protocol fault, data fault, and FPGA chip temperature fault information through SPI bus communication and forwards the protocol fault, data fault, and FPGA chip temperature fault information to the ARINC664 terminal fault information summarization module. The ARINC664 terminal fault information summarization module summarizes the protocol fault, data fault, and FPGA chip temperature fault information from the MCU_FPGA module, the power supply voltage fault information from the power supply voltage monitoring module, the power supply temperature fault information from the power supply temperature fault monitoring module, and the MCU temperature abnormal fault information from the MCU chip temperature detection module, and sends the power supply voltage abnormal, power supply temperature abnormal, protocol fault, data fault, MCU chip temperature abnormal, and FPGA chip temperature abnormal fault information to the interface display module and the fault reporting module. The interface display module draws the interface and drives the display module to display the fault information. The fault reporting module integrates the fault information into a data packet in a specific format and reports it to the fault information collection host computer module through an independent transmission link.

[0021] Refer to Figure 3 , during the operation of the present invention, if the watchdog timer module in the MCU subsystem generates a timeout error, it indicates that an error has occurred in the MCU-side program. At this time, the system will be unable to report faults. This watchdog timer error will trigger the reset hardware circuit module to generate a reset signal, which is sent to the MCU subsystem and the FPGA subsystem to complete the reset of the ARINC664 terminal, thereby enabling the ARINC664 terminal to restore the fault reporting ability.

[0022] Refer to Figure 4, assume that the ARINC664 terminal system part in the present invention includes a first ARINC664 terminal system, a second ARINC664 terminal system, and a third ARINC664 terminal system. These three terminal systems and any ARINC664 switch product form an AFDX network, and network data communication is carried out between the ARINC664 terminal systems through the ARINC664 switch product. The three terminal systems communicate with the upper computer module for fault information collection through three independent links respectively, reporting the fault information of their respective terminals. The upper computer module for fault information collection collects the error information from all ARINC664 terminals in this AFDX network and conducts summary and processing.

[0023] The above is only a further description of the present invention and is not intended to limit the present invention. All equivalent implementations of the present invention should be included within the scope of the claims of the present invention. For those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solution and inventive concept of the present invention, and all such changes or substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. An ARINC664 terminal system for real-time detection and reporting of network faults, characterized in that, The system includes an ARINC664 terminal and a host computer module (13) for collecting fault information. The ARINC664 terminal includes a power supply module (1), a power supply voltage monitoring module (2), a power supply temperature monitoring module (3), a reset circuit module (4), an AFDX network connection module (5), an MCU microcontroller subsystem (6), an FPGA programmable gate array subsystem (7), a display module (8), an application program interface module (9), and a high-speed data memory module (10). The power supply voltage monitoring module (2) is connected to the power supply module (1) and the MCU microcontroller subsystem (6) for monitoring the power supply voltage. The power supply temperature monitoring module (3) is connected to the power supply module (1) and the MCU microcontroller subsystem (6) for monitoring the power supply temperature. The reset circuit module (4) is connected to the power supply module (1), the MCU microcontroller subsystem (6), and the FPGA programmable gate array subsystem (7) for controlling the reset of the ARINC664 terminal when a failure is reported. The AFDX network connection module (5) is connected to the power supply module (1) and the FPGA programmable gate array subsystem (7) for accessing the physical layer of the AFDX avionics network to transmit and receive data. The MCU microcontroller subsystem (6) is connected to the power supply module (1), the power supply voltage monitoring module (2), the power supply temperature monitoring module (3), the reset circuit module (4), the FPGA programmable gate array subsystem (7), the display module (8), and the host computer module (13) for collecting fault information such as abnormal power supply voltage, abnormal power supply temperature, protocol faults, data faults, abnormal MCU chip temperature, and abnormal FPGA chip temperature in the ARINC664 terminal, displaying the fault information on the display module (8), and transmitting it to the host computer module (13) for collecting fault information. The FPGA programmable gate array subsystem (7) is connected to the power supply module (1), the reset circuit module (4), the AFDX network connection module (5), the MCU microcontroller subsystem (6), the application program interface module (9), and the high-speed data memory module (10) for interacting with the upper-layer application program of the ARINC664 terminal, encapsulating the application program data sent by the application program interface module (9) into network data packets conforming to the ARINC664 standard protocol, and sending the data packets to the AFDX network connection module (5), unloading the ARINC664 protocol from the data packets received from the AFDX network connection module (5) to obtain the application program data and sending it to the application program interface module (9), caching the data through the high-speed data memory module (10) during data transmission and reception, detecting protocol faults in the ARINC664 terminal system, data faults occurring during network data processing, and abnormal FPGA chip temperature faults, and transmitting the fault information to the MCU microcontroller subsystem (6).The display module (8) is connected to the power supply module (1) and the MCU microcontroller subsystem (6) for locally displaying fault information at the ARINC664 terminal; the application programming interface module (9) is connected to the FPGA programmable gate array subsystem (7) to implement the upper-layer application program of the ARINC664 terminal; the high-speed data memory module (10) is connected to the power supply module (1) and the FPGA programmable gate array subsystem (7), which is implemented by the cache resources inside the FPGA chip and the off-chip high-speed memory DDR4 chip, and provides high-speed caching for the data processing of the ARINC664 terminal; The upper computer module (13) for collecting fault information is connected to the MCU microcontroller subsystem (6) in the ARINC664 terminal. The upper computer module (13) for collecting fault information can be connected to multiple ARINC664 terminals through independent links to summarize and process the fault information of all ARINC664 terminals in the AFDX network.

2. The ARINC664 terminal system for real-time detection and reporting of network faults according to claim 1, characterized in that The power supply module (1) includes a power supply module (11) for the fault detection circuit and a power supply module (12) for the ARINC664 terminal. The power supply module (11) for the fault detection circuit is connected to the power supply voltage monitoring module (2), the power supply temperature monitoring module (3), the reset circuit module (4), the MCU microcontroller subsystem (6) and the display module (8), and is powered by an independent power supply to improve the power supply safety of the power supply voltage monitoring module, the power supply temperature monitoring module, the reset circuit module, the MCU microcontroller subsystem and the display module used to implement fault monitoring and reporting. The power supply module (12) for the ARINC664 terminal is connected to the AFDX network connection module (5), the FPGA programmable gate array subsystem (7) and the high-speed data memory module (10) to provide power for the AFDX network connection module, the FPGA programmable gate array subsystem and the high-speed data memory module required to implement the ARINC664 protocol.

3. The ARINC664 terminal system for real-time detection and reporting of network faults according to claim 1, characterized in that, The MCU microcontroller subsystem (6) includes an MCU chip temperature detection module (61), a watchdog timing module (62), an ARINC664 terminal fault information summarization module (63), an MCU_FPGA communication module (64), an interface display module (65), and a fault reporting module (66); the MCU chip temperature detection module (61) is connected to the ARINC664 terminal fault information summarization module (63), and uses the temperature sensor built in the MCU chip and the ADC of the MCU to perform temperature measurement and calculation to realize the detection of the MCU chip temperature; the watchdog timing module (62) is connected to the reset circuit module (4), and uses the hardware watchdog timer built in the MCU to perform timeout detection to realize the detection of MCU program faults; the ARINC664 terminal fault information summarization module (63) is connected to the power supply voltage monitoring module (2), the power supply temperature monitoring module (3), the MCU chip temperature detection module (61), the MCU_FPGA communication module (64), the interface display module (65), and the fault reporting module (66), and realizes the summarization and processing of power supply voltage anomalies, power supply temperature anomalies, MCU chip temperature anomalies, protocol faults, data faults, and FPGA chip temperature anomaly fault information from the MCU_FPGA communication module (64), sends the fault information to the interface display module (65) for fault interface display, and sends the fault information to the fault reporting module (66) for fault information reporting; the MCU_FPGA communication module (64) is connected to the FPGA programmable gate array subsystem (7) for bus communication with the FPGA programmable gate array subsystem, and receives protocol faults, data faults, and FPGA chip temperature anomaly fault information transmitted from the FPGA programmable gate array subsystem. The interface display module (65) is connected to the ARINC664 terminal fault information summarization module (63) and the display module (8) to realize the driving and drawing of the ARINC664 terminal display interface. The fault reporting module (66) is connected to the ARINC664 terminal fault information summarization module (63) and the fault information collection host computer module (13) to realize the integration of power supply voltage anomalies, power supply temperature anomalies, protocol faults, data faults, MCU chip temperature anomalies, and FPGA chip temperature anomaly fault information into data packets in a specific format, and report them to the fault information collection host computer module (13) through an independent transmission link.

4. An ARINC664 terminal system for real-time detection and reporting of network faults according to claim 1, characterized in that, The FPGA programmable gate array subsystem (7) includes an FPGA chip temperature detection module (71), an ARINC664 data sending module (72), an ARINC664 data receiving module (73), an FPGA_MCU communication module (74), a protocol and data processing fault information summarization module (75), an ARINC664 protocol fault detection module (76), an ARINC664 data communication module (77), a logic internal and external cache data storage verification module (78), and an ARINC664 data packet processing module (79); the FPGA chip temperature detection module (71) is connected to the protocol and data processing fault information summarization module (75), uses the built-in temperature sensor and ADC of the FPGA chip to perform temperature measurement and calculation, and realizes the detection of the internal temperature of the FPGA chip; the ARINC664 data sending module (72) is connected to the AFDX network connection module (5) and the ARINC664 protocol fault detection module (76), realizes the virtual link sending logic and the dual-redundancy link sending logic, encapsulates the data packet after the ARINC664 protocol fault detection module (76) completes the protocol error detection into a MAC frame and sends it to the physical layer AFDX network connection module (5), and completes the network data sending function of the ARINC664 terminal; the ARINC664 data receiving module (73) is connected to the AFDX network connection module (5) and the ARINC664 protocol fault detection module (76), realizes the virtual link receiving logic and the dual-redundancy link receiving logic, receives the physical layer data packet from the AFDX network connection module (5), unloads the MAC frame protocol and sends it to the ARINC664 protocol fault detection module (76) for protocol detection, and completes the network data receiving function of the ARINC664 terminal; the FPGA_MCU communication module (74) is connected to the MCU microcontroller subsystem (6) and the protocol and data processing fault information summarization module (75), realizes sorting the protocol faults, data faults, and FPGA chip temperature abnormal fault information summarized by the protocol and data processing fault information summarization module (75) into a specific data format, and transmits it to the MCU microcontroller subsystem (6) through the communication bus; the protocol and data processing fault information summarization module (75) is connected to the FPGA chip temperature detection module (71), the FPGA_MCU communication module (74), the ARINC664 protocol fault detection module (76), and the logic internal and external cache data storage verification module (78), realizes the summarization and processing of the protocol fault information of the ARINC664 protocol fault detection module (76), the data fault information of the logic internal and external cache data storage verification module (78), and the FPGA chip temperature abnormal fault information of the FPGA chip temperature detection module (71), and sends the fault information to the FPGA_MCU communication module (74);The ARINC664 protocol fault detection module (76) is connected to the ARINC664 data transmission module (72), the ARINC664 data reception module (73), the protocol and data processing fault information summarization module (75), and the ARINC664 data packet processing module (79). It implements the virtual link identifier legality verification logic, virtual link bandwidth allocation legality verification logic, bandwidth allocation interval BAG legality verification logic, scheduler scheduling result verification logic, frame format error detection logic, frame length anomaly detection logic, ARINC664 protocol stack error detection logic, redundancy management fault detection logic, end-to-end delay overrun detection logic, traffic detection logic, and EDE integrity check logic through FPGA logic code to complete the protocol fault detection function. It performs protocol fault detection on the data packets from the ARINC664 data packet processing module (79), and the data packets after protocol fault detection are sent to the ARINC664 data transmission module (72). It also performs protocol fault detection on the data packets from the ARINC664 data reception module (73), and the data packets after protocol fault detection are sent to the ARINC664 data packet processing module (79), and the protocol fault information is sent to the protocol and data processing fault information summarization module (75). The ARINC664 data communication module (77) is connected to the internal and external cache data storage and verification module (78) and the application program interface module (9), and uses PCIe bus communication to send and receive application data with the ARINC664 terminal application program interface module. For the application data sent by the application program interface module (9), the ARINC664 data communication module (77) forwards the application data to the internal and external cache data storage and verification module (78). For the data sent by the internal and external cache data storage and verification module (78), the ARINC664 data communication module forwards this data to the application program interface module (9).The internal and external cache data storage verification module (78) is connected to the protocol and data processing fault information summarization module (75), the ARINC664 data communication module (77), the ARINC664 data packet processing module (79), and the high-speed data memory module (10). When receiving data sent from the ARINC664 data communication module (77), the internal and external cache data storage verification module (78) will send these data to the high-speed data memory module (10) for data caching and forward them to the ARINC664 data packet processing module (79). When receiving data from the ARINC664 data packet processing module (79), the internal and external cache data storage verification module (78) will send these data to the high-speed data memory module (10) for data caching and forward them to the ARINC664 data communication module (77). During the above caching and forwarding process, CRC verification is used to implement data integrity check, and the ECC verification algorithm is used to verify the data, so as to detect and correct the single-event upset data faults occurring during the data caching and processing process, as well as detect the multi-bit flip errors, complete the data fault detection, and send the data fault information to the protocol and data processing fault information summarization module (75); the ARINC664 data packet processing module (79) is connected to the ARINC664 protocol fault detection module (76) and the internal and external cache data storage verification module (78) to implement the virtual link scheduling and bandwidth allocation logic, the bandwidth interval allocation logic, and the traffic shaping logic. For the data from the ARINC664 protocol fault detection module (76), the ARINC664 data packet processing module (79) will unload the ARINC664 protocol from these data and send the data after protocol unloading to the internal and external cache data storage verification module (78). For the data from the internal and external cache data storage verification module (78), the ARINC664 data packet processing module (79) will encapsulate these data into ARINC664 protocol frames and send the ARINC664 protocol frames to the ARINC664 protocol fault detection module (76) to implement network data processing and the ARINC664 protocol.;

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