Method for preparing CZT radiation chip with high energy resolution

Abstract

The invention discloses a method for preparing a CZT high-energy-resolution radiation chip, and belongs to the technical field of electrical component production, and the method comprises the following steps: S1, growing a CZT crystal; s2, preparing a required CZT sheet by adopting the CZT crystal; s3, injecting a certain dose of fluorine ions into the CZT sheet; s4, performing an annealing process on the CZT sheet after the fluorine ions are injected, so that the fluorine ions are uniformly diffused in the CZT sheet to improve lattice defects during growth of the CZT crystal; s5, indium ions are injected into the surface layer of the cathode of the CZT sheet, so that the resistivity of the CZT sheet is improved, the energy band structure of the CZT sheet is changed, and a stronger radiation signal is generated; s6, the annealing process is carried out again, so that indium ions are more uniformly distributed on the surface layer of the CZT sheet; s7, plating platinum on the cathode surface of the CZT sheet, and plating indium on the anode surface of the CZT sheet; and S8, respectively connecting the CZT sheet with the cathode and the anode of the detector, and then packaging the CZT sheet with a shell. The method has the advantages that lattice defects are improved, and the carrier migration life product is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of the production of electrical components, and particularly relates to a method for preparing a CZT high-energy resolution radiation chip. Background Art

[0002] CZT (cadmium zinc telluride) radiation detection material is an important semiconductor material, which is widely used in radiation detectors, especially for X-ray, γ-ray and neutron detection. This material has some unique physical properties, which make it have significant advantages in radiation detection. An important index of the detector is energy resolution, and the factors affecting energy resolution include bulk resistivity, carrier drift lifetime product and surface leakage current, etc. During the growth process of CZT material, lattice defects (such as vacancies, dislocations, etc.) usually occur, and these defects will cause carrier scattering and reduce the mobility. In the prior art, in order to solve such problems, elements are doped during the growth process of CZT material, and by filling these defects or changing the nature of the defects, the carrier scattering is reduced, and the electron mobility and carrier lifetime are improved; however, during the growth process of this CZT crystal, due to the segregation effect of the doped elements and different segregation coefficients, the distribution of the doped elements in the CZT crystal is uneven in the transverse and longitudinal directions, so the consistency of the detector made of this CZT crystal is very poor. In order to improve the uniformity of the distribution of the doped elements, fill the lattice defects, improve the electron mobility and carrier lifetime, a method for preparing a CZT high-energy resolution radiation chip is proposed. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0004] For this reason, the present invention proposes a method for preparing a CZT high-energy resolution radiation chip, and this method for preparing a CZT high-energy resolution radiation chip has the advantages of improving lattice defects and increasing the carrier drift lifetime product.

[0005] According to an embodiment of the present invention, the method for preparing a CZT high-energy resolution radiation chip includes the following steps: S1. Grow a CZT crystal; S2. Prepare a required CZT wafer using the CZT crystal; S3. Inject a certain dose of fluoride ions into the CZT wafer; S4. Perform an annealing process on the CZT wafer injected with fluoride ions to uniformly diffuse the fluoride ions in the CZT wafer, so as to improve the lattice defects during the growth of the CZT crystal; S5. Inject indium ions into the cathode surface layer of the CZT wafer to increase the resistivity of the CZT wafer and change the energy band structure of the CZT wafer to generate a stronger radiation signal; S6. Perform the annealing process again to make the distribution of indium ions on the surface layer of the CZT wafer more uniform; S7. Deposit platinum on the cathode surface of the CZT wafer and deposit indium on the anode surface of the CZT wafer; S8. Connect the CZT wafer to the cathode and anode of the detector respectively, and then encapsulate it with a housing.

[0006] According to an embodiment of the present invention, in S3, the ion implantation energy is 30 - 50 keV; the concentration of fluorine (F) ions in the CZT wafer reaches 30 ppm through ion implantation.

[0007] According to an embodiment of the present invention, in S4, the annealing process temperature is 650°, and it is maintained for 12 hours. The atmosphere is an oxygen-free environment maintained by an inert gas to avoid oxidation.

[0008] According to an embodiment of the present invention, in S5, indium ions are implanted into the surface layer of the CZT wafer, with a depth of 200 - 500 nm, and the concentration of indium ions in the surface layer of the CZT wafer is 20 ppm.

[0009] According to an embodiment of the present invention, in S6, the annealing process temperature is 550°, the temperature holding time is 1 - 2 hours, and the atmosphere is an oxygen-free environment maintained by an inert gas.

[0010] According to an embodiment of the present invention, after the S6 step, use photoresist to protect the cathode surface and anode surface of the CZT wafer, and at the same time expose the four side surfaces of the CZT wafer, and then form an insulating layer on the four side surfaces of the CZT wafer to reduce the surface leakage of the CZT wafer and improve the accuracy of subsequent detection data.

[0011] According to an embodiment of the present invention, the insulating layer is a silicon dioxide layer, and the thickness of the insulating layer is 500 nm.

[0012] According to an embodiment of the present invention, the insulating layer is prepared by chemical vapor deposition, and the deposition temperature is 300°C - 400°C.

[0013] According to an embodiment of the present invention, in S2, cut the CZT wafer according to the orientation of the CZT crystal. The size of the CZT wafer is 10 mm x 10 mm x 1 mm, and then grind and polish the CZT wafer to make the surface roughness of the CZT wafer reach Ra ≤0.5 µm.

[0014] According to an embodiment of the present invention, in S7, both indium plating and platinum plating adopt magnetron sputtering technology, the sputtering power is 50 - 200 W, the thickness of the platinum layer after sputtering is 500 nm, and the thickness of the indium layer after sputtering is 500 nm - 1 µm.

[0015] The beneficial effects of the present invention are as follows. By injecting fluoride ions into the CZT wafer, the lattice defects during the growth of the CZT crystal are improved, the deep energy levels in the CZT wafer are eliminated, and the carrier migration lifetime product in the CZT wafer is increased. By injecting indium ions to a certain depth on the surface layer of the CZT wafer, the resistivity of the CZT wafer is increased, and the energy band structure of the CZT wafer is changed to generate a stronger radiation signal. By preparing a silicon dioxide layer on the four side walls of the CZT wafer during the production process, the contact between the CZT wafer and impurity ions before encapsulation is reduced, so the leakage current is reduced and the accuracy of subsequent detection data is improved.

[0016] Other features and advantages of the present invention will be described in the following specification, and in part, will become apparent from the specification or be understood by implementing the present invention.

[0017] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein: Figure 1 is a line graph showing the influence of F doping on the energy resolution of CZT in the present invention; Figure 2 is a line graph showing the influence of In doping on the energy resolution of CZT in the present invention; Figure 3 is a cross-sectional schematic diagram of the chip structure of the present invention; Reference numerals: 1, cathode conductive layer; 2, anode conductive layer; 3, insulating layer; 5, CZT wafer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following details the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0020] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the features defined as "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. In the description of the present invention, it should be noted that, unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0021] The method for preparing a CZT high energy resolution radiation chip according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings.

[0022] As Figure 3 shown, the method for preparing a CZT high energy resolution radiation chip according to an embodiment of the present invention includes the following steps: S1. Grow a CZT crystal by a liquid phase method, where the zinc element is 10%, and no other elements are doped in this process to reduce the phenomenon of uneven distribution of dopants in the CZT crystal due to different segregation effect coefficients during the growth of the CZT crystal; the growth temperature range of the CZT crystal includes but is not limited to 1100 °C, and the cooling rate is 1 °C / h - 2 °C / h, and stable cooling is maintained to reduce internal stress.

[0023] S2. Prepare a required CZT wafer 5 from the CZT crystal; cut the CZT wafer 5 according to the orientation of the CZT crystal, the size of the CZT wafer 5 is 10 mm x 10 mm x 1 mm, and precise scribing is performed to facilitate subsequent electrode deposition, and then the CZT wafer 5 is ground and polished to make the surface roughness of the CZT wafer 5 reach Ra ≤ 0.5 µm.

[0024] S3. Inject a certain dose of fluoride ions into the CZT wafer 5; the ion implantation energy is 30 - 50 keV; through ion implantation, the concentration of fluorine (F) ions in the CZT wafer 5 reaches 30 ppm.

[0025] S4. Anneal the CZT wafer 5 after injecting fluoride ions. The annealing process temperature is 650 °C and it is maintained for 12 hours. The atmosphere is an oxygen-free environment maintained by an inert gas to avoid oxidation; the inert gas includes but is not limited to nitrogen or argon, so that the fluoride ions are evenly diffused in the CZT wafer 5 to improve the lattice defects during the growth of CZT crystals. Since during the CZT growth process, the saturated vapor pressure of Cd (cadmium) is relatively large, cadmium vacancies are easily formed during crystal growth, resulting in the absorption of carriers by defects during the transmission process after the carrier signal is generated. By injecting fluoride ions, a large number of deep energy levels in the CZT wafer 5 can be eliminated, and the carrier mobility-lifetime product in the CZT wafer 5 can be improved.

[0026] S5. Inject indium ions into the cathode surface layer of the CZT wafer 5 to a depth of 200 - 500 nm, and make the surface concentration of indium ions in the CZT wafer 5 20 ppm, so as to increase the resistivity of the CZT wafer 5 and change the energy band structure of the CZT wafer 5 to generate a stronger radiation signal.

[0027] S6. Perform the annealing process again to make the distribution of indium ions on the surface layer of the CZT wafer 5 more uniform; the annealing process temperature is 550 °C, and the temperature holding time is 1 - 2 hours. The atmosphere is an oxygen-free environment maintained by an inert gas; the temperature holding time in this process is only 1 - 2 hours to increase the uniformity of the indium ion distribution on the surface layer of the CZT wafer 5 while reducing the diffusion amount of indium ions into the deep layer of the CZT wafer 5; at the same time, this annealing process also realizes the repair of the damaged lattice during the ion implantation process.

[0028] S61. Use photoresist to protect the cathode and anode surfaces of the CZT wafer 5 to prevent the subsequent insulating layer 3 from covering the cathode and anode surfaces; at the same time, the four side surfaces of the CZT wafer 5 are exposed, and then an insulating layer 3 is formed on all four side surfaces of the CZT wafer 5 to reduce the surface leakage current of the CZT wafer 5; the insulating layer 3 is a silicon dioxide layer, and the thickness of the insulating layer 3 is 500 nm; the insulating layer 3 is prepared by chemical vapor deposition, and the deposition temperature is 300 °C - 400 °C; during the production process, the CZT wafer 5 is extremely likely to adhere to impurity ions, such as sodium ions and chloride ions on the producer's hands or gloves, etc. These impurity ions will cause a relatively large surface leakage current in the CZT wafer 5. Usually, when the CZT wafer 5 is applied to a detector, a certain compensation will be preset for the detection data according to the leakage current situation, but there is a certain error between this compensation and the actual leakage current, so it will lead to inaccurate detection data. By preparing a silicon dioxide layer during the production process, the contact between the CZT wafer 5 and impurity ions before packaging is reduced, so the accuracy of subsequent detection data is improved.

[0029] S7. Platinum is plated on the cathode surface of the CZT wafer 5 to form the cathode conductive layer 1, and indium is plated on the anode surface of the CZT wafer 5 to form the anode conductive layer 2; both indium plating and platinum plating use the magnetron sputtering process, the sputtering power is 50 - 200 W, the thickness of the platinum layer after sputtering is 500 nm, and the thickness of the indium layer after sputtering is 500 nm - 1 µm.

[0030] S8. Use precision welding technology to weld the cathode and anode leads of the detector to the appropriate contact points of the CZT wafer 5, and then use a resin housing for encapsulation to ensure its mechanical stability and prevent environmental pollution. The encapsulation can use sealant or other high-strength bonding materials to ensure the long-term stability of the detector performance.

[0031] After simply growing CZT crystals and then using ion implantation, the CZT wafer 5 is prepared into a composite electrode structure to give play to the advantages of different doping elements. The implantation of fluorine ions improves the lattice defects during CZT crystal growth, eliminates the deep energy levels in the CZT wafer 5, and increases the carrier mobility-lifetime product in the CZT wafer 5; indium ions are implanted to a certain depth on the surface layer of the CZT wafer 5, which increases the resistivity of the CZT wafer 5 and changes the energy band structure of the CZT wafer 5, generating a stronger radiation signal; in addition, by preparing a silicon dioxide layer on the four sidewalls of the CZT wafer 5 during the production process, the contact between the CZT wafer 5 and impurity ions before encapsulation is reduced, so the leakage current is reduced and the accuracy of subsequent detection data is improved.

[0032] As Figure 1 shown, when the In concentration is fixed at 50 ppm, as the F concentration increases from 0 to 200 ppm, the energy resolution decreases from 2.0% to 1.6%, indicating that F doping helps to improve the energy resolution.

[0033] As Figure 2 shown, when the F concentration is fixed at 100 ppm, as the In concentration increases from 0 to 100 ppm, the energy resolution decreases from 2.2% to 1.6%, indicating that In doping also has a similar optimization effect.

[0034] By implanting indium ions only on the surface layer of the CZT wafer 5, it is avoided that during the deep-layer propagation of the signal in the CZT wafer 5, (indium doping will form indium-tellurium clusters and absorb the generated signal). Therefore, during the signal transmission process, the signal mainly passes through the F-doped region, thus ensuring the intensity of the signal in the deep-layer propagation of the CZT wafer 5, and reducing the energy resolution of the CZT wafer 5 from 2 - 1.5% to below 1%.

[0035] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0036] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for preparing a CZT high energy resolution radiation chip, characterized in that, It includes the following steps: S1. Grow a CZT crystal; S2. Prepare a required CZT wafer (5) using the CZT crystal; S3. Inject a certain dose of fluoride ions into the CZT wafer (5); S4. Perform an annealing process on the CZT wafer (5) after injecting fluoride ions to uniformly diffuse the fluoride ions in the CZT wafer (5) to improve the lattice defects during the growth of the CZT crystal; S5. Inject indium ions into the cathode surface layer of the CZT wafer (5) to increase the resistivity of the CZT wafer (5) and change the energy band structure of the CZT wafer (5); S6. Perform the annealing process again to make the indium ions more uniformly distributed on the surface layer of the CZT wafer (5); S7. Deposit platinum on the cathode surface of the CZT wafer (5) and deposit indium on the anode surface of the CZT wafer (5); S8. Connect the CZT wafer (5) to the cathode and anode of the detector respectively, and then encapsulate it using a housing.

2. The method for preparing a CZT high energy resolution radiation chip according to claim 1, wherein, In S3, the ion implantation energy is 30 - 50 keV; the concentration of fluoride ions in the CZT wafer (5) is made to reach 30 ppm through ion implantation.

3. The method for preparing a CZT high energy resolution radiation chip according to claim 2, wherein In S4, the annealing process temperature is 650°C and it is maintained for 12 hours, and the atmosphere is an oxygen-free environment maintained using an inert gas.

4. The method for preparing a CZT high energy resolution radiation chip according to claim 3, wherein In S5, indium ions are injected into the surface layer of the CZT wafer (5) to a depth of 200 - 500 nm, and the concentration of indium ions on the surface layer of the CZT wafer (5) is 20 ppm.

5. The method for preparing a CZT high energy resolution radiation chip according to claim 4, characterized in that, In S6, the annealing process temperature is 550°C, the temperature holding time is 1 - 2 hours, and the atmosphere is an oxygen-free environment maintained using an inert gas.

6. The method for preparing a CZT high energy resolution radiation chip according to claim 5, characterized in that, After step S6, use photoresist to protect the cathode and anode surfaces of the CZT wafer (5), and at the same time expose the four side surfaces of the CZT wafer (5), and then form an insulating layer (3) on the four side surfaces of the CZT wafer (5) to reduce the surface leakage of the CZT wafer (5).

7. The method for preparing a CZT high energy resolution radiation chip according to claim 6, characterized in that, The insulating layer (3) is a silicon dioxide layer, and the thickness of the insulating layer (3) is 500 nm.

8. The method for preparing a CZT high energy resolution radiation chip according to claim 7, characterized in that, The insulating layer (3) is prepared by chemical vapor deposition, and the deposition temperature is 300°C - 400°C.

9. The method for preparing a CZT high energy resolution radiation chip according to claim 8, wherein, In S2, cut the CZT wafer (5) according to the orientation of the CZT crystal. The size of the CZT wafer (5) is 10 mm x 10 mm x 1 mm, and then grind and polish the CZT wafer (5) to make the surface roughness of the CZT wafer (5) reach Ra ≤ 0.5 µm.

10. The method for preparing a CZT high energy resolution radiation chip according to claim 9, wherein In S7, both indium deposition and platinum deposition use magnetron sputtering technology, the sputtering power is 50 - 200 W, the thickness of the platinum layer after sputtering is 500 nm, and the thickness of the indium layer after sputtering is 500 nm - 1 µm.

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