Parallel receiving method and system for high-speed 16 QAM (Quadrature Amplitude Modulation) data demodulation

Abstract

The invention discloses a parallel receiving method and system for high-speed 16 QAM (Quadrature Amplitude Modulation) data demodulation, and the method comprises the following steps: S1, carrying out the sampling of received intermediate-frequency 16 QAM data through a high-speed ADC (Analog to Digital Converter), and obtaining four paths of signals through the serial-to-parallel conversion function of the ADC; s2, converting the four paths of signals into 32 paths of parallel signals at a conversion rate of 1: 8 by using a serial-to-parallel converter special for the FPGA; and S3, carrying out digital orthogonal down-conversion on the 32 paths of parallel signals to obtain 16 paths of baseband signals of an I path and a Q path, and then sequentially carrying out matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization and 16QAM judgment decoding to complete parallel receiving. According to the invention, the requirement of high bit rate is met based on three key technologies of timing synchronization, blind equalization and carrier synchronization, and the receiving and demodulation recovery functions of high-speed data in a 16 QAM modulation mode can be effectively completed.

Description

Technical Field

[0001] The invention belongs to the field of remote sensing satellite high-speed digital receivers, and in particular relates to a parallel receiving method and system for high-speed 16QAM data demodulation. Background Art

[0002] With the development of the global economy, countries around the world are increasingly prioritizing advancements in aerospace technology, and remote sensing satellites have gradually become a key focus. Data acquired by remote sensing satellites can be applied in a wide range of fields, including meteorological observation, missile warning, resource exploration, and ecological and environmental assessment, playing a vital role in my country's social development. Remote sensing data processing is both a challenging and crucial area of research today. As a key component of remote sensing satellites, the data processing and transmission system primarily consists of the satellite's onboard transmitter and the ground-based receiving station. These systems are responsible for compressing, framing, encoding, modulating, and performing the corresponding demodulation, decoding, and decompression operations on remote sensing data. However, with the continuous advancement of remote sensing satellite technology, the resolution of cameras and radars onboard remote sensing satellites has steadily increased, resulting in a dramatic increase in the amount of remote sensing data to be processed. This has also necessitated the use of higher-order modulation schemes in remote sensing satellite data transmission systems, increasing the data rates required by ground receiving stations. Furthermore, due to changes in the space environment, the signal-to-noise ratio of remote sensing satellite signals has gradually decreased, posing new challenges for signal synchronization at ground receiving stations.

[0003] High-bit-rate digital receivers have no restrictions on the information content they transmit and can be used in scenarios with large data volumes. Currently, research in high-speed data transmission in my country started relatively late, with bit rates generally reaching the hundreds of Mbps level. These are mostly applied to low-order modulation schemes such as BPSK and QPSK, leaving a significant gap compared to advanced international technologies. For example, around 2000, the 54th Research Institute of China Electronics Technology Group Corporation developed a QPSK prototype with a bit rate of 150 Mbps. In 2007, the Beijing Institute of Telemetry Technology developed BPSK and QPSK receivers with bit rates ranging from 20 Mbps to 600 Mbps. In 2012, Tsinghua University developed a 16QAM high-speed demodulation prototype with a bit rate of 2 Gbps. However, with the continuous increase in transmitted data volumes and data rates, and the increasing scarcity of spectrum resources, higher-order modulation schemes that combine amplitude and phase information, such as M-QAM and M-APSK, have become more widely used. However, higher-order modulation schemes can lead to reduced noise immunity and increased synchronization algorithm complexity, posing new challenges for the implementation of high-bit-rate digital receivers. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a parallel receiving method and system for high-speed 16QAM data demodulation. Based on the three key technologies of timing synchronization, blind equalization and carrier synchronization, the method adapts to the requirements of high code rate and can effectively complete the reception and demodulation recovery functions of high-speed data under the 16QAM modulation mode.

[0005] The object of the present invention is achieved through the following technical solution: a parallel receiving method for high-speed 16QAM data demodulation, comprising the following steps:

[0006] S1. Use a high-speed ADC to sample the received 16QAM IF data and use the ADC's serial-to-parallel conversion function to generate four signals.

[0007] S2. Use the FPGA-specific serial-to-parallel converter to convert the 4-channel signal into 32 parallel signals at a conversion rate of 1:8.

[0008] S3. In the FPGA, the 32 parallel signals are digitally orthogonally down-converted to obtain 16 baseband signals each for the I and Q channels. Matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization, and 16QAM decision decoding are then performed in sequence to complete parallel reception.

[0009] A parallel receiving system for high-speed 16QAM data demodulation, comprising:

[0010] High-speed ADC, used to sample the received IF 16QAM data and obtain four-channel signals using the ADC's serial-to-parallel conversion function;

[0011] The serial-to-parallel conversion module uses a dedicated FPGA serial-to-parallel converter to convert 4-channel signals into 32-channel parallel signals at a conversion rate of 1:8;

[0012] The parallel receiving and processing module is used to obtain 16 baseband signals of I and Q channels through digital orthogonal down-conversion of 32 parallel signals, and then perform matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization and 16QAM decision decoding in sequence to complete parallel reception.

[0013] The beneficial effects of the present invention are: 1. Based on the background of a sharp increase in data volume, the present invention aims to solve the problem that traditional data transmission testers are difficult to achieve very high code rates or can only be applied to low-order modulation methods. A parallel architecture receiver solution for high-speed 16QAM data demodulation is proposed, which can achieve a code rate of 1.25Gsps under the 16QAM modulation method, effectively improving the data rate of the input intermediate frequency signal.

[0014] 2. The present invention improves the traditional Gardner timing synchronization algorithm, modifies the timing error estimation formula for the 16QAM modulation mode, and changes the loop filter and interpolation controller to a form suitable for FPGA implementation, thereby reducing the timing error and improving the timing synchronization performance.

[0015] 3. The present invention improves the traditional CADAMA blind equalization algorithm, corrects the equalization error estimation formula according to the constellation diagram of 16QAM modulation, and uses the relaxation advance transform technology to correct the tap coefficient update formula. It simplifies the parallel implementation structure of the algorithm without sacrificing performance and effectively eliminates inter-code interference.

[0016] 4. This invention improves the traditional PFD carrier synchronization algorithm and designs an FPGA implementation method of the Arctan approximation algorithm to replace the traditional Cordic IP core, saving a lot of logic resources and shortening the timing delay, effectively eliminating the frequency deviation and phase deviation in the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the overall flow chart of the parallel architecture receiver for high-speed 16QAM data demodulation proposed by the present invention;

[0018] Figure 2 32-way high-speed parallel timing synchronization principle block diagram designed for the present invention;

[0019] Figure 3 The principle block diagram of the high-speed parallel blind equalizer designed for the present invention;

[0020] Figure 4 This is a principle block diagram of the high-speed parallel carrier synchronization designed for the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0022] like Figure 1 As shown, a parallel receiving method for high-speed 16QAM data demodulation includes the following steps:

[0023] S1. Use a high-speed ADC to sample the received 16QAM IF data and use the ADC's serial-to-parallel conversion function to generate four signals.

[0024] In modern communication systems, there are three main receiver architectures: superheterodyne receivers, zero-IF receivers, and low-IF receivers. In a low-IF receiver, the signal undergoes a first-stage mixing process, outputting a low-IF signal. This signal is then sampled directly at the IF, and the resulting signal is fed into a digital signal processing device for full digital demodulation. The present invention employs a low-IF receiver because it maintains high receiver integration and significantly reduces losses such as DC offset and local oscillator leakage.

[0025] The input is a 16QAM high-speed data stream with an intermediate frequency of 1.25GHz and a symbol rate of 1.25Gsps. The high-speed ADC samples at a sampling rate of 5GHz to obtain four signals with a rate of 1.25GHz. The FPGA-specific serial-to-parallel converter Iserdes then converts the four 1.25GHz signals into 32 156.25MHz signals at a conversion rate of 1:8 as the input signal of the FPGA. At the same time, the FPGA clock signal should also be 156.25MHz.

[0026] S2. Use the FPGA-specific serial-to-parallel converter to convert the 4-channel signal into 32 parallel signals at a conversion rate of 1:8.

[0027] S3. The 32 parallel signals are digitally orthogonally down-converted to 16 baseband signals each for I and Q channels. Matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization, and 16QAM decision decoding are then performed in sequence to complete parallel reception.

[0028] Since the intermediate frequency f c is 1.25GHz, and the ADC sampling rate f s The sampling rate is 5 GHz, which means the sampling rate is four times the intermediate frequency. The baseband signal after digital orthogonal down-conversion is expressed as:

[0029]

[0030] Where n is the serial number of the discrete digital signal, S(n) is the nth parallel signal, n = 1, 2, ..., 31;

[0031] I(n) and Q(n) are the in-phase component and quadrature component of the n-th parallel signal;

[0032] There is no need to generate a local oscillator signal. Instead, the I and Q baseband signals can be obtained by performing odd-even alternating extraction and inversion on S(n), which can be expressed as:

[0033]

[0034] After the mixer-free digital orthogonal down-conversion, the 32-channel input data is converted into 16 channels of I and Q data, completing the down-conversion task of the intermediate frequency signal.

[0035] The output of the digital orthogonal down-conversion is matched filtered to amplify the signal-to-noise ratio.

[0036] Due to the non-ideal overall transmission characteristics of the system, the waveforms of the preceding and following symbols are distorted and widened. When the tail of the previous waveform spreads to the sampling moment of the current symbol, inter-symbol interference will occur, interfering with the decision of the current symbol. According to the Nyquist first criterion, inter-symbol interference can be eliminated when the overall characteristics of the baseband system are equivalent to an ideal low-pass filter. However, since ideal low-pass filters cannot be realized in reality, raised cosine roll-off filters are usually used as an approximation.

[0037] The transfer function H(ω) of the raised cosine roll-off filter is determined to be:

[0038]

[0039] Where ω is the digital angular frequency in the filter transfer function, T s is the sampling period of the code element, α is the roll-off coefficient of the raised cosine roll-off filter, and its value range is [0,1]. The value of the roll-off coefficient affects the characteristics of the transfer function. By analyzing the transfer function and time domain response of the filter, it can be seen that the larger α is, the faster the tail decay in the system impulse response, but the bandwidth will also increase, resulting in reduced bandwidth utilization. Therefore, considering the performance requirements, α = 0.35 can be selected.

[0040] Assuming that the channel is ideal, in order to ensure that the system has the minimum bit error rate under the condition of additive white Gaussian noise, the transfer function H of the matched filter is R (ω) is expressed as

[0041]

[0042] For H R (ω) Inverse Fourier transform, get its impulse response h(t), h(t) according to T s Sampling is performed to obtain its discrete impulse response h(n);

[0043] Convolve the input signal x(n) to get the output signal

[0044]

[0045] Where x(n) represents the input signal, y(n) represents the output signal, l1 is the length of the input signal, l2 is the length of the raised cosine roll-off filter from the impulse response, and h(nm) is 0 when the value of nm is not in the range of 0 to l2-1.

[0046] In a high-speed receiver implemented in an FPGA, it is impossible to calculate h(nm) in real time. Therefore, a square-root raised cosine filter is designed using a lookup table, given a roll-off factor α. The value of h(t) is stored in ROM in advance. During the calculation, the value of nm is calculated and then used as an index to retrieve the corresponding h(nm) from the ROM for calculation. Specifically, the rcosdesign function is used in MATLAB to design a square-root raised cosine filter with a roll-off factor α of 0.35. Considering the consumption of FPGA memory resources, a total of 4096 h(t) values are obtained. These values are quantized to 12 bits according to the fixed-point number rules in the FPGA, resulting in a ROM core with a width of 12 and a depth of 4096.

[0047] The raised cosine matched filter operation uses FIR calculations with 2x oversampling to achieve higher accuracy. After the raised cosine, the I / Q channels are 32 each, and each channel still has a frequency of 156.25 MHz. Therefore, after matched filtering, the 16-channel I and Q data are converted into 32-channel I and Q signals, which amplifies the signal-to-noise ratio.

[0048] After matched filtering, 16 channels of data each of I and Q are converted into 32 channels of data each of I and Q, which amplifies the signal-to-noise ratio.

[0049] The 32 signals obtained by matched filtering are used as input. Every 4 input signals x(4k), x(4k+1), x(4k+2), and x(4k+3) are interpolated through the filter to obtain an optimal sampling point y(k), where k = 0, 1, 2...7. 8 outputs are obtained from the 32 parallel inputs.

[0050] In a digital receiver, to accurately recover data, a timing synchronization pulse sequence is required at the receiving end as a marker for sampling decisions. The frequency of this timing pulse sequence is equal to the frequency of the symbol sequence, and the phase corresponds to the optimal sampling point. The process of generating this timing synchronization pulse is called timing synchronization.

[0051] Based on the traditional Gardner timing synchronization algorithm, the present invention designs a 32-way high-speed parallel timing synchronization principle block diagram, as shown in the attached figure. Figure 2 shown.

[0052] The oversampling multiple is 4 times, so every 4 input signals can get one optimal sampling point through the interpolation filter, and 32 parallel inputs can get 8 outputs. In order to improve the speed of timing synchronization, the first 2 of the 8 channels and the middle point are selected to estimate the timing error, and then the estimated error is sent to the loop filter and interpolation controller module, and the output is m k and μ k To control the interpolation position, where: m kIt is called the interpolation base point, which represents the interpolation position of the kth interpolation relative to the input sampling point, μ k The fractional interval represents the ratio of the interval between the interpolation point and the input sampling point to the input period. The interpolation filter uses a cubic interpolation filter, which is implemented using the Farrow structure. Specifically, the interpolation filter uses a cubic interpolation filter because it has a wide and flat mainlobe frequency response, lower sidelobe peaks, and better stopband attenuation characteristics, most similar to the amplitude-frequency characteristics of an ideal interpolation filter. The use of the Farrow structure for the cubic interpolation filter is suitable for FPGA implementation.

[0053] In the timing error detection algorithm, in order to adapt to the high-order modulation mode of 16QAM, the following form is proposed

[0054]

[0055] Among them, y0(k) represents the first of two adjacent sampling points, and y1(k) represents the second of two adjacent sampling points. Represents the middle sampling point between two sampling points; for the 32 parallel input signals, the first 8 signals are involved in the timing error detection, x(0)-x(3) represent the first 4 sampling points, x(4)-x(7) represent the last 4 sampling points, and the middle 4 sampling points are x(2)-x(5); these three groups of signals are output as sequences y0, y1, Participate in the calculation of formula (6); sgn is the sign function, when the value of the independent variable is negative, the result is -1, when it is positive, the result is 1, and when it is zero, it is equal to 0; γ is the parameter affected by the raised cosine characteristic, which should be equal to the matched filter at T s / 2; e(k) in formula (6) is the calculated timing error;

[0056] After the estimated timing error is obtained, it is sent to the loop filter and interpolation controller in sequence; the loop filter adopts the form of a second-order ideal integral filter, and its digital system function can be expressed as

[0057]

[0058] Among them, τ1 and τ2 are time constants, and the values of c1 and c2 are related to the time constants τ1 and τ2. Therefore, the first task in designing a digital loop filter is to design appropriate values of c1 and c2. When c1 and c2 meet When the system timing synchronization capture speed and anti-noise performance are better, but the calculation of division in FPGA is not convenient, and the decimal can only be expressed in the format of fixed-point numbers. Select c1=2 -14 , In this way, the integer power of 2 can be directly realized in FPGA by right shifting a certain number of bits, simplifying the calculation;

[0059] Input the timing error sequence e(k) into the loop filter with the system function F(z), and we get:

[0060] g(k)=e(k)*f(k)

[0061] Where g(k) is the output signal, f(k) is the inverse Z transform of F(z), * is the convolution symbol, and the output signal is connected to the interpolation controller for interpolation correction and the next round of testing and iteration;

[0062] The interpolation controller is implemented in the form of a numerically controlled oscillator (NCO). Its function is to generate a periodic interpolation enable signal according to the control word and calculate the interpolation base point m of each interpolation point. k and fractional interval μ k , passed to the interpolation filter module to generate interpolation sampling points: The update formula of NCO is expressed as:

[0063] η(m)=[η(m-1)-ω(m-1)]mod(-1) (8)

[0064] Where η(m) is the output of the NCO, ω(m) is the control word of the NCO, and is also the output of the loop filter;

[0065] When the timing error e(k) detected by the timing error detector converges to the set value, the final interpolation filter parameter m is determined. k With μ k Perform timed synchronization;

[0066] Since only the first two signals are used to estimate the timing error, for the following signals:

[0067]

[0068] After timing synchronization of the I and Q signals respectively, 32 channels of data for each of the I and Q channels are obtained, and 8 channels of data for each of the I and Q channels are obtained, and the optimal sampling point is captured as the output data.

[0069] Blind equalization is performed on the timing synchronization output to completely eliminate inter-symbol interference.

[0070] In digital receivers, multipath effects, channel fading, ADC in-band amplitude and phase inconsistencies, and timing synchronization sampling deviations can all cause inter-symbol interference (ISI). This seriously affects the decision of code elements in the receiver and the improvement of data transmission rates. To completely eliminate ISI, equalization technology is required, so the signal needs to be equalized after timing synchronization.

[0071] Based on the traditional CADAMA blind equalization algorithm, the present invention designs a principle block diagram of a high-speed parallel blind equalizer, as shown in the attached figure. Figure 3 shown.

[0072] The entire principle block diagram mainly consists of three parts: equalizer filtering, error calculation and tap coefficient update.

[0073] The input signal first enters the equalizer filter module to obtain the equalized output. Only the first path is used to calculate the error. After the error is obtained, the input signal is delayed for a certain period of time. This delay is a preset value and remains unchanged during the entire equalization process to ensure that the timing of the input signal and the equalization error are consistent. The two parts complete the update of the tap coefficient together and send the updated tap coefficient to the filter module for use:

[0074] When the equalizer filter module is processed, the formula is as follows:

[0075] y(k+i)=W T (k+i)X(k+i)≈W T (k)X(k+i)(9)

[0076] Among them, X(k) is the input before filtering, y(k) is the output after filtering, and W T (k) is the matrix transpose of the filter tap coefficients; after obtaining the equalized output, only the first path is used, denoted as y n ; Calculate the error; Because there are three concentric circles in the 16QAM constellation diagram, with radii denoted as R1, R2, and R3 respectively, the radius of the standard point should be determined by setting the threshold value; let the inner circle threshold be Th1 = (R1 + R2) / 2, and the outer circle threshold be Th2 = (R2 + R3) / 2, the calculation formula of the equalization error is expressed as

[0077]

[0078] By judging |y n | 2 The matching expected radius is selected according to the range of the balancing, which can reduce the balancing error and improve the balancing speed and accuracy.

[0079] Finally, the tap coefficients are updated using an 8-way parallel structure. The 8-way parallel signals are input into the equalizer to complete equalization and generate output signals. The first output signal is extracted for equalization error calculation and equalizer correction. At the same time, the delay d introduced by the coefficient update needs to be considered. Assuming that the product of the error coefficient and the input data remains almost unchanged during the 8×d updates, the update formula for the tap coefficients is obtained through the delay approximation technique and the summation approximation technique of the relaxed advance transform technique:

[0080]

[0081] μ is set to 2 -10 ≈0.001;

[0082] The tap coefficients of the equalization filter are continuously updated according to the calculated equalization error, so that the subsequent equalization results are more accurate;

[0083] After each update is completed, the tap coefficients are used to process each signal until the signal reception is completed. After blind equalization, the I channel and Q channel still have 8 channels of data each, eliminating inter-symbol interference.

[0084] Carrier synchronization is performed on the output of blind equalization to eliminate frequency and phase deviations in the signal.

[0085] In a digital receiver, when the transmitted and received carrier frequencies are inconsistent or the Doppler effect is present, the received signal will have a certain frequency and phase deviation from the transmitting signal, making it difficult for the receiver to correctly judge and decode the signal. This requires a carrier synchronization module. Carrier synchronization compensates the carrier frequency and phase at the receiving end, ensuring that the local oscillator at the receiving end is synchronized with the carrier frequency and phase at the transmitting end.

[0086] Based on the traditional PFD carrier synchronization algorithm, the present invention designs a principle block diagram of high-speed parallel carrier synchronization, as shown in the attached figure. Figure 4 shown.

[0087] The input signal is first power-detected. If it is within the window, it is sent to the phase detector to compare with the standard constellation point to calculate the phase difference. If it is outside the window, it is sent to the frequency detector. The output of the frequency and phase detector is then sent to the loop filter and NCO module to be compensated with the delayed input signal to obtain the carrier synchronization output:

[0088] Since the output of the phase detector or frequency detector is connected to the loop filter module, the error estimation is performed in the phase domain. The phase detector is divided into two parts: inverse tangent calculation and phase difference calculation:

[0089] The function of the inverse tangent module is to obtain the phase of the constellation points within the window and obtain the phase of the eight standard corner points for use by the phase difference calculation module. In MATLAB, the calculation of the inverse tangent can directly call the atan2 function. In FPGA, it is usually implemented using the Cordic IP core. However, the calculation of the Arctan value by the Cordic IP core will bring about a large resource occupation and high latency. Therefore, after researching the literature, the present invention uses the following Arctan approximation formula:

[0090]

[0091] Here, x is the quotient of the imaginary and real parts of the constellation point, that is, the tangent value of the constellation point, so arctan(x) is the phase of the constellation point; the imaginary part of the constellation point takes the Q-channel data, and the real part of the constellation point takes the I-channel data; the phase difference is the constellation point closest to the constellation point to be detected on the standard constellation diagram, and the current constellation point is determined to be the closest constellation point: the signal values of the I-channel and Q-channel of the standard constellation point are used to replace the values after blind equalization, thus obtaining the standard signal point after carrier synchronization;

[0092] In an embodiment of the present application, the method for implementing the formula in FPGA is to use a state machine. The present invention proposes an implementation method and designs a state machine conversion relationship, which is specifically as follows: ① Idle state: In this state, wait for the input of calculation data, and jump to the next state after the data is input; ② Division state: In this state, calculate the ratio of the imaginary part to the real part of the input constellation point, that is, x in the formula, and the division calculation is implemented by calling the divider; ③ Multiplication state 1: Calculate the multiplication results of πx / 4, x(|x|-1), and 0.0663|x| in the formula in sequence, and the multiplication calculation is implemented by calling the multiplier; ④ Multiplication state 2: Calculate the multiplication result of x(|x|-1)×(0.2447+0.0663|x|) in the formula; ⑤ Result state: Calculate the final result of the formula, obtain the output of the inverse tangent, and jump back to the idle state.

[0093] The loop filter and NCO are the same as those in timing synchronization and will not be repeated here;

[0094] After carrier synchronization, the I and Q channels still contain 8 channels of data each, but the frequency deviation and phase deviation in the signal are completely eliminated.

[0095] The carrier synchronization output is subjected to frame synchronization and 16QAM hard decision to obtain the final output of the receiver.

[0096] First, the frame header sequence is used to synchronize the output of the carrier synchronization. Through frame synchronization, the signal is divided into several consecutive frames of data. Finally, the decision decoding is completed to complete the inverse transformation of the constellation mapping and obtain the transmitted 01 bit stream.

[0097] Before generating the transmission signal, the transmitter adds a 32-bit hexadecimal sequence, known as the frame header sequence, to the front of the data frame. The receiver then uses the same frame header for correlation calculations. If the complete frame header is detected, the maximum correlation value should be 32. The correlation values at other positions are smaller, resulting in a correlation peak of 32. This method is called the correlation peak detection algorithm.

[0098] After frame synchronization is completed, the undemodulated 16QAM signal is obtained. Next, the 16QAM demapping hard decision is performed according to the 16QAM mapping method. The 8-channel I and Q data are mapped into bit data. Taking any one channel of I / Q data as an example, the mapping process to obtain a 4-bit signal is as follows, where 2A and 0 correspond to the two scale values in the 16QAM constellation diagram.

[0099]

[0100] A parallel receiving system for high-speed 16QAM data demodulation, comprising:

[0101] High-speed ADC, used to sample the received IF 16QAM data and obtain four-channel signals using the ADC's serial-to-parallel conversion function;

[0102] The serial-to-parallel conversion module uses a dedicated FPGA serial-to-parallel converter to convert 4-channel signals into 32-channel parallel signals at a conversion rate of 1:8;

[0103] The parallel receiving and processing module is used to obtain 16 baseband signals of I and Q channels through digital orthogonal down-conversion of 32 parallel signals, and then perform matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization and 16QAM decision decoding in sequence to complete parallel reception.

[0104] The above is a specific embodiment of the present invention. It should be pointed out that those skilled in the art can clearly understand that the above embodiments cited by the present invention are only used to illustrate and verify the rationality and feasibility of the method, and are not used to limit the inventive method. Although the present invention can be effectively illustrated and described by the embodiments, there are many variations in the present invention without departing from the spirit of the present invention. Without departing from the spirit and essence of the inventive method, those skilled in the art can make various corresponding changes or deformations according to the inventive method, but these corresponding changes or deformations all fall within the scope of protection required by the inventive method.

Claims

1. A parallel receiving method for high-speed 16QAM data demodulation, characterized by: The following steps are involved: S1. Use a high-speed ADC to sample the received 16QAM IF data and use the ADC's serial-to-parallel conversion function to generate four signals. S2. Use the FPGA-specific serial-to-parallel converter to convert the 4-channel signal into 32 parallel signals at a conversion rate of 1:

8. S3. In the FPGA, the 32 parallel signals are digitally orthogonally down-converted to obtain 16 baseband signals each for the I and Q channels. Matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization, and 16QAM decision decoding are then performed in sequence to complete parallel reception.

2. The parallel receiving method for high-speed 16QAM data demodulation according to claim 1, characterized in that: The received intermediate frequency 16QAM data intermediate frequency frequency f c 、High speed ADC with f s The sampling rate is f s is the intermediate frequency f c four times.

3. The parallel receiving method for high-speed 16QAM data demodulation according to claim 1, wherein: The step S3 comprises: The 32-channel parallel signal is digitally orthogonally down-converted to obtain 16-channel I and 16-channel Q baseband signals; Perform matched filtering on the output of digital orthogonal down-conversion to amplify the signal-to-noise ratio of the signal; Synchronize the output of the matched filter to capture the best sampling point; Blind equalization is performed on the output of timing synchronization to completely eliminate inter-symbol interference; Carrier synchronization is performed on the output of blind equalization to eliminate frequency and phase deviations in the signal; Frame synchronization and 16QAM hard decision are performed on the carrier synchronization output to obtain the final output.

4. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The method of performing digital orthogonal down-conversion on the 32 parallel signals to obtain 16 baseband signals of I and Q, includes: The baseband signal after digital orthogonal down conversion is expressed as: Where n is the serial number of the discrete digital signal, S(n) is the nth parallel signal, n = 1, 2, ..., 31; I(n) and Q(n) are the in-phase component and quadrature component of the n-th parallel signal; There is no need to generate a local oscillator signal. Instead, the I and Q baseband signals can be obtained by performing odd-even alternating extraction and inversion on S(n), which can be expressed as: After the mixer-free digital orthogonal down-conversion, the 32-channel input data is converted into 16 channels of I and Q data, completing the down-conversion task of the intermediate frequency signal.

5. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The method of performing matched filtering on the output of the digital orthogonal down-conversion to amplify the signal-to-noise ratio of the signal includes: The transfer function H(ω) of the raised cosine roll-off filter is determined as: Where ω is the digital angular frequency in the filter transfer function, T s is the sampling period of the code element, α is the roll-off coefficient of the raised cosine roll-off filter, and its value range is [0,1]; Assuming that the channel is ideal, in order to ensure that the system has the minimum bit error rate under the condition of additive white Gaussian noise, the transfer function H of the matched filter is R (ω) is expressed as For H R (ω) Inverse Fourier transform, get its impulse response h(t), h(t) according to T s Sampling is performed to obtain its discrete impulse response h(n); Convolve the input signal x(n) to get the output signal Where x(n) represents the input signal, y(n) represents the output signal, l1 is the length of the input signal, l2 is the length of the raised cosine roll-off filter from the impulse response, and h(nm) is 0 when the value of nm is not in the range of 0 to l2-1. In a high-speed receiver implemented on an FPGA, h(nm) cannot be calculated in real time. Therefore, a square-root raised cosine filter is designed using a lookup table, given a given roll-off coefficient α. The value of h(t) is stored in ROM in advance. During calculation, the value of nm is calculated and then used as an index to retrieve the corresponding h(nm) from the ROM for calculation. The raised cosine matched filter operation performs FIR calculations through 2x oversampling to achieve higher accuracy. After the raised cosine, the I / Q channels are 32 each. After matched filtering, the 16-channel I and Q data are converted into 32-channel I and Q signals, which amplifies the signal-to-noise ratio.

6. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The method of performing timing synchronization on the output of the matched filter to capture the optimal sampling point includes: The 32 signals obtained by matched filtering are used as input. Every 4 input signals x(4k), x(4k+1), x(4k+2), and x(4k+3) are interpolated through the filter to obtain an optimal sampling point y(k), where k = 0, 1, 2...

7. 8 outputs are obtained from the 32 parallel inputs. Before timing synchronization, the timing error needs to be estimated: In order to improve the speed of timing synchronization, the first two of the eight paths and the middle point are selected to estimate the timing error. The estimated error is then sent to the loop filter and interpolation controller module, and the output is m k and μ k To control the interpolation position, where: m k It is called the interpolation base point, which represents the interpolation position of the kth interpolation relative to the input sampling point, μ k It is called fractional interval, which represents the ratio of the interval between the interpolation point and the input sampling point to the input period. The interpolation filter uses the form of cubic interpolation filter. The Farrow structure is used to implement the cubic interpolation filter. Specifically: In the timing error detection algorithm, in order to adapt to the high-order modulation mode of 16QAM, the following form is proposed Among them, y0(k) represents the first of two adjacent sampling points, and y1(k) represents the second of two adjacent sampling points. Represents the middle sampling point between two sampling points; for the 32 parallel input signals, the first 8 signals are involved in the timing error detection, x(0)-x(3) represent the first 4 sampling points, x(4)-x(7) represent the last 4 sampling points, and the middle 4 sampling points are x(2)-x(5); these three groups of signals are output as sequences y0, y1, Participate in the calculation of formula (6); sgn is the sign function, when the value of the independent variable is negative, the result is -1, when it is positive, the result is 1, and when it is zero, it is equal to 0; γ is the parameter affected by the raised cosine characteristic, which should be equal to the matched filter at T s / 2; e(k) in formula (6) is the calculated timing error; After the estimated timing error is obtained, it is sent to the loop filter and interpolation controller in sequence; the loop filter adopts the form of a second-order ideal integral filter, and its digital system function can be expressed as Among them, τ1 and τ2 are time constants, and c1 and c2 are preset coefficients; Input the timing error sequence e(k) into the loop filter with the system function F(z), and we get: g(k)=e(k)*f(k) Where g(k) is the output signal, f(k) is the inverse Z transform of F(z), * is the convolution symbol, and the output signal is connected to the interpolation controller for interpolation correction and the next round of testing and iteration; The interpolation controller is implemented in the form of a numerically controlled oscillator (NCO). Its function is to generate a periodic interpolation enable signal according to the control word and calculate the interpolation base point m of each interpolation point. k and fractional interval μ k , passed to the interpolation filter module to generate interpolation sampling points: The update formula of NCO is expressed as η(m)=[η(m-1)-ω(m-1)]mod(-1) (8) Where η(m) is the output of the NCO, ω(m) is the control word of the NCO, and is also the output of the loop filter; When the timing error e(k) detected by the timing error detector converges to the set value, the final interpolation filter parameter m is determined. k With μ k Perform timed synchronization; Since only the first two signals are used to estimate the timing error, for the following signals: After timing synchronization of the I and Q signals respectively, 32 channels of data for each of the I and Q channels are obtained, and 8 channels of data for each of the I and Q channels are obtained, and the optimal sampling point is captured as the output data.

7. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The blind equalization of the timing synchronization output to completely eliminate inter-symbol interference includes: The input signal first enters the equalizer filter module to obtain the equalized output. Only the first path is used to calculate the error. After the error is obtained, the input signal is delayed for a certain period of time. This delay is a preset value and remains unchanged during the entire equalization process to ensure that the timing of the input signal and the equalization error are consistent. The two parts complete the update of the tap coefficient together and send the updated tap coefficient to the filter module for use: When the equalizer filter module is processed, the formula is as follows: y(k+i)=W T (k+i)X(k+i)≈W T (k)X(k+i)(9) Among them, X(k) is the input before filtering, y(k) is the output after filtering, and W T (k) is the matrix transpose of the filter tap coefficients; after obtaining the equalized output, only the first path is used, denoted as y n ; Calculate the error; Because there are three concentric circles in the 16QAM constellation diagram, with radii denoted as R1, R2, and R3 respectively, the radius of the standard point should be determined by setting the threshold value; let the inner circle threshold be Th1 = (R1 + R2) / 2, and the outer circle threshold be Th2 = (R2 + R3) / 2, the calculation formula of the equalization error is expressed as By judging |y n | 2 The matching expected radius is selected according to the range of the balancing, which can reduce the balancing error and improve the balancing speed and accuracy. Finally, the tap coefficients are updated using an 8-way parallel structure. The 8-way parallel signals are input into the equalizer to complete equalization and generate output signals. The first output signal is extracted for equalization error calculation and equalizer correction. At the same time, the delay d introduced by the coefficient update needs to be considered. Assuming that the product of the error coefficient and the input data remains almost unchanged during the 8×d updates, the update formula for the tap coefficients is obtained through the delay approximation technique and the summation approximation technique of the relaxed advance transform technique: After each update is completed, the tap coefficients are used to process each signal until the signal reception is completed. After blind equalization, the I channel and Q channel still have 8 channels of data each, eliminating inter-symbol interference.

8. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The step of performing carrier synchronization on the output of the blind equalization to eliminate frequency deviation and phase deviation in the signal includes: The input signal is first power-detected. If it is within the window, it is sent to the phase detector to compare with the standard constellation point to calculate the phase difference. If it is outside the window, it is sent to the frequency detector. The output of the frequency and phase detector is then sent to the loop filter and NCO module to be compensated with the delayed input signal to obtain the carrier synchronization output: Since the output of the phase detector or frequency detector is connected to the loop filter module, the error estimation is performed in the phase domain. The phase detector is divided into two parts: inverse tangent calculation and phase difference calculation: The function of the inverse tangent module is to obtain the phase of the constellation points in the window and obtain the phase of the 8 standard corner points for use by the phase difference calculation module. The following Arctan approximation formula is used Here, x is the quotient of the imaginary and real parts of the constellation point, that is, the tangent value of the constellation point, so arctan(x) is the phase of the constellation point; the imaginary part of the constellation point takes the Q-channel data, and the real part of the constellation point takes the I-channel data; the phase difference is the constellation point closest to the constellation point to be detected on the standard constellation diagram, and the current constellation point is determined to be the closest constellation point: the signal values of the I-channel and Q-channel of the standard constellation point are used to replace the values after blind equalization, thus obtaining the standard signal point after carrier synchronization; The loop filter and NCO are the same as those in timing synchronization; After carrier synchronization, the I and Q channels still contain 8 channels of data each, but the frequency deviation and phase deviation in the signal are completely eliminated.

9. The parallel receiving method for high-speed 16QAM data demodulation according to claim 3, characterized in that: include: The carrier synchronization output is subjected to frame synchronization and 16QAM hard decision to obtain the final output: First, the frame header sequence is used to synchronize the output of the carrier synchronization. Through frame synchronization, the signal is divided into several consecutive frames of data. Finally, the decision decoding is completed to complete the inverse transformation of the constellation mapping and obtain the transmitted 01 bit stream. Before generating the transmission signal, the transmitter adds a 32-bit hexadecimal sequence, known as the frame header sequence, to the front of the data frame. The receiver then uses the same frame header for correlation calculations. If the complete frame header is detected, the maximum correlation value should be 32. The correlation values at other positions are smaller, resulting in a correlation peak of 32. This method is called the correlation peak detection algorithm. After frame synchronization is completed, the undemodulated 16QAM signal is obtained. Next, the 16QAM demapping hard decision is performed according to the 16QAM mapping method. The 8-channel I and Q data are mapped into bit data. Taking any one channel of I / Q data as an example, the mapping process to obtain a 4-bit signal is as follows, where 2A and 0 correspond to the two scale values in the 16QAM constellation diagram.

10. A parallel receiving system for high-speed 16QAM data demodulation, using the method according to any one of claims 1 to 9, characterized in that: include: High-speed ADC, used to sample the received IF 16QAM data and obtain four-channel signals using the ADC's serial-to-parallel conversion function; The serial-to-parallel conversion module uses a dedicated FPGA serial-to-parallel converter to convert 4-channel signals into 32-channel parallel signals at a conversion rate of 1:8; The parallel receiving and processing module is used to obtain 16 baseband signals of I and Q channels through digital orthogonal down-conversion of 32 parallel signals, and then perform matched filtering, timing synchronization, blind equalization, carrier synchronization, frame synchronization and 16QAM decision decoding in sequence to complete parallel reception.

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