Wafer cutting method
By bonding quartz or sapphire wafers as hard masks on the front and back of the wafer and performing etching and cutting, the problem of high difficulty in growing thick masks is solved, and the wafer cutting efficiency and quality is improved. It is suitable for a variety of wafer types.
Patent Information
- Application Number
- CN202510574363.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-05
- Filing Date
- 2025-05-06
- Publication Date
- 2025-08-08
AI Technical Summary
The existing wafer cutting methods have problems of high difficulty and increased internal stress when growing thick mask materials, resulting in low cutting efficiency and poor quality, especially when cutting wafers with thicknesses greater than 50 μm.
Quartz wafers or sapphire wafers are used as hard masks, and they are bonded to the front and back sides of the wafers, forming a cutting path through etching, and removing the hard mask through dry etching to achieve wafer separation.
Improves the efficiency and quality of wafer cutting, reduces the growth time of hard masks, which can be reused and are suitable for different types of wafer cutting.
Smart Images
Figure CN120453234A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a wafer cutting method. Background Art
[0002] The current methods for cutting wafers into independent bare cores are: ① Blade cutting. This technology uses a high-speed rotating abrasive blade to cut along the cutting channel. The blade tip is generally made of diamond. It is suitable for cutting wafers of various materials, has a fast cutting speed, and has been widely used. However, like any mechanical cutting method, blade cutting relies on the physical removal of material, which may cause the bare core to break and crack, resulting in product damage and reduced yield. ② Laser ablation cutting. This technology focuses the laser beam on the surface of the material. When the input laser energy is greater than the ablation threshold of the material, the material is melted, evaporated or decomposed and then removed. However, after cooling, the evaporated material gas is easily redeposited on the sides and surface of the cutting path to form a heat-affected zone such as a recast layer, affecting the quality of the bare core. If a bare core to wafer bonding process is required later, the yield of the process will also be affected. ③ Laser invisible cutting. This technology focuses the laser inside the material. After absorbing the laser energy, the material vaporizes to form micro-nano channels. After multiple laser scans, an internal modified layer is formed. Finally, a splitting process is used to expand the cracks between the multiple modified layers inside the wafer to achieve wafer cutting. The thermal effect is small and the edge collapse is less. However, for epitaxial wafers with complex epitaxial layers, the light absorption of the epitaxial layer will cause the laser hidden cutting to fail. ④ Plasma cutting. This technology deposits a layer of hard mask material on the surface of the wafer and prepares the cutting channel. Then, the material in the cutting channel is removed by dry etching. It can process small-sized bare cores and thin wafers (thickness 20μm to 50μm) faster, cleaner, and without damaging the bare core.
[0003] However, in current plasma cutting technology, the etching selectivity ratio of wafer material to hard mask material is generally between 10:1 or 20:1. That is to say, a wafer with a thickness of 50μm needs to grow a hard mask material with a thickness of 5μm or 2.5μm or more. If thicker wafers (greater than 50μm) need to be cut, a thicker hard mask material needs to be grown. However, the difficulty of growing thicker hard mask materials increases. In addition, when growing thicker hard mask materials, the different lattice constants of the hard mask material and the wafer material will lead to an increase in internal stress, resulting in problems with growth quality.
[0004] Therefore, it is of great significance to develop new wafer cutting methods. Summary of the Invention
[0005] The purpose of the present invention is to overcome the problems existing in the above-mentioned prior art and provide a wafer cutting method.
[0006] The present invention is achieved through the following technical solutions:
[0007] The present invention provides a wafer cutting method, comprising the following steps:
[0008] (1) Bonding a hard mask A to the front side of a wafer to be cut, and bonding a hard mask B to the back side of the wafer to be cut; etching cutting paths on the hard mask A and the hard mask B; the hard mask A and the hard mask B independently include at least one of a quartz wafer and a sapphire wafer;
[0009] (2) Etching the wafer to be cut through the cutting path to remove the hard mask A and the hard mask B to obtain a cut bare core.
[0010] In the cutting method of the present invention, general wafer materials such as quartz wafers, sapphire wafers, etc. are respectively bonded to the upper and lower surfaces of the wafer to be cut to serve as hard masks for plasma cutting, and then the bonded three-layer stacked wafers are etched and cut through the cutting path, and then the wafers and the hard masks are debonded to obtain separated bare cores. Since quartz wafers, sapphire wafers, etc. can be obtained by general wafer manufacturing processes in the semiconductor manufacturing industry, the manufacturing process is mature and the thickness can be controlled, a thicker mask can be obtained by directly bonding them to the wafer to be cut. The bonding process does not have the quality problems of the material growth process, and the time for direct wafer bonding is very short, less than the time for growing the material. After cutting, after cleaning, it can be reused in the cutting process of the next wafer. This can effectively solve the problem of long time and difficulty in growing thick masks on current wafers, while improving the efficiency of wafer cutting.
[0011] Preferably, in step (1), the thickness of the wafer to be cut is not less than 50 μm.
[0012] The wafer dicing method of the present invention can dicing thicker wafers without growing a thicker hard mask, thereby improving process efficiency and dicing quality. Furthermore, the present invention is not limited to the type of wafer to be diced; for example, epitaxial wafers and ordinary wafer substrates are all suitable for the dicing method of the present invention.
[0013] In a specific embodiment of the present invention, the thickness of the wafer to be cut is 60 μm-120 μm.
[0014] Preferably, in step (1), the hard mask A and the hard mask B are quartz wafers.
[0015] Quartz wafers are less expensive than sapphire wafers.
[0016] In the present invention, hard masks A and B are preferably made of the same wafer type, and are generally different from the type of wafer to be cut, to facilitate selective etching and reduce hard mask consumption. Hard masks A and B can also be made of different wafer types to achieve the same process effect, but the consumption of hard masks A and B will differ due to different etching selectivities.
[0017] Preferably, in step (1), the bonding adopts wafer direct bonding technology.
[0018] Direct wafer bonding can achieve a thick hard mask on the wafer to be cut. Since it is temporary bonding, the required bonding energy is not high, so the bonding time is short. In addition, the preparation of the cutting lanes on the wafer serving as the hard mask is an independent process, which can be mass-produced and stored waiting for use in the cutting process. After one cutting, the remaining thickness of the hard mask wafer can also be used in the next process within the usable range, thereby improving the wafer cutting efficiency.
[0019] Specifically, using direct wafer bonding technology, the hard mask A and the front side of the wafer to be cut are first plasma activated, and then megasonic cleaning is performed. The hard mask A is then bonded to the front side of the wafer to be cut, and aligned by the positioning edge of the wafer to obtain a two-layer stacked wafer. Similarly, using direct wafer bonding technology, the hard mask B and the back side of the wafer to be cut are plasma activated. The plasma activation power of the hard mask B may be lower than the power of the hard mask A. Then megasonic cleaning is performed, and the hard mask B is bonded to the back side of the wafer to be cut. The positioning edge of the wafer is used to obtain a three-layer stacked wafer.
[0020] Preferably, in step (1), the cutting lines on the hard mask A or the cutting lines on the hard mask B are not closed figures, and the cutting lines on the hard mask A and the cutting lines on the hard mask B are combined to form a closed figure.
[0021] The cutting paths on the hard mask A or the cutting paths on the hard mask B are arranged according to the specific bare core arrangement required, and the distance between the cutting paths can be adjusted according to the size and distribution of the actual bare core, as long as it can be maintained that: there are open cutting paths on a single hard mask A or B, and a closed figure is formed when the hard masks A and B are combined, so that independent bare cores can be obtained after debonding.
[0022] Preferably, in step (1), the cutting lines on the hard mask A are horizontal cutting lines, and the cutting lines on the hard mask B are vertical cutting lines.
[0023] The cutting lines on the hard mask A or the cutting lines on the hard mask B can be adjusted according to the required closed figure. In order to simplify the preparation process, it is preferred that the cutting lines on the hard mask A are cutting lines in the horizontal direction of the closed figure, and the cutting lines on the hard mask B are cutting lines in the vertical direction of the closed figure.
[0024] In a specific embodiment of the present invention, the cutting lines on the hard mask A and the cutting lines on the hard mask B are perpendicular to each other, the cutting lines on the hard mask A are horizontal cutting lines, and the cutting lines on the hard mask B are vertical cutting lines.
[0025] In a specific embodiment of the present invention, horizontal cutting paths parallel to each other can be set on the hard mask A, and vertical cutting paths parallel to each other can be set on the hard mask B, and the length of the cutting paths is distanced from the edges of the hard masks A and B to ensure the integrity of the wafer, and more preferably the cutting paths are symmetrical; subsequently, the three-layer stacked wafer after bonding is etched and cut, and after the material in the horizontal cutting paths is etched, the material in the vertical cutting paths is etched in turn. After all etching is completed, the hard mask and the wafer are debonded from each other by mechanical peeling to obtain a separated bare core; and the hard masks A and B with the cutting paths can be cleaned and reused next time.
[0026] Preferably, in the step (1), the method of etching cutting lines on the hard mask A and the hard mask B includes laser induced deep etching technology.
[0027] Laser-induced deep etching (LIDE) is an advanced micro-nanofabrication technology that combines laser modification and wet etching. First, a laser is used to create a modified area for the cut street on a hard mask. Then, a wet etching process is used to etch the modified area. Conventionally, different wet chemical solutions are used to expose the cut street, depending on the type of hard mask A and hard mask B.
[0028] Preferably, in step (1), the ratio of the thickness of the hard mask A plus the thickness of the wafer to be cut to the width of the cutting path on the hard mask A does not exceed 50; the ratio of the thickness of the hard mask B plus the thickness of the wafer to be cut to the width of the cutting path on the hard mask B does not exceed 50.
[0029] In the etching process, there's a correlation between etch depth and etch width. As etch depth increases in high-aspect-ratio structures, reactants become more difficult to penetrate and products become less likely to evaporate. When the etch depth exceeds a certain critical value, the etch rate slows or even stops. Therefore, the present invention achieves good etching results by ensuring the ratio of the width of the cutting street to the thickness of the hard masks A and B plus the thickness of the wafer to be cut falls within the aforementioned range, enabling efficient wafer cutting.
[0030] Preferably, in step (2), the etching is dry etching; more specifically, the dry etching includes inductively coupled reactive ion etching (ICPRIE).
[0031] Specifically, in step (2), the wafer to be cut is first etched through the cutting path on the hard mask A, and then the wafer to be cut is etched through the cutting path on the hard mask B, so that the wafer to be cut is separated to obtain a bare core.
[0032] Preferably, in step (2), the removal method includes at least one of heating and mechanical stripping.
[0033] In the cutting method of the present invention, two hard mask wafers in the three-layer stacked wafer can be released by simple heating or mechanical peeling to obtain a bare core after the wafer is cut.
[0034] The present invention has the following beneficial effects: by independently preparing the hard mask required for plasma dicing and bonding the hard mask to the wafer to be diced via direct wafer bonding, the present invention increases the hard mask thickness required for plasma dicing of the wafer to be diced, thereby increasing the thickness of the wafer required for plasma dicing. The bonding process time is also shorter than the material growth process time. Furthermore, the hard mask can be used multiple times, improving process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 Schematic diagram of the process of the wafer cutting method of Example 1;
[0036] Figure 2 Schematic diagram of preparing cutting streets by laser-induced deep etching of a quartz wafer in the wafer cutting method of Example 1;
[0037] Figure 3 Schematic diagram of direct wafer bonding, dry etching, and debonding in the wafer dicing method of Example 1;
[0038] Figure 4 Schematic diagram of direct wafer bonding, dry etching, and debonding in the wafer cutting method of Example 2. DETAILED DESCRIPTION
[0039] To better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below in conjunction with specific embodiments. Those skilled in the art should understand that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0040] Unless otherwise specified, the experimental methods used in the examples are conventional methods; the materials, reagents, etc. used are all available from commercial sources unless otherwise specified.
[0041] Example 1
[0042] The flow chart of the wafer cutting method of this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0043] (1) Using laser-induced deep etching technology, a laser is used to scan the area where a cutting path is required in a quartz wafer 1 with a thickness of 100 μm to form a modified area. A total of 7 horizontal cutting paths are scanned to form a modified area. The cutting path width is 100 μm, and the cutting path length is a certain distance away from the edge of the wafer to ensure the integrity of the wafer and the symmetry of the cutting path. Then, a BOE solution is used to etch away the laser-modified area in the quartz wafer 1 to form a cutting path;
[0044] Using the same method, 7 vertical cutting streets with a width of 100 μm are etched on the quartz wafer 2 with the same thickness of 100 μm. The etching schematic diagram is shown in FIG. Figure 2 As shown;
[0045] Utilize direct wafer bonding technology, the quartz wafers 1, 2 with cutting streets are bonded to the InP epitaxial wafer or GaAs epitaxial wafer to be cut of 60 μm thickness (the epitaxial layer material of InP epitaxial wafer can be AlInP, GaInP, InGaAs, and the epitaxial layer material of GaAs epitaxial wafer can be AlGaAs, InGaAs); Quartz wafers 1, 2 and epitaxial wafer have been polished on both sides in advance, first, the front side of quartz wafer 1 (hard mask A) and the front side of epitaxial wafer are respectively subjected to O2 plasma activation, 60W, 60s, and then the front sides of the two wafers are cleaned using a megasonic cleaning process to remove particles and increase water molecules, and then the quartz wafer 1 and the epitaxial wafer are placed in a bonding device, the two wafers are aligned by the wafer positioning edge, and then a pressure of 100N is applied under vacuum at room temperature for 5 minutes to bond the two wafers face to face to obtain a two-layer stacked wafer;
[0046] Next, the front side of quartz wafer 2 (hard mask B) and the epitaxial wafer surface in the two-layer stacked wafer (i.e., the back side of the individual epitaxial wafers) were activated with O2 plasma at 30W for 60s, and then the surfaces were cleaned using a megasonic cleaning process. The quartz wafer 2 and the two-layer stacked wafer were then placed in a bonding machine and aligned using the wafer positioning edges. A pressure of 100N was then applied under vacuum at room temperature for 5 minutes to bond the two-layer stacked wafer to the quartz wafer 2, ultimately forming a three-layer stacked wafer of quartz-epitaxial wafer-quartz.
[0047] (2) After obtaining the above-mentioned three-layer stacked wafer, the epitaxial wafer material in the cutting path that is not protected by the hard masks A and B in the three-layer stacked wafer is etched away by a dry etching process; a gas with a Cl2:CH4:H2 ratio of 5:8:7 is used to etch the InP epitaxial material at an etching rate of about 20 nm / s; or a gas with a SiCl4:Ar ratio of 15:5 is used to etch the GaAs epitaxial material at an etching rate of about 20 nm / s, and the etching process is continued for 50 minutes. After the material in the horizontal cutting path is etched on the front side of the three-layer stacked wafer, the three-layer stacked wafer is turned over and etched for another 50 minutes to complete the etching of the material in the vertical cutting path;
[0048] After the plasma cutting process is completed, the quartz wafer 2 with weaker bonding force is first released from the back of the three-layer stacked wafer by heating to 70°C and mechanically peeling, and then the quartz wafer 1 is released from the two-layer stacked wafer. Finally, the epitaxial wafer forms a separated bare core.
[0049] Example 2
[0050] The flow chart of the wafer cutting method of this embodiment is as follows: Figure 4 As shown, the specific steps include:
[0051] (1) Using laser-induced deep etching technology, a laser is used to scan a sapphire wafer 1 with a thickness of 200 μm where a cutting path is required to form a modified area, and a modified area of a horizontal cutting path of a hexagonal bare core is scanned out. The cutting path width is 100 μm, and the cutting path length is a certain distance away from the edge of the wafer to ensure the integrity of the wafer and the symmetry of the cutting path. Then, a mixed solution of concentrated sulfuric acid and concentrated phosphoric acid is used to etch away the laser-modified area in the sapphire wafer 1 at 200-300°C to form a cutting path;
[0052] Using the same method, a sapphire wafer 2 with the same thickness of 200 μm is etched to form vertical scribe lines of hexagonal bare cores with a scribe line width of 100 μm.
[0053] Utilize direct wafer bonding technology to bond the above-mentioned sapphire wafers 1 and 2 with cutting streets to a 120 μm thick InP epitaxial wafer or a GaAs epitaxial wafer to be cut (the epitaxial layer material of the InP epitaxial wafer can be AlInP, GaInP, InGaAs, and the epitaxial layer material of the GaAs epitaxial wafer can be AlGaAs, InGaAs); the sapphire wafers 1 and 2 and the epitaxial wafer have been polished on both sides in advance, first, the front side of the sapphire wafer 1 (hard mask A) and the front side of the epitaxial wafer are respectively activated by O2 plasma at 60W for 60s, and then the front sides of the two wafers are cleaned using a megasonic cleaning process to remove particles and increase water molecules, and then the sapphire wafer 1 and the epitaxial wafer are placed in a bonding device, the two wafers are aligned by the wafer positioning edge, and then a pressure of 100N is applied under vacuum at room temperature for 5 minutes to bond the two wafers face to face to obtain a two-layer stacked wafer;
[0054] Next, the front side of sapphire wafer 2 (hard mask B) and the epitaxial wafer surface in the two-layer stacked wafer (i.e., the back side of a single epitaxial wafer) were activated with O2 plasma at 30W for 60s, and then the surfaces were cleaned using a megasonic cleaning process. The sapphire wafer 2 and the two-layer stacked wafer were then placed in a bonding device and aligned using the wafer positioning edges. A pressure of 100N was then applied at room temperature under vacuum for 5 minutes to bond the two-layer stacked wafer to the sapphire wafer 2, ultimately forming a three-layer stacked wafer of sapphire-epitaxial-sapphire.
[0055] (2) After obtaining the above-mentioned three-layer stacked wafer, the epitaxial wafer material in the cutting path that is not protected by the hard masks A and B in the three-layer stacked wafer is etched away by a dry etching process; a gas with a Cl2:CH4:H2 ratio of 5:8:7 is used to etch the InP epitaxial material at an etching rate of about 20 nm / s; or a gas with a SiCl4:Ar ratio of 15:5 is used to etch the GaAs epitaxial material at an etching rate of about 20 nm / s, and the etching process is continued for 100 minutes. After the material in the horizontal cutting path is etched on the front side of the three-layer stacked wafer, the three-layer stacked wafer is turned over and etched for another 100 minutes to complete the etching of the material in the vertical cutting path;
[0056] After the above-mentioned plasma cutting process is completed, the sapphire wafer 2 with weaker bonding force is first released from the back of the three-layer stacked wafer by heating to 70°C and mechanically peeling, and then the sapphire wafer 1 is released from the two-layer stacked wafer. Finally, the epitaxial wafer forms a separated bare core.
[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the essence and scope of the technical solutions of the present invention.
Claims
1. A wafer cutting method, characterized in that: The following steps are involved: (1) Bonding a hard mask A to the front side of a wafer to be cut, and bonding a hard mask B to the back side of the wafer to be cut; etching cutting paths on the hard mask A and the hard mask B; the hard mask A and the hard mask B independently include at least one of a quartz wafer and a sapphire wafer; (2) Etching the wafer to be cut through the cutting path to remove the hard mask A and the hard mask B to obtain a cut bare core.
2. The wafer cutting method according to claim 1, wherein: In the step (1), the thickness of the wafer to be cut is not less than 50 μm.
3. The wafer cutting method according to claim 1, wherein: In the step (1), the hard mask A and the hard mask B are quartz wafers.
4. The wafer cutting method according to claim 1, wherein: In the step (1), the bonding adopts wafer direct bonding technology.
5. The wafer cutting method according to claim 1, wherein: In the step (1), the cutting lines on the hard mask A or the cutting lines on the hard mask B are not closed figures, and the cutting lines on the hard mask A and the cutting lines on the hard mask B are combined to form a closed figure.
6. The wafer cutting method according to claim 5, characterized in that: In the step (1), the cutting lines on the hard mask A are horizontal cutting lines, and the cutting lines on the hard mask B are vertical cutting lines.
7. The wafer cutting method according to claim 1, wherein: In the step (1), the method of etching the cutting lines on the hard mask A and the hard mask B includes a laser induced deep etching technology.
8. The wafer cutting method according to claim 1, wherein: In step (1), the ratio of the thickness of the hard mask A plus the thickness of the wafer to be cut to the width of the cutting path on the hard mask A does not exceed 50; the ratio of the thickness of the hard mask B plus the thickness of the wafer to be cut to the width of the cutting path on the hard mask B does not exceed 50.
9. The wafer cutting method according to claim 1, wherein: In the step (2), the etching is dry etching.
10. The wafer cutting method according to claim 1, wherein: In the step (2), the removal method includes at least one of heating and mechanical stripping.