Overlay precision control method and system for feed-forward etching deviation

Abstract

The invention provides an overlay precision control method and system for feed-forward etching deviation, and belongs to the field of semiconductors. The overlay precision control method for feed-forward etching deviation comprises the following steps: providing an overlay mark; acquiring line widths Em and Em'of the overlay mark in the edge area of the aligned layer, and calculating to obtain Km = Em / Em '; measuring overlay error data of the alignment layer, and establishing a linear model of the overlay error along with the position of the surface of the wafer; acquiring the line width En and En'of the overlay mark in the edge area of any subsequent aligned layer, and calculating to obtain Kn = En / En '; and on the basis of the Km, the Kn and the linear model, performing pre-compensation correction on any subsequent alignment layer. According to the method, correction feedforward is provided for alignment layer overlay errors after photoetching according to the measurement result of the mark, the influence caused by asymmetry of the wafer edge area overlay mark due to the etching process is reduced, and the stability of the alignment layer overlay errors after photoetching is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a feedforward etching deviation overlay precision control method and system. Background Art

[0002] As process technology shrinks, overlay accuracy control is crucial for alignment between photolithography layers. Failure to achieve this alignment can lead to shorts or disconnects in electronic devices, severely impacting product yield. Diffraction-based overlay (DBO) measurement is widely used in advanced technology nodes, such as 28nm and below.

[0003] In advanced nodes, for DBO measurement, the bottom grating asymmetry (BGA) caused by etching is considered to be the main factor affecting the measurement accuracy. BGA affects the intensity difference between the positive and negative first-order diffraction light, resulting in poor measurement accuracy. In the self-alignment imaging process, the DBO mark located at the edge of the wafer is particularly affected by the BGA phenomenon due to the influence of the etching process, and its etching deviation is always not fixed. Since the current lithography uses ADI overlay accuracy measurement results as a compensation reference for the subsequent alignment layer, this type of non-fixed etching deviation becomes very difficult to control for the subsequent alignment layer.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a method and system for controlling overlay accuracy of feedforward etching deviation, so as to solve the problem that the non-fixed etching deviation becomes very difficult to control for the subsequent alignment layer.

[0006] In order to solve the above technical problems, the present invention provides a feedforward etching deviation overlay accuracy control method, comprising:

[0007] Providing an overlay mark, and forming the overlay mark on the original wafer as the overlay mark of the aligned layer;

[0008] Obtain the line widths Em and Em' of the overlay mark in the edge area of the aligned layer, and calculate Km=Em / Em';

[0009] Measure the overlay error data of the alignment layer and establish a linear model of the overlay error versus wafer surface position;

[0010] forming the overlay mark on a subsequent wafer as an overlay mark for a subsequent aligned layer;

[0011] Obtain the line widths En and En' of the overlay mark of any subsequent aligned layer edge region, and calculate Kn=En / En';

[0012] Based on Km, Kn and the linear model, any subsequent alignment layer is pre-corrected.

[0013] Preferably, providing an overlay mark and forming the overlay mark on the original wafer as the overlay mark of the aligned layer includes:

[0014] forming the overlay mark on the original wafer and forming a core shaft on the surface of the original wafer;

[0015] forming a sidewall around the mandrel by a self-alignment process;

[0016] The mandrel is removed, and the sidewalls on both sides of the mandrel serve as overlay marks of the aligned layer.

[0017] Preferably, the core shafts are evenly distributed along the transverse direction.

[0018] Preferably, the core shafts are evenly distributed along the longitudinal direction, and the core shafts are divided.

[0019] Preferably, the number of the core shafts is greater than or equal to 5.

[0020] Preferably, when manufacturing the mask, the overlay mark is placed close to the DBO overlay mark of the corresponding layer.

[0021] Preferably, the self-aligned imaging process includes SADP and SAOP.

[0022] Preferably, the pre-correction of any subsequent alignment layer based on Km, Kn and the linear model comprises:

[0023] Based on Km, Kn and the linear model, a pre-compensation correction is performed on the edge overlay error feature quantity of any subsequent alignment layer feedforward λ*(Kn / Km) times, where λ is a constant.

[0024] Preferably, λ is determined by the maintenance cycle of the etching machine.

[0025] Based on the same inventive concept, the present invention also provides an overlay accuracy control system for feedforward etching deviation, comprising:

[0026] an acquisition module, configured to acquire line widths Em and Em' of the overlay mark in the edge region of the aligned layer; acquire line widths En and En' of the overlay mark in any subsequent edge region of the aligned layer, and calculate Kn=En / En';

[0027] The logic operation module is used to calculate Km=Em / Em'; measure the overlay error data of the alignment layer and establish a linear model of the overlay error with the wafer surface position; calculate Kn=En / En'; based on Km, Kn and the linear model, pre-compensate and correct any subsequent alignment layer.

[0028] Compared with the prior art, the feedforward etching deviation overlay accuracy control method of the present invention has the following advantages:

[0029] The present invention utilizes an overlay mark design to generate an overlay mark error after etching in a self-aligned imaging process, while maintaining the mark's etching behavior consistent with the main etch pattern. Measurement of the overlay mark characterizes the asymmetric distortion caused by the etching process of the aligned layer at the wafer edge. The measurement results of the overlay mark provide a corrective feedforward for the subsequent alignment layer overlay error during photolithography, reducing the impact of the overlay mark asymmetry in the wafer edge region caused by the etching process and improving the stability of the subsequent alignment layer overlay error.

[0030] The overlay accuracy control system of the feedforward etching deviation provided by the present invention and the overlay accuracy control method of the feedforward etching deviation provided by the present invention belong to the same inventive concept. Therefore, the overlay accuracy control system of the feedforward etching deviation provided by the present invention has at least all the advantages of the overlay accuracy control method of the feedforward etching deviation provided by the present invention. The measurement results of the mark are used to provide a corrected feedforward for the subsequent alignment layer overlay error of the lithography, thereby reducing the impact of the asymmetry of the overlay mark in the edge area of the wafer caused by the etching process and improving the stability of the subsequent alignment layer overlay error. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Flowchart of a method for controlling overlay accuracy of feedforward etching deviation in one embodiment of the present invention;

[0032] Figure 2 1 is a schematic diagram of a graphic structure of a mandrel in which an overlay mark is formed on an original wafer in one embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of the remaining side walls after the core shaft is removed in one embodiment of the present invention;

[0034] Figure 4 1 is a schematic diagram of an edge overlay error characteristic of a raw wafer in one embodiment of the present invention;

[0035] In the figure,

[0036] 100-mandrel; 200-side wall;

[0037] 300-raw wafer. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the present invention clearer, the overlay accuracy control method and system of the feedforward etching deviation proposed by the present invention are further described in detail below in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same figure mark is sometimes used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0040] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0041] It is particularly important to note that in the following embodiments, the term "longitudinal" refers to a direction parallel to the length of the core shaft 100 (ie, Figure 2 The term "transverse" refers to a direction parallel to the width of the mandrel 100 (i.e., Figure 2 (direction of arrow X)

[0042] The core idea of the present invention is to provide a feedforward etching deviation overlay accuracy control method, which can provide correction feedforward for the subsequent alignment layer overlay error of the lithography, reduce the impact of the asymmetry of the overlay mark in the wafer edge area caused by the etching process, and improve the stability of the subsequent alignment layer overlay error.

[0043] In order to realize the above idea, the present invention provides a feedforward etching deviation overlay accuracy control method. Figures 1 to 4 A specific embodiment of a feedforward etching deviation overlay accuracy control method disclosed herein includes the following steps S1 to S3.

[0044] Step S1: providing an overlay mark, and forming the overlay mark on the original wafer 300 as the overlay mark of the aligned layer.

[0045] Specifically, refer to Figure 1 and Figure 2 As shown, the pattern of the overlay mark can be a rectangle, a square, etc. In this embodiment, the preferred structure of the overlay mark is a rectangular pattern. The overlay mark involves two directions, X and Y. The overlay mark is formed on the original wafer 300 as the overlay mark of the aligned layer, including:

[0046] First, the overlay marks are formed on the original wafer 300 respectively, and the core shaft 100 is formed on the surface of the wafer. The rectangular overlay marks are formed on the original wafer 300 by exposure, development and etching, and the core shaft 100 is formed on the surface of the original wafer 300. The core shaft 100 formed by the overlay marks is uniformly distributed in the transverse direction according to the design rules. That is, the core shaft 100 can be uniformly distributed in the transverse direction. The core shaft 100 is also distributed in the longitudinal direction. However, considering that it is affected by the lithography process conditions of the alignment layer, such as the light during exposure, the core shaft 100 needs to be segmented.

[0047] Next, a spacer 200 is formed around the mandrel 100 by a self-alignment process. The self-alignment process includes but is not limited to SADP and SAOP processes. The spacer 200 is formed around the mandrel 100 by a self-alignment process.

[0048] Then, the mandrel 100 is removed, and the sidewalls 200 on both sides of the mandrel 100 serve as overlay marks for the aligned layer. The mandrel 100 is removed through a wet etching process, and the sidewalls 200 remaining on both sides of the mandrel 100 serve as overlay marks for the aligned layer. Each mandrel 100 is subsequently etched using a SADP process, leaving two substrates with etched patterns. That is, at least the sidewalls 200 on both sides of the mandrel 100 along the longitudinal direction are left. There are at least five mandrels 100.

[0049] Step S2: Obtain the line widths Em and Em' of the overlay mark aligned with the edge area of the layer; and calculate Km=Em / Em'.

[0050] Specifically, refer to Figures 1 to 3 As shown, after the alignment layer operation of the original wafer 300 is completed, the overlay mark of the edge area of the aligned layer is measured using CDSEM to obtain a direct representation value of the overlay error mark, that is, the line width ratio of the two side walls, Km=Em / Em'.

[0051] Step S3: measuring the overlay error data of the alignment layer and establishing a linear model of the overlay error versus the wafer surface position.

[0052] Specifically, refer to Figures 1 to 4 As shown in the figure, in order to perform feedforward compensation for the overlay error of the subsequent wafer self-alignment process, an overlay mark design is performed before the mask is made. When the mask is made, the overlay mark is placed close to the DBO mark of the corresponding layer. The DBO result of the subsequent alignment layer of the above wafer is measured, and the linear overlay error of the wafer at the edge position is stripped out to form the edge overlay error characteristic. The distribution diagram of the overlay error is shown in the figure. Figure 4 As shown, the overlay error data of the alignment layer is measured, that is, Figure 4 The data shown by arrow a in the figure is used to build a linear model of the overlay error as it varies with wafer surface position. The linear model uses 10 correction parameters, including six for correcting the exposure grid: translation in the X and Y directions (Tx, Ty), magnification and shrinkage in the X and Y directions (Mx and My), rotation (Rw), and diagonal distortion (NO); and four correction parameters within the exposure area: symmetrical magnification or reduction (Ms), asymmetrical magnification or reduction (Ma), symmetrical rotation (Rs), and asymmetrical rotation (Ra).

[0053] Step S4: forming the overlay mark on a subsequent wafer as an overlay mark for a subsequent aligned layer.

[0054] Step S5: obtaining the line widths En and En' of the overlay mark of any subsequent aligned layer edge region; and calculating Kn=En / En'.

[0055] Specifically, refer to Figures 1 to 3 As shown, when subsequent wafers are actually shipped, after the subsequent wafer alignment layer operation is completed, the overlay mark of any subsequent aligned layer is measured using CDSEM to obtain a direct representation value of the overlay mark of the subsequent aligned layer, Kn=En / En'.

[0056] Step S6: Based on Km, Kn and the linear model, pre-correct any subsequent alignment layer.

[0057] Specifically, refer to Figures 1 to 4 As shown, based on the results of the above two measurements, the edge overlay error characteristic quantity of the corresponding proportion of any subsequent alignment layer feedforward is corrected, and the feedforward percentage can be adjusted by analyzing the correlation of past data. Based on Km, Kn and the linear model, the edge overlay error characteristic quantity of any subsequent alignment layer feedforward is pre-compensated by λ·(Kn / Km) times, where λ is a constant. λ is determined by the maintenance cycle of the etching machine. Once the etching machine is determined, the enclosure cycle of the etching machine generally does not change, so the value of λ is a constant. The measurement result after etching the overlay error mark of the aligned layer is used as the subsequent alignment layer feedforward compensation to pre-compensate the variation behavior of the etching process at the edge of the wafer during the SADP process.

[0058] This embodiment discloses a method for controlling overlay accuracy using feedforward etching deviation. By designing an overlay mark, an overlay mark error is generated after etching in a self-aligned imaging process, while maintaining the etching behavior of the mark consistent with the main etch pattern. Measurement of the overlay mark characterizes the asymmetric distortion caused by the etching process of the aligned layer at the wafer edge. The measurement results of the mark provide a corrective feedforward for the overlay error of the subsequent alignment layer during photolithography, reducing the impact of the overlay mark asymmetry in the wafer edge region caused by the etching process and improving the stability of the subsequent alignment layer overlay error.

[0059] This embodiment also discloses an overlay accuracy control system for feedforward etching deviation, comprising:

[0060] an acquisition module, configured to acquire line widths Em and Em' of the overlay mark in the edge region of the aligned layer; acquire line widths En and En' of the overlay mark in any subsequent edge region of the aligned layer, and calculate Kn=En / En';

[0061] The logic operation module is used to calculate Km=Em / Em'; measure the overlay error data of the alignment layer and establish a linear model of the overlay error with the wafer surface position; calculate Kn=En / En'; based on Km, Kn and the linear model, pre-compensate and correct any subsequent alignment layer.

[0062] The overlay accuracy control system of the feedforward etching deviation provided in this embodiment and the overlay accuracy control method of the feedforward etching deviation provided in this embodiment belong to the same inventive concept. Therefore, the overlay accuracy control system of the feedforward etching deviation provided in this embodiment has at least all the advantages of the overlay accuracy control method of the feedforward etching deviation provided in this embodiment. The measurement results of the mark are used to provide a correction feedforward for the subsequent alignment layer overlay error of the lithography, thereby reducing the impact of the asymmetry of the overlay mark in the edge area of the wafer caused by the etching process and improving the stability of the subsequent alignment layer overlay error.

[0063] In summary, the above embodiments provide a detailed description of the different configurations of the overlay accuracy control method and system for the feedforward etching deviation. Of course, the above description is only a description of the preferred embodiment of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above implementation. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A feedforward etching deviation overlay accuracy control method, characterized in that: include: Providing an overlay mark, and forming the overlay mark on the original wafer as the overlay mark of the aligned layer; Obtain the line widths Em and Em' of the overlay mark in the edge area of the aligned layer, and calculate Km=Em / Em'; Measure the overlay error data of the alignment layer and establish a linear model of the overlay error versus wafer surface position; forming the overlay mark on a subsequent wafer as an overlay mark for a subsequent aligned layer; Obtain the line widths En and En' of the overlay mark of any subsequent aligned layer edge region, and calculate Kn=En / En'; Based on Km, Kn and the linear model, any subsequent alignment layer is pre-corrected.

2. The overlay accuracy control method of feedforward etching deviation according to claim 1, characterized in that: The step of providing an overlay mark and forming the overlay mark on the original wafer as the overlay mark of the aligned layer includes: forming the overlay mark on the original wafer and forming a core shaft on the surface of the original wafer; forming a sidewall around the mandrel by a self-alignment process; The mandrel is removed, and the sidewalls on both sides of the mandrel serve as overlay marks of the aligned layer.

3. The overlay accuracy control method of feedforward etching deviation according to claim 2, characterized in that: The core shafts are evenly distributed along the transverse direction.

4. The overlay accuracy control method of feedforward etching deviation according to claim 2, characterized in that: The core shafts are evenly distributed along the longitudinal direction and are divided.

5. The overlay accuracy control method of feedforward etching deviation according to claim 2, characterized in that: The number of the core shafts is greater than or equal to 5.

6. The overlay accuracy control method of feedforward etching deviation according to claim 2, characterized in that: When making the mask, place the overlay mark close to the DBO overlay mark of the corresponding layer.

7. The overlay accuracy control method of feedforward etching deviation according to claim 2, characterized in that: The self-aligned imaging process includes SADP and SAOP.

8. The overlay accuracy control method of feedforward etching deviation according to claim 1, characterized in that: The pre-correction of any subsequent alignment layer based on Km, Kn and the linear model includes: Based on Km, Kn and the linear model, a pre-compensation correction is performed on the edge overlay error feature quantity of any subsequent alignment layer feedforward λ*(Kn / Km) times, where λ is a constant.

9. The overlay accuracy control method of feedforward etching deviation according to claim 8, characterized in that: λ is determined by the maintenance cycle of the etching machine.

10. A feedforward etching deviation overlay accuracy control system, characterized in that: include: An acquisition module, configured to acquire line widths Em and Em' of the overlay mark aligned with the edge region of the layer; Obtain the line widths En and En' of the overlay mark of any subsequent aligned layer edge region, and calculate Kn=En / En'; Logical operation module, used to calculate Km=Em / Em'; Measure the overlay error data of the alignment layer and establish a linear model of the overlay error versus wafer surface position; calculate Kn = En / En'; Based on Km, Kn and the linear model, any subsequent alignment layer is pre-corrected.

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