Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display. The display panel includes: a driving circuit; the drive circuit comprises n levels of cascaded shift register units. The first output end or the second output end of the xth-level shift register unit is electrically connected with the forward input end of the yth-level shift register unit, and the reverse input end of the yth-level shift register unit is electrically connected with the first output end or the second output end of the kth-level shift register unit; in a forward scanning mode, the first-stage shift register unit to the nth-stage shift register unit sequentially output effective pulses of first grid signals and sequentially output effective pulses of second grid signals; in a reverse scanning mode, the n -stage shift register unit to the first-stage shift register unit sequentially output effective pulses of first grid signals and sequentially output effective pulses of second grid signals. According to the technical scheme, the narrow frame can be realized on the premise of meeting the scanning requirement of the forward and reverse scanning mode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, electronic products with display functions have been widely used in various fields. For example, televisions, mobile phones, computers, personal digital assistants, etc. are all electronic products with display functions, becoming an indispensable part of people's lives and work. Among them, the display panel is the core structure that realizes the display function of electronic products.

[0003] A display panel typically includes a plurality of pixel circuits and a driving circuit arranged in an array. The driving circuit provides a gate driving signal to each row of pixels and can scan the pixel circuits row by row so that each row of pixel circuits displays light and the display panel presents a corresponding display image.

[0004] However, due to the limitations of the function and structure of the driving circuit, when a pixel circuit includes multiple functional modules, different driving circuits need to be set up to provide gate driving signals to different functional modules in the pixel circuit, so that the driving circuit occupies a larger space, which is not conducive to the narrow frame of the display panel and affects the display effect of the display panel. Summary of the Invention

[0005] The present invention provides a display panel and a display device, which can reduce the size of a driving circuit, thereby facilitating a narrow frame of the display panel and improving the display effect of the display panel.

[0006] In a first aspect, the present invention provides a display panel, comprising:

[0007] A driving circuit; the driving circuit includes n-stage cascaded shift register units; n is a positive integer greater than or equal to 2;

[0008] The shift register unit includes a scan control module, a drive control module, a first output module, a second output module, a forward input terminal, a reverse input terminal, a forward control terminal, a reverse control terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal, and a second output terminal; in the same shift register unit, the scan control module is electrically connected to the forward input terminal, the reverse input terminal, the forward control terminal, the reverse control terminal, and the input node respectively; the drive control module is electrically connected to at least the input node, the first clock terminal, the first node, and the second node respectively; the first output module is electrically connected to at least the first node, the second node, the second clock terminal, and the first output terminal respectively; the second output module is electrically connected to at least the first node, the second node, the third clock terminal, and the second output terminal respectively;

[0009] The first output terminal or the second output terminal of the shift register unit at the x-th stage is electrically connected to the forward input terminal of the shift register unit at the y-th stage, and the reverse input terminal of the shift register unit at the y-th stage is electrically connected to the first output terminal or the second output terminal of the shift register unit at the k-th stage; where 1 ≤ x < y < k ≤ n, and x, y, and k are all positive integers;

[0010] The valid pulses of the first gate signal output from the first output terminal and the second gate signal output from the second output terminal of the same shift register unit are shifted in sequence.

[0011] The operating modes of the display panel include a forward scan mode and a reverse scan mode; in the forward scan mode, the valid pulses of the first gate signal are sequentially output from the first-stage shift register unit to the n-th stage shift register unit, and the valid pulses of the second gate signal are sequentially output; in the reverse scan mode, the valid pulses of the first gate signal are sequentially output from the n-th stage shift register unit to the first-stage shift register unit, and the valid pulses of the second gate signal are sequentially output.

[0012] In a second aspect, the present invention further provides a display device, including: the display panel of the first aspect.

[0013] The technical solution provided by the present invention is to respectively provide a first output module, a second output module, a first output terminal, and a second output terminal in a shift register unit of a driving circuit, and the first output module controls the first gate signal output by the first output terminal, and the second output module controls the second gate signal output by the second output terminal, so that the effective pulses of the first gate signal and the second gate signal output by the same shift register unit can be shifted in sequence, that is, each shift register unit can output two gate driving signals shifted in sequence, thereby facilitating a reduction in the number of shift register units in the driving circuit, thereby reducing the occupied space of the driving circuit, and further facilitating a narrow frame of the display panel and improving the display effect of the display panel; at the same time, by electrically connecting the first output terminal or the second output terminal of the x-th shift register unit to the positive input terminal of the y-th shift register unit, and electrically connecting the negative input terminal of the y-th shift register unit to the first output terminal or the second output terminal of the k-th shift register unit, When the display panel operates in a forward scan mode, each shift register unit can, under the control of a signal received at its forward input terminal, a clock signal at each clock terminal, and a forward scan control signal at its forward control terminal, enable the first to nth shift register units to sequentially output the effective level of the first gate signal and the effective level of the second gate signal; and when the display panel operates in a reverse scan mode, each shift register unit can, under the control of a signal received at its reverse input terminal, a clock signal at each clock terminal, and a reverse scan control signal at its reverse control terminal, enable the nth to firstth shift register units to sequentially output the effective level of the first gate signal and the effective level of the second gate signal. That is, the first and second gate signals output by each shift register unit in the driving circuit can cooperate with the forward scan mode and the reverse scan mode of the display panel, enabling the driving circuit to have forward and reverse scan functions. In this way, while ensuring that the driving circuit has a small size, the driving circuit has forward and reverse scan functions, meets the scanning requirements of the display panel in different modes, broadens the application scenarios of the display panel, and improves the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a structural diagram of a display panel in related technology;

[0015] Figure 2 is a structural diagram of another display panel in related technology;

[0016] Figure 3 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 1 is a structural diagram of a shift register unit provided by an embodiment of the present invention;

[0018] Figure 5 This is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 6 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0020] Figure 7 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 is a schematic structural diagram of a driving circuit provided by an embodiment of the present invention;

[0022] Figure 9 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0023] Figure 10 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0024] Figure 11 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0025] Figure 12 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 13 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0027] Figure 14 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0028] Figure 15 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0029] Figure 16 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0030] Figure 17 This is a driving timing diagram of a shift register unit in a forward scanning mode provided by an embodiment of the present invention;

[0031] Figure 18 This is a driving timing diagram of a shift register unit in a reverse scan mode provided by an embodiment of the present invention;

[0032] Figure 19 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0033] Figure 20 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0034] Figure 21 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0035] Figure 22 1 is a structural diagram of another shift register unit provided by an embodiment of the present invention;

[0036] Figure 23 This is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0037] Figure 24 This is a driving timing diagram of another shift register unit provided by an embodiment of the present invention;

[0038] Figure 25 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0039] Figure 26 This is a driving timing diagram of a driving circuit in a forward scanning mode provided by an embodiment of the present invention;

[0040] Figure 27 This is a driving timing diagram of a driving circuit in a reverse scanning mode provided by an embodiment of the present invention;

[0041] Figure 28 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0042] Figure 29 is another driving timing diagram of a driving circuit in a positive scanning mode provided by an embodiment of the present invention;

[0043] Figure 30 is another driving timing diagram of a driving circuit in a reverse scanning mode provided by an embodiment of the present invention;

[0044] Figure 31 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0045] Figure 32 This is another driving timing diagram of a driving circuit in a forward scanning mode provided by an embodiment of the present invention;

[0046] Figure 33 This is another driving timing diagram of a driving circuit in a reverse scanning mode provided by an embodiment of the present invention;

[0047] Figure 34 is a structural diagram of another driving circuit provided by an embodiment of the present invention;

[0048] Figure 35 This is another driving timing diagram of a driving circuit in a forward scanning mode provided by an embodiment of the present invention;

[0049] Figure 36 This is another driving timing diagram of a driving circuit in a reverse scanning mode provided by an embodiment of the present invention;

[0050] Figure 37 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0052] Figure 1 This is a schematic diagram of the structure of a display panel in related technology, such as Figure 1 As shown, the display panel 001 may include a display area AA′ and a non-display area NA′ surrounding the display area AA′. A plurality of pixel circuits 01 arranged in an array are provided in the display area AA′. The pixel circuit 01 may include at least a driving module, a light-emitting module, a first preset module and a second preset module. For example, the first preset module may include a reset module, and the second preset module may include a data writing module. The reset module can reset the driving module, and the data writing module can control the data signal to be written to the driving module. The driving module is used to selectively drive the light-emitting module to emit light according to the data signal, that is, the first preset module and the second preset module are turned on in different time periods to control the signal written into the pixel circuit 01.

[0053] Correspondingly, a driving circuit 02 is provided in the non-display area NA′. The driving circuit 02 includes at least a first driving circuit 021 and a second driving circuit 022. Each shift register unit 0211 in the first driving circuit 021 provides a gate driving signal to the first preset module of each row of pixel circuits 01 to control whether the first preset module is turned on or off. Each shift register unit 0221 in the second driving circuit 022 provides a gate driving signal to the second preset module of each row of pixel circuits 01 to control whether the second preset module is turned on or off. In this way, the first driving circuit 021 and the second driving circuit 022 can drive each row of pixel circuits 01 to display and emit light normally.

[0054] However, since the first preset module and the second preset module in the pixel circuit 01 need to be controlled by the first driving circuit 021 and the second driving circuit 022 respectively, the non-display area NA′ needs to be equipped with at least two driving circuits, namely the first driving circuit 021 and the second driving circuit 022. Therefore, a larger driving circuit setting space needs to be reserved in the non-display area NA′, which makes the size of the non-display area NA′ larger, which is not conducive to the narrow frame of the display panel.

[0055] In some related technologies, such as Figure 2 As shown, the first preset module and the second preset module of the pixel circuit 01 can also be electrically connected to the same driving circuit 02, so that the same driving circuit 02 provides gate driving signals to the first preset module and the second preset module of the pixel circuit 01 respectively. For example, the i+1th stage shift register unit 0201 of the driving circuit 02 can provide a gate driving signal to the first preset module of the i+1th row pixel circuit 02, and provide a gate driving signal to the second preset module of the i-th row pixel circuit 02, so as to control the first preset module of the i+1th row pixel circuit and the second preset module of the i-th row pixel circuit to be turned on or off. However, when the display panel working module includes a forward scanning mode and a reverse scanning mode, in the forward scanning mode, the first-stage shift register unit 0201 to the last-stage shift register unit 0201 of the driving circuit 02 sequentially output the effective pulse of the gate driving signal, so that the first preset module and the second preset module of the same pixel circuit 02 can be turned on in sequence, and in two adjacent rows of pixel circuits 02, the turn-on time of the first preset module of the pixel circuit 02 in the previous row is before the turn-on time of the first preset module of the pixel circuit 02 in the next row, and the turn-on time of the second preset module of the pixel circuit 02 in the previous row is before the turn-on time of the first preset module of the pixel circuit 02 in the next row. Before the turn-on time of the second preset module of the next row of pixel circuits 02, so that each row of pixel circuits 02 can display light normally; while in the reverse scanning mode, the last-stage shift register unit 0201 to the first-stage shift register unit 0201 of the driving circuit 02 sequentially output the valid pulses of the gate driving signal. At this time, the turn-on time of the first preset module in the same pixel circuit will be after the turn-on time of the second preset module, so that the driving module in the pixel circuit cannot be reset and data written normally, resulting in the pixel circuit being unable to display light normally, affecting the display effect of the display panel.

[0056] In summary, how to ensure that the display panel meets the driving requirements of various working modes while reducing the occupied space of the driving circuit, reducing the size of the driving circuit, and reducing the size of the display panel has become a technical problem that needs to be solved urgently.

[0057] To solve the above problems, an embodiment of the present invention provides a display panel, which includes: a driving circuit; the driving circuit includes n cascaded shift register units; n is a positive integer greater than or equal to 2; the shift register unit includes a scan control module, a driving control module, a first output module, a second output module, a forward input terminal, a reverse input terminal, a forward control terminal, a reverse control terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal, and a second output terminal; in the same shift register unit, the scan control module is electrically connected to the forward input terminal, the reverse input terminal, the forward control terminal, the reverse control terminal, and an input node respectively; the driving control module is at least electrically connected to the input node, the first clock terminal, a first node, and a second node respectively; the first output module is at least electrically connected to the first node, the second node, the second clock terminal, and the first output terminal respectively; the second output module is at least electrically connected to the first node, the second node, the third clock terminal, and the second output terminal respectively; the first output terminal or the second output terminal of the x-th shift register unit is electrically connected to the forward input terminal of the y-th shift register unit, and the reverse input terminal of the y-th shift register unit is electrically connected to the first output terminal or the second output terminal of the k-th shift register unit; where 1 ≤ x < y < k ≤ n, and x, y, and k are all positive integers; the valid pulses of the first gate signal output by the first output terminal and the second gate signal output by the second output terminal of the same shift register unit are shifted in sequence; the working modes of the display panel include a forward scan mode and a reverse scan mode; in the forward scan mode, the first shift register unit to the n-th shift register unit sequentially output the valid pulses of the first gate signal and sequentially output the valid pulses of the second gate signal; in the reverse scan mode, the n-th shift register unit to the first shift register unit sequentially output the valid pulses of the first gate signal and sequentially output the valid pulses of the second gate signal.

[0058] By adopting the above technical solution, a first output module, a second output module, a first output terminal and a second output terminal are respectively provided in the shift register unit of the driving circuit, and the first output module controls the first gate signal output by the first output terminal, and the second output module controls the second gate signal output by the second output terminal, so that the effective pulses of the first gate signal and the second gate signal output by the same shift register unit can be shifted in sequence, that is, each shift register unit can output two gate driving signals shifted in sequence, which is beneficial to reducing the number of shift register units in the driving circuit, thereby reducing the occupied space of the driving circuit, and further contributing to a narrow frame of the display panel and improving the display effect of the display panel; at the same time, by electrically connecting the first output terminal or the second output terminal of the x-th shift register unit to the positive input terminal of the y-th shift register unit, and electrically connecting the reverse input terminal of the y-th shift register unit to the first output terminal or the second output terminal of the k-th shift register unit, When the display panel operates in a forward scan mode, the shift register units of each stage can, under the control of the signal received at the forward input terminal, the clock signal at each clock terminal, and the forward scan control signal at the forward control terminal, enable the first to n-th shift register units to sequentially output the effective level of the first gate signal and the effective level of the second gate signal; and when the display panel operates in a reverse scan mode, the shift register units of each stage can, under the control of the signal received at the reverse input terminal, the clock signal at each clock terminal, and the reverse scan control signal at the reverse control terminal, enable the n-th to first-stage shift register units to sequentially output the effective level of the first gate signal and the effective level of the second gate signal, that is, the first gate signal and the second gate signal output by the shift register units of each stage in the driving circuit can cooperate with the forward scan mode and the reverse scan mode of the display panel, so that the driving circuit has forward and reverse scan functions. In this way, while ensuring that the driving circuit has a small size, the driving circuit has forward and reverse scan functions, meets the scanning requirements of the display panel in different modes, broadens the application scenarios of the display panel, and improves the display effect of the display panel.

[0059] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0060] Figure 3 is a structural diagram of a display panel provided by an embodiment of the present invention, Figure 4 This is a structural diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Figure 3 and Figure 4The display panel 100 includes a driving circuit 10, which includes a cascaded n-stage shift register unit 101; the shift register unit 101 includes a scanning control module 110, a driving control module 120, a first output module 130, a second output module 140, a positive input terminal INF, a negative input terminal INB, a positive control terminal U2D, a negative control terminal D2U, a first clock terminal CK1, a second clock terminal CK2, a third clock terminal CK3, a first output terminal OUT1 and a second output terminal OUT2. In the same shift register unit 101, the scan control module 110 is electrically connected to the positive input terminal INF, the negative input terminal INB, the positive control terminal U2D, the negative control terminal D2U, and the input node Q0, respectively. The drive control module 120 is electrically connected to at least the input node Q0, the first clock terminal CK1, the first node Q1, and the second node Q2, respectively. The first output module 130 is electrically connected to at least the first node Q1, the second node Q2, the second clock terminal CK2, and the first output terminal OUT1, respectively. The second output module 140 is electrically connected to at least the first node Q1, the second node Q2, the third clock terminal CK3, and the second output terminal OUT2, respectively. The valid pulses of the first gate signal S1 output from the first output terminal OUT1 and the second gate signal S2 output from the second output terminal OUT2 of the same shift register unit 101 are sequentially shifted.

[0061] It can be understood that n can be a positive integer greater than or equal to 2, that is, two or more shift register units 101 can be provided in the driving circuit 10. The specific number of settings can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0062] In which, the display panel 100 may include a display area AA and a non-display area NA surrounding the display area AA, the driving circuit 10 may be arranged in the non-display area NA, and a plurality of pixel circuits 20 and a plurality of gate signal lines 30 arranged in an array may be provided in the display area AA, the gate signal line 30 may include a first gate signal line 31 and a second gate signal line 32, each pixel circuit 30 may be electrically connected to the first gate signal line 31 and the second gate signal line 32, respectively, and at least part of the pixel circuits 20 located in the same row are electrically connected to the same first gate signal line 31, and at least part of the pixel circuits 20 located in the same row are electrically connected to the same second gate signal line 32; at this time, the first output terminal OUT1 of each level of the shift register unit 101 may be electrically connected to different first gate signal lines 31, respectively, and the shift register units 101 at each level may be electrically connected to different first gate signal lines 31, respectively. The second output end OUT2 of the register unit 101 can be electrically connected to different second gate signal lines 32, so as to be able to output the first gate signal S1 to each first gate signal line 31, and to output the second gate signal S2 to each second gate signal line 32, so that each first gate signal line 31 can transmit the first gate signal S1 output by each level of shift register unit 101 to each row of pixel circuits 20, and each second gate signal line 32 can transmit the second gate signal S2 output by each level of shift register unit 101 to each row of pixel circuits 20, so as to realize row-by-row scanning of each pixel circuit 20, so that each row of pixel circuits 20 can write corresponding display signals, control each row of pixel circuits 20 to display light, and enable the display panel 100 to present the corresponding display screen.

[0063] It should be noted that the above description is only based on the example of the driving circuit 10 being located in the non-display area NA and the pixel circuit 20 being located in the display area AA. In other embodiments of the present invention, the pixel circuit 20 and the driving circuit 10 may also be both located in the display area AA, so that the number of devices arranged in the non-display area NA of the display panel 100 is sufficiently small, thereby reducing the size of the non-display area NA of the display panel 100, thereby facilitating a narrow frame of the display panel 100 and enabling the display panel 100 to have a higher screen-to-body ratio.

[0064] For ease of description, without special limitations, the embodiments of the present invention all take the example of the driving circuit being located in the non-display area of the display panel and the pixel circuit being located in the display area of the display panel as an example to exemplify the technical solutions of the embodiments of the present invention.

[0065] Continue to refer Figure 3 and Figure 4In the same shift register unit 101, the scan control module 110 is electrically connected to the forward input terminal INF, the reverse input terminal INB, the forward control terminal U2D, the reverse control terminal D2U and the input node Q0, respectively, so that the scan control module 110 can control the signal of the input node Q0 according to the forward scan control signal u2d of the forward control terminal U2D, the reverse scan control signal d2u of the reverse control terminal D2U, the forward input signal Vinf of the forward input terminal, and the reverse input signal Vinb of the reverse input terminal INB.

[0066] In an exemplary embodiment, the scan control module 110 can control the transmission path of the forward input signal Vinf of the forward input terminal INF to the input node Q0 according to the forward scan control signal u2d of the forward control terminal U2D, so that when the forward scan control signal u2d is at a valid level, the scan control module 110 can control the forward input signal Vinf of the forward input terminal INF to be transmitted to the input node Q0; at the same time, the scan control module 110 can also control the transmission path of the reverse input signal Vinb of the reverse input terminal INB to be transmitted to the input node Q0 according to the reverse scan control signal d2u of the reverse control terminal D2U, so that when the reverse scan control signal d2u is at a valid level, the scan control module 110 can control the reverse input signal Vinb of the reverse input terminal INB to be transmitted to the input node Q0.

[0067] It is understood that, provided that the scan control module 110 is capable of controlling the signal at the input node Q0, the embodiments of the present invention do not limit the specific implementation of the scan control module 110. At the same time when the display panel is displaying an image, the polarities of the forward scan control signal u2d and the reverse scan control signal d2u can be opposite to ensure that the scan control module 110 can function normally.

[0068] In an optional embodiment, the operating mode of the display panel 100 includes a forward scan mode and a reverse scan mode. In the forward scan mode, the forward scan control signal u2d can be at an active level, and the reverse scan control signal d2u can be at an inactive level; in the reverse scan mode, the reverse scan control signal d2u is at an active level, and the forward scan control signal u2d is at an inactive level. Thus, in the forward scan mode, the forward input signal Vinf of the forward input terminal INF can be transmitted to the input node Q0 under the control of the forward scan control signal u2d, while the reverse input signal Vinb of the reverse input terminal INB cannot be transmitted to the input node Q0, so that the signal of the input node Q0 can be consistent with the forward input signal Vinf; and in the reverse scan mode, the reverse input signal Vinb of the reverse input terminal INB can be transmitted to the input node Q0 under the control of the reverse scan control signal d2u, while the forward input signal Vinf of the forward input terminal INF cannot be transmitted to the input node Q0, so that the signal of the input node Q0 can be consistent with the reverse input signal Vinb.

[0069] Continue to refer Figure 3 and Figure 4 Since the driving control module 120 is electrically connected to at least the input node Q0, the first clock terminal CK1, the first node Q1, and the second node Q2 in the same shift register unit 101, the driving control module 120 can control the signal of the first node Q1 and the signal of the second node Q2 according to the signal of the input node Q0 and the first clock signal ck1 of the first clock terminal CK1. For example, when the signal of the input node Q0 and the first clock signal ck1 are both at valid levels, the signal of the first node Q1 can be controlled to be at a valid level, and the signal of the second node Q2 can be controlled to be at an invalid level; during at least a portion of the time when the signal of the input node Q0 is at an invalid level, the signal of the first node Q1 can be controlled to be at an invalid level, and the signal of the second node Q2 can be controlled to be at a valid level. In this way, the signal of the first node Q1 and the signal of the second node Q2 can be controlled to have different polarities during at least a portion of the time.

[0070] At the same time, in the same shift register unit 101, the first output module 130 is electrically connected to at least the first node Q1, the second node Q2, the second clock terminal CK2 and the first output terminal OUT1, so that the first input module 130 can control the first gate signal S1 output by the first output terminal OUT1 according to the signal of the first node Q1, the signal of the second node Q2, and the second clock signal ck2 of the second clock terminal CK2. For example, when the signal of the first node Q1 and the second clock signal ck2 are both at a valid level and the signal of the second node Q2 is at an invalid level, the first output module 130 can control the first output terminal OUT1 to output the valid level of the first gate signal S1. Conversely, the first output terminal OUT1 outputs the first gate signal S1. The second output module 140 is electrically connected to at least the first node Q1, the second node Q2, the third clock terminal CK3 and the second output terminal OUT2, so that the second output module 140 can control the second gate signal S2 output by the second output terminal OUT2 according to the signal of the first node Q1, the signal of the second node Q2, and the third clock signal ck3 of the third clock terminal CK3. For example, when the signal of the first node Q1 and the third clock signal ck3 are both at valid levels and the signal of the second node Q2 is at an invalid level, the second output module 140 can control the second output terminal OUT2 to output the valid level of the second gate signal S2; otherwise, the second output terminal OUT2 outputs the invalid level of the second gate signal S2. In this way, both the first output module 130 and the second output module 140 can output gate drive signals under the control of the signal at the first node Q1 and the signal at the second node Q2. The first gate signal S1 outputted from the first output terminal OUT1 by the first output module 130 and the second gate signal S2 outputted from the second output terminal OUT2 by the second output module 140 can be the same or different. Specifically, the difference can be determined based on the second clock signal ck2 received by the first output module 130 and the third clock signal ck3 received by the second output module 140. For example, when the valid pulses of the second clock signal ck2 and the third clock signal ck3 shift sequentially within one clock cycle, the valid pulses of the first gate signal S1 and the second gate signal S2 can shift sequentially. In this case, the same shift register unit 101 can simultaneously output two different gate drive signals. When 2n different gate drive signals are required, only n shift register units 101 need to be provided in the drive circuit 10, thereby reducing the number of shift register units 101 provided in the drive circuit 10 and further reducing the size of the drive circuit 10. When the driving circuit 10 is disposed in the non-display area NA of the display panel 100 , it is beneficial to reduce the size of the non-display area NA of the display panel 100 , which is beneficial to a narrow frame of the display panel 100 .

[0071] It can be understood that the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 each include a high level and a low level that change with a certain clock period. The active level of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 can be either the high level or the low level, and the active levels of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 can be the same or different, which can be specifically designed according to actual needs. In the embodiments of the present invention, the active levels of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 are taken as an example of the low level to exemplarily illustrate the technical solutions of the embodiments of the present invention. At the same time, within the active pulse time period of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3, the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 will remain at the active level, and in the remaining time periods, the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 will remain at the inactive level. In addition, the active pulse times of the first clock signal ck1, the second clock signal ck2, and the third clock signal ck3 do not overlap, which can be specifically designed according to actual needs, and the embodiments of the present invention do not make specific limitations on this.

[0072] Figure 5 is a driving timing diagram of a display panel provided by an embodiment of the present invention. Figure 6 is another driving timing diagram of a display panel provided by an embodiment of the present invention. Referring to Figures 3 to 6 , the first output terminal OUT1 or the second output terminal OUT2 of the x-th stage shift register unit Gx is electrically connected to the forward input terminal INF of the y-th stage shift register unit Gy, and the reverse input terminal INB of the y-th stage shift register unit Gy is electrically connected to the first output terminal OUT1 or the second output terminal OUT2 of the k-th stage shift register unit Gk; where 1 ≤ x < y < k ≤ n, and x, y, and k are all positive integers; at this time, the working mode of the display panel 100 can include a forward scan mode and a reverse scan mode; in the forward scan mode, the first stage shift register unit G1 to the n-th stage shift register unit Gn sequentially output the active pulses of the first gate signal S1, and sequentially output the active pulses of the second gate signal S2; in the reverse scan mode, the n-th stage shift register unit Gn to the first stage shift register unit G1 sequentially output the active pulses of the first gate signal S1, and sequentially output the active pulses of the second gate signal S2. [[ID=**10**]]

[0073] Among them, the x-th shift register unit Gx, the y-th shift register unit Gy and the k-th shift register unit Gk can be three-stage shift register units 101 that are adjacent in sequence. For example, when x is equal to i, y can be equal to i+1, and k can be equal to i+2; or, the x-th shift register unit Gx, the y-th shift register unit Gy and the k-th shift register unit Gk can also be non-adjacent three-stage shift register units 101. For example, when x is equal to i, y can be equal to i+2, and k can be equal to i+4. On the premise that the core invention of the embodiment of the present invention can be realized, the embodiment of the present invention does not specifically limit the values of x, y and k.

[0074] In an optional embodiment, Figure 7 FIG. 1 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 7 As shown, the display panel 100 may include a display area AA and a non-display area at least partially surrounding the display area AA, and the non-display area may include a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area; when x=ym, k=y+m, and m is a positive integer greater than 1, the shift register units (101A or 101B) of each level cascaded with each other constitute a sub-driving circuit (10A or 10B); wherein, part of the sub-driving circuit (10A) is located in the first non-display area NA1, and part of the sub-driving circuit (10B) is located in the second non-display area NA2.

[0075] Wherein, m is a positive integer greater than 1, that is, m can be any positive integer equal to 2, 3, or greater. Taking m equal to 2 as an example, the shift register units 101A (Gi, Gi+2, and Gi+4) of each odd-numbered stage can constitute the first sub-driving circuit 10A, and the shift register units 101B (Gi+1, Gi+3, and Gi+5) of each even-numbered stage can constitute the second sub-driving circuit 10B, where i is an odd number. The first sub-driving circuit 10A can be disposed in the first non-display area NA1, and the second sub-driving circuit 10B can be disposed in the second non-display area NA2.

[0076] In an exemplary embodiment, in the first sub-driving circuit 10A, the positive input terminal INF of the i+2-stage shift register unit Gi+2 can be electrically connected to the second output terminal OUT2 of the i-stage shift register unit Gi, and the negative input terminal INB of the i+2-stage shift register unit Gi+2 can be electrically connected to the second output terminal OUT2 of the i+4-stage shift register unit Gi+4, so that in the positive scanning mode, the second gate signal S2i of the i-stage shift register unit Gi is combined with the clock signals received by the i+2-stage shift register unit Gi+2, etc., to control the effective pulse time of the first gate signal S1i+2 and the second gate signal S2i+2 output by the i+2-stage shift register unit Gi+2, thereby ensuring that the i+2-stage shift register unit Gi+2 outputs the first The effective pulse time of the gate signal S1i+2 and the second gate signal S2i+2 is located after the effective pulse time of the second gate signal S2i of the i-th shift register unit Gi; in the reverse scanning mode, the second gate signal S2i+4 of the i+4-th shift register unit Gi+4 is combined with the clock signals received by the i+2-th shift register unit Gi+2 to control the effective pulse time of the first gate signal S1i+2 and the second gate signal S2i+2 output by the i+2-th shift register unit Gi+2, ensuring that the effective pulse time of the first gate signal S1i+2 and the second gate signal S2i+2 output by the i+2-th shift register unit Gi+2 is located after the effective pulse time of the second gate signal S2i+4 of the i+4-th shift register unit Gi+4.

[0077] Correspondingly, in the second sub-driving circuit 10B, the positive input terminal INF of the i+3-th stage shift register unit Gi+3 can be electrically connected to the second output terminal OUT2 of the i+1-th stage shift register unit Gi+1, and the negative input terminal INB of the i+3-th stage shift register unit Gi+3 can be electrically connected to the second output terminal OUT2 of the i+5-th stage shift register unit Gi+5, so that in the positive scanning mode, the second gate signal S2i+1 of the i+1-th stage shift register unit Gi+1 is combined with the clock signals received by the i+3-th stage shift register unit Gi+3 to control the effective level time of the first gate signal S1i+3 and the second gate signal S2i+3 output by the i+3-th stage shift register unit Gi+3, thereby ensuring that the i+3-th stage shift register unit Gi+3 outputs the first gate signal S1i+3 and the second gate signal S2i+3. The effective pulse time of the pole signal S1i+3 and the second gate signal S2i+3 is located after the effective pulse time of the second gate signal S2i+1 of the i+1-th level shift register unit Gi+1; in the reverse scanning mode, the second gate signal S2i+5 of the i+5-th level shift register unit Gi+5 is combined with the clock signals received by the i+3-th level shift register unit Gi+3 to control the effective pulse time of the first gate signal S1i+3 and the second gate signal S2i+3 output by the i+3-th level shift register unit Gi+3, ensuring that the effective pulse time of the first gate signal S1i+3 and the second gate signal S2i+3 output by the i+3-th level shift register unit Gi+3 is located after the effective pulse time of the second gate signal S2i+5 of the i+5-th level shift register unit Gi+5.

[0078] At the same time, in the forward scanning mode, the effective pulse time of the first gate signal S1i output by the i-th shift register unit Gi can be located before the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1, and the effective pulse time of the second gate signal S2i output by the i-th shift register unit Gi can be located before the effective pulse time of the second gate signal S2i+1 output by the i+1-th shift register unit Gi+1; the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1 is located before the effective pulse time of the first gate signal S1i+2 output by the i+2-th shift register unit Gi+2, and the effective pulse time of the second gate signal S2i+1 output by the i+1-th shift register unit Gi+1 can be located before the effective pulse time of the second gate signal S2i+1 output by the i+1-th shift register unit Gi+1. The effective pulse time of the second gate signal S2i+1 output by element Gi+1 is located before the effective pulse time of the second gate signal S2i+2 output by the i+2-th level shift register unit Gi+2; similarly, the effective pulse time of the second gate signal S2i+4 output by the i+4-th level shift register unit Gi+4 is located before the effective pulse time of the second gate signal S2i+5 output by the i+5-th level shift register unit Gi+5; when each level of shift register unit (101A or 101B) is electrically connected to a row of pixel circuits 20, serpentine scanning from the first row to the last row of pixel circuits 20 can be achieved, which is beneficial to improving the display uniformity of each pixel circuit 20, thereby improving the display effect of the display panel.

[0079] Correspondingly, in the reverse scanning mode, when each level of shift register unit (101A or 101B) is electrically connected to a row of pixel circuits 20, serpentine scanning from the last row to the first row of pixel circuits 20 can also be achieved, which is beneficial to improving the display uniformity of each pixel circuit and further improving the display effect of the display panel.

[0080] In addition, by respectively arranging the first sub-driving circuit 10A and the second driving sub-circuit 10B in the first non-display area NA1 and the second non-display area NA2 on the opposite sides of the display area AA, the sizes of the first non-display area NA1 and the second non-display area NA2 on the opposite sides of the display area AA are kept consistent, so that the display frames on the opposite sides of the display area AA in the display panel 100 are symmetrically distributed, which is beneficial to improving the aesthetics of the display panel 100 while ensuring the display effect of the display panel 100.

[0081] It should be noted that the above description only illustrates the setting method of the shift register units at each level by taking m equal to 2 as an example. In the embodiment of the present invention, the specific setting method of the shift register units at each level is not limited to this and can be designed according to actual needs. The embodiment of the present invention does not make specific limitations on this.

[0082] Continue to refer Figures 3 to 6, because the first output terminal OUT1 or the second output terminal OUT2 of the x-th stage shift register unit Gx is electrically connected to the positive input terminal INF of the y-th stage shift register unit Gy, the first gate signal S1 outputted from the first output terminal OUT1 or the second gate signal S2 outputted from the second output terminal OUT2 of the x-th stage shift register unit Gx can be used as the positive input signal Vinf of the positive input terminal INF of the y-th stage shift register unit Gy. Therefore, in the positive scanning mode, the first gate signal S1 or the second gate signal S2 outputted from the x-th stage shift register unit Gx and the positive scanning control signal u2d of the positive control terminal U2D of the y-th stage shift register unit Gy can be used to control the signal of the input node Q0 of the y-th stage shift register unit Gy, thereby controlling the first gate signal S1 and the second gate signal S2 outputted from the y-th stage shift register unit Gy. When the reverse input terminal INB of the y-th stage shift register unit Gy is electrically connected to the first output terminal OUT1 or the second output terminal OUT2 of the k-th stage shift register unit Gk, the first gate signal S1 output from the first output terminal OUT1 or the second gate signal S2 output from the second output terminal OUT2 of the k-th stage shift register unit Gk can be used as the reverse input signal Vinb of the reverse input terminal INB of the y-th stage shift register unit Gy. Therefore, in the reverse scan mode, the first gate signal S1 or the second gate signal S2 output from the k-th stage shift register unit Gk and the reverse scan control signal d2u of the reverse control terminal D2U of the y-th stage shift register unit Gy can be used to control the signal of the input node Q0 of the y-th stage shift register unit Gy, thereby controlling the first gate signal S1 and the second gate signal S2 output from the y-th stage shift register unit Gy. In this way, by setting the connection method between the y-th level shift register unit Gy, the x-th level shift register unit Gx and the k-th level shift register unit Gk, the driving circuit 10 can meet the different working modes of the display panel 100, that is, the driving circuit 10 can meet the forward scanning mode and the reverse scanning mode of the display panel 100, that is, meet diversified application requirements.

[0083] It can be understood that, in the embodiment of the present invention, the first output terminal OUT1 or the second output terminal OUT2 of the x-th stage shift register unit Gx is electrically connected to the positive input terminal INF of the y-th stage shift register unit Gy. Figure 8 and Figure 10 As shown, the first output terminal OUT1 of the x-th stage shift register unit Gx is electrically connected to the positive input terminal INF of the y-th stage shift register unit Gy, or, as shown Figure 9 and Figure 11As shown, the second output terminal OUT2 of the x-th shift register unit Gx is electrically connected to the positive input terminal INF of the y-th shift register unit Gy; correspondingly, the negative input terminal INB of the y-th shift register unit Gy is electrically connected to the first output terminal OUT1 or the second output terminal OUT2 of the k-th shift register unit Gk. Figure 8 and Figure 11 As shown, the inverting input terminal INB of the y-th stage shift register unit Gy is electrically connected to the first output terminal OUT1 of the k-th stage shift register unit Gk, or, as shown Figure 9 and Figure 10 As shown, the inverting input terminal INB of the y-th stage shift register unit Gy is electrically connected to the second output terminal OUT2 of the k-th stage shift register unit Gk. The specific connection method can be designed according to actual needs, and the embodiment of the present invention does not make specific restrictions on this. For the convenience of description, under the premise of no special restrictions, the embodiments of the present invention are all based on Figure 8 or Figure 9 The cascade mode shown in the figure is used to exemplarily illustrate the technical solution of the embodiment of the present invention.

[0084] It can also be understood that in both the forward scanning mode and the reverse scanning mode, the effective pulses of the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 will shift sequentially. That is, for the same shift register unit 101, in both the forward scanning mode and the reverse scanning mode, the effective pulse start time of the first gate signal S1 is before the effective pulse start time of the second gate signal S2, and the effective pulse end time of the first gate signal S1 is before the effective pulse end time of the second gate signal S2. At the same time, the effective pulse widths of the first gate signal S1 and the second gate signal S2 of the same shift register unit 101 can be the same or different, and can be specifically designed according to actual needs. This is not specifically limited in the embodiment of the present invention.

[0085] In addition, since the valid pulses of the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 are shifted in sequence, each stage of the shift register unit 101 can provide two gate signals to the pixel circuit 20 . At this time, the first output terminal OUT1 and the second output terminal OUT2 of the same shift register unit 101 can be electrically connected to different rows of pixel circuits 20, respectively, so that each level of shift register unit 101 controls the working process of at least two rows of pixel circuits 20; or, the first output terminal OUT1 and the second output terminal OUT2 of the same shift register unit 101 can also be electrically connected to different modules of the same pixel circuit 20 to control the on-off state of different modules in the same pixel circuit 20; or, when the first output terminal OUT1 and the second output terminal OUT2 of the same shift register unit 101 are electrically connected to different modules of the same pixel circuit 20, respectively, the pixel circuit 20 can at least include a first preset module and a second preset module, and at this time the first output terminal OUT1 can be electrically connected to the first preset modules of two adjacent rows of pixel circuits 20, and the second output terminal OUT2 can be electrically connected to the second preset modules of two adjacent rows of pixel circuits 20.

[0086] In an optional embodiment, Figure 12 This is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, with reference to Figure 3 and Figure 12 When the display panel 100 includes a display area AA, and a plurality of pixel circuits 20 arranged in an array are disposed in the display area AA, the pixel circuits 20 include at least a first preset module 201 and a second preset module 202. In this case, the first gate signal S1 and the second gate signal S2 of the same shift register unit 101 are respectively used to control the conduction or shutdown of the first preset module 201 and the second preset module 202 of the same pixel circuit 20. That is, the first gate signal S1 of the shift register unit 101 can control the first preset module 201 to provide a corresponding signal to a node electrically connected thereto, and the second gate signal S2 of the shift register unit 101 can control the second preset module 202 to provide a corresponding signal to a node electrically connected thereto, thereby controlling the driving process of the pixel circuit 20. In this manner, there is no need to separately provide corresponding shift register units 101 for the first preset module 201 and the second preset module 202 of the pixel circuit 20, which is beneficial for reducing the number of shift register units 101 disposed in the display panel 100, and for reducing the size of the driving circuit 10, thereby facilitating a narrow frame of the display panel 100.

[0087] It is understood that the first preset module 201 and the second preset module 202 may include active and / or passive devices. Active devices may include, for example, transistors, and passive devices may include, for example, capacitors, resistors, inductors, etc. When the first preset module 201 includes a PMOS transistor, when the first gate signal S1 is a low-level signal, the first gate signal S1 is an effective pulse, that is, the effective level of the first gate signal S1 is a low level, so that the low-level first gate signal S1 can control the PMOS transistor to turn on; and when the first gate signal S1 is a high-level signal, the first gate signal S1 is an inactive level, so that the high-level first gate signal S1 controls the PMOS transistor to turn off. Conversely, when the first preset module 201 includes an NMOS transistor, the high level of the first gate signal S1 can control the NMOS transistor to turn on, and the low level of the first gate signal S1 can control the NMOS transistor to turn off. For PMOS or NMOS transistors included in the second preset module 202, the second gate signal S2 has a similar condition to the first gate signal S1. For details, please refer to the above description and no specific limitation is given here. For ease of description, unless otherwise specified, the embodiments of the present invention are based on the example of the transistors in the first preset module 201 and the second preset module 202 being PMOS transistors to illustrate the technical solutions of the embodiments of the present invention.

[0088] It is also understandable that the first preset module and the second preset module of the pixel circuit can be any modules in the pixel circuit and can be selected according to actual needs. The pixel circuit and its preset modules mentioned in the embodiments of the present invention are exemplarily described below with typical examples.

[0089] In an optional embodiment, if Figure 12 As shown, the pixel circuit 20 may include a driving module 210, a data writing module 220, a compensation module 230 and a reset module 240; the driving module 210 may include a driving transistor T1; the data writing module 220 is electrically connected to the first electrode of the driving transistor T1; the compensation module 230 is electrically connected between the second electrode of the driving transistor T1 and the gate of the driving transistor T1; and the reset module 240 is electrically connected to the gate of the driving transistor T1.

[0090] The display panel 100 may further include a plurality of light-emitting elements 40, and the pixel circuits 20 are electrically connected to the light-emitting elements 40. The driver module 210 may selectively provide a driving current to the light-emitting elements 40 to drive the light-emitting elements 40 to emit light. The data writing module 220 is configured to provide a data signal Vdata to the driver module 210, so that the driver module 210 can generate a driving current for driving the light-emitting elements 40 to emit light based on the data signal Vdata. The reset module 240 is configured to provide a reset signal to the driver module 210 to reset the driver module 210. The compensation module 230 is configured to compensate for the data signal Vdata when the data writing module 220 provides the data signal Vdata to the driver module 210, thereby ensuring that the driver module 210 can provide an accurate driving current to the light-emitting elements 40 and control the light emission accuracy of the light-emitting elements 40.

[0091] It will be appreciated that since the light-emitting element 40 is typically a current-driven element, and the data signal Vdata provided by the data writing module 220 is typically a voltage signal, a driving transistor T1 is provided in the driving module 210 to write the data signal Vdata provided by the data writing module 220 to the gate of the driving transistor T1. This allows the driving transistor T1 to generate a corresponding driving current based on the signal at its gate and provide the current to the light-emitting element 40, thereby driving the light-emitting element 40 to emit light of a corresponding brightness. In this case, one of the source and drain of the driving transistor T1 receives the positive power signal PVDD, and the other is coupled to the anode of the light-emitting element 40. The cathode of the light-emitting element 40 can receive the negative power signal PVEE. Thus, a voltage difference exists between the positive power signal PVDD and the negative power signal PVEE, forming a current path. This allows the driving transistor T1 to generate a driving current and provide the current to the light-emitting element 40, thereby driving the light-emitting element 40 to emit light.

[0092] Continue to refer Figure 12 The driving cycle of the pixel circuit 20 may include a reset phase, a write phase and a light-emitting phase performed in sequence; in the reset phase, the reset module 240 may provide a reset signal Vref to the gate of the driving transistor T1 to reset the gate of the driving transistor T1; in the write phase, the data write module 220 may provide a data signal Vdata to the driving transistor T1, and at the same time, the compensation module 230 may supplement the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1; in the light-emitting phase, the driving module 210 provides a driving current to the light-emitting element 40 according to the gate signal of its driving transistor T1 to drive the light-emitting element 40 to emit light.

[0093] Among them, the control end of the reset module 240 can receive a first scanning signal, the first scanning signal controls the conduction and shutdown of the reset module 240, and can control the reset module 240 to be turned on during the effective pulse time period of the first scanning signal, so that the reset module 240 can write the reset signal Vref to the gate of the driving transistor T1; the control end of the data writing module 220 can receive a second scanning signal, the second scanning signal controls the conduction and shutdown of the data writing module 220, and can control the data writing module 220 to be turned on during the effective pulse time period of the second scanning signal, so that the data writing module 220 can control the data signal Vdata to be written to the driving module 210; the control end of the compensation module 230 can receive a third scanning signal, the third scanning signal controls the conduction and shutdown of the compensation module 230, and can control the compensation module 230 to be turned on during the effective pulse time period of the third scanning signal, so that the compensation module 230 can compensate the threshold voltage Vth of the driving transistor T1 to the gate of the driving transistor T1.

[0094] Combined with reference Figure 3 、 Figure 4 and Figure 12 The first preset module 201 may include a reset module 240, and the second preset module 202 may include a data writing module 220 and / or a compensation module 230. At this time, the first gate signal S1 may be used as a first scanning signal, and the second gate signal S2 may be used as a second scanning signal and / or a third scanning signal, that is, the reset modules 240 of at least some of the pixel circuits 20 located in the same row may be connected to the same first gate signal line 31, and the data writing modules 220 and / or the compensation modules 230 of at least some of the pixel circuits 20 located in the same row may be connected to the same second gate signal line 32. In this way, the first gate signal S1 transmitted by the first gate signal line 31 can control the reset module 240 to be turned on or off, and the second gate signal S2 transmitted by the second gate signal line 32 can control the data writing module 220 and / or the compensation module 230 to be turned on or off. Moreover, since the effective pulses of the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 are shifted in sequence, that is, the effective pulse time of the first gate signal S1 is before the effective pulse time of the second gate signal S2, so that within a driving cycle of the same pixel circuit 20, the on-time of the reset module 240 is before the on-time of the data writing module 220 and / or the compensation module 230, so that after the reset module 240 resets the driving transistor T1, the data signal Vdata and the threshold voltage of the driving transistor T1 are written to the gate of the driving transistor T1 through the data writing module 220 and the compensation module 230, so that the pixel circuit 20 can operate normally, and in the subsequent light-emitting stage, the pixel circuit 20 can accurately provide a driving circuit to the light-emitting element 40, so that the light-emitting element 40 can accurately emit light.

[0095] In an exemplary embodiment, the reset module 240 includes a reset transistor T4, a first electrode of the reset transistor T4 receives a reset signal Vref, a second electrode of the reset transistor T4 is electrically connected to the gate of the driving transistor T1, and the gate of the reset transistor T4 receives a first gate signal S1, so that the first gate signal S1 controls the conduction or shutdown of the reset transistor T4; the data writing module 220 may include a data writing transistor T2, a first electrode of the data writing transistor T2 receives a data signal Vdata, a second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, and the gate of the data writing transistor T2 receives a second gate signal S2, so that the second gate signal S2 controls the conduction or shutdown of the data writing transistor T2; the compensation module 230 includes a compensation transistor T3, a first electrode of the compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, a second electrode of the compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the compensation transistor T3 receives a second gate signal S2, so that the second gate signal S2 controls the conduction or shutdown of the compensation transistor T3.

[0096] Based on the above embodiment, the pixel circuit 20 may optionally further include an initialization module 250, which is connected to the anode of the light-emitting element 40 and is used to provide an initialization signal Vini to the light-emitting element 40 to initialize the anode of the light-emitting element 40. The initialization module 250 can be turned on or off under the control of the fourth scan signal, and when the fourth scan signal controls the initialization module 250 to be turned on, the initialization signal Vini can be provided to the anode of the light-emitting element 40. Before the light-emitting element 40 emits light, the initialization module 250 can be used to initialize the anode of the light-emitting element 40. In this case, the first gate signal S1 or the second gate signal S2 can also serve as the fourth scan signal to control the initialization module 250 to be turned on or off.

[0097] In an exemplary embodiment, the initialization module 250 may include an initialization transistor T5, a first electrode of the initialization transistor T5 receives the initialization signal Vini, a second electrode of the initialization transistor T5 is electrically connected to the anode of the light-emitting element 40, and a gate of the initialization transistor T5 receives a first gate signal S1 or a second gate signal S2, so that the first gate signal S1 or the second gate signal S2 can control the initialization transistor T5 to be turned on or off.

[0098] Based on the above embodiment, the pixel circuit 20 may optionally further include a light emission control module, which may include a first light emission control module 260 and a second light emission control module 270. The first light emission control module 260 and the second light emission control module 270 may control the current path between the positive power supply signal PVDD and the negative power supply signal PVEE, thereby controlling the time during which the driving transistor T1 provides the driving current to the light emitting element 40. The first light emission control module 260 and the second light emission control module 270 may be turned on or off under the control of the light emission control signal EM. When the light emission control signal EM controls the first light emission control module 260 and the second light emission control module 270 to be turned on, the driving transistor T1 may generate a driving current and provide the driving current to the light emitting element 40, thereby driving the light emitting element 40 to emit light.

[0099] In an exemplary embodiment, the first light-emitting control module 260 may include a first light-emitting control transistor T6, and the second light-emitting control module 270 may include a second light-emitting control transistor T7. The first electrode of the first light-emitting control transistor T6 receives a positive power supply signal PVDD, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T1, the first electrode of the second light-emitting control transistor T7 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the second light-emitting control transistor T7 is electrically connected to the anode of the light-emitting element 40. The gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T7 both receive a light-emitting control signal EM, so that the light-emitting control signal EM can control the first light-emitting control transistor T6 and the second light-emitting control transistor T7 to be turned on or off at the same time.

[0100] Based on the above embodiment, the pixel circuit 20 may further include a storage capacitor Cst, a first plate of which receives a fixed signal (e.g., a positive power supply signal PVDD), and a second plate is electrically connected to the gate of the driving transistor T1 to store the signal at the gate of the driving transistor T1.

[0101] It should be noted that Figure 12 The structure of the pixel circuit 20 is described for exemplary purposes only, but the structure of the pixel circuit 20 is not limited thereto. As long as the core invention of the embodiment of the present invention can be achieved, the embodiment of the present invention does not limit the specific structure of the pixel circuit.

[0102] Based on the above pixel circuit, the first gate signal S1 outputted from the first output terminal OUT1 of the shift register unit 101 in the embodiment of the present invention can control the on / off of the reset module 240, or the first gate signal S1 outputted from the first output terminal OUT1 can simultaneously control the on / off of the reset module 240 and the initialization module 250. The second gate signal S2 outputted from the second output terminal OUT2 of the shift register unit 101 can only control the on / off of the data write module 220 or the compensation module 230, or the second gate signal S2 outputted from the second output terminal OUT2 can simultaneously control the on / off of the data write module 220 and the compensation module 230. Taking the example of the first gate signal S1 being used to control the on / off of the reset module 240 and the initialization module 250, and the second gate signal S2 being used to control the on / off of the data write module 220 and the compensation module 230, the driving principle of the pixel circuit 20 is described below.

[0103] refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 12 When the working mode of the display panel 100 is the forward scanning mode, the first-stage shift register unit G1 to the n-th-stage shift register unit Gn respectively provide the first gate signal S1 to the reset module 240 and the initialization module 250 of the first to n-th rows of pixel circuits 20, and respectively provide the second gate signal S2 to the data writing module 220 and the compensation module 230 of the first to n-th rows of pixel circuits 20, so that the first to n-th rows of pixel circuits 20 can sequentially enter the reset and initialization phases, and the first to n-th rows of pixel circuits can sequentially enter the writing and compensation phases, and the reset and initialization phases of the pixel circuits 20 in the same row are located before their writing and compensation phases. For example, in the display time of one frame of the display panel 100, the reset and initialization phases of the pixel circuits 20 in the same row are located before their writing and compensation phases. The reset and initialization phase t11 of the first row of pixel circuits 20, the writing and compensation phase t21 of the first row of pixel circuits 20, the reset and initialization phase t12 of the second row of pixel circuits 20, the writing and compensation phase t22 of the second row of pixel circuits 20, ..., the reset and initialization phase t1n of the n-th row of pixel circuits 20, and the writing and compensation phase t2n of the n-th row of pixel circuits 20 are performed sequentially, and after the reset and initialization phase, and the writing and compensation phase of each row of pixel circuits 20, the light emitting phase of the row of pixel circuits 20 will be entered, so that the light emitting elements 40 electrically connected thereto from the first row to the n-th row of pixel circuits 20 will be driven in sequence to emit light, so that the display panel 100 presents a corresponding display screen in the positive scanning mode.

[0104] refer to Figure 3 、 Figure 4 、 Figure 6 and Figure 12When the working mode of the display panel 100 is the reverse scan mode, the n-th stage shift register unit Gn to the first stage shift register unit G1 will respectively provide the first gate signal S1 to the reset module 240 and the initialization module 250 of the n-th row to the first row pixel circuit 20, and respectively provide the second gate signal S2 to the data writing module 220 and the compensation module 230 of the n-th row to the first row pixel circuit 20, so that the n-th row to the first row pixel circuit 20 can sequentially enter the reset and initialization phases, and the n-th row to the first row pixel circuit can sequentially enter the writing and compensation phases, and the reset and initialization phases of the pixel circuits 20 in the same row are located before their writing and compensation phases. For example, in the display time of one frame of the display panel 100, the reset and initialization phases of the pixel circuits 20 in the same row are located before their writing and compensation phases. The reset and initialization phase t1n of the n-th row pixel circuit 20, the writing and compensation phase t2n of the n-th row pixel circuit 20, ..., the reset and initialization phase t12 of the second row pixel circuit 20, the writing and compensation phase t22 of the second row pixel circuit 20, the reset and initialization phase t11 of the first row pixel circuit 20, and the writing and compensation phase t21 of the first row pixel circuit 20 are performed again, and after the reset and initialization phase, and the writing and compensation phase of each row pixel circuit 20, the light emitting phase of the row pixel circuit 20 will be entered, so that the light emitting elements 40 electrically connected to them from the n-th row to the first row pixel circuits 20 will be driven in sequence to emit light, so that the display panel 100 presents a corresponding display screen in the reverse scanning mode.

[0105] In this embodiment, a first output module, a second output module, a first output terminal, and a second output terminal are respectively provided in the shift register unit of the driving circuit, and the first output module controls the first gate signal output by the first output terminal, and the second output module controls the second gate signal output by the second output terminal, so that the effective pulses of the first gate signal and the second gate signal output by the same shift register unit can be shifted in sequence, that is, each shift register unit can output two gate driving signals that are shifted in sequence, so as to be able to control the turning on and off of at least two modules that are not turned on at the same time in the same pixel circuit, without the need to separately provide corresponding shift register units, thereby facilitating a reduction in the number of shift register units in the driving circuit, thereby reducing the occupied space of the driving circuit, and further facilitating a narrow frame of the display panel and improving the display effect of the display panel; at the same time, by electrically connecting the first output terminal or the second output terminal of the x-th shift register unit to the positive input terminal of the y-th shift register unit, the negative input terminal of the y-th shift register unit is connected to the k-th shift register unit. The first output end or the second output end of the shift register unit is electrically connected so that when the working mode of the display panel is the forward scan mode, the shift register units at each stage can, under the control of the signal received at the forward input end, the clock signal at each clock end and the forward scan control signal at the forward control end, enable the first-stage shift register unit to the n-stage shift register unit to sequentially output the effective level of the first gate signal and the effective level of the second gate signal; and when the working mode of the display panel is the reverse scan mode, the shift register units at each stage can, under the control of the signal received at the reverse input end, the clock signal at each clock end and the reverse scan control signal at the reverse control end, enable the n-stage shift register unit to the first-stage shift register unit to sequentially output the effective level of the first gate signal and the effective level of the second gate signal, that is, the first gate signal and the second gate signal output by the shift register units at each stage in the driving circuit can cooperate with the forward scan mode and the reverse scan mode of the display panel, so that the driving circuit has forward and reverse scan functions. In this way, while ensuring that the driving circuit has a small size, the driving circuit has forward and reverse scanning functions, meeting the scanning requirements of the display panel in different modes, broadening the application scenarios of the display panel, and improving the display effect of the display panel.

[0106] It should be understood that the above description is merely an exemplary description of the shift register unit and the manner in which the shift register unit provides the first gate signal and the second gate signal to the pixel circuit. The present invention does not impose any specific limitations on this description, provided that the core features of the present invention can be achieved. To more clearly explain the present invention, a typical example of a shift register unit is described below.

[0107] Optional, Figure 13 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 13 As shown, the scan control module 110 includes a forward scan control transistor M11 and a reverse scan control transistor M12; the gate of the forward scan control transistor M11 is electrically connected to the forward control terminal U2D, the first electrode of the forward scan control transistor M11 is electrically connected to the forward input terminal INF, and the second electrode of the forward scan control transistor M11 is electrically connected to the input node Q0; the gate of the reverse scan control transistor M12 is electrically connected to the reverse control terminal D2U, the first electrode of the reverse scan control transistor M12 is electrically connected to the reverse input terminal INB, and the second electrode of the reverse scan control transistor M12 is electrically connected to the input node Q0.

[0108] Among them, the forward scan control signal u2d of the forward control terminal U2D can control the forward scan control transistor M11 to be turned on or off, and when the forward scan control signal u2d is at an effective level, the forward scan control transistor M11 can be controlled to be turned on, and the forward scan control transistor M11 can transmit the forward input signal Vinf of the forward input terminal INF to the input node Q0, so that the signal of the input node Q0 can be consistent with the forward input signal Vinf. The reverse scan control signal d2u of the reverse control terminal D2U can control the reverse scan control transistor M12 to be turned on or off, and when the reverse scan control signal d2u is at an effective level, the reverse scan control transistor M12 can be controlled to be turned on, and the reverse scan control transistor M12 can transmit the reverse input signal Vinb of the reverse input terminal INB to the input node Q0, so that the signal of the input node Q0 can be consistent with the reverse input signal Vinb.

[0109] In the forward scan mode, the forward scan control signal u2d is at a valid level, and the reverse scan control signal d2u is at an invalid level, so that the signal at the input node Q0 in the forward scan mode can be consistent with the forward input signal Vinf; and in the reverse scan mode, the reverse scan control signal d2u is at a valid level, and the forward scan control signal u2d is at an invalid level, so that the signal at the input node Q0 in the reverse scan mode can be consistent with the reverse input signal Vinb.

[0110] Since the positive input terminal INF of the y-th stage shift register unit Gy is electrically connected to the first input terminal OUT1 or the second output terminal OUT2 of the x-th stage shift register unit Gx, and the negative input terminal INB of the y-th stage shift register unit Gy is electrically connected to the first input terminal OUT1 or the second output terminal OUT2 of the k-th stage shift register unit Gk, in the forward scanning mode, the signal of the input node Q0 of the y-th stage shift register unit Gy can be consistent with the first gate signal S1x or the second gate signal S2x output by the x-th stage shift register unit Gx, and in the reverse scanning mode, the signal of the input node Q0 of the y-th stage shift register unit Gy can be consistent with the first gate signal S1x or the second gate signal S2x output by the x-th stage shift register unit Gx. The signal of the input node Q0 of the element Gy can be consistent with the first gate signal S1k or the second gate signal S2k output by the k-th shift register unit Gk, thereby realizing sequential shifting of the effective pulses of the first gate signal S1 output from the first-stage shift register unit G1 to the n-th-stage shift register unit Gn, and sequential shifting of the effective pulses of the second gate signal S2 in the forward scanning mode, and realizing sequential shifting of the effective pulses of the first gate signal S1 output from the n-th-stage shift register unit Gn to the first-stage shift register unit G1, and sequential shifting of the effective pulses of the second gate signal S2 in the reverse scanning mode.

[0111] Optional, Figure 14 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 14 As shown, the driving control module 120 includes a first node control submodule 121, a second node control submodule 122 and a node mutual control submodule 123; the shift register unit 101 also includes a fourth clock terminal CK4, a first level terminal VGL and a second level terminal VGH; in the same shift register unit 101, the first node control submodule 121 is electrically connected to the input node Q0, the first clock terminal CK1 and the first node Q1 respectively; the second node control submodule 122 is electrically connected to the first clock terminal CK1, the first level terminal VGL and the second node Q2 respectively; the node mutual control submodule 123 is electrically connected to the second level terminal VGH, the first node Q1, the second node Q2, the first clock terminal CK1 and the fourth clock terminal CK4 respectively; wherein, the effective pulse time of the fourth clock signal ck4 received by the fourth clock terminal CK4 does not overlap with the effective pulse time of the first clock signal ck1 received by the first clock terminal CK1.

[0112] It can be understood that the first level terminal VGL can receive the first level signal Vgl, and the second level terminal VGH can receive the second level signal Vgh. The polarity of the first level signal Vgl and the second level signal Vgh can be opposite, that is, when the first level signal Vgl is at a low level, the second level signal Vgh is at a high level; or, when the first level signal Vgl is at a high level, the second level signal Vgh can be at a low level.

[0113] It is also understood that the fourth clock signal ck4 can also include a high level and a low level that vary with a certain clock cycle, and the effective level of the fourth clock signal ck4 can be a high level or a low level, which can be specifically designed according to actual needs. The embodiments of the present invention are all described by exemplifying the technical solutions of the embodiments of the present invention using the effective level of the fourth clock signal ck4 being a low level. At the same time, during the effective pulse period of the fourth clock signal ck4, the fourth clock signal ck4 will remain at an effective level, and during the remaining time periods, the fourth clock signal ck4 will remain at an inactive level.

[0114] In addition, since the valid pulse time of the first clock signal ck1 does not overlap with the valid pulse time of the fourth clock signal ck4, when the fourth clock signal ck4 is at a valid level, the first clock signal ck1 is at an invalid level, and when the first clock signal ck1 is at a valid level, the fourth clock signal ck4 is at an invalid level.

[0115] Among them, continue to refer to Figure 14 The first node control submodule 121 is electrically connected to the input node Q0, the first clock terminal CK1 and the first node Q1, respectively, so that the first node control submodule 121 can control the signal of the first node Q1 according to the signal of the input node Q0 and the first clock signal ck1 of the first clock terminal CK1. For example, the first node control submodule 121 can be turned on or off under the control of the first clock signal ck1, and when the first clock signal ck1 is at a valid level, the first node control submodule 121 is controlled to be turned on, so that the signal of the input node Q0 can be transmitted to the first node Q1, and the signal of the first node Q1 can be consistent with the signal of the input node Q0; conversely, when the first clock signal ck1 is at an invalid level, the first node control submodule 121 is controlled to be turned off, so that the signal of the input node Q0 cannot be transmitted to the first node Q1, and the signal of the first node Q1 will remain unchanged under the premise that no other signals are written.

[0116] In an exemplary embodiment, if Figure 15As shown, the first node control submodule 121 may include a first node control transistor M21. The gate of the first node control transistor M21 may be electrically connected to the first clock terminal CK1, the first electrode of the first node control transistor M21 may be electrically connected to the input node Q0, and the second electrode of the first node control transistor M21 may be electrically connected to the first node Q1. In this way, the first node control transistor M21 may be turned on or off under the control of the first clock signal ck1 of the first clock terminal CK1. When the first clock signal ck1 controls the first node control transistor M21 to be turned on, the input node Q0 and the first node Q1 may be controlled to form a conductive path, so that the signal of the input node Q0 is transmitted to the first node Q1, and the signal of the first node Q1 remains consistent with the signal of the input node Q0.

[0117] In an optional embodiment, if Figure 16 As shown, the first node control transistor M21 may be a dual-gate transistor. In this case, the first node control transistor M21 may have a lower leakage current, thereby ensuring the accuracy of the signal at the first node Q1.

[0118] In other optional embodiments, other transistors involved in the shift register unit 101 may also be dual-gate transistors, so that each dual-gate transistor in the shift register unit 101 has a lower leakage current, thereby ensuring the accuracy of the signal at each node in the shift register unit 101. The specific structure of each transistor in the shift register unit 101 can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this. For ease of description, without special limitations, the embodiment of the present invention takes the case where each transistor in the shift register unit is a single-gate transistor as an example to exemplify the technical solutions of the embodiment of the present invention.

[0119] Continue to refer Figure 14 The second node control submodule 122 is electrically connected to the first clock terminal CK1, the first level terminal VGL and the second node Q2, respectively, so that the second node control submodule 122 can control the signal of the second node Q2 according to the first clock signal ck1 of the first clock terminal CK1 and the first level signal vgl of the first level terminal VGL. For example, the second node control submodule 122 can be turned on or off under the control of the first clock signal ck1, and when the first clock signal ck1 is at a valid level, the second node control submodule 122 is controlled to be turned on, so that the first level signal Vgl can be transmitted to the second node Q2, and the signal of the second node Q2 can be consistent with the first level signal Vgl; conversely, when the first clock signal ck1 is at an invalid level, the second node control submodule 122 is controlled to be turned off, so that the first level signal Vgl cannot be transmitted to the second node Q2. Under the premise that no other signals are written, the signal of the second node Q2 will remain unchanged.

[0120] In an exemplary embodiment, if Figure 15 As shown, the second node control submodule 122 may include a second node control transistor M22. The gate of the second node control transistor M22 may be electrically connected to the first clock terminal CK1, the first electrode of the second node control transistor M22 may be electrically connected to the first level terminal VGL, and the second electrode of the second node control transistor M22 may be electrically connected to the second node Q2. In this way, the second node control transistor M22 may be turned on or off under the control of the first clock signal ck1 of the first clock terminal CK1. When the first clock signal ck1 controls the second node control transistor M22 to be turned on, the first level signal Vgl may be controlled to be transmitted to the second node Q2, and the first level signal Vgl of the second node Q2 may remain consistent.

[0121] Continue to refer Figure 14 The node mutual control submodule 123 is electrically connected to the second level terminal VGH, the first node Q1, the second node Q2, the first clock terminal CK1 and the fourth clock terminal CK4, respectively, so that the node mutual control submodule 123 can control the signal of the second node Q2 according to the signal of the first node Q1 and the first clock signal ck1 of the first clock terminal CK1, and control the signal of the first node Q1 according to the second level signal Vgh of the second level terminal VGH, the signal of the second node Q1 and the fourth clock signal ck4 of the fourth clock terminal CK4, so that the signals of the first node Q1 and the second node Q2 clamp each other, ensuring that at least part of the time when the signal of the first node Q1 has a certain level does not overlap with the effective level time of the signal of the second node Q2.

[0122] In an exemplary embodiment, if Figure 15 As shown, the node mutual control submodule 123 may include a first node mutual control transistor M23, a second node mutual control transistor M24, and a third node mutual control transistor M25. The gate of the first node mutual control transistor M23 may be electrically connected to the first node Q1, the first electrode of the first node mutual control transistor M23 may be electrically connected to the first clock terminal CK1, and the second electrode of the first node mutual control transistor M23 may be electrically connected to the second node Q2; the gate of the second node mutual control transistor M24 may be electrically connected to the second node Q2, the first electrode of the second node mutual control transistor M24 may be electrically connected to the second level terminal VGH, and the second electrode of the second node mutual control transistor M24 may be electrically connected to the first electrode of the third node mutual control transistor M25; the gate of the third node mutual control transistor M25 may be electrically connected to the fourth clock terminal CK4, and the second electrode of the third node mutual control transistor M25 may be electrically connected to the first node Q1.

[0123] During the time period when the signal at the first node Q1 is at an active level, the first-node mutual-controlled transistor M23 can be controlled to be in a conductive state, so that the first-node mutual-controlled transistor can transmit the first clock signal ck1 to the second node Q2. The signal at the second node Q2 remains consistent with the first clock signal ck1. That is, when the first clock signal ck1 is at an active level, the signal at the second node Q2 is at an active level, and when the first clock signal ck1 is at an inactive level, the signal at the second node Q2 also changes to an inactive level. Correspondingly, when the signal at the second node Q2 is at an active level, the third-node mutual-controlled transistor M25 is in a conductive state, so that the second-level signal Vgh can be transmitted to the first electrode of the second-node mutual-controlled transistor M24. At this time, if the fourth clock signal ck4 is at an active level, the second-node mutual-controlled transistor M24 can be in a conductive state, so that the second-level signal Vgh transmitted to the first electrode of the second-node mutual-controlled transistor M24 can be further transmitted to the first node Q1, so that the signal at the first node Q1 remains consistent with the second-level signal Vgh, and the signal at the first node Q1 is at an inactive level. In this way, during at least part of the time when the signal of the first node Q1 is at a valid level, the signal of the second node Q2 will remain at an invalid level, and during at least part of the time when the signal of the second node Q2 is at a valid level, the signal of the first node Q1 can remain at an invalid level, so that the signal of the first node Q1 and the signal of the second node Q2 can control each other, ensuring that the first output module 130 electrically connected to the first node Q1 and the second node Q2 respectively can stably output the first gate signal S1, and the second output module 140 can stably output the second gate signal S2.

[0124] It can be understood that since the node mutual control submodule 123 can control the signal of the second node Q2 according to the first clock signal ck1 and the signal of the first node Q1, and control the signal of the first node Q1 according to the second level signal Vgh, the fourth clock signal ck4, and the signal of the second node Q2, in order to ensure that the signals of the first node Q1 and the second node Q2 can control each other and do not interfere with each other, the effective level time of the first clock signal ck1 and the effective level time of the fourth clock signal ck4 can be set not to overlap, so that when the first clock signal ck1 is at a valid level, the fourth clock signal ck4 is at an invalid level, so that when the first node mutual control transistor M23 transmits the effective level of the first clock signal ck1 to the second node Q2, the second node mutual control transistor M24 can be in a closed state, preventing the second level signal Vgh from being transmitted to the first node Q1 and affecting the accuracy of the signal of the first node Q1; accordingly, when the fourth clock signal ck4 is at a valid level, the first clock signal ck1 is at an invalid level, so that during the time period when the second level signal Vgh is transmitted to the first node Q1 through the third node mutual control transistor M25 and the second node mutual control transistor M24, it affects the signal of the second node Q2.

[0125] Furthermore, to ensure that the valid pulses of the first gate signal S1 output by each shift register unit 101 are sequentially shifted, as well as the valid pulses of the second gate signal S2 output by each shift register unit 101, when the first gate signal S1 or the second gate signal of the shift register unit 101 cascaded with the current shift register unit 101 is at an active level, the signal at the input node Q0 is at an active level, and the first clock signal ck1 is at an active level. This allows the first clock signal ck1 to control the first node control submodule 121 to be in a conductive state, and the signal at the input node Q0 is transmitted to the first node Q1 to charge the first node Q1. At this time, the second clock signal ck2 and the third clock signal ck3 can remain at an inactive level, allowing both the first gate signal S1 and the second gate signal S2 to remain at an inactive level. After charging the first node Q1, the first clock signal ck1 transitions to an inactive level. At this point, the second clock signal ck2 and the third clock signal ck3 can be sequentially controlled to transition to active levels, allowing the valid pulses of the first gate signal S1 and the second gate signal S2 to be sequentially output. Thus, the effective pulse times of the first clock signal ck1 , the second clock signal ck2 and the third clock signal ck3 do not overlap. For example, within one clock cycle, the effective pulse times of the first clock signal ck1 , the second clock signal ck2 and the third clock signal ck3 are shifted sequentially.

[0126] Accordingly, since the effective pulse time of the fourth clock signal ck4 does not overlap with the effective pulse time of the first clock signal ck1, the effective pulse times of the second clock signal ck2 and the third clock signal ck3 do not overlap with the effective pulse time of the first clock signal ck1. In this case, in an optional embodiment, when the second clock terminal CK2 is used to receive the second clock signal ck2 and the third clock terminal CK3 is used to receive the third clock signal ck3, the fourth clock signal ck4 can be the same as the second clock signal ck2 or the third clock signal ck3, and the fourth clock terminal CK4 can reuse the second clock terminal CK2 or the third clock terminal CK3. In this way, the number of clock terminals provided in the shift register unit 101 can be reduced, and the number of clock signals provided to the same shift register unit 101 can be reduced, thereby simplifying the structure of the shift register unit and reducing the number of signal transmission lines used to transmit clock signals, which in turn is conducive to a narrow frame of the display panel.

[0127] It should be noted that the above description is only an example of the structure of the drive control module 120. On the premise that the drive control module 120 can accurately control the signals of the first node Q1 and the second node Q2, the embodiment of the present invention does not limit the specific structure of the drive control module 120.

[0128] Optional, such as Figure 15 As shown, the first output module 130 may include a first output transistor M31 and a second output transistor M32; at this time, the shift register unit 101 may further include a second level terminal VGH; in the same shift register unit 101, the gate of the first output transistor M31 is electrically connected to the first node Q1, the first electrode of the first output transistor M31 is electrically connected to the second clock terminal CK2, and the second electrode of the first output transistor M31 is electrically connected to the first output terminal OUT1; the gate of the second output transistor M32 is electrically connected to the second node Q2, the first electrode of the second output transistor M32 is electrically connected to the second level terminal VGH, and the second electrode of the second output transistor M32 is electrically connected to the first output terminal OUT1.

[0129] The signal at the first node Q1 can control the on / off state of the first output transistor M31. When the signal at the first node Q1 is at an active level, the first output transistor M31 can be turned on, allowing the second clock signal ck2 at the second clock terminal CK2 to be transmitted to the first output terminal OUT1, so that the first gate signal S1 outputted from the first output terminal OUT1 is consistent with the second clock signal ck2. The signal at the second node Q2 can control the on / off state of the second output transistor M32. When the signal at the second node Q2 is at an active level, the second output transistor M32 can be turned on, allowing the second level signal Vgh at the second level terminal VGH to be transmitted to the first output terminal OUT1, so that the first gate signal S1 outputted from the first output terminal OUT1 is consistent with the second level signal Vgh. In this way, by controlling the signals at the first node Q1 and the second node Q2, the on-times of the first output transistor M31 and the second output transistor M32 can be controlled, thereby controlling the effective pulse time of the first gate signal S1 outputted from the first output terminal OUT1.

[0130] Optional, continue to refer to Figure 15 , the second output module 140 includes a third output transistor M41 and a fourth output transistor M42; at this time, the shift register unit 101 also includes a second level terminal VGH; in the same shift register unit 101, the gate of the third output transistor M41 is electrically connected to the first node Q1, the first electrode of the third output transistor M41 is electrically connected to the third clock terminal CK3, and the second electrode of the third output transistor M41 is electrically connected to the second output terminal OUT2; the gate of the fourth output transistor M42 is electrically connected to the second node Q2, the first electrode of the fourth output transistor M42 is electrically connected to the second level terminal VGH, and the second electrode of the fourth output transistor M42 is electrically connected to the second output terminal OUT2.

[0131] The signal at the first node Q1 can control the on / off state of the third output transistor M41. When the signal at the first node Q1 is at an active level, the third output transistor M41 can be turned on, allowing the third clock signal ck3 from the third clock terminal CK3 to be transmitted to the second output terminal OUT2, so that the second gate signal S2 output from the second output terminal OUT2 is consistent with the third clock signal ck3. The signal at the second node Q2 can control the on / off state of the fourth output transistor M42. When the signal at the second node Q2 is at an active level, the fourth output transistor M42 can be turned on, allowing the second level signal Vgh from the second level terminal VGH to be transmitted to the second output terminal OUT2, so that the second gate signal S2 output from the second output terminal OUT2 is consistent with the second level signal Vgh. In this way, by controlling the signals at the first node Q1 and the second node Q2, the on-times of the third output transistor M41 and the fourth output transistor M42 can be controlled, thereby controlling the effective pulse time of the second gate signal S2 output from the second output terminal OUT2.

[0132] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the working process of the shift register unit is exemplarily described below using a typical example.

[0133] Figure 17 : is a driving timing diagram of a shift register unit in a forward scanning mode provided by an embodiment of the present invention. Figure 18 This is a driving timing diagram of a shift register unit in a reverse scan mode provided by an embodiment of the present invention, referring to Figure 15 、 Figure 17 and Figure 18 The driving cycle of the shift register unit 101 includes a t1 phase, a t2 phase, a t3 phase and a t4 phase.

[0134] refer to Figure 15 and Figure 17 In the forward scan mode, the forward scan control signal u2d received by the forward control terminal U2D is at a valid level, and the reverse scan control signal d2u received by the reverse control terminal D2U is at an invalid level. At this time, the forward scan control transistor M11 is turned on and the reverse scan control transistor M12 is turned off, so that the signal of the input node Q0 is consistent with the forward input signal Vinf of the forward input terminal INF.

[0135] Before stage t1, the forward input signal Vinf is at an invalid level, so that the signal of the input node Q0 is at an invalid level. When the first clock signal ck1 is at an effective level, the first node control transistor M21 and the second node control transistor M22 are controlled to be turned on, so that the signal of the first node Q1 is consistent with the signal of the input node Q0, and the signal of the second node Q2 is consistent with the first level signal Vgl, that is, the signal of the first node Q1 is an invalid circuit, and the signal of the second node Q2 is at an effective level. The first output transistor M31 and the third output transistor M41 are both in the off state, the second output transistor M32 and the fourth output transistor M42 are both in the on state, and the first gate signal S1 output by the first output terminal OUT1 and the second gate signal S2 output by the second output terminal OUT1 are both consistent with the second level signal Vgh, that is, the first gate signal S1 and the second gate signal S2 are both at an invalid level.

[0136] In the t1 phase, the positive input signal Vinf is at a valid level, the first clock signal ck1 is at a valid level, the second clock signal ck2, the third clock signal ck3 and the fourth clock signal ck4 are at an invalid level, the signal of the input node Q0 is at a valid level, the valid level of the input node Q0 can be transmitted to the first node Q1, the signal of the first node Q1 becomes a valid level, the first output transistor M31 and the third output transistor M41 are turned on, the first gate signal S1 is consistent with the second clock signal ck2, and the second gate signal S2 is consistent with the third clock signal ck3, so that the first gate signal S1 and the second gate signal S2 are both kept at an invalid level. At the same time, the first level signal Vgl is transmitted to the second node Q2, and because the first node Q1 is at a valid level, the first node mutual-controlled transistor M23 is turned on, so that the valid level of the first clock signal ck1 is also transmitted to the second node Q2, the second node Q2 is at a valid level, the second output transistor M32 and the fourth output transistor M42 are also in a turned-on state, and the second level signal Vgh of the second level terminal VGH is also transmitted to the first output terminal OUT1 and the second output terminal OUT2, so that the first output terminal OUT1 outputs the invalid level of the first gate signal S1, and the second output terminal OUT2 outputs the invalid level of the second gate signal S2.

[0137] In the t2 phase, the forward input signal Vinf is at an invalid level, the first clock signal ck1 and the third clock signal ck3 are at an invalid level, the second clock signal ck2 and the fourth clock signal ck4 are at an effective level, the first node control transistor M21 and the second node control transistor M22 are both in a closed state, the invalid level of the input node Q0 cannot be transmitted to the first node Q1, and the first level signal Vgl cannot be transmitted to the second node Q2, and the signal of the first node Q1 can be maintained at an effective level; at the same time, the signal of the first node Q1 controls the first node mutual control transistor M23 to be turned on, so that the invalid level of the first clock signal ck1 is transmitted to the second node Q2, so that the signal of the second node Q2 becomes an invalid level, and the third node mutual control transistor M 25 is in the off state. At this time, even if the fourth clock signal ck4 controls the second-node mutual-controlled transistor M24 to be turned on, the second-level signal Vgh cannot be transmitted to the first node Q1, so that the first node Q1 can maintain a valid level. At this time, the signal of the first node Q1 can control the first output transistor M31 and the third output transistor M41 to be turned on, and the signal of the second node Q2 controls the second output transistor M32 and the fourth output transistor M42 to be turned off, so that the first gate signal S1 output by the first output terminal OUT1 is consistent with the second clock signal ck2, and the second gate signal S2 output by the second output terminal OUT2 is consistent with the third clock signal ck3, that is, the first gate signal S1 is at a valid level, and the second gate signal is at an invalid level.

[0138] In the t3 stage, the forward input signal Vinf maintains an invalid level, the first clock signal ck1, the second clock signal ck2 and the fourth clock signal ck4 are invalid levels, and the third clock signal ck3 is valid level. Under the premise that no new signal is written, the signal of the first node Q1 remains at a valid level, the signal of the second node Q2 remains at an invalid level, the first output transistor M31 and the third output transistor M41 continue to remain in the on state, the second output transistor M32 and the fourth output transistor M42 continue to remain in the off state, the first gate signal S1 becomes an invalid level, and the second gate signal S2 becomes a valid level.

[0139] In the t4 phase, the forward input signal Vinf maintains an invalid level, the first clock signal ck1 is an effective level, the second clock signal ck2, the third clock signal ck3 and the fourth clock signal ck4 are invalid levels, so that the first node control transistor M21 and the second node control transistor M22 are turned on again, the invalid level of the input node Q0 is transmitted to the first node Q1, the first level signal Vgl is transmitted to the second node Q2, so that the signal of the first node Q1 becomes an invalid level, and the signal of the second node Q2 becomes an effective level, the first output transistor M31 and the third output transistor M41 are turned off, the second output transistor M32 and the fourth output transistor M42 are turned on, and the second level signal Vgh is transmitted to the first output terminal OUT1 and the second output terminal OUT2, so that the first output terminal OUT1 outputs the invalid level of the first gate signal S1, and the second output terminal OUT2 outputs the invalid level of the second gate signal S2.

[0140] After stage t4, the positive input signal Vinf continues to remain at an invalid level, so that under the control of the first clock signal ck1 and the fourth clock signal ck4, the invalid level signal can be continuously supplemented to the first node Q1, and the signal of the second node Q2 will jump between the valid level and the invalid level until entering the next driving cycle.

[0141] In this way, in the positive scan mode, the shift register unit 101 can control the effective pulses of the first gate signal S1 output by the first output terminal OUT1 and the second gate signal S2 output by the second output terminal OUT2 to shift in sequence based on the positive input signal Vinf of the positive input terminal INF, the first clock signal ck1, the second clock signal ck2, the third clock signal ck3 and the fourth clock signal ck4, to ensure that in the positive scan mode, the pixel circuit electrically connected to the shift register unit 101 can operate normally, so that the display panel can accurately display the picture.

[0142] Accordingly, reference Figure 15 and Figure 18 In the reverse scan mode, the forward scan control signal u2d received by the forward control terminal U2D is at an invalid level, and the reverse scan control signal d2u received by the reverse control terminal D2U is at a valid level. At this time, the reverse scan control transistor M12 is turned on and the forward scan control transistor M11 is turned off, so that the signal of the input node Q0 is consistent with the reverse input signal Vinb of the reverse input terminal INB.

[0143] The driving process of the shift register unit 101 in the reverse scanning mode is similar to that in the forward scanning mode. For details, please refer to the above description of the driving process of the shift register unit 101 in the forward scanning mode, which will not be repeated here.

[0144] It can be understood that in the reverse scan mode, the shift register unit 101 can control the effective pulses of the first gate signal S1 output by the first output terminal OUT1 and the second gate signal S2 output by the second output terminal OUT2 to shift in sequence based on the reverse input signal Vinb of the reverse input terminal INB, the first clock signal ck1, the second clock signal ck2, the third clock signal ck3 and the fourth clock signal ck4, to ensure that in the reverse scan mode, the pixel circuit electrically connected to the shift register unit 101 can operate normally, so that the display panel can accurately display the picture.

[0145] Based on the above embodiment, optionally, Figure 19 is a structural diagram of another shift register unit provided by an embodiment of the present invention. Figure 20 is a structural diagram of another shift register unit provided by an embodiment of the present invention. Figure 21 This is a structural diagram of another shift register unit provided by an embodiment of the present invention, referring to Figures 19 to 21 The shift register unit 101 further includes a first voltage stabilizing module 151 . In the same shift register unit 101 , the first output module 130 and / or the second output module 140 are electrically connected to the first node Q1 through the first voltage stabilizing module 151 .

[0146] Among them, when the first output module 130 includes a first output transistor M31 and a second output transistor M32, and the second output module 140 includes a third output transistor M41 and a fourth output transistor M42, the first output module 130 and / or the second output module 140 is electrically connected to the first node Q1 through the first voltage stabilizing module 151. It can be understood that the gate of the first output transistor M31 and / or the gate of the third output transistor M41 is electrically connected to the first node Q1 through the first voltage stabilizing module 151. At this time, the node to which the gate of the first output transistor M31 and / or the gate of the third output transistor M41 is electrically connected is a different node from the first node Q1, so that the first voltage stabilizing module 151 can isolate the gate of the first output transistor M31 and / or the gate of the third output transistor M41 from the first node Q1. The gate of the output transistor M41 and the first node Q1 ensure that the signals of the first node Q1 and the gate of the first output transistor M31 and / or the gate of the third output transistor M41 are relatively stable, thereby preventing the signal fluctuation of the first node Q1 from affecting the signal of the gate of the first output transistor M31 and / or the gate of the third output transistor M41, or the signal fluctuation of the gate of the first output transistor M31 and / or the gate of the third output transistor M41 from affecting the signal of the first node Q1, thereby affecting the accuracy of the first gate signal S1 output by the first output terminal OUT1 and / or the second gate signal S2 output by the second output terminal OUT2, thereby facilitating the improvement of the working stability of the shift register unit 101 and the improvement of the display effect of the display panel.

[0147] In an exemplary embodiment, the first voltage stabilizing module 151 may include a first voltage stabilizing transistor M51, a first electrode of the first voltage stabilizing transistor M51 may be electrically connected to the first node Q1, a second electrode of the first voltage stabilizing transistor M51 may be electrically connected to the first output module 130 and / or the second output module 140, for example, the second electrode of the first voltage stabilizing transistor M51 may be electrically connected to the gate of the first output transistor M31 and / or the gate of the third output transistor M41, the gate of the first voltage stabilizing transistor M51 may receive a first voltage stabilizing control signal, and when the signal at the first node Q1 and the signal at the gate of the first output transistor M31 and / or the gate of the third output transistor M41 are both within the normal signal range, the first voltage stabilizing control signal may control the first voltage stabilizing transistor M51 to be in an on state.

[0148] The first voltage-stabilizing transistor M51 may be an N-type transistor or a P-type transistor, and may be specifically designed according to actual needs, which is not specifically limited in the embodiments of the present invention. Taking the first voltage-stabilizing transistor M51 as a P-type transistor as an example, the first voltage-stabilizing control signal may be a low-level signal. In this case, the first voltage-stabilizing control signal may reuse the first-level signal Vgl of the first level terminal VGL, thereby reducing the number of signals provided to the shift register unit 101 and reducing the driving cost of the shift register unit 101.

[0149] It is understandable that the first output module 130 and / or the second output module 140 are electrically connected to the first node Q1 through the first voltage stabilizing module 151, that is, Figure 19 As shown, the first output module 130 and the second output module 140 are both indirectly electrically connected to the first node Q1 through the first voltage stabilizing module 151, or as shown in FIG. Figure 20 As shown, the first output module 130 is indirectly electrically connected to the first node Q1 through the first voltage stabilizing module 151, and the second output module 140 can be directly electrically connected to the first node Q1, or, as shown in FIG. Figure 21 As shown, the second output module 140 is indirectly electrically connected to the first node Q1 via the first voltage stabilizing module 151, while the first output module 130 is directly electrically connected to the first node Q1. The connection method between the first output module 130 and the second output module 140 and the first node Q1 can be designed according to actual needs and is not specifically limited in this embodiment of the present invention.

[0150] In another alternative embodiment, Figure 22 is a structural diagram of another shift register unit provided by an embodiment of the present invention, such as Figure 22As shown, the shift register unit 101 may further include a second voltage stabilizing module 152 and a third voltage stabilizing module 153. In the same shift register unit 101, the first output module 130 is electrically connected to the first node Q1 via the second voltage stabilizing module 152; and the second output module 140 is electrically connected to the first node Q1 via the third voltage stabilizing module 153. In this case, the first output module 130 and the second output module 140 are indirectly electrically connected to the first node Q1 via different voltage stabilizing modules (i.e., the second voltage stabilizing module 152 and the third voltage stabilizing module 153), respectively.

[0151] Specifically, by providing a second voltage stabilizing module 152 between the first output module 130 and the first node Q1, the second voltage stabilizing module 152 can ensure that the signal at the first node Q1 and the signal at the node directly electrically connected to the first output module 130 remain relatively stable, allowing the first output module 130 to accurately control the first output terminal OUT1 to output the first gate signal S1. Simultaneously, by providing a third output module 153 between the second output module 140 and the first node Q1, the third output module 153 can ensure that the signal at the first node Q1 and the signal at the node directly electrically connected to the second output module 140 remain relatively stable, allowing the second output module 140 to accurately control the second output terminal OUT2 to output the second gate signal S2. In this way, when the first gate signal S1 and the second gate signal S2 control the operation of the pixel circuit in the display panel, the corresponding signals can be accurately written into the pixel circuit, ensuring that the pixel circuit can control the light-emitting element to accurately emit light, thereby facilitating an improved display effect of the display panel.

[0152] In an optional embodiment, the second voltage stabilizing module 152 may include a second voltage stabilizing transistor M52, a gate of which may receive a second voltage stabilizing control signal, a first electrode of the second voltage stabilizing transistor M52 may be electrically connected to the first node Q1, and a second electrode of the first voltage stabilizing transistor M52 may be electrically connected to the first output module 130. When the signal at the first node Q1 and the signal at the node directly electrically connected to the first output module 130 are both within a normal signal range, the second voltage stabilizing control signal may control the second voltage stabilizing transistor M52 to be in an on state.

[0153] The third voltage stabilization module 153 may include a third voltage stabilization transistor M53, a gate of which may receive a third voltage stabilization control signal, a first electrode of the third voltage stabilization transistor M53 may be electrically connected to the first node Q1, and a second electrode of the third voltage stabilization transistor M53 may be electrically connected to the second output module 140. When the signal at the first node Q1 and the signal at the node directly electrically connected to the second output module 140 are both within a normal signal range, the third voltage stabilization control signal may control the third voltage stabilization transistor M53 to be in an on state.

[0154] The channel types of the second voltage-stabilizing transistor M52 and the third voltage-stabilizing transistor M53 can be the same or different, that is, both can be N-type transistors or P-type transistors, or one of them can be a P-type transistor and the other can be an N-type transistor. The specific design can be based on actual needs and is not specifically limited in the embodiment of the present invention. Taking the example that the second voltage-stabilizing transistor M52 and the third voltage-stabilizing transistor M53 are both P-type transistors, the second voltage-stabilizing control signal and the third voltage-stabilizing control signal can both be low-level signals. In this case, the second voltage-stabilizing control signal and the third voltage-stabilizing control signal can both reuse the first-level signal Vgl of the first level terminal VGL, which is beneficial to reducing the number of signals provided to the shift register unit 101 and reducing the driving cost of the shift register unit 101.

[0155] Based on the above embodiment, optionally, refer to Figures 19 to 22 In any of the figures, the shift register unit 101 may further include a first capacitor C1, a first plate of the first capacitor C1 may receive a fixed-level signal, and the fixed-level signal may, for example, reuse the second-level signal Vgh of the second-level terminal VGH; the second plate of the first capacitor C1 may be electrically connected to the second node Q2, so that the first capacitor C1 may store the signal of the second node Q2, so that under the premise that no other signal is written, the signal of the second node Q2 may be maintained as the signal written in the previous stage, thereby ensuring the stability of the signal of the second node Q2, improving the control accuracy of the first output module 130 and the second output module 140, and further facilitating improving the accuracy of the first gate signal S1 output by the first output terminal OUT1 and the second gate signal S2 output by the second output terminal OUT2.

[0156] Optional, continue to refer to Figures 19 to 22 In any of the figures, the shift register unit 101 may further include a second capacitor C2 and a third capacitor C3, the second capacitor C2 being electrically connected between the first output terminal OUT1 and the gate of the first output transistor M31, and the third capacitor C3 being electrically connected between the second output terminal OUT2 and the gate of the third output transistor M41. When the first gate signal S1 of the first output terminal OUT1 changes, the second capacitor C2 can couple the change in the first gate signal S1 to the gate of the first output transistor M31, thereby pulling down or raising the voltage of the gate signal of the first output transistor M31, so that the gate signal of the first output transistor M31 has a high driving capability, thereby driving the first output transistor M31 to be accurately turned on or off. Similarly, the third capacitor C3 can couple the change in the second gate signal S2 of the second output terminal OUT2 to the gate of the third output transistor M41, thereby providing a high driving capability for the gate signal of the third output transistor M41 to be accurately turned on or off.

[0157] It is understood that the above description is only an example of the structure of the shift register unit 101, and the specific structure of the shift register unit 101 is not limited to this, provided that the core invention of the embodiment of the present invention can be achieved. Figure 22 The structure of the shift register unit shown is used as an example to illustrate the technical solution of the embodiment of the present invention.

[0158] In an optional embodiment, Figure 23 This is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, referring to Figure 22 and Figure 23 , a frame display time DT of the display panel includes multiple clock cycles T0; within a clock cycle T0, in the same shift register unit 101, the valid pulses of the second clock signal ck2 of the second clock terminal CK2 and the third clock signal ck3 of the third clock terminal CK3 are shifted in sequence.

[0159] The display time DT1 of a single frame of the display panel can be understood as the time required for the valid pulses of the first gate signal and the second gate signal to be sequentially output by each stage of the shift register unit in the driving circuit. In other words, the duration of the display time DT of a single frame of the display panel can be equivalent to the time between the start times of two adjacent valid pulses of the first gate signal S1 output by the first stage of the shift register unit in the positive scanning mode, or the time between the start times of two adjacent valid pulses of the first gate signal S1 output by the nth stage of the shift register unit in the reverse scanning mode.

[0160] Accordingly, a clock cycle can be understood as the time between the start times of two adjacent valid pulses of any clock signal, for example, the time T0 between the start times of two adjacent valid pulses of the first clock signal ck1. For the same shift register unit, within one clock cycle, the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, and the fourth clock signal ck4 each include at least one valid pulse. Furthermore, because a single frame display time DT includes multiple clock cycles, the first clock signal ck1, the second clock signal ck2, the third clock signal ck3, and the fourth clock signal ck4 can include multiple valid pulses within one frame display time DT.

[0161] Furthermore, within a clock cycle T0, the sequential shifting of the effective pulses of the second clock signal ck2 and the third clock signal ck3 can be understood as meaning that the effective pulse time of the second clock signal ck2 can precede the effective pulse time of the third clock signal ck3. In an optional embodiment, within a clock cycle T00, the time between the end moment of the effective pulse of the second clock signal ck2 and the start moment of the effective pulse of the third clock signal ck3 can be p*H; H can be the vibration period of the crystal oscillator in the driver chip that provides the clock signal to the shift register unit 101, that is, H can be the unit duration of the clock signal, and p can be a positive integer. This configuration ensures that the interval time between the effective pulse of the first gate signal S1 of the first output terminal OUT1 and the effective pulse of the second gate signal S2 of the second output terminal OUT2 is p*H.

[0162] Specifically, because the first output module 130 and the second output module 140 are both electrically connected to the first node Q1 and the second node Q2, the first output module 130 and the second output module 140 can control the first gate signal S1 outputted by the first output terminal OUT1 and the second gate signal S2 outputted by the second output terminal OUT2, respectively, based on the signal at the first node Q1 and the signal at the second node Q2. In an exemplary embodiment, when the first node Q1 is at an active level, the first output module 130 can transmit the second clock signal ck2 from the second clock terminal CK2 to the first output terminal OUT1, and the second output module 140 can transmit the third clock signal ck3 from the third clock terminal CK3 to the second output terminal OUT, so that the first gate signal S1 outputted by the first output terminal OUT1 can be consistent with the second clock signal ck2, and the second gate signal S2 outputted by the second output terminal OUT2 can be consistent with the third clock signal ck3. In this way, within one clock cycle T0, by shifting the effective pulses of the second clock signal ck2 of the second clock end CK2 and the third clock signal ck3 of the third clock end CK3 in the same shift register unit 101 in sequence, the effective pulses of the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 can be shifted in sequence, so that the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 can be used to respectively control different modules in the pixel circuit, which is beneficial to reducing the number of shift register units set in the driving circuit, reducing the size of the driving circuit, and further beneficial to the narrow bezel of the display panel.

[0163] Optional, continue to refer to Figure 22 and Figure 23When the duration of the clock cycle T0 is 2*T, each clock cycle T0 includes a first time period T01 and a second time period T02, both of which are continuous and have a duration of T. Within a clock cycle T0, in the same shift register unit 101, the valid pulses of the second clock signal ck2 and the third clock signal ck3 are both located in the first time period T01 or the second time period T02. With this arrangement, within a clock cycle T0, the valid pulse of the second clock signal ck2 and the valid pulse of the third clock signal ck3 of the same shift register unit 101 are two consecutive valid pulses, so that the valid pulses of the first gate signal S1 and the second gate signal S2 output by the shift register unit 101 can also be two consecutive valid pulses. When the first gate signal S1 and the second gate signal S2 output by the same shift register unit 101 are used to control the conduction or shutdown of different modules in the same pixel circuit, the two modules of the pixel circuit can be turned on or off in two consecutive time periods, thereby shortening the driving cycle of the pixel circuit and further facilitating an increase in the refresh rate of the display panel, thereby meeting the display requirements of the display panel with a high refresh rate.

[0164] Optional, continue to refer to Figure 22 and Figure 23 In a clock cycle T0, in the same shift register unit 101, the effective pulse time of the first clock signal ck1 is earlier than the effective pulse time of the second clock signal ck2.

[0165] Specifically, because the drive control module 120 can control the signal transmission path between the input node Q0 and the first node Q1 based on the first clock signal ck1, for example, when the first clock signal ck1 is a valid pulse, the drive control module 120 can transmit the signal at the input node Q0 to the first node Q1, so that the signal at the first node Q1 can be consistent with the signal at the input node Q0. At the same time, the signal at the first node Q1 can control the first output transistor M31 in the first output module 130 and the third output transistor M41 in the second output module 140 to turn on or off. When the first output transistor M31 and the third output transistor M41 are controlled to turn on, the first output transistor M31 can transmit the second clock signal ck2 to the first output terminal OUT1, and the third output transistor M41 can transmit the third clock signal ck3 to the second output terminal OUT2.

[0166] In addition, since in the positive scan mode, the signal of the input node Q0 of the y-th stage shift register unit is consistent with the first gate signal or the second gate signal of the x-th stage shift register unit, and the effective pulse time of the first gate signal of the x-th stage shift register unit is before the effective pulse time of the first gate signal of the y-th stage shift register unit, and the effective pulse time of the second gate signal of the x-th stage shift register unit is before the effective pulse time of the second gate signal of the y-th stage shift register unit. In this way, by making the effective pulse time of the first clock signal ck1 before the effective pulse time of the second clock signal ck2, it is possible to ensure that when the second clock signal ck2 becomes a valid level, the effective pulse of the first gate signal or the second gate signal of the x-th stage shift register unit is written to the first node Q1, thereby ensuring that before the second clock signal ck2 becomes a valid level, the first output transistor M31 of the first output module 130 and the third output transistor M41 of the second output module 140 are controlled to be in the on state, ensuring that the first output transistor M31 can completely transmit the effective pulse of the second clock signal ck2 to the first output terminal OUT1, and ensuring that the third output transistor M41 can completely transmit the effective pulse of the third clock signal ck3 to the second output terminal OUT2, so that the first gate signal S1 of the first output terminal OUT1 and the second gate signal S2 of the second output terminal OUT2 can have complete effective pulses, which is beneficial to improving the accuracy of the first gate signal S1 and the second gate signal S2 output by the shift register unit 101.

[0167] In an alternative embodiment, continue to refer to Figure 22 and Figure 23 When the x-th shift register unit receives the first clock signal ck1x, the second clock signal ck2x and the third clock signal ck3x, and the y-th shift register unit receives the first clock signal ck1y, the second clock signal ck2y and the third clock signal ck3y, within one clock cycle in the positive scanning mode, the effective pulse time of the third clock signal ck3x of the x-th shift register unit is located before the effective pulse time of the second clock signal ck2y of the y-th shift register unit, so that the effective pulse time of the second gate signal S2x output by the x-th shift register unit can be located before the effective pulse time of the first gate signal S1y output by the y-th shift register unit, so that when the first gate signal S1 and the second gate signal S2 output by each shift register unit are used to control the working process of the pixel circuit, each pixel circuit can be scanned row by row in the positive scanning mode.

[0168] Accordingly, in the reverse scan mode, the signal at the input node Q0 of the y-th shift register unit is consistent with the first gate signal or the second gate signal of the k-th shift register unit, and the effective pulse time of the first gate signal of the k-th shift register unit is located before the effective pulse time of the first gate signal of the y-th shift register unit, and the effective pulse time of the second gate signal of the k-th shift register unit is located before the effective pulse time of the second gate signal of the y-th shift register unit. In this way, by ensuring that the effective pulse time of the first clock signal ck1 is located before the effective pulse time of the second clock signal ck2, the accuracy of the first gate signal S1 and the second gate signal S2 output by the shift register unit 101 can also be improved. The specific implementation method can be referred to the description of the forward scan mode above and will not be repeated here.

[0169] In an alternative embodiment, continue to refer to Figure 22 and Figure 23 When the y-th stage shift register unit receives the first clock signal ck1y, the second clock signal ck2y and the third clock signal ck3y, and the k-th stage shift register unit receives the first clock signal ck1k, the second clock signal ck2k and the third clock signal ck3k, within a clock cycle T0 in the reverse scanning mode, the effective pulse time of the third clock signal ck3k of the k-th stage shift register unit is located before the effective pulse time of the second clock signal ck2y of the y-th stage shift register unit, so that the effective pulse time of the second gate signal S2k output by the k-th stage shift register unit can be located before the effective pulse time of the first gate signal S1y output by the y-th stage shift register unit, so that when the first gate signal S1 and the second gate signal S2 output by the shift register units of each stage are used to control the working process of the pixel circuit, each pixel circuit can be scanned row by row in the reverse scanning mode.

[0170] Optional, continue to refer to Figure 22 and Figure 23 When the length of the clock cycle T0 is 2*T, each clock cycle T0 includes a first time period T01 and a second time period T02, both of which are continuous and have a duration of T; within a clock cycle T0, in the same shift register unit 101, the valid pulse of the first clock signal ck1 is located in the first time period T01, and the valid pulses of the second clock signal ck2 and the third clock signal ck3 are located in the second time period, that is, the first clock signal ck1 and the second clock signal ck2 and the third clock signal ck3 can be respectively located in different time periods of the same clock cycle, so that the effective pulse duration and start time of the first clock signal ck1 can be flexibly set, ensuring the accuracy of the signal transmitted to the first node Q1, which is beneficial to improving the accuracy of the first gate signal S1 and the second gate signal S2 output by the shift register unit 101.

[0171] In another alternative embodiment, Figure 24 This is another driving timing diagram of a shift register unit provided by an embodiment of the present invention, referring to Figure 22 and Figure 24 When the length of the clock cycle T0 is 2*T, each clock cycle T0 includes a first time period T01 and a second time period T02, both of which are continuous and have a duration of T; within a clock cycle T0, in the same shift register unit 101, the valid pulses of the first clock signal ck1 and the second clock signal ck2 are both located in the first time period T01, and the valid pulse of the third clock signal ck3 is located in the second time period T02. At this time, the second clock signal ck2 and the third clock signal ck3 can be located in different time periods in the same clock cycle T0, so that the effective pulse interval time of the second clock signal ck2 and the third clock signal ck3 can be flexibly set to meet the effective pulse interval time requirements of the first gate signal S1 and the second gate signal S2 output by the shift register unit 101.

[0172] It can be understood that, within one clock cycle, for the same shift register unit, under the premise that the effective pulse time of the first clock signal ck1 is before the effective pulse time of the second clock signal ck2, and the effective pulse time of the second clock signal ck2 is before the effective pulse time of the third clock signal ck3, the effective pulse interval time between the first clock signal ck1 and the second clock signal ck2, the effective pulse interval time between the second clock signal ck2 and the third clock signal ck3, and the effective pulse widths of the first clock signal ck1, the second clock signal ck2 and the third clock signal ck3 can all be designed according to actual needs, and the embodiments of the present invention do not make specific limitations on this.

[0173] On the basis of the above embodiments, optionally, Figure 25 is a structural diagram of another driving circuit provided by an embodiment of the present invention, Figure 26 : is a driving timing diagram of a driving circuit in a forward scanning mode provided by an embodiment of the present invention. Figure 27 This is a driving timing diagram of a driving circuit in a reverse scanning mode provided by an embodiment of the present invention, with reference to Figures 25 to 27 In the forward scanning mode, the effective pulse time of the second gate signal S2i output by the i-th shift register unit Gi is located before the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1; in the reverse scanning mode, the effective pulse time of the second gate signal S2i+1 output by the i+1-th shift register unit Gi+1 is located before the effective pulse time of the first gate signal S1i output by the i-th shift register unit Gi.

[0174] For example, taking i equal to 1, i+1, etc. as an example, in the forward scanning mode, the effective pulse time t31 of the second gate signal S21 output by the first-stage shift register unit G1 is located before the effective pulse time t22 of the first gate signal S12 output by the second-stage shift register unit G2; in the reverse scanning mode, the effective pulse time t32 of the second gate signal S22 output by the second-stage shift register unit G2 is located before the effective pulse time t21 of the first gate signal S11 output by the first-stage shift register unit G1.

[0175] Alternatively, taking i equals n-1 and i+1 equals n as an example, in the forward scanning mode, the effective pulse time t3n-1 of the second gate signal S2n-1 output by the n-1th level shift register Gn-1 is located before the effective pulse time t2n of the first gate signal S1n output by the n-1th level shift register Gn; in the reverse scanning mode, the effective pulse time t3n of the second gate signal S2n output by the n-1th level shift register Gn is located before the effective pulse time t2n-1 of the first gate signal S1n-1 output by the n-1th level shift register Gn-1.

[0176] It can be understood that when the first output terminal OUT1 and the second output terminal OUT2 of the i-th stage shift register unit Gi are electrically connected to the i-th row pixel circuit, so that the first gate signal S1i and the second gate signal S2i output by the i-th stage shift register unit Gi respectively control the reset phase and the data writing phase of the i-th row pixel circuit, the time period during which the i-th stage shift register unit G1i outputs the effective pulse of the first gate signal S1i is the reset phase of the i-th row pixel circuit, so that the i-th row pixel circuit can be reset during this time period; the time period during which the i-th stage shift register unit G1i outputs the effective pulse of the second gate signal S2i is the data writing phase of the i-th row pixel circuit. According to the data writing stage, the data signal can be written into the i-th row pixel circuit accordingly during this time period; similarly, the first output terminal OUT1 and the second output terminal OUT2 of the i+1-th stage shift register unit are electrically connected to the i+1-th row pixel circuit to respectively control the reset stage and the data writing stage of the i+1-th row pixel circuit, so that during the effective pulse time period when the i+1-th stage shift register unit outputs the first gate signal S1i+1, the i+1-th row pixel circuit can be reset, and during the effective pulse time period when the i+1-th stage shift register unit outputs the second gate signal S2i+1, the data signal can be written into the i+1-th row pixel circuit accordingly.

[0177] Among them, in the positive scan mode, by making the effective pulse time of the second gate signal S2i output by the i-th level shift register unit Gi before the effective pulse time of the first gate signal S1i+1 output by the i+1-th level shift register unit Gi+1, the data writing phase of the i-th row pixel circuit can be placed before the reset phase of the i+1-th row pixel circuit, that is, the reset phase of the i+1-th row pixel circuit will be entered only after the i-th row pixel circuit completes the reset and data writing, so that the reset and data writing of the i-th row pixel circuit do not interfere with the reset and data writing of the i+1-th row pixel circuit.

[0178] Similarly, in the reverse scanning mode, the effective pulse time of the second gate signal S2i+1 output by the i+1-th level shift register Gi+1 is before the effective pulse time of the first gate signal S1i output by the i-th level shift register Gi, so that the reset phase of the i-th row pixel circuit will be entered only after the i+1-th row pixel circuit is reset and data writing is completed, ensuring that the reset and data writing of the i-th row pixel circuit do not interfere with the reset and data writing of the i+1-th row pixel circuit.

[0179] Optional, continue to refer to Figures 25 to 27 When x=ym, k=y+m, the display panel also includes 2*m first clock signal lines 510 and 2*m second clock signal lines 520; adjacent 2*m-level shift register units 101 constitute a shift register unit group 101A; m is a positive integer, for example, m is 1, and two adjacent levels of shift register units 101 constitute a shift register unit group 101A, for example, the first-level shift register unit G1 and the second-level shift register unit G2 constitute a shift register unit group 101A. At this time, the display panel can include two first clock signal lines 510 (i.e., first clock signal lines 501 and 502), and two second clock signal lines 520 (i.e., second clock signal lines 503 and 504).

[0180] The display time DT of a frame of the display panel includes multiple clock cycles T0; the duration of the clock cycle T0 is greater than or equal to 2*m*H, where H is the duration of a clock unit; within a clock cycle T0, the clock signals transmitted by each first clock signal line 510 are shifted in sequence; and within a clock cycle T0, the clock signals transmitted by each second clock signal line 520 are shifted in sequence. For example, when m is equal to 1, the clock cycle T0 can be equal to 4*H. At this time, the valid pulses of the clock signal Ck11 transmitted by the first clock signal line 501 and the clock signal Ck12 transmitted by the first clock signal line 502 are shifted in sequence, and the valid pulses of the clock signal Ck21 transmitted by the second clock signal line 503 and the clock signal Ck22 transmitted by the second clock signal line 504 are shifted in sequence. Moreover, within a clock cycle T0, the valid pulses of the clock signals Ck11, Ck22, Ck12, and Ck21 are shifted in sequence.

[0181] In the same shift register unit group 101A, the first clock terminal CK1 of each stage of the shift register unit 101 is electrically connected to each first clock signal line 510, and the third clock terminal CK3 of each stage of the shift register unit 101 is electrically connected to each second clock signal line 520; the second clock terminal CK2 of the i+m-th stage shift register unit Gi+m and the first clock terminal CK1 of the i-th stage shift register unit Gi are electrically connected to the same first clock signal line 510; i is a positive integer less than or equal to n. For example, the first clock terminal CK1 of the first-stage shift register unit G1 is electrically connected to the first clock signal line 501, the first clock terminal CK1 of the second-stage shift register unit G2 is electrically connected to the first clock signal line 502, the third clock terminal CK3 of the first-stage shift register unit is electrically connected to the second clock signal line 503, the third clock terminal CK3 of the second-stage shift register unit G2 is electrically connected to the second clock signal line 504, and the second clock terminal CK2 of the second-stage shift register unit is electrically connected to the first clock signal line 501, and the second clock terminal CK2 of the third-stage shift register unit G3 is electrically connected to the first clock signal line 502.

[0182] For example, taking i equal to 1 and m equal to 1, since the first clock terminal CK1 of the shift register unit 101 of the same stage can control the signal transmission path between its positive input terminal INF or negative input terminal INB and its first node, and the second clock terminal CK2 controls the effective pulse time of the first gate signal S1 of the first output terminal OUT1, and the third clock terminal CK3 controls the effective pulse time of the second gate signal S2 of the second output terminal OUT2, in the forward scanning mode, when the first-stage shift register unit G1 outputs the effective pulse of the first gate signal S11, by making the clock signal Ck12 received by the first clock terminal CK1 of the second-stage shift register unit G2 a valid pulse, the effective pulse of the first gate signal S11 can be transmitted to the first node of the second-stage shift register unit G2, thereby enabling the signal at the first node of the second-stage shift register unit G2 to control the clock signal Ck11 received by the second clock terminal CK2 of the second-stage shift register unit G2 to be transmitted to the first output terminal OUT1, and control the clock signal Ck22 received by the third clock terminal CK3 of the second-stage shift register unit G2 to be transmitted to the second output terminal OUT2. By electrically connecting the first clock terminal CK1 of the first-stage shift register unit G1 to the first clock signal line 501, the first clock terminal CK1 of the second-stage shift register unit G2 to the first clock signal line 502, the third clock terminal CK3 of the first-stage shift register unit G2 to the second clock signal line 503, the third clock terminal CK3 of the second-stage shift register unit G2 to the second clock signal line 504, the second clock terminal CK2 of the first-stage shift register unit G1 to the first clock signal line 502, and the second clock terminal CK2 of the second-stage shift register unit G2 to the first clock signal line 501, it is possible to ensure that the first-stage shift register unit The effective pulses of the first gate signal S11 and the second gate signal S21 output by the element G1 are shifted in sequence, and the effective pulse time of the first gate signal S12 output by the second-stage shift register G2 is located after the effective pulse time of the second gate signal S21 output by the first-stage shift register G1, so that in the positive scanning mode, the effective pulses of the first gate signal (S11, S12, S13, ..., S1n-2, S1n-1, S1n) and the second gate signal (S21, S22, S23, ..., S2n-2, S2n-1, S2n) output from the first-stage shift register G1 to the n-th stage shift register Gn are shifted in sequence.

[0183] Correspondingly, in the reverse scan mode, the first clock terminal CK1 of the n-1th stage shift register unit Gn-1 is electrically connected to the first clock signal line 501, the first clock terminal CK1 of the n-1th stage shift register unit Gn is electrically connected to the first clock signal line 502, the third clock terminal CK3 of the n-1th stage shift register unit is electrically connected to the second clock signal line 503, the third clock terminal CK3 of the n-1th stage shift register unit Gn is electrically connected to the second clock signal line 504, and the second clock terminal CK4 of the n-1th stage shift register unit is electrically connected to the second clock signal line 505. CK2 is electrically connected to the first clock signal line 502, and the second clock end CK2 of the n-th stage shift register unit is electrically connected to the first clock signal line 501, so that in the reverse scanning mode, the valid pulses of the first gate signal (S1n, S1n-1, S1n-2, ..., S13, S12, S11) and the second gate signal (S2n, S2n-1, S2n-2, ..., S23, S22, S21) output from the n-th stage shift register unit Gn to the first stage shift register unit G1 are shifted sequentially.

[0184] In addition, the first clock terminal CK1 of the i-th shift register unit Gi and the first clock terminal CK1 of the i+2*m-th shift register unit Gi+2*m are electrically connected to the same first clock signal line 510, and the third clock terminal CK3 of the i-th shift register unit Gi and the third clock terminal CK3 of the i+2*m-th shift register unit Gi+2*m are electrically connected to the same second clock signal line 520. In this way, while ensuring that the first gate signal S1 and the second gate signal S2 are accurately output by each stage of the shift register unit 101, the number of clock signal lines can be reduced, thereby simplifying the structure of the display panel and further facilitating a narrow frame of the display panel.

[0185] It should be noted that the above is merely an example of m being equal to 1 to illustrate the technical solution of the embodiment of the present invention. In the embodiment of the present invention, m may also be a positive integer greater than 1, for example, Figures 28 to 30As shown, when m is equal to 2, the display panel may include four first clock signal lines 510 (511, 512, 513, 514) and four second clock signal lines 520 (521, 522, 523, 524). Each of the first clock signal lines 511, 512, 513, 514 transmits a clock signal Ck11A, Ck12A, Ck13A, Ck14A, respectively, and each of the second clock signal lines 520 (521, 522, 523, 524) transmits a clock signal Ck21A, Ck22A, Ck23A, Ck24A, respectively. At this time, within one clock cycle, the effective pulses of the clock signals Ck13A, Ck21A, Ck14A, Ck22A, Ck11A, Ck23A, Ck12A, and Ck24A are shifted sequentially. Adjacent four-stage shift register units 101 constitute a shift register unit group 101A. For example, the first-stage shift register unit G1, the second-stage shift register unit G2, the third-stage shift register unit G3, and the fourth-stage shift register unit G4 constitute a shift register unit group 101A, ..., and the n-3-stage shift register unit Gn-3, the n-2-stage shift register unit Gn-2, the n-1-stage shift register unit Gn-1, and the fourth-stage shift register unit G4 constitute a shift register unit group 101A. The present embodiment does not specifically limit the value of m, provided that the core inventive concept of the present embodiment can be achieved.

[0186] In another alternative embodiment, reference Figures 31 to 33 When m is greater than 1, the third clock signal of the i-th shift register unit Gi is the same as the first clock signal of the i+m+1-th shift register unit Gi+m+1. For example, when m is equal to 2, the third clock signal Ck21 of the first-stage shift register unit G1 can be the same as the first clock signal Ck14 of the fourth-stage shift register unit G4. In this case, the third clock terminal CK3 of the first-stage shift register unit G1 and the first clock terminal CK1 of the fourth-stage shift register unit G4 can both be electrically connected to the first clock signal line 514, so that the second clock signal line used to transmit the clock signal Ck21 can reuse the first clock signal line 514. This configuration can reduce the number of clock signals provided to the driving circuit 10, which is beneficial for reducing the driving cost of the driving circuit 10. At the same time, it is beneficial for reducing the number of clock signal lines, thereby facilitating a narrow frame of the display panel.

[0187] It can be understood that when m is equal to 2, the second clock terminal CK2 of the third-stage shift register unit G3 and the first clock terminal CK1 of the first-stage shift register unit G1 are electrically connected to the same first clock signal line 511, the second clock terminal CK2 of the fourth-stage shift register unit G4 and the first clock terminal CK1 of the second-stage shift register unit G2 are electrically connected to the same first clock signal line 512, and the third clock terminal CK3 of the third-stage shift register unit G3 is also electrically connected to the first clock signal line 512, so that in the positive scanning mode, the third-stage shift register unit G3 outputs the first clock signal line 511. The effective pulses of the first gate signal S13 and the second gate signal S23 are shifted in sequence, and the effective pulse of the second gate signal S23 of the third-stage shift register unit G3 overlaps with the effective pulse of the first gate signal S14 of the fourth-stage shift register unit G4; and in the reverse scanning mode, the effective pulses of the first gate signal S14 and the second gate signal S24 output by the fourth-stage shift register unit G4 are shifted in sequence, and the effective pulse of the second gate signal S24 of the fourth-stage shift register unit G4 overlaps with the effective pulse of the first gate signal S13 of the third-stage shift register unit G3.

[0188] In an alternative embodiment, continue to refer to Figures 31 to 33 In the forward scanning mode, the effective pulse time of the first gate signal S1i output by the i-th shift register unit Gi is located before the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1; the effective pulse time of the second gate signal S2i output by the i-th shift register unit Gi overlaps with the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1; in the reverse scanning mode, the effective pulse time of the first gate signal S1i+1 output by the i+1-th shift register unit Gi+1 is located before the effective pulse time of the first gate signal S1i output by the i-th shift register unit Gi; the effective pulse time of the second gate signal S2i+1 output by the i+1-th shift register unit Gi+1 overlaps with the effective pulse time of the first gate signal S1i output by the i-th shift register unit Gi. i is a positive integer less than or equal to n.

[0189] Among them, when the first gate signal S1i and the second gate signal S2i output by the i-th stage shift register unit Gi are used to respectively control the reset phase and the data writing phase of the i-th row pixel circuit, and the first gate signal S1i+1 and the second gate signal S2i+1 output by the i+1-th stage shift register unit Gi+1 are used to respectively control the reset phase and the data writing phase of the i+1-th row pixel circuit, by making the effective pulse time of the second gate signal S2 and the first gate signal S1 of the two adjacent stages of the shift register unit overlap, it is possible to make the data writing phase of the previous row of pixel circuits and the reset phase of the next row of pixel circuits in the two adjacent rows in the forward scanning mode the same phase, and in the reverse scanning mode the data writing phase of the next row of pixel circuits and the reset phase of the previous row of pixel circuits are the same phase, thereby shortening the driving cycle of the display panel, and further improving the display effect of the display panel.

[0190] It should be noted that the above description is only an example of the clock signals received by the first clock end, the second clock end and the third clock end of the shift register unit, taking the example of the positive input end of the y-th shift register unit being electrically connected to the first output end of the x-th shift register unit, and the reverse input end of the y-th shift register unit being electrically connected to the first output end of the k-th shift register unit. In an embodiment of the present invention, when the positive input end of the y-th shift register unit is electrically connected to the second output end of the x-th shift register unit, and the reverse input end of the y-th shift register unit is electrically connected to the second output end of the k-th shift register unit, the first clock signal received by the first clock end of each stage of the shift register unit can be adaptively adjusted, which can also meet the requirement of sequential shifting of the first gate signal and the second gate signal output by each stage of the shift register unit in the forward scanning mode and the reverse scanning mode.

[0191] In an alternative embodiment, reference Figures 34 to 36, when x=ym, k=y+m, the display panel further includes 2*m first clock signal lines 510 and 2*m second clock signal lines 520; the display time DT of one frame of the display panel includes multiple clock cycles T0; the duration of the clock cycle T0 is greater than or equal to 2*m*H, where H is the duration of one clock unit; within one clock cycle T0, the effective pulses of the clock signals transmitted by each first clock signal line 510 are shifted in sequence; and within one clock cycle T0, the effective pulses of the clock signals transmitted by each second clock signal line 520 are shifted in sequence; the adjacent 2* The m-stage shift register units 101 constitute a shift register unit group 101A; in the same shift register unit group 101A, the first clock terminal CK1 of each stage of the shift register unit 101 is electrically connected to each first clock signal line 510, and the second clock terminal CK2 of each stage of the shift register unit 101 is electrically connected to each second clock signal line 520; the third clock terminal CK3 of the i+m-th stage shift register unit Gi+m and the first clock terminal CK1 of the i-th stage shift register unit Gi are electrically connected to the same first clock signal line 510; i is a positive integer less than or equal to n.

[0192] Taking m as 2 as an example, the display panel may include four first clock signal lines 510 and four second clock signal lines 520, namely, first clock signal lines 51, 52, 53, and 54, and second clock signal lines 55, 56, 57, and 58. The first clock signal lines 51, 52, 53, and 54 transmit clock signals Ck1A, Ck1B, Ck1C, and Ck1D, respectively, and the second clock signal lines 55, 56, 57, and 58 transmit clock signals Ck2A, Ck2B, Ck2C, and Ck2D, respectively. Within a clock cycle T0, the valid pulses of the clock signals Ck1A, Ck1B, Ck1C, and Ck1D are shifted sequentially, and the valid pulses of the clock signals Ck2A, Ck2B, Ck2C, and Ck2D are shifted sequentially.

[0193] Correspondingly, the adjacent four-level shift register units 101 constitute a shift register unit group 101A. For example, the first-level shift register unit G1, the second-level shift register unit G2, the third-level shift register unit G3 and the fourth-level shift register unit G4 constitute a shift register unit group 101A, ..., and the n-3-level shift register unit Gn-3, the n-2-level shift register unit Gn-2, the n-1-level shift register unit Gn-1 and the fourth-level shift register unit G4 constitute a shift register unit group 101A. At this time, the first clock terminals CK1 of the first-stage shift register unit G1, the second-stage shift register unit G2, the third-stage shift register unit G3 and the fourth-stage shift register unit G4 are electrically connected to the first clock signal lines 51, 52, 53 and 54 respectively, and the second clock terminals CK2 of the first-stage shift register unit G1, the second-stage shift register unit G2, the third-stage shift register unit G3 and the fourth-stage shift register unit G4 are electrically connected to the second clock signal lines 55, 56, 57 and 58 respectively, and the second clock terminals CK3 of the first-stage shift register unit G1, the second-stage shift register unit G2, the third-stage shift register unit G3 and the fourth-stage shift register unit G4 are electrically connected to the second clock signal lines 55, 56, 57 and 58 respectively. The third clock terminal CK3 of the shift register unit G2, the third-stage shift register unit G3, and the fourth-stage shift register unit G4 are electrically connected to the first clock signal terminals 53, 54, 51, and 52, respectively, so that the clock signal Ck1A received by the first clock terminal CK1 of the first shift register unit G1 can be multiplexed as the clock signal of the third clock terminal CK3 of the third shift register unit G3, and the clock signal Ck1B received by the first clock terminal CK1 of the second shift register unit G2 can be multiplexed as the clock signal of the third clock terminal CK3 of the fourth shift register unit G4. In this way, the first gate signal and the second gate signal of the shift register unit 101 of the same stage can be shifted in sequence, and the first gate signal output by each stage of the shift register unit 101 can be shifted in sequence in both the forward scanning mode and the reverse scanning mode, and the second gate signal output by each stage of the shift register unit 101 can be shifted in sequence, thereby meeting the scanning requirements of the display panel in different modes.

[0194] Based on the above embodiment, optionally, when m is greater than 1, the second clock signal of the i-th shift register unit Gi is the same as the first clock signal of the i+m-1-th shift register unit Gi+m-1. For example, when m is equal to 2, the second clock signal Ck2A of the first-stage shift register unit G1 can be the same as the first clock signal Ck1B of the second-stage shift register unit G2. In this case, the first clock terminal CK1 of the first-stage shift register unit G1 and the second clock terminal CK2 of the second-stage shift register unit G2 can both be electrically connected to the first clock signal line 52, so that the second clock signal line 55 for transmitting the clock signal Ck2A can reuse the first clock signal line 51. This configuration can reduce the number of clock signals provided to the driving circuit 10, which is beneficial to reducing the driving cost of the driving circuit 10; at the same time, it is beneficial to reduce the number of clock signal lines, thereby facilitating a narrow frame of the display panel.

[0195] Based on the above embodiment, optionally, refer to Figures 25 to 36 In any of the figures, when x=ym, k=y+m, the display panel further includes m first start signal lines 61 and m second start signal lines 62; m is a positive integer; the positive input end INF of each shift register unit 101 in the first-stage shift register unit G1 to the m-th stage shift register unit Gm is electrically connected to each first start signal line 61 respectively; the reverse input end INB of each shift register unit 101 in the n-m+1-th stage shift register unit Gn-m+1 to the n-th stage shift register unit Gn is electrically connected to each second start signal line 62 respectively; in the forward scanning mode, each first start signal line 61 transmits the valid pulse of the first start signal STVF in sequence; in the reverse scanning mode, each second start signal line 62 transmits the valid pulse of the second start signal STVB in sequence.

[0196] Taking m equal to 2 as an example, the first-stage shift register unit G1 and the second-stage shift register unit G2 can be electrically connected to the first start signal lines 611 and 612 respectively, and the n-th stage shift register unit Gn and the n-1-th stage shift register unit Gn-1 are electrically connected to the second start signal lines 621 and 622 respectively. In this way, in the forward scanning mode, the valid pulses of the first start signal STVF1 transmitted by the first start signal line 611 and the first start signal STVF2 transmitted by the first start signal line 612 are shifted in sequence, so that the first gate signal S11 output by the first-stage shift register unit G1 and the second-stage shift register unit G2 can sequentially output the valid pulses of the first gate signal S12, and the second gate signal S21 output by the first-stage shift register unit G1 and the second-stage shift register unit G2 can sequentially output the valid pulses of the second gate signal S22, thereby ensuring that the third-stage shift register unit G3 to the n-th-stage shift register unit Gn directly or indirectly cascaded with the first-stage shift register unit G1 and the second-stage shift register unit G2 can sequentially output the valid pulses of the first gate signal S1 and the second gate signal S2; in the reverse scanning mode, the second start signal line 621 is connected to the first-stage shift register unit G1 and the second-stage shift register unit G2. The effective pulses of the second start signal STVB1 and the second start signal STVB2 transmitted by the second start signal line 622 are shifted in sequence, so that the first gate signal S1n output by the n-th shift register Gn and the n-1-th shift register Gn-1 can output the effective pulses of the first gate signal S1n-1 in sequence, and the second gate signal S2n output by the n-th shift register Gn and the n-1-th shift register Gn-1 can output the effective pulses of the second gate signal S2n-1 in sequence, ensuring that the n-2-th shift register Gn-2 directly or indirectly cascaded with the n-th shift register Gn and the n-1-th shift register Gn-1 to the first shift register G1 can output the effective pulses of the first gate signal S1 and the second gate signal S2 in sequence, thereby meeting the scanning requirements of the display panel in different modes.

[0197] In addition, the display panel may also include a first signal transmission line 81, a second signal transmission line 82, a third signal transmission line 71 and a fourth signal transmission line 72, the first signal transmission line 81 is used to transmit the first level signal Vgl, the second signal transmission line 82 is used to transmit the second level signal Vgh, the third signal transmission line 71 is used to transmit the forward scanning control signal u2d, and the fourth signal transmission line 72 is used to transmit the reverse scanning control signal d2u. At this time, the first level end VGL of the shift register unit 101 at each level is electrically connected to the first signal transmission line 81, the second level end VGH of the shift register unit 101 at each level is electrically connected to the second signal transmission line 82, the forward control end U2D of the shift register unit 101 at each level is electrically connected to the third signal transmission line 71, and the reverse control end D2U of the shift register unit 101 at each level is electrically connected to the fourth signal transmission line 72, so that the shift register unit 101 at each level can accurately receive the first level signal Vgl, the second level signal Vgh, the forward scanning control signal u2d and the reverse scanning control signal d2u, so that the shift register unit 101 at each level can accurately output the first gate signal and the second gate signal, thereby improving the display effect of the display panel while meeting the scanning requirements of the display panel in different modes.

[0198] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising the display panel provided in embodiments of the present invention. Therefore, the display device possesses the technical features of the display panel and driving method provided in embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in embodiments of the present invention. Similarities can be found in the above description of the display panel provided in embodiments of the present invention, and will not be repeated here.

[0199] For example, Figure 37 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 37 As shown, the display device 200 includes the display panel 100 provided in an embodiment of the present invention. The display device 200 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0200] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: Including: A driving circuit; the driving circuit includes n cascaded shift register units; n is a positive integer greater than or equal to 2; The shift register unit includes a scanning control module, a driving control module, a first output module, a second output module, a forward input terminal, a reverse input terminal, a forward control terminal, a reverse control terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal and a second output terminal; in the same shift register unit, the scanning control module is electrically connected to the forward input terminal, the reverse input terminal, the forward control terminal, the reverse control terminal and an input node respectively; The driving control module is at least electrically connected to the input node, the first clock terminal, a first node and a second node respectively; the first output module is at least electrically connected to the first node, the second node, the second clock terminal and the first output terminal respectively; the second output module is at least electrically connected to the first node, the second node, the third clock terminal and the second output terminal respectively; The first output terminal or the second output terminal of the x-th stage shift register unit is electrically connected to the forward input terminal of the y-th stage shift register unit, and the reverse input terminal of the y-th stage shift register unit is electrically connected to the first output terminal or the second output terminal of the k-th stage shift register unit; where 1≤x<y<k≤n, and x, y and k are all positive integers; The valid pulses of the first gate signal output from the first output terminal and the second gate signal output from the second output terminal of the same shift register unit are shifted in sequence; The working modes of the display panel include a forward scan mode and a reverse scan mode; in the forward scan mode, the first stage shift register unit to the n-th stage shift register unit sequentially output the valid pulses of the first gate signal and sequentially output the valid pulses of the second gate signal; in the reverse scan mode, the n-th stage shift register unit to the first stage shift register unit sequentially output the valid pulses of the first gate signal and sequentially output the valid pulses of the second gate signal.

2. The display panel according to claim 1, wherein: The forward control terminal receives a forward scan control signal, and the reverse control terminal receives a reverse scan control signal; In the forward scan mode, the forward scan control signal is at an effective level, and the reverse scan control signal is at an invalid level; In the reverse scan mode, the reverse scan control signal is at an effective level, and the forward scan control signal is at an invalid level.

3. The display panel according to claim 1, wherein: The scanning control module includes a forward scan control transistor and a reverse scan control transistor; The gate of the forward scan control transistor is electrically connected to the forward control terminal, the first pole of the forward scan control transistor is electrically connected to the forward input terminal, and the second pole of the forward scan control transistor is electrically connected to the input node; The gate of the reverse scan control transistor is electrically connected to the reverse control terminal, the first pole of the reverse scan control transistor is electrically connected to the reverse input terminal, and the second pole of the reverse scan control transistor is electrically connected to the input node.

4. The display panel according to claim 1, wherein: The display time of one frame of the display panel includes multiple clock cycles; within one clock cycle, in the same shift register unit, the valid pulses of the second clock signal at the second clock end and the third clock signal at the third clock end are shifted in sequence.

5. The display panel according to claim 4, wherein: When the duration of the clock cycle is 2*T, each of the clock cycles includes a first time period and a second time period that are both consecutive and have a duration of T; Within one clock cycle, in the same shift register unit, valid pulses of the second clock signal and the third clock signal are both located in the first time period or the second time period.

6. The display panel according to claim 4, wherein: In one clock cycle, in the same shift register unit, the effective pulse time of the first clock signal is prior to the effective pulse time of the second clock signal.

7. The display panel according to claim 6, wherein: When the duration of the clock cycle is 2*T, each of the clock cycles includes a first time period and a second time period that are both consecutive and have a duration of T; Within one clock cycle, in the same shift register unit, the valid pulse of the first clock signal is located in the first time period, and the valid pulses of the second clock signal and the third clock signal are located in the second time period.

8. The display panel according to claim 6, wherein: When the duration of the clock cycle is 2*T, each of the clock cycles includes a first time period and a second time period that are both consecutive and have a duration of T; Within one clock cycle, in the same shift register unit, the valid pulses of the first clock signal and the second clock signal are both located in the first time period, and the valid pulse of the third clock signal is located in the second time period.

9. The display panel according to claim 4, wherein: In one clock cycle in the forward scanning mode, the effective pulse time of the third clock signal of the x-th shift register unit is before the effective pulse time of the second clock signal of the y-th shift register unit; In one clock cycle in the back-scan mode, a valid pulse time of the third clock signal of the k-th shift register unit is earlier than a valid pulse time of the second clock signal of the y-th shift register unit.

10. The display panel according to claim 1, wherein In the forward scanning mode, the effective pulse time of the second gate signal output by the shift register unit of the i-th stage is before the effective pulse time of the first gate signal output by the shift register unit of the (i+1)-th stage; In the reverse scan mode, the effective pulse time of the second gate signal output by the (i+1)th stage shift register unit is before the effective pulse time of the first gate signal output by the (i)th stage shift register unit.

11. The display panel according to claim 1, wherein In the forward scanning mode, the effective pulse time of the first gate signal output by the shift register unit of the i-th stage is before the effective pulse time of the first gate signal output by the shift register unit of the i+1-th stage; the effective pulse time of the second gate signal output by the shift register unit of the i-th stage overlaps with the effective pulse time of the first gate signal output by the shift register unit of the i+1-th stage; i is a positive integer less than or equal to n; In the reverse scanning mode, the effective pulse time of the first gate signal output by the shift register unit of the i+1th level is before the effective pulse time of the first gate signal output by the shift register unit of the i-th level; the effective pulse time of the second gate signal output by the shift register unit of the i+1th level overlaps with the effective pulse time of the first gate signal output by the shift register unit of the i-th level.

12. The display panel according to claim 1, wherein When x=ym, k=y+m, the display panel further includes 2*m first clock signal lines and 2*m second clock signal lines; m is a positive integer; The display time of one frame of the display panel includes multiple clock cycles; the duration of the clock cycle is greater than or equal to 2*m*H, where H is the duration of one clock unit; In one of the clock cycles, the valid pulses of the clock signals transmitted by the first clock signal lines are sequentially shifted; and in one of the clock cycles, the valid pulses of the clock signals transmitted by the second clock signal lines are sequentially shifted; Adjacent 2*m stages of the shift register units constitute a shift register unit group; in the same shift register unit group, the first clock terminals of the shift register units at each stage are electrically connected to the first clock signal lines, and the third clock terminals of the shift register units at each stage are electrically connected to the second clock signal lines, respectively. The second clock terminal of the shift register unit at the i+mth stage and the first clock terminal of the shift register unit at the ith stage are electrically connected to the same first clock signal line; i is a positive integer less than or equal to n.

13. The display panel according to claim 12, wherein: When m is greater than 1, the third clock signal of the shift register unit at the i-th stage is the same as the first clock signal of the shift register unit at the (i+m+1)-th stage.

14. The display panel according to claim 1, wherein When x=ym, k=y+m, the display panel further includes 2*m first clock signal lines and 2*m second clock signal lines; The display time of one frame of the display panel includes multiple clock cycles; the duration of the clock cycle is greater than or equal to 2*m*H, where H is the duration of one clock unit; In one of the clock cycles, the valid pulses of the clock signals transmitted by the first clock signal lines are sequentially shifted; and in one of the clock cycles, the valid pulses of the clock signals transmitted by the second clock signal lines are sequentially shifted; Adjacent 2*m stages of the shift register units constitute a shift register unit group; in the same shift register unit group, the first clock terminals of the shift register units at each stage are electrically connected to the first clock signal lines, and the second clock terminals of the shift register units at each stage are electrically connected to the second clock signal lines. The third clock terminal of the shift register unit at the i+mth stage and the first clock terminal of the shift register unit at the ith stage are electrically connected to the same first clock signal line; i is a positive integer less than or equal to n.

15. The display panel according to claim 14, wherein: When m is greater than 1, the second clock signal of the i-th shift register unit is the same as the first clock signal of the (i+m-1)-th shift register unit.

16. The display panel according to claim 1, wherein When x=ym, k=y+m, the display panel further includes m first start signal lines and m second start signal lines; m is a positive integer; The positive input end of each of the shift register units in the first stage to the m-th stage is electrically connected to each of the first start signal lines; The inverting input end of each of the shift register units in the (n-m+1)th stage to the (n)th stage is electrically connected to each of the second start signal lines; In the forward scanning mode, each of the first start signal lines sequentially transmits a valid pulse of the first start signal; In the reverse scan mode, each of the second start signal lines sequentially transmits a valid pulse of the second start signal.

17. The display panel according to claim 1, wherein: Also includes: Display area; the display area is provided with a plurality of pixel circuits arranged in an array; The pixel circuit includes at least a first preset module and a second preset module; The first gate signal and the second gate signal of the same shift register unit are respectively used to control the turning on or off of the first preset module and the second preset module of the same pixel circuit.

18. The display panel according to claim 17, wherein: The pixel circuit includes a compensation module, a data writing module, a reset module and a driving module; The driving module includes a driving transistor; the data writing module is electrically connected to a first electrode of the driving transistor; the compensation module is electrically connected between a second electrode of the driving transistor and a gate of the driving transistor; and the reset module is electrically connected to the gate of the driving transistor. The first preset module includes the reset module; the second preset module includes the data writing module and / or the compensation module.

19. The display panel according to claim 1, wherein include: a display area and a non-display area at least partially surrounding the display area; the non-display area includes a first non-display area and a second non-display area located on opposite sides of the display area; When x=ym, k=y+m, and m is a positive integer greater than 1, the shift register units of each stage connected in cascade form a sub-driving circuit; Part of the sub-driving circuits is located in the first non-display area, and part of the sub-driving circuits is located in the second non-display area.

20. The display panel according to claim 1, wherein The drive control module includes a first node control submodule, a second node control submodule and a node mutual control submodule; The shift register unit further includes a fourth clock terminal, a first level terminal, and a second level terminal; in the same shift register unit, the first node control submodule is electrically connected to the input node, the first clock terminal, and the first node respectively; The second node control submodule is electrically connected to the first clock terminal, the first level terminal and the second node respectively; The node mutual control submodule is electrically connected to the second level end, the first node, the second node, the first clock end and the fourth clock end respectively; The effective pulse times of the fourth clock signal received by the fourth clock end and the first clock signal received by the first clock end do not overlap.

21. The display panel according to claim 20, wherein: The second clock terminal is used to receive a second clock signal, and the third clock terminal is used to receive a third clock signal; The fourth clock signal is the same as the second clock signal or the third clock signal.

22. The display panel according to claim 1, wherein The shift register unit further includes a first voltage stabilizing module; In the same shift register unit, the first output module and / or the second output module are electrically connected to the first node through the first voltage stabilizing module.

23. The display panel according to claim 1, wherein The shift register unit further includes a second voltage stabilizing module and a third voltage stabilizing module; In the same shift register unit, the first output module is electrically connected to the first node through the second voltage stabilizing module; the second output module is electrically connected to the first node through the third voltage stabilizing module.

24. The display panel according to claim 1, wherein The first output module includes a first output transistor and a second output transistor; The shift register unit further includes a second level terminal; in the same shift register unit, the gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the second clock terminal, and the second electrode of the first output transistor is electrically connected to the first output terminal; A gate of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the second level end, and a second electrode of the second output transistor is electrically connected to the first output end.

25. The display panel according to claim 1, wherein The second output module includes a third output transistor and a fourth output transistor; The shift register unit also includes a second level end; in the same shift register unit, the gate of the third output transistor is electrically connected to the first node, the first electrode of the third output transistor is electrically connected to the third clock end, and the second electrode of the third output transistor is electrically connected to the second output end; the gate of the fourth output transistor is electrically connected to the second node, the first electrode of the fourth output transistor is electrically connected to the second level end, and the second electrode of the fourth output transistor is electrically connected to the second output end.

26. A display device, characterized in that: include: The display panel according to any one of claims 1 to 25.

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