Power semiconductor module packaging framework, design and preparation method

Abstract

The invention belongs to the technical field of semiconductors, and discloses a power semiconductor module packaging framework and a design and preparation method thereof. A first copper-clad ceramic substrate; interconnection of the upper surface and the lower surface of the power semiconductor chip is realized through the solder layer; the carbon reinforced metal matrix composite material cushion block is bonded with the upper surface of the chip through the solder layer; a second copper-clad ceramic substrate; a second heat sink base plate; compared with a traditional material, the heat dissipation performance is improved by more than 30%, the heat resistance can be remarkably reduced, and the heat dissipation performance is improved. The thermal expansion coefficients of the diamond / aluminum, the diamond / silver, the graphene / silver and the graphene / copper are better matched with those of the power semiconductor chip, so that the packaging framework can reduce the interface thermal stress by more than 35%, the possibility of interface layering caused by thermal circulation is reduced, and the reliability of the double-sided cooling power semiconductor device is greatly improved. According to the innovative scheme, the problem of heat-force mismatch in traditional double-sided cooling packaging is effectively solved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a power semiconductor module packaging architecture, design and preparation method. Background Art

[0002] Power semiconductor devices are core components of modern power electronics systems. Their thermal performance and reliability directly determine power conversion efficiency and system lifespan. With the industrialization of third-generation wide-bandgap semiconductor materials, such as SiC and GaN, the power density of power devices has increased exponentially, making thermal management a key bottleneck restricting the industry's development. Research shows that for every 10°C increase in device junction temperature, its operating life is shortened by approximately 50%. Traditional single-sided cooling packages are no longer able to meet the heat dissipation requirements of the new generation of power modules.

[0003] In the field of double-sided cooling packaging technology, metal buffer blocks serve as the key interface material connecting the chip and the heat sink, and their performance directly affects the overall heat dissipation effect. Current mainstream solutions include: 1) pure copper gaskets (thermal conductivity 390W / mK), which have excellent thermal conductivity, but their thermal expansion coefficient (17ppm / K) is seriously mismatched with the power semiconductor chip; 2) pure molybdenum gaskets (thermal expansion coefficient 5.1ppm / K), which solve the thermal matching problem, but the thermal conductivity of 138W / mK causes the thermal resistance to increase by more than 35%; 3) copper-molybdenum composite gaskets, which partially take into account the requirements of thermal conductivity and thermal matching, but still have problems such as anisotropic thermal conductivity and excessive density.

[0004] Of particular concern is that, under high-temperature, high-current operating conditions, existing metal gasket materials can also lead to the following chain reactions: 1) interfacial delamination due to thermal cycling; and 2) enhanced electromagnetic interference. These issues severely limit the application of double-sided cooling technology in high-end fields such as aerospace and new energy vehicles.

[0005] To address the above technical pain points, there is an urgent need to develop new buffer gasket materials that have high thermal conductivity, matching thermal expansion coefficient and good mechanical strength, and optimize their integration with double-sided cooling architecture to break through the current heat dissipation and reliability limits of power semiconductor packaging.

[0006] Through the above analysis, the problems and defects of the existing technology are as follows:

[0007] (1) Although pure copper gasket (thermal conductivity 390W / mK) has excellent thermal conductivity, its thermal expansion coefficient (17ppm / K) is seriously mismatched with the power semiconductor chip.

[0008] (2) Pure molybdenum gasket (thermal expansion coefficient 5.1 ppm / K) solves the thermal matching problem, but the thermal conductivity of 138 W / mK causes the thermal resistance to increase by more than 35%.

[0009] (3) Although copper-molybdenum composite gaskets partially take into account the requirements of thermal conductivity and thermal matching, they still have problems such as anisotropic thermal conductivity and excessive density.

[0010] (4) Under high temperature and high current conditions, existing metal gasket materials will also cause the following chain problems: interface delamination caused by thermal cycling; enhanced electromagnetic interference. Summary of the Invention

[0011] In view of the problems existing in the prior art, the present invention provides a power semiconductor module packaging architecture.

[0012] The present invention is implemented as follows: a power semiconductor module packaging architecture comprises, from top to bottom:

[0013] a first radiator base plate;

[0014] a first copper-clad ceramic substrate;

[0015] The power semiconductor chip is interconnected on the upper and lower surfaces through the solder layer;

[0016] The carbon reinforced metal matrix composite pad is bonded to the upper surface of the chip through a solder layer;

[0017] a second copper-clad ceramic substrate;

[0018] a second radiator base plate;

[0019] The carbon reinforced metal matrix composite material pad, power semiconductor chip and solder are bonded together by potting glue;

[0020] Wherein: carbon reinforced metal matrix composite material pads include but are not limited to diamond / aluminum pads, diamond / silver pads, graphene / silver and graphene / copper pads;

[0021] Power semiconductor chips include but are not limited to Si-based, SiC-based and GaN-based power semiconductor chips.

[0022] Furthermore, the solder includes but is not limited to lead-containing / lead-free solder, gold-tin solder, and nano-silver paste.

[0023] Furthermore, the double-sided copper-clad ceramic substrate includes but is not limited to AlN, Al2O3, ZTA, and Si3N4 ceramic materials.

[0024] Furthermore, the radiator base plate includes but is not limited to a copper radiator, an aluminum radiator and an AlSiC radiator.

[0025] Another object of the present invention is to provide a method for preparing a power semiconductor module packaging architecture:

[0026] 1) Step 1: Processing a carbon reinforced metal matrix composite spacer of a specified size and subjecting the processed spacer to chemical nickel plating and gold / silver electroplating to enhance its wettability to solder / sintered silver paste;

[0027] 2) Step 2: Print solder on the copper-clad ceramic substrate, bond the power semiconductor chip to the solder, and solder them together to achieve electrical interconnection between the power semiconductor chip and the copper-clad ceramic substrate;

[0028] 3) Step 3: Print solder on the upper surface of the power semiconductor chip, and bond the lower surface of the processed carbon-reinforced metal matrix composite pad to the upper surface of the chip for welding to achieve electrical interconnection between the power semiconductor chip and the pad;

[0029] 4) Step 4: Print solder on another copper-clad ceramic substrate and bond the top surface of the pad to the solder, electrically interconnecting the top and bottom surfaces of the power semiconductor chip to the two copper-clad ceramic substrates. This allows the power semiconductor chip to dissipate heat simultaneously through both the bottom and top surfaces of the chip, a process known as double-sided cooling.

[0030] 4) Step 5: Print solder on the outer copper surfaces of the first and second copper-clad ceramic substrates for soldering to the heat sink base, achieving substrate-heat sink interface connection. After soldering, pot the device.

[0031] Another object of the present invention is to provide a heat dissipation path for a power semiconductor module packaging architecture:

[0032] The first heat dissipation path is power semiconductor chip-solder layer-copper-clad ceramic substrate-solder layer-radiator base plate;

[0033] The second heat dissipation path is power semiconductor chip-solder layer-carbon reinforced metal matrix composite material pad-solder layer-copper clad ceramic substrate-solder layer-radiator base plate.

[0034] In combination with the above technical solutions and the technical problems solved, please analyze the advantages and positive effects of the technical solutions to be protected by the present invention from the following aspects:

[0035] First, innovative metal-based composite materials such as diamond / aluminum, diamond / silver, graphene / silver, and graphene / copper are used as buffer pads. The thermal conductivity of these materials can exceed 500W / mK, and can reach up to 1200W / mK, which is more than 30% higher than traditional materials. It can significantly reduce thermal resistance and improve heat dissipation performance.

[0036] The thermal expansion coefficients of diamond / aluminum, diamond / silver, graphene / silver, and graphene / copper are more closely matched to those of power semiconductor chips. Therefore, the proposed packaging architecture can reduce interface thermal stress by more than 35%, lowering the possibility of interface delamination due to thermal cycling, thereby significantly improving the reliability of double-sided cooled power semiconductor devices.

[0037] The innovative solution of the present invention effectively solves the thermal-mechanical mismatch problem in traditional double-sided cooling packages, provides a reliable heat dissipation solution for high-power density semiconductor devices, and has broad application prospects in new energy vehicles, smart grids and other fields.

[0038] The technical solution of the present invention solves a technical problem that people have been eager to solve but have never been able to succeed. The heat dissipation performance and reliability of traditional power semiconductor modules have always been restricted by the thermal conductivity and thermal expansion coefficient of the pad material. Most of the existing technologies use copper-molybdenum composite pads instead of copper pads to reduce the mismatch of thermal expansion coefficients, but this greatly reduces the thermal conductivity from 390W / mK of copper pads to 200W / mK of copper-molybdenum alloys, and the heat dissipation performance of the power semiconductor module is greatly reduced. The power semiconductor module based on carbon-reinforced metal-based composite pads proposed by the present invention can not only optimize the problem of thermal expansion coefficient matching, but also greatly improve the heat dissipation performance of the double-sided cooling module. Compared with the existing technology, the present invention has significant technical progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a diagram of a power semiconductor module packaging architecture based on a carbon-reinforced metal matrix composite material pad provided by an embodiment of the present invention.

[0040] Figure 2 The present invention provides a flow chart for preparing a power semiconductor module based on a carbon-reinforced metal matrix composite material pad.

[0041] Figure 3 The present invention provides a schematic diagram of the heat dissipation path of a power semiconductor module based on a carbon-reinforced metal matrix composite material pad.

[0042] Figure 4 A 3D model diagram of a power semiconductor module is provided in an embodiment of the present invention.

[0043] Figure 5 This is a diagram showing the maximum junction temperature results of a traditional double-sided cooling module chip based on a copper-molybdenum composite pad provided by an embodiment of the present invention.

[0044] Figure 6 This is a diagram showing the maximum junction temperature results of the double-sided cooling module chip based on diamond / silver pads provided in an embodiment of the present invention.

[0045] Figure 7This is a diagram showing thermal stress results of a traditional double-sided cooling module based on copper pads provided by an embodiment of the present invention.

[0046] Figure 8 This is a diagram showing the thermal stress results of a double-sided cooling module based on diamond / silver pads provided in an embodiment of the present invention.

[0047] Figure 1 In: 1. Power semiconductor chip; 2. Carbon reinforced metal matrix composite material spacer; 3. First copper-clad ceramic substrate; 4. Second copper-clad ceramic substrate; 5. First radiator base plate; 6. Second radiator base plate; 7. Solder; 8. Potting compound. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] The present invention proposes a power semiconductor module packaging architecture based on a carbon reinforced metal matrix composite spacer to improve the heat dissipation performance of a double-sided cooling package and solve the thermal-mechanical mismatch problem in a traditional double-sided cooling package.

[0050] like Figure 1 As shown, an embodiment of the present invention provides a power semiconductor module packaging architecture comprising:

[0051] The proposed power semiconductor module is composed of a carbon reinforced metal matrix composite spacer, a power semiconductor chip, solder, a double-sided copper-clad ceramic substrate, and a heat sink base. The power semiconductor module packaging architecture based on the carbon reinforced metal matrix composite spacer proposed in the present invention is shown in the figure below. Figure 1 The package structure includes from bottom to top:

[0052] First radiator base plate 5;

[0053] A first copper-clad ceramic substrate 3;

[0054] The power semiconductor chip 1 is interconnected on the upper and lower surfaces through the solder layer;

[0055] The carbon reinforced metal matrix composite material pad 2 is bonded to the upper surface of the chip through a solder layer;

[0056] A second copper-clad ceramic substrate 4;

[0057] Second radiator base plate 6.

[0058] The carbon reinforced metal matrix composite material pad 2, the power semiconductor chip 1, and the solder 7 are bonded together by a potting compound 8;

[0059] Among them: carbon reinforced metal matrix composite material pads 2 include but are not limited to diamond / aluminum pads, diamond / silver pads, graphene / silver and graphene / copper pads; power semiconductor chips 1 include but are not limited to Si-based, SiC-based and GaN-based power semiconductor chips; solder 7 includes but is not limited to lead-containing / lead-free solder, gold-tin solder, nano-silver paste, etc.; double-sided copper-clad ceramic substrates include but are not limited to AlN, Al2O3, ZTA, Si3N4 and other ceramic materials; radiator base plates include but are not limited to copper radiators, aluminum radiators and AlSiC radiators.

[0060] The power semiconductor module packaging architecture proposed in this paper fully utilizes the excellent thermal conductivity of carbon-reinforced metal matrix composites (CRMMCs), achieving efficient heat dissipation from the power chip through a double-sided path. In the module structure, the power semiconductor chip is interconnected using top and bottom solder. The bottom surface is directly soldered to the first copper-clad ceramic substrate, and the top surface is connected to the CRMMC pad via a solder layer. This top and bottom thermal path design significantly shortens the path length for heat transfer from the chip to the heat sink, significantly reducing thermal resistance.

[0061] The carbon-reinforced metal matrix composite spacers in this structure not only provide heat dissipation but also structural support and stress buffering. Given the intense thermal cycling experienced by power chips during on-off switching, stress concentration is a critical issue. The carbon-reinforced components (such as diamond and graphene) in the spacer material impart ultra-high thermal conductivity, while the metal matrix (such as aluminum or silver) provides excellent mechanical toughness, achieving an excellent balance between heat dissipation and mechanical compatibility.

[0062] The solder connections between the upper and lower surfaces of the chip utilize low- or medium-temperature solder systems, such as gold-tin alloys or nano-silver pastes, effectively reducing interfacial defects caused by thermal expansion mismatch during the soldering process. This robust solder structure ensures long-term thermal and electrical performance stability, particularly in high-power density applications. The design of the upper and lower solder layers also optimizes stress distribution, preventing failure modes caused by localized strain accumulation, such as solder joint fatigue cracking or chip warping.

[0063] During the packaging process, the chip, carbon-reinforced spacers, and solder are encapsulated with potting compound to further enhance structural integrity and environmental adaptability. The introduction of potting compound effectively prevents moisture and contaminants from invading sensitive components, preventing failures caused by reduced insulation resistance or metal migration. Furthermore, the potting material provides a buffering effect against mechanical shock and vibration, enabling the module to adapt to even harsher environments.

[0064] The first and second heat sink bases, located above and below the module, are tightly bonded to the copper-clad ceramic substrate, creating an efficient heat dissipation platform. Ceramic substrate materials such as aluminum nitride (AlN) or silicon nitride (Si3N4) not only offer excellent thermal conductivity but also high dielectric strength, providing the necessary electrical isolation for the device under high-voltage, high-current operation. The heat sink base can be made of copper, aluminum, or AlSiC, depending on system requirements, offering a flexible balance between thermal conductivity, weight, and cost.

[0065] Overall, the power semiconductor module packaging architecture of this invention, through the innovative introduction of carbon-reinforced metal matrix composite spacers, synergistically optimizes the chip's thermal management and mechanical reliability, significantly improving the module's power density and lifespan. Compared to traditional single-sided cooling packaging structures, this solution achieves lower junction temperatures, higher current carrying capacity, and superior reliability in practical applications, making it particularly suitable for new energy vehicle electric drive systems, industrial inverters, and high-power power electronics.

[0066] The preparation process of the power semiconductor module based on the carbon reinforced metal matrix composite material pad proposed in the present invention mainly includes the following five steps, and the flow chart is as follows: Figure 2 As shown:

[0067] 1) The first step is to process a carbon reinforced metal matrix composite pad of a specified size and electroplating the processed pad with electroless nickel plating and gold / silver plating to enhance its wettability to solder / sintered silver paste.

[0068] 2) The second step: printing solder on the copper-clad ceramic substrate, bonding the power semiconductor chip to the solder and soldering them together to achieve electrical interconnection between the power semiconductor chip and the copper-clad ceramic substrate.

[0069] 3) The third step: printing solder on the upper surface of the power semiconductor chip, bonding the lower surface of the processed carbon reinforced metal matrix composite pad to the upper surface of the chip for welding, and realizing electrical interconnection between the power semiconductor chip and the pad.

[0070] 4) Step 4: Print solder on another copper-clad ceramic substrate and bond the top surface of the pad to the solder, electrically interconnecting the top and bottom surfaces of the power semiconductor chip with the two copper-clad ceramic substrates. This allows the power semiconductor chip to dissipate heat simultaneously through both its bottom and top surfaces, a process known as double-sided cooling.

[0071] 4) Step 5: Print solder on the outer copper surfaces of the first and second copper-clad ceramic substrates for soldering to the heat sink base, achieving substrate-heat sink interface connection. After soldering, pot the device.

[0072] Figure 3A schematic diagram of the heat dissipation paths for a power semiconductor module based on a carbon-reinforced metal matrix composite (CRMMC) spacer is shown. Path 1 is the power semiconductor chip - solder layer - copper-clad ceramic substrate - solder layer - heat sink baseplate; Path 2 is the power semiconductor chip - solder layer - CRMMC spacer - solder layer - copper-clad ceramic substrate - solder layer - heat sink baseplate. This demonstrates that the material properties of the spacer play a crucial role in the performance of the double-sided cooling module. Conventional copper spacers have a thermal conductivity of 390 W / mK and a coefficient of thermal expansion of 17 ppm / K. The diamond / aluminum, diamond / silver, graphene / silver, and graphene / copper spacers employed in this invention have thermal conductivities ranging from 500 W / mK to 1200 W / mK, representing an approximately 30%-208% improvement over copper. Furthermore, their coefficient of thermal expansion, ranging from 5 ppm / K to 12 ppm / K, is closer to that of the power semiconductor chip, significantly reducing thermal stress at the interface between the spacer and the power semiconductor chip. Therefore, this invention effectively solves the thermal-mechanical mismatch problem in traditional double-sided cooling packages, providing a reliable heat dissipation solution for high-power density semiconductor devices. Furthermore, the proposed power semiconductor module packaging architecture based on carbon-reinforced metal matrix composite spacers requires no specialized manufacturing processes and is simple to prepare, showing broad application prospects in new energy vehicles, smart grids, and other fields.

[0073] A 3D model of a power semiconductor module designed by the present invention is shown in FIG. Figure 4 The fabrication process is as follows: diamond / aluminum, diamond / silver, graphene / silver, and graphene / copper carbon-reinforced metal matrix composites are cut and polished into 5mm×6mm×2mm pads, followed by 3μm electroless nickel plating and 1μm gold electroplating. An 80μm thick solder is printed on the copper layer of the ceramic substrate, and the power semiconductor chip is vacuum reflowed (peak temperature 280-300°C). An 80μm thick solder is then printed on the top surface of the chip, and the pad is vacuum reflowed (peak temperature 280-300°C). An 80μm thick solder is printed on the copper layer of another ceramic substrate, and vacuum reflowed (peak temperature 280-300°C). An 80μm thick solder is printed on the outer copper layers of both ceramic substrates, and vacuum reflowed (peak temperature 280-300°C) is performed on the heat sinks on both sides to achieve substrate-heat sink interface connection. In order to compare the performance of double-sided cooling modules using carbon reinforced metal matrix composite pads and traditional pads, double-sided cooling modules with copper pads, copper-molybdenum composite pads and diamond / copper pads were also prepared.

[0074] The first is a comparison of heat dissipation performance. The thermal conductivity of the copper pad used is 390W / mK, the thermal conductivity of the copper-molybdenum pad is 200W / mK, the thermal conductivity of the diamond-copper pad is 550W / mK, the thermal conductivity of the diamond / aluminum pad is 600W / mK, the thermal conductivity of the diamond / silver pad is 1200W / mK, the thermal conductivity of the graphene / silver pad is 830W / mK, and the thermal conductivity of the graphene / copper pad is 710W / mK. The power loss of the power semiconductor chip is 150W, the heat transfer coefficient of the upper and lower heat dissipation interfaces is 2500W / m2K, and the ambient temperature is 30°C. The maximum junction temperature results of the double-sided cooling chip based on the copper-molybdenum composite pad and the proposed diamond / silver pad are as follows: Figure 5 and Figure 6 When using copper-molybdenum composite spacers, the maximum junction temperature of the chip is approximately 132.4°C; when using diamond / silver spacers, the maximum junction temperature of the chip is approximately 122.6°C. The architecture proposed in this invention reduces the maximum junction temperature of the chip by approximately 10°C.

[0075] The second is the comparison of thermal stress. In order to make the comparison effect more obvious, this embodiment places the module in an environment of 300°C to analyze the thermal stress of the module. The thermal expansion coefficient of the copper pad used is 17ppm / K, the thermal expansion coefficient of the copper-molybdenum pad is 8ppm / K, the thermal expansion coefficient of the diamond / copper is 7.5ppm / K, the thermal expansion coefficient of the diamond / aluminum pad is 7ppm / K, the thermal expansion coefficient of the diamond / silver pad is 6.5ppm / K, the thermal expansion coefficient of the graphene / silver pad is 7ppm / K, and the thermal expansion coefficient of the graphene / copper pad is 6.7ppm / K. The thermal stress results of the double-sided cooling module based on the copper pad and the proposed diamond / silver pad are as follows: Figure 7 and Figure 8 When copper pads are used, the maximum thermal stress reaches 2431.8 MPa, and the module experiences significant thermal deformation. When diamond / silver pads are used, the maximum thermal stress reaches 1486.9 MPa, and the module experiences almost no thermal deformation. The proposed architecture reduces maximum thermal stress by approximately 40%.

[0076] The maximum junction temperature results and thermal stress results of the chips using copper pads, copper-molybdenum composite pads, diamond / copper pads, diamond / aluminum pads, diamond / silver pads, graphene / silver pads and graphene / copper pads are summarized in Table 1. It can be seen that although the heat dissipation performance of the copper pads is slightly better than that of the copper-molybdenum composite pads, their severely mismatched thermal expansion coefficients cause the double-sided cooling module to bear greater thermal stress. The thermal expansion coefficients of the copper-molybdenum composite pads are more matched, but their heat dissipation performance is poor. Although the diamond / copper pads can balance the problems of heat dissipation performance and thermal stress, their effect is not as good as the carbon-reinforced metal-based composite pads proposed in the present invention. Therefore, the carbon-reinforced metal-based composite pads used in the present invention have obvious advantages over traditional methods in terms of both heat dissipation performance and thermal expansion coefficient matching.

[0077] Table 1

[0078]

[0079]

[0080] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A power semiconductor module packaging architecture, characterized in that: The packaging architecture includes: a first radiator base plate; a first copper-clad ceramic substrate located on the first radiator bottom plate; a power semiconductor chip located on the first copper-clad ceramic substrate, wherein the power semiconductor chip is connected to the first copper-clad ceramic substrate via a first solder layer; A carbon-reinforced metal-based composite material pad located on the power semiconductor chip, wherein the pad is connected to the power semiconductor chip via a second solder layer; a second copper-clad ceramic substrate positioned on the carbon-reinforced metal matrix composite pad; a second radiator base plate located on the second copper-clad ceramic substrate; Among them, the power semiconductor chip, carbon reinforced metal matrix composite material pad and solder layer are integrally bonded and sealed by potting glue.

2. The power semiconductor module packaging architecture according to claim 1, wherein: The carbon-reinforced metal-based composite material pad is made of diamond / aluminum, diamond / silver, graphene / silver or graphene / copper composite material.

3. The power semiconductor module packaging architecture according to claim 1, wherein: The power semiconductor chip is a power semiconductor chip based on silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) material.

4. The power semiconductor module packaging architecture according to claim 1, wherein: The first solder layer and the second solder layer include lead-containing solder, lead-free solder, gold-tin solder or nano-silver paste.

5. The power semiconductor module packaging architecture according to claim 1, wherein: The first copper-clad ceramic substrate and the second copper-clad ceramic substrate are selected from aluminum nitride (AlN), aluminum oxide (Al2O3), zirconium-toughened alumina (ZTA) or silicon nitride (Si3N4).

6. The power semiconductor module packaging architecture according to claim 1, wherein: The first radiator base plate and the second radiator base plate are made of copper, aluminum or aluminum silicon carbide (AlSiC) material.

7. A method for preparing a power semiconductor module packaging architecture, characterized in that: The steps include: 1) preparing a carbon reinforced metal matrix composite spacer and performing surface nickel plating and gold / silver plating treatment; 2) printing solder on the first copper-clad ceramic substrate and soldering the power semiconductor chip thereon; 3) Printing solder on the power semiconductor chip and welding the carbon reinforced metal matrix composite pad to the chip surface; 4) printing solder on the second copper-clad ceramic substrate, and welding the carbon-reinforced metal matrix composite pad to the second copper-clad ceramic substrate; 5) Welding the first and second radiator base plates to the outer sides of the first and second copper-clad ceramic substrates respectively; 6) The overall structure is encapsulated.

8. The preparation method according to claim 7, wherein The soldering step is performed using a reflow soldering or sintering process.

9. The preparation method according to claim 7, wherein The potting adopts silicone or epoxy potting materials with excellent high temperature resistance and moisture heat resistance.

10. A method for designing a heat dissipation path for a power semiconductor module, characterized in that: include: Heat dissipation path No. 1: power semiconductor chip → first solder layer → first copper-clad ceramic substrate → radiator base plate; Heat dissipation path No. 2: power semiconductor chip → second solder layer → carbon reinforced metal matrix composite material pad → third solder layer → second copper-clad ceramic substrate → radiator base plate.

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