SiC power semiconductor module with low parasitic parameter and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a SiC power semiconductor module with low parasitic parameters and a preparation method thereof. Background Art

[0002] With the rapid development of new energy vehicles, renewable energy generation, industrial inverters, and other fields, power electronics systems are placing higher demands on the power density, switching frequency, and reliability of power semiconductor modules. Silicon carbide (SiC) devices, due to their high voltage resistance, low conduction loss, and high-frequency operation, are gradually replacing traditional silicon (Si)-based devices and becoming the preferred choice for high-voltage, high-power applications. However, existing SiC power modules still face the following key challenges in packaging design:

[0003] Heat dissipation bottleneck: The high power density of SiC devices causes the chip junction temperature to rise rapidly, while the traditional single-sided heat dissipation structure has a large thermal resistance and insufficient heat dissipation efficiency, which easily causes thermal stress concentration and reduces the long-term reliability of the module.

[0004] Parasitic parameter issues: Traditional power modules utilize wire bonding and a single-sided interconnect structure, resulting in high parasitic inductance in the circuit. This can cause severe voltage overshoot and oscillation during high-frequency switching, increasing switching losses and potentially damaging the device. Furthermore, high parasitic capacitance can also compromise signal integrity at high frequencies.

[0005] Increased electromagnetic interference: Due to the extremely fast switching speed of SiC devices, the high parasitic inductance and asymmetric layout inside the module will aggravate high-frequency electromagnetic noise, affect the electromagnetic compatibility performance of the system, and increase the design difficulty and cost of the filter circuit.

[0006] To address the above issues, an innovative packaging technology is urgently needed to achieve efficient double-sided heat dissipation while reducing parasitic parameters and optimizing electromagnetic compatibility.

[0007] Through the above analysis, the problems and defects of the existing technology are as follows:

[0008] (1) Heat dissipation bottleneck: The high power density of SiC devices causes the chip junction temperature to rise rapidly, while the traditional single-sided heat dissipation structure has a large thermal resistance and insufficient heat dissipation efficiency, which easily causes thermal stress concentration and reduces the long-term reliability of the module.

[0009] (2) Parasitic parameter issues: Traditional power modules use wire bonding and a single-sided interconnect structure, resulting in large parasitic inductance in the circuit. This can cause severe voltage overshoot and oscillation during high-frequency switching, increasing switching losses and potentially damaging the device. Furthermore, high parasitic capacitance can also affect signal integrity under high-frequency conditions.

[0010] (3) Increased electromagnetic interference: Due to the extremely fast switching speed of SiC devices, the high parasitic inductance and asymmetric layout inside the module will aggravate high-frequency electromagnetic noise, affect the electromagnetic compatibility performance of the system, and increase the design difficulty and cost of the filter circuit. Summary of the Invention

[0011] In view of the problems existing in the prior art, the present invention provides a SiC power semiconductor module with low parasitic parameters and a preparation method thereof.

[0012] The present invention is implemented as follows: a SiC power semiconductor module with low parasitic parameters includes:

[0013] SiC power semiconductor chip, SiC power semiconductor chip substrate pad, positive power terminal, negative power terminal, output power terminal, positive side intermediate layer intermediate layer pad, positive side ceramic decoupling capacitor, positive side substrate intermediate layer pad, negative side intermediate layer intermediate layer pad, negative side ceramic decoupling capacitor, negative side substrate intermediate layer pad, first copper-clad ceramic substrate, third copper-clad ceramic substrate, fourth copper-clad ceramic substrate, second copper-clad ceramic substrate, first commutation circuit intermediate copper layer, second commutation circuit intermediate copper layer;

[0014] SiC power semiconductor chips include but are not limited to SiC MOSFET, SiC JFET, SiCIGBT and SiC diode chips;

[0015] SiC power semiconductor chip substrate pads include but are not limited to copper pads, molybdenum pads, copper-molybdenum composite pads and other composite material pads;

[0016] The first copper-clad ceramic substrate, the third copper-clad ceramic substrate, the fourth copper-clad ceramic substrate, and the second copper-clad ceramic substrate include, but are not limited to, AlN, Al2O3, ZTA, and Si3N4 ceramic materials.

[0017] Furthermore, the commutation method of the intermediate copper layer of the first commutation loop is as follows:

[0018] Start from the positive side ceramic decoupling capacitor, then pass through the SiC power semiconductor chip and SiC power semiconductor chip substrate spacer to the negative side ceramic decoupling capacitor, and then pass through the negative side substrate middle layer spacer to the middle copper layer of the first commutation circuit;

[0019] Finally, it returns to the positive side ceramic decoupling capacitor through the intermediate layer pad of the positive side substrate;

[0020] In the first commutation loop, the current directions in the two paths from the SiC power semiconductor chip substrate pad to the SiC power semiconductor chip and the copper layer between the first commutation loop are opposite, thereby achieving mutual inductance cancellation and reducing the parasitic inductance of the first commutation loop.

[0021] Furthermore, the commutation method of the middle copper layer of the second commutation loop is as follows:

[0022] Start from the positive side ceramic decoupling capacitor, then pass through the SiC power semiconductor chip and SiC power semiconductor chip substrate spacer to the negative side ceramic decoupling capacitor, and then pass through the negative side substrate middle layer spacer to the middle copper layer of the first commutation circuit;

[0023] Then it passes through the intermediate layer block on the negative side to the intermediate copper layer of the second commutation circuit, then passes through the intermediate layer block on the positive side back to the intermediate copper layer of the first commutation circuit, and finally passes through the intermediate layer block on the positive side substrate back to the positive side ceramic decoupling capacitor;

[0024] In the second commutation loop, the current directions from the positive-side ceramic decoupling capacitor to the SiC power semiconductor chip, and from the SiC power semiconductor chip substrate pad to the negative-side ceramic decoupling capacitor and the middle copper layer path of the second commutation loop are opposite, thereby achieving mutual inductance cancellation and reducing the parasitic inductance of the second commutation loop.

[0025] Another object of the present invention is to provide a method for preparing a SiC power semiconductor module with low parasitic parameters, comprising:

[0026] Step 1: laminating the first and second copper-clad ceramic substrates and the third and fourth copper-clad ceramic substrates respectively by welding / sintering;

[0027] Step 2: Print solder on the copper-clad ceramic substrate, and solder / sinter the SiC power semiconductor chip, the pad, the power terminal, and the ceramic decoupling capacitor to the copper-clad ceramic substrate;

[0028] Step 3: Print solder on the copper-clad ceramic substrate and electrically interconnect the SiC power semiconductor chip and the two pairs of stacked copper-clad ceramic substrates through welding / sintering;

[0029] Step 4: Add potting material to the welded / sintered module by injection and solidify.

[0030] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0031] The invention proposes a new double-sided cooling SiC power module structure, which effectively reduces parasitic inductance and suppresses electromagnetic interference through low-inductance interconnection design and three-dimensional integrated packaging, providing an ideal solution for high-power density and high-reliability power electronic systems.

[0032] The present invention proposes a SiC power semiconductor module with low parasitic parameters and a preparation method thereof, which has the following advantages:

[0033] The innovative integration of ceramic decoupling capacitors in double-sided cooled SiC power semiconductor modules shortens the commutation loop path of the SiC power semiconductor modules, thereby reducing the parasitic inductance of the modules.

[0034] By using the copper interlayer of the multilayer copper-clad ceramic substrate to provide a commutation path for the SiC power semiconductor devices, the innovative concept of mutual inductance cancellation in the dual commutation circuits is introduced, further reducing the module's parasitic inductance. Furthermore, the interlayer of the multilayer copper-clad ceramic substrate acts as an electromagnetic interference shield, suppressing the propagation of electromagnetic interference, thereby reducing the design difficulty and cost of the filter circuit.

[0035] The innovative solution of the present invention effectively reduces the parasitic inductance of the double-sided cooled SiC power semiconductor module, provides a reliable solution for high-power density and high-reliability power electronic systems, and has broad application prospects.

[0036] Unlike traditional double-sided cooled SiC power semiconductor modules, the SiC power semiconductor module with low parasitic parameters proposed by the present invention replaces the single copper-clad ceramic substrates on the bottom and top layers with laminated copper-clad ceramic substrates. The proposed structure connects the positive and negative ceramic decoupling capacitors in series through the pad and the middle copper layer of the laminated copper-clad ceramic substrate. Therefore, the proposed double-sided cooled SiC power semiconductor module will commutate through the middle copper layer of the laminated ceramic substrate, that is, it has two commutation loops. The proposed structure can also clamp the potential value of the middle copper layer of the laminated copper-clad ceramic substrate to half of the DC bus voltage, thereby suppressing the electromagnetic interference signal inside the module. Therefore, the middle copper layer of the laminated ceramic substrate also acts as an electromagnetic interference shielding layer.

[0037] The technical solution of the present invention solves a technical problem that people have been eager to solve but have never been able to successfully solve. Although the traditional SiC double-sided cooling power semiconductor module uses a pad with smaller parasitic parameters to replace the bonding wire of the traditional single-sided cooling module to achieve electrical connection, the power terminal of the SiC double-sided cooling power semiconductor module will still introduce a large parasitic inductance in the commutation circuit. In response to the above problem, the present invention reduces the area of the commutation circuit by integrating a ceramic decoupling capacitor inside the module, thereby reducing the parasitic inductance of the SiC dual-mode cooling power semiconductor module. The present invention also provides two commutation circuits for the module through the middle copper layer of the laminated copper-clad ceramic substrate, and further reduces the parasitic inductance of the module by mutual inductance cancellation in the two circulating circuits. In addition, the proposed structure can also clamp the potential value of the middle copper layer of the laminated copper-clad ceramic substrate to half of the DC bus voltage, thereby suppressing the electromagnetic interference signal inside the module. Therefore, the middle copper layer of the laminated ceramic substrate also acts as an electromagnetic interference shielding layer. Compared with the existing technology, the structure proposed in the present invention achieves a significant reduction in parasitic inductance and a significant improvement in electromagnetic compatibility while maintaining excellent heat dissipation performance by optimizing the current path and electric field distribution, providing an ideal solution for high-frequency and high-power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a structural block diagram of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0039] Figure 2 3 is a schematic front view of the structure of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0040] Figure 3 1 is a schematic side view of the structure of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0041] Figure 4 This is a first commutation circuit diagram of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0042] Figure 5 This is a second commutation circuit diagram of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0043] Figure 6 This is a flow chart for preparing a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0044] Figure 7 1 is a diagram showing the parasitic inductance extraction results of a SiC double-sided cooling power semiconductor module without integrated ceramic decoupling capacitors provided by an embodiment of the present invention.

[0045] Figure 8 4 is a diagram showing the parasitic inductance extraction results of a SiC power semiconductor module with low parasitic parameters provided by an embodiment of the present invention.

[0046] In the figure: 1. SiC power semiconductor chip; 2. SiC power semiconductor chip substrate pad; 3. Positive power terminal; 4. Negative power terminal; 5. Output power terminal; 6. Positive side intermediate layer intermediate layer pad; 7. Positive side ceramic decoupling capacitor; 8. Positive side substrate intermediate layer pad; 9. Negative side intermediate layer intermediate layer pad; 10. Negative side ceramic decoupling capacitor; 11. Negative side substrate intermediate layer pad; 12. First copper-clad ceramic substrate; 13. Third copper-clad ceramic substrate; 14. Fourth copper-clad ceramic substrate; 15. Second copper-clad ceramic substrate; 16. First commutation circuit intermediate copper layer; 17. Second commutation circuit intermediate copper layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] like Figure 1 As shown, an embodiment of the present invention provides a SiC power semiconductor module with low parasitic parameters, including:

[0049] SiC power semiconductor chip 1, SiC power semiconductor chip substrate spacer 2, positive power terminal 3, negative power terminal 4, output power terminal 5, positive side intermediate layer spacer 6, positive side ceramic decoupling capacitor 7, positive side substrate intermediate layer spacer 8, negative side intermediate layer spacer 9, negative side ceramic decoupling capacitor 10, negative side substrate intermediate layer spacer 11, first copper-clad ceramic substrate 12, third copper-clad ceramic substrate 13, fourth copper-clad ceramic substrate 14, second copper-clad ceramic substrate 15, first commutation circuit intermediate copper layer 16, second commutation circuit intermediate copper layer 17;

[0050] SiC power semiconductor chips 1 include but are not limited to SiC MOSFET, SiC JFET, SiCIGBT and SiC diode chips;

[0051] The SiC power semiconductor chip substrate pads 2 include but are not limited to copper pads, molybdenum pads, copper-molybdenum composite pads and other composite material pads;

[0052] The first copper-clad ceramic substrate 12 , the third copper-clad ceramic substrate 13 , the fourth copper-clad ceramic substrate 14 and the second copper-clad ceramic substrate 15 include, but are not limited to, AlN, Al 2 O 3 , ZTA and Si 3 N 4 ceramic materials.

[0053] The commutation method of the middle copper layer 16 of the first commutation loop provided by the embodiment of the present invention is as follows:

[0054] Start from the positive side ceramic decoupling capacitor, then pass through the SiC power semiconductor chip and SiC power semiconductor chip substrate spacer to the negative side ceramic decoupling capacitor, and then pass through the negative side substrate middle layer spacer to the middle copper layer of the first commutation circuit;

[0055] Finally, it returns to the positive side ceramic decoupling capacitor through the intermediate layer pad of the positive side substrate;

[0056] In the first commutation loop, the current directions in the two paths from the SiC power semiconductor chip substrate pad to the SiC power semiconductor chip and the copper layer between the first commutation loop are opposite, thereby achieving mutual inductance cancellation and reducing the parasitic inductance of the first commutation loop.

[0057] The commutation method of the middle copper layer 17 of the second commutation loop provided by the embodiment of the present invention is as follows:

[0058] Start from the positive side ceramic decoupling capacitor, then pass through the SiC power semiconductor chip and SiC power semiconductor chip substrate spacer to the negative side ceramic decoupling capacitor, and then pass through the negative side substrate middle layer spacer to the middle copper layer of the first commutation circuit;

[0059] Then it passes through the intermediate layer block on the negative side to the intermediate copper layer of the second commutation circuit, then passes through the intermediate layer block on the positive side back to the intermediate copper layer of the first commutation circuit, and finally passes through the intermediate layer block on the positive side substrate back to the positive side ceramic decoupling capacitor;

[0060] In the second commutation loop, the current directions from the positive-side ceramic decoupling capacitor to the SiC power semiconductor chip, and from the SiC power semiconductor chip substrate pad to the negative-side ceramic decoupling capacitor and the middle copper layer path of the second commutation loop are opposite, thereby achieving mutual inductance cancellation and reducing the parasitic inductance of the second commutation loop.

[0061] 1. In this double-sided cooled SiC module, the SiC power semiconductor chip 1 is metallurgically bonded (positionally) to the substrate pad 2 and the first copper-clad ceramic substrate 12 through high-temperature brazing or a silver sintered layer. This allows the chip heat to be directly transferred to the ceramic substrate and simultaneously discharged through the upper and lower heat dissipation surfaces, minimizing the interface thermal resistance (R_interface↓) and balancing the thermal gradient.

[0062] 2. The first commutation loop intermediate copper layer 16 and the second commutation loop intermediate copper layer 17 are placed between the fourth copper-clad ceramic substrate 14 and the second copper-clad ceramic substrate 15. Their mirror-image layout (connection relationship) ensures that the currents in the two return paths flow in opposite directions, canceling out the self-inductance L_self formed by the wire loops (ΔL ≈ 0), thereby reducing the overall parasitic inductance L_par. Furthermore, the copper layer thickness, trace width, and spacing are optimized through electromagnetic simulation to control the coupling coefficient between the distributed capacitance C_par and the distributed inductance.

[0063] 3. The positive power terminal 3, negative power terminal 4, and output power terminal 5 are tightly connected to the copper layer of the copper-clad ceramic substrate via a metal bonding layer, and form low-resistance contact with the intermediate layer pads 6, 9, 11 and decoupling capacitors 7 and 10. The decoupling capacitors are placed close to the power terminals, which can effectively reduce the loop area (A_loop↓) and suppress high-frequency electromagnetic interference. The O-ring and metal pressure plate cooperate to ensure the protection level and electrical insulation reliability of the inner and outer shells of the module.

[0064] 4. The entire module adopts a composite process of bolt pre-tightening and quantitative bonding. Elastic washers and metal studs are used to apply uniform compressive stress (σ_pre≈10–20MPa) between the ceramic substrate and the water-cooled plate to ensure stable contact resistance of each metallization layer, via, and commutation copper layer. At the same time, the matching design of different CTE materials and finite element thermal-mechanical coupling analysis are used to achieve a balance between interface stress relaxation and structural stiffness during thermal cycling, ensuring electrical-thermal-mechanical reliability under long-term operation.

[0065] The present invention is specifically implemented:

[0066] The present invention proposes a SiC power semiconductor module with low parasitic parameters and a preparation method thereof, which effectively reduces parasitic inductance and suppresses electromagnetic interference through low-inductance interconnect design and three-dimensional integrated packaging. The structure of the SiC power semiconductor module with low parasitic parameters is as follows: Figures 1 to 3 As shown, it mainly includes SiC power semiconductor chips, spacers, power terminals, copper-clad ceramic substrates, and ceramic decoupling capacitors. Among them, SiC power semiconductor chips include but are not limited to SiC MOSFETs, SiC JFETs, SiC IGBTs, and SiC diode chips; spacers include but are not limited to copper spacers, molybdenum spacers, copper-molybdenum composite spacers, and other composite spacers; copper-clad ceramic substrates include but are not limited to ceramic materials such as AlN, Al2O3, ZTA, and Si3N4.

[0067] Unlike traditional double-sided cooled SiC power semiconductor modules, the SiC power semiconductor module with low parasitic parameters proposed by the present invention replaces the single copper-clad ceramic substrates on the bottom and top layers with laminated copper-clad ceramic substrates. The proposed structure connects the positive and negative ceramic decoupling capacitors in series through the pad and the middle copper layer of the laminated copper-clad ceramic substrate. Therefore, the proposed double-sided cooled SiC power semiconductor module will commutate through the middle copper layer of the laminated ceramic substrate, that is, it has two commutation loops. The proposed structure can also clamp the potential value of the middle copper layer of the laminated copper-clad ceramic substrate to half of the DC bus voltage, thereby suppressing the electromagnetic interference signal inside the module. Therefore, the middle copper layer of the laminated ceramic substrate also acts as an electromagnetic interference shielding layer.

[0068] like Figure 4 The figure shows the first commutation circuit of the proposed SiC power semiconductor module with low parasitic parameters. The commutation path is as follows: starting from the positive-side ceramic decoupling capacitor, then passing through the SiC power semiconductor chip and the SiC power semiconductor chip substrate spacer to the negative-side ceramic decoupling capacitor, then passing through the negative-side substrate intermediate layer spacer to the intermediate copper layer of the first commutation circuit, and finally returning to the positive-side ceramic decoupling capacitor through the positive-side substrate intermediate layer spacer. In the first commutation circuit, the current directions in the two paths—from the SiC power semiconductor chip substrate spacer to the SiC power semiconductor chip and the intermediate copper layer of the first commutation circuit—are opposite, thus achieving mutual inductance cancellation and reducing the parasitic inductance of the first commutation circuit.

[0069] like Figure 5 The second commutation circuit of the proposed SiC power semiconductor module with low parasitic parameters is shown. Its commutation path is as follows: starting from the positive-side ceramic decoupling capacitor, then passing through the SiC power semiconductor chip and the SiC power semiconductor chip substrate pad to the negative-side ceramic decoupling capacitor, then passing through the negative-side substrate intermediate layer pad to the middle copper layer of the first commutation circuit, then passing through the negative-side intermediate layer intermediate layer pad to the middle copper layer of the second commutation circuit, then passing through the positive-side intermediate layer intermediate layer pad back to the middle copper layer of the first commutation circuit, and finally passing through the positive-side substrate intermediate layer pad back to the positive-side ceramic decoupling capacitor. In the second commutation circuit, the current directions of the positive-side ceramic decoupling capacitor to the SiC power semiconductor chip and the SiC power semiconductor chip substrate pad to the negative-side ceramic decoupling capacitor are opposite to those of the second commutation circuit middle copper layer, thereby achieving mutual inductance cancellation and reducing the parasitic inductance of the second commutation circuit.

[0070] The embodiment of the present invention provides a method for preparing a SiC power semiconductor module with low parasitic parameters, and the preparation process is as follows: Figure 6 As shown, it mainly includes the following four steps:

[0071] S101, laminating the first and second copper-clad ceramic substrates and the third and fourth copper-clad ceramic substrates respectively by welding / sintering;

[0072] S102, printing solder on the copper-clad ceramic substrate, and soldering / sintering the SiC power semiconductor chip, the spacer, the power terminal, and the ceramic decoupling capacitor to the copper-clad ceramic substrate;

[0073] S103, printing solder on the copper-clad ceramic substrate, and electrically interconnecting the SiC power semiconductor chip and the two pairs of stacked copper-clad ceramic substrates through welding / sintering;

[0074] S104, adding potting material to the welded / sintered module by injection and curing.

[0075] Another object of the present invention is to provide a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method for preparing a SiC power semiconductor module with low parasitic parameters.

[0076] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the method for preparing a SiC power semiconductor module with low parasitic parameters.

[0077] Another object of the present invention is to provide an information data processing terminal, wherein the information data processing terminal is used to implement the SiC power semiconductor module with low parasitic parameters.

[0078] Low parasitic parameters: refers to the low parasitic resistance, inductance, capacitance, and other parameters introduced by the device structure or packaging, which can reduce energy loss and signal interference, and improve switching performance. Double-sided cooling: Dissipates heat simultaneously on the top and bottom surfaces of the power device (for example, heat sinks are added to both the top and bottom). SiC: A third-generation semiconductor material with high voltage and high temperature resistance and low conduction losses. Power semiconductor module: A semiconductor module (such as MOSFET, IGBT) used for power conversion and control.

[0079] The preparation process of a SiC power semiconductor module with low parasitic parameters proposed in this embodiment is as follows: 80μm thick solder is printed on the surfaces of the first and third copper-clad ceramic substrates, and these are vacuum reflowed (peak temperature 280°C) with the second and fourth copper-clad ceramic substrates to achieve the lamination of the copper-clad ceramic substrates; 80μm thick solder is printed on the copper layers of the two laminated ceramic substrates, and the SiC power semiconductor chip, pad, power terminal and ceramic decoupling capacitor are vacuum reflowed (peak temperature 280°C); 80μm thick solder is further printed on the copper layers of the two laminated ceramic substrates, and vacuum reflowed (peak temperature 280°C) is performed to achieve electrical interconnection between the SiC power semiconductor chip and the two pairs of laminated copper-clad ceramic substrates; finally, the soldered module is injected with potting material and cured. This embodiment module integrates ceramic decoupling capacitors in the double-sided cooling SiC power semiconductor module, shortening the commutation circuit path of the SiC power semiconductor module, thereby reducing the module's parasitic inductance. This embodiment also uses the middle layer of copper in the laminated copper-clad ceramic substrate to provide a commutation path for the SiC power semiconductor device, introducing the concept of mutual inductance cancellation in the dual commutation circuit, further reducing the parasitic inductance of the module. In addition, the middle layer of the laminated copper-clad ceramic substrate in this embodiment also acts as an electromagnetic interference shielding layer, suppressing the propagation of electromagnetic interference, thereby reducing the design difficulty and cost of the filter circuit. In order to compare the performance of the proposed SiC power semiconductor module with low parasitic parameters, a SiC double-sided cooling power semiconductor module without integrated ceramic decoupling capacitors was also prepared.

[0080] like Figure 7 The figure shows the parasitic inductance extraction results of a SiC double-sided cooling power semiconductor module without integrated ceramic decoupling capacitors. The parasitic inductance of the module is 34.9nH at a frequency of 10MHz. Figure 8 The figure shows the parasitic inductance extraction results for the SiC power semiconductor module with low parasitic parameters proposed in this embodiment. At a frequency of 10MHz, the module's parasitic inductance is 5.1nH, which is approximately 60% lower than the parasitic inductance of a SiC double-sided cooled power semiconductor module without integrated ceramic decoupling capacitors. By optimizing the current path and electric field distribution, the module proposed in this embodiment achieves a significant reduction in parasitic inductance and a significant improvement in electromagnetic compatibility while maintaining the excellent heat dissipation performance of the SiC double-sided cooled power semiconductor module, providing an ideal solution for high-frequency, high-power applications.

[0081] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A SiC power semiconductor module with low parasitic parameters, characterized in that: include: SiC power semiconductor chips; SiC power semiconductor chip-substrate spacer; Positive power terminal, negative power terminal, output power terminal; Positive electrode side intermediate layer-pad, negative electrode side intermediate layer-pad; Positive side ceramic decoupling capacitor, negative side ceramic decoupling capacitor; Positive electrode side substrate-intermediate layer spacer, negative electrode side substrate-intermediate layer spacer; a first copper-clad ceramic substrate, a second copper-clad ceramic substrate, a third copper-clad ceramic substrate, and a fourth copper-clad ceramic substrate; a first commutation loop middle copper layer and a second commutation loop middle copper layer; Wherein, the SiC power semiconductor chip is connected to the SiC power semiconductor chip-substrate pad via a metal bonding layer; The SiC power semiconductor chip-substrate spacer is connected to the first copper-clad ceramic substrate via a metal bonding layer; The middle copper layer of the first commutation circuit is electrically connected to the fourth copper-clad ceramic substrate and the second copper-clad ceramic substrate; The second commutation loop middle copper layer is electrically connected to the fourth copper-clad ceramic substrate and the second copper-clad ceramic substrate.

2. The double-sided cooling SiC power semiconductor module according to claim 1, characterized in that: The SiC power semiconductor chip is selected from any one of SiC MOSFET, SiC JFET, SiC IGBT and SiC diode.

3. The double-sided cooling SiC power semiconductor module according to claim 1, characterized in that: The SiC power semiconductor chip-substrate pad is selected from any one of a copper pad, a molybdenum pad, a copper-molybdenum composite pad or other metal composite material pads.

4. The double-sided cooling SiC power semiconductor module according to claim 1, wherein: The first, second, third and fourth copper-clad ceramic substrates are respectively composed of any one of AlN-based copper-clad ceramic, Al2O3-based copper-clad ceramic, ZTA-based copper-clad ceramic or Si3N4-based copper-clad ceramic.

5. The double-sided cooling SiC power semiconductor module according to claim 1, wherein: The positive side ceramic decoupling capacitor is arranged between the positive side intermediate layer-pad and the positive side substrate-intermediate layer pad, and is electrically connected to the positive side substrate-intermediate layer pad through the copper layer on the surface of the copper-clad ceramic substrate.

6. The double-sided cooling SiC power semiconductor module according to claim 1, characterized in that: The negative side ceramic decoupling capacitor is arranged between the negative side intermediate layer-pad and the negative side substrate-intermediate layer pad, and is electrically connected to the negative side substrate-intermediate layer pad through the copper layer on the surface of the copper-clad ceramic substrate.

7. The double-sided cooling SiC power semiconductor module according to claim 1, wherein: The middle copper layer of the first commutation loop is electrically connected to the third copper-clad ceramic substrate and the first copper-clad ceramic substrate through metallized vias.

8. The double-sided cooling SiC power semiconductor module according to claim 1, wherein: The positive power terminal, the negative power terminal and the output power terminal are respectively mechanically fastened to the surface of the corresponding copper-clad ceramic substrate through a metal bonding layer.

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