Voltage margin adjusting circuit, power management circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of power circuits, in particular to a voltage margin adjusting circuit, a power management circuit, a chip and electronic equipment. The voltage margin adjusting circuit comprises a voltage margin collecting circuit, a transconductance amplifier and a feedback voltage generating circuit. The voltage margin collecting circuit obtains third voltage according to the difference value of the first output voltage and the second output voltage. The transconductance amplifier obtains a first current according to the first reference voltage and the third voltage; the feedback voltage generation circuit is used for generating corresponding feedback voltage according to the first current; therefore, equivalently, the voltage margin of the low-dropout regulator at the current moment is sampled in real time to adjust the magnitude of the feedback voltage, and finally, the first DC-DC converter adjusts the first output voltage output at the next moment according to the adjusted feedback voltage and the second reference voltage, so that the voltage margin of the low-dropout regulator is dynamically adjusted. Normal work of devices in the circuit can be guaranteed, and electric energy waste is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of power supply circuits, and in particular to a voltage margin adjustment circuit, a power management circuit, a chip, and an electronic device. Background Art

[0002] In electronic devices, batteries are usually used to power the electronic devices, and a power management module (PMU) is equipped to convert the battery voltage to the voltage required by the device, providing a stable power supply for subsequent devices. Generally, the power management module includes a first DC-DC converter and a low-dropout regulator. The first DC-DC converter is also called a DCDC converter, and the low-dropout regulator (LDO) is also called a low-dropout linear regulator or a low-dropout regulator. It is a type of linear DC regulator and has the same purpose of providing a stable DC voltage supply. The first DC-DC converter is first used to convert the battery voltage to a potential slightly higher than the target voltage, and then the output voltage of the first DC-DC converter is converted to the voltage required by the device through the low-dropout regulator.

[0003] In the related art, a certain headroom voltage is set for low-dropout voltage regulators. Headroom voltage is also called voltage margin. In a circuit, voltage margin is the voltage drop consumed within the circuit that cannot be converted into energy for the output voltage. Therefore, the voltage margin setting must be reasonable. If the voltage margin is set too large, it will lead to energy waste. If the voltage margin is set too low, the normal operation of the components in the circuit cannot be guaranteed. Therefore, in the related art, in order to ensure the normal operation of each component in the circuit, the voltage margin is usually set to a large fixed value. This will cause a certain amount of energy waste and reduce the energy conversion efficiency of the power management module. Summary of the Invention

[0004] The present application provides a voltage margin adjustment circuit, a power management circuit, a chip and an electronic device to solve the technical problem that the power management module in the related art may cause a certain amount of power waste, thereby reducing the energy conversion efficiency of the power management module.

[0005] In a first aspect, the present application provides a voltage margin adjustment circuit, which is applied to a power management circuit. The power management circuit includes a first DC-DC converter and a low-dropout voltage regulator, wherein the first DC-DC converter and the low-dropout voltage regulator are electrically connected, the first DC-DC converter is used to receive an input voltage and perform voltage conversion on the input voltage to obtain a first output voltage, and the low-dropout voltage regulator is used to process the first output voltage to obtain a second output voltage; characterized in that the voltage margin adjustment circuit includes: a voltage margin acquisition circuit, a transconductance amplifier, and a feedback voltage generation circuit;

[0006] The voltage margin acquisition circuit is configured to sample the first output voltage and the second output voltage, and obtain a third voltage according to a difference between the first output voltage and the second output voltage; the third voltage is used to represent the voltage margin of the low dropout regulator at a current moment;

[0007] The transconductance amplifier is configured to receive a first reference voltage and a third voltage, and obtain a first current according to the first reference voltage and the third voltage;

[0008] The feedback voltage generating circuit is configured to generate a corresponding feedback voltage according to the first current;

[0009] The first DC-DC converter is further configured to receive a second reference voltage and adjust the first output voltage to be output at a next moment according to the feedback voltage and the second reference voltage.

[0010] In one possible design, the voltage margin acquisition circuit includes a first sampling terminal and a second sampling terminal, the first sampling terminal being connected to the output terminal of the first DC-DC converter to sample the first output voltage, and the second sampling terminal being connected to the output terminal of the low-dropout regulator to sample the second output voltage;

[0011] The output end of the voltage margin acquisition circuit is connected to the negative input end of the transconductance amplifier to output the third voltage to the transconductance amplifier, and the positive input end of the transconductance amplifier is used to receive the first reference voltage;

[0012] The feedback voltage generation includes a current extraction circuit and a voltage divider circuit, wherein the input end of the voltage divider circuit is connected to the output end of the first DC-DC converter, and the output end of the voltage divider circuit is grounded; the current extraction circuit is connected to a first voltage dividing node on the voltage divider circuit, and the first DC-DC converter is connected to the first voltage dividing node or the second voltage dividing node on the voltage divider circuit to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node; wherein the voltage on the second voltage dividing node is less than the voltage on the first voltage dividing node;

[0013] The current extraction circuit includes an input end, an output end, and a driving end. The input end of the current extraction circuit is connected to a first voltage dividing node on the voltage dividing circuit, the output end of the current extraction circuit is grounded, and the driving end of the current extraction circuit is connected to the output end of the transconductance amplifier to receive the first current. The current extraction circuit is configured to pull up or pull down a feedback voltage on the first voltage dividing node or the second voltage dividing node when triggered by the first current.

[0014] The positive input terminal of the first DC-DC converter is used to receive the second reference voltage, and the negative input terminal of the first DC-DC converter is connected to the first voltage dividing node or the second voltage dividing node on the voltage dividing circuit to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node.

[0015] In one possible design, the voltage margin adjustment circuit further includes a first current limiting circuit, wherein the first current limiting circuit is connected to the current extraction circuit;

[0016] The first current limiting circuit is used to limit the third current on the current extraction circuit to be less than or equal to a first current threshold.

[0017] In one possible design, the voltage margin adjustment circuit further includes a second current limiting circuit, and the second current limiting circuit is connected to the current extraction circuit;

[0018] The second current limiting circuit is used to limit the third current on the current extraction circuit to be greater than or equal to a second current threshold.

[0019] In one possible design, the voltage margin acquisition circuit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, and a third transistor;

[0020] A first end of the first resistor is connected to the output end of the low-dropout regulator, a second end of the first resistor is connected to the first electrode of the first transistor, and a second electrode and a control electrode of the first transistor are both grounded;

[0021] A first end of the second resistor is connected to the output end of the first DC-DC converter, a second end of the second resistor is connected to the first electrode of the second transistor and the second electrode of the third transistor, respectively, the second electrode of the second transistor and the control electrode of the third transistor are both grounded, and the first electrode of the third transistor is grounded via the third resistor; the first electrode of the third transistor is the output end of the voltage margin acquisition circuit;

[0022] The resistance values of the first resistor, the second resistor and the third resistor are all the same.

[0023] In one possible design, the current extraction circuit includes a first capacitor, a fourth transistor, and a fourth resistor;

[0024] The first end of the first capacitor and the control electrode of the fourth transistor are both connected to the output end of the transconductance amplifier, the second electrode of the fourth transistor is connected to the first voltage dividing node on the voltage dividing circuit, and the first electrode of the fourth transistor is grounded through the fourth resistor.

[0025] In one possible design, the voltage divider circuit includes a fifth resistor, a sixth resistor, and a seventh resistor;

[0026] A first end of the fifth resistor is connected to the output end of the first DC-DC converter, a second end of the fifth resistor is connected to the first end of the sixth resistor, a second end of the sixth resistor is connected to the first end of the seventh resistor, and a second end of the seventh resistor is grounded.

[0027] In one possible design, the first current limiting circuit includes a fifth transistor, a sixth transistor, an error amplifier, and a seventh resistor;

[0028] The control electrode and the second electrode of the fifth transistor are both used to receive a first bias current, and the first electrode of the fifth transistor is grounded through the seventh resistor; the positive input terminal of the error amplifier is connected to the second electrode of the fifth transistor, and the reverse input terminal of the error amplifier is connected to the output terminal of the transconductance amplifier; the output terminal of the error amplifier is connected to the control electrode of the sixth transistor, the first electrode of the sixth transistor is used to receive a power supply voltage, and the second electrode of the sixth transistor is connected to the output terminal of the transconductance amplifier.

[0029] In one possible design, the second current limiting circuit includes a seventh transistor and an eighth transistor;

[0030] The control electrode of the seventh transistor, the second electrode of the seventh transistor, and the control electrode of the eighth transistor are all used to receive a second bias current, and the first electrode of the seventh transistor is grounded; the second electrode of the eighth transistor is connected to the second end of the fourth resistor, the first end of the fourth resistor is connected to the first electrode of the fourth transistor, and the first electrode of the eighth transistor is grounded.

[0031] In a second aspect, the present application further provides a power management circuit, the power management circuit comprising a first DC-DC converter and a low-voltage dropout regulator, the first DC-DC converter and the low-voltage dropout regulator being electrically connected, the first DC-DC converter being configured to receive an input voltage and perform voltage conversion on the input voltage to obtain a first output voltage, the low-voltage dropout regulator being configured to process the first output voltage to obtain a second output voltage;

[0032] The power management circuit further includes a voltage margin adjustment circuit as described in any one of the above items.

[0033] In a third aspect, the present application further provides a chip, comprising the voltage margin adjustment circuit as described in any one of the above items.

[0034] In a fourth aspect, the present application further provides an electronic device, which includes the voltage margin adjustment circuit as described in any one of the above items; or the electronic device includes the chip as described above.

[0035] The voltage margin adjustment circuit provided by the first aspect above includes: a voltage margin acquisition circuit, a transconductance amplifier, and a feedback voltage generation circuit, wherein the voltage margin acquisition circuit is used to sample the first output voltage and the second output voltage, and obtain a third voltage based on the difference between the first output voltage and the second output voltage; the third voltage is used to represent the voltage margin of the low-dropout regulator at the current moment; the transconductance amplifier is used to receive the first reference voltage and the third voltage, and obtain a first current based on the first reference voltage and the third voltage; the feedback voltage generation circuit is used to generate a corresponding feedback voltage based on the first current; this is equivalent to real-time sampling of the voltage margin of the low-dropout regulator at the current moment, converting the voltage margin into a first current, and then raising or lowering the feedback voltage according to the magnitude of the first current to adjust the magnitude of the feedback voltage. Finally, the first DC-DC converter adjusts the first output voltage output at the next moment based on the adjusted feedback voltage and the second reference voltage. This achieves dynamic adjustment of the voltage margin of the low-dropout regulator. In this way, even when the input voltage and output voltage of the low-dropout regulator change, the first output voltage of the low-dropout regulator can be dynamically feedback-adjusted, so that the voltage margin of the low-dropout regulator is always stable at a reasonable set value, thereby ensuring the normal operation of the components in the circuit without causing waste of electric energy, thereby improving the energy conversion efficiency of the power management module.

[0036] The beneficial effects provided in the above-mentioned other aspects and the possible designs of the above-mentioned other aspects can be referred to the beneficial effects brought about by the above-mentioned first aspect and the possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 One of the schematic diagrams of the power management module structure provided for related technologies;

[0038] Figure 2 A schematic diagram of the headroom voltage provided in an embodiment of the present application;

[0039] Figure 3 The second schematic diagram of the power management module structure provided for related technologies;

[0040] Figure 4 This is one of the schematic diagrams of the voltage margin adjustment circuit structure provided in an embodiment of the present application;

[0041] Figure 5 This is the second schematic diagram of the voltage margin adjustment circuit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0043] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0044] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0045] The transistor in this application is a three-terminal transistor, whose three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field-effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field-effect transistor, its control electrode refers to the gate of the field-effect transistor, the first electrode can be the drain or source of the field-effect transistor, and the corresponding second electrode can be the source or drain of the field-effect transistor.

[0046] The power management module PMU is a commonly used functional circuit in circuits that can provide stable power supply for electronic devices. The power management module includes a first DC-DC converter and a low-voltage dropout regulator. The first DC-DC converter converts the battery voltage to a potential slightly higher than the target voltage, and then converts the output voltage of the first DC-DC converter into the voltage required by the device through the low-voltage dropout regulator. Figure 1 One of the schematic diagrams of the power management module structure provided for related technologies, see Figure 1 As shown, the power management module includes a first DC-DC converter 11 and a first low-voltage dropout regulator 12. The first DC-DC converter 11 is first used to convert the input voltage VIN to a level slightly higher than the target voltage. The first low-voltage dropout regulator 12 then converts the first output voltage Vo_dcdc of the first DC-DC converter 11 to the second output voltage Vo_1do required by the device. In this way, the first DC-DC converter 11 can achieve voltage conversion with high efficiency. The cascaded first low-voltage dropout regulator 12 can then filter out the ripple of the output voltage of the first DC-DC converter 11, thereby providing a stable power supply for the electronic device. Therefore, the power management module can achieve high-efficiency power conversion while ensuring that the output voltage of the first low-voltage dropout regulator 12 has low ripple.

[0047] Figure 2 For the headroom voltage diagram provided in the embodiment of this application, please refer to Figure 2 As shown, the first output voltage Vo_dcdc of the first DC-DC converter 11 has a certain ripple, which is processed by the first low-dropout regulator 12 to output a stable second output voltage Vo_1do. The difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do is the headroom voltage of the first low-dropout regulator 12.

[0048] Usually, a certain headroom voltage is set for low-voltage difference regulators. The headroom voltage is also called voltage margin / voltage margin. In the circuit, the voltage margin is the voltage drop consumed inside the circuit and cannot be converted into energy for the output voltage. Therefore, the voltage margin setting should be reasonable. If the voltage margin is set too large, it will lead to waste of electric energy. If the voltage margin is set too low, the normal operation of the components in the circuit cannot be guaranteed. Therefore, in the related art, in order to ensure the normal operation of each component in the circuit, the voltage margin is usually set to a larger fixed value. Specifically, after determining the target voltage output by the low-voltage difference regulator, the first DC-DC converter is usually controlled to output a higher voltage to the low-voltage difference regulator, thereby ensuring that the low-voltage difference regulator has a larger voltage margin. This will cause a certain amount of electric energy waste and reduce the energy conversion efficiency of the power management module.

[0049] Furthermore, the numerous error factors that affect voltage margin setting also make it difficult to set a fixed voltage margin in related technologies. This is because, to ensure the normal operation of various components in the circuit, the voltage margin setting value is usually large. For example, error factors that commonly affect voltage margin setting include input voltage error, output voltage error, and reference voltage error of a low-dropout regulator, thus increasing the difficulty of voltage margin setting.

[0050] Figure 3 For the second schematic diagram of the power management module structure provided for related technologies, please refer to Figure 3As shown, the power management module includes a first DC-DC converter 11 and a first low-voltage dropout regulator 12. The input terminal of the first DC-DC converter 11 is used to receive an input voltage VIN and perform high-efficiency conversion on the input voltage VIN to obtain a first output voltage Vo_dcdc. The first low-voltage dropout regulator 12 performs voltage regulation and filtering on the first output voltage Vo_dcdc to obtain a second output voltage Vo_1do. The power management module also includes a first feedback voltage sampling device 13 and a second feedback voltage sampling device 14. The sampling terminal of the first feedback voltage sampling device 13 is connected to the output terminal of the first DC-DC converter 11, and the output terminal of the first feedback voltage sampling device 13 is connected to the negative input terminal of the first DC-DC converter 11. The first feedback voltage sampling device 13 is used to sample a first feedback voltage VFB1 corresponding to the first output voltage Vo_dcdc. The first feedback voltage VFB1 can reflect the magnitude change of the first output voltage Vo_dcdc. The sampling end of the second feedback voltage sampling 14 is connected to the output end of the first low-voltage difference regulator 12, and the output end of the second feedback voltage sampling 14 is connected to the negative input end of the first low-voltage difference regulator 12. The second feedback voltage sampling 14 is used to sample the second feedback voltage VFB2 corresponding to the second output voltage Vo_1do. The second feedback voltage VFB2 can reflect the change in the size of the second output voltage Vo_1do.

[0051] Specifically, the first feedback voltage sampling 13 provided in this embodiment includes an eleventh resistor R11 and a twelfth resistor R12, the first end of the eleventh resistor R11 is connected to the output end of the first DC-DC converter 11, the second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is grounded, and the first end of the twelfth resistor R12 is connected to the negative input end of the first DC-DC converter 11 to sample the first feedback voltage VFB1 on the first end of the twelfth resistor R12, and then output the sampled first feedback voltage VFB1 to the negative input end of the first DC-DC converter 11. The positive input end of the first DC-DC converter 11 is used to receive the eleventh reference voltage Vref11. The first DC-DC converter 11 includes a first output voltage feedback regulation module, which can feedback-regulate the first output voltage Vo_dcdc output by the first DC-DC converter 11 according to the eleventh reference voltage Vref11 and the first feedback voltage VFB1, so that the first output voltage Vo_dcdc output by the first DC-DC converter 11 is stabilized at a target value.

[0052] Among them, the second feedback voltage sampling 14 provided in this embodiment includes a thirteenth resistor R13 and a fourteenth resistor R14, the first end of the thirteenth resistor R13 is connected to the output end of the first low-voltage difference regulator 12, the second end of the thirteenth resistor R13 is connected to the first end of the fourteenth resistor R14, the second end of the fourteenth resistor R14 is grounded, and the first end of the fourteenth resistor R14 is connected to the negative input end of the first low-voltage difference regulator 12 to sample the second feedback voltage VFB2 on the first end of the fourteenth resistor R14, and then output the sampled second feedback voltage VFB2 to the negative input end of the first low-voltage difference regulator 12, and the positive input end of the first low-voltage difference regulator 12 is used to receive the twelfth reference voltage Vref12. The first low-voltage dropout regulator 12 includes a second output voltage feedback regulation module, which can feedback and regulate the second output voltage Vo_1do output by the first DC-DC converter 11 according to the twelfth reference voltage Vref12 and the second feedback voltage VFB2, so that the second output voltage Vo_1do output by the first low-voltage dropout regulator 12 is stable at a target value. In this embodiment, the relationship between the size of the eleventh resistor R11 and the twelfth resistor R12 can be set as: R 11 :R 12 =(K-1):1, the relationship between the thirteenth resistor R13 and the fourteenth resistor R14 can be set to: R 13 :R 14 =(K-1):1, where R 11 Indicates the resistance value of the eleventh resistor R11, R 12 Indicates the resistance value of the twelfth resistor R12, R 13 The resistance value of the thirteenth resistor R13, R 14 represents the resistance value of the fourteenth resistor R14, and K represents a preset voltage division coefficient.

[0053] As can be seen from the above description, in the related art, the output voltages of the first DC-DC converter 11 and the first low-dropout regulator 12 are generally feedback-regulated by setting corresponding reference voltages. The headroom voltage of the first low-dropout regulator 12 is the difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do. In this embodiment, several factors that have a significant impact on the headroom voltage are selected for analysis as follows:

[0054] First, due to the voltage feedback control error of the first DC-DC converter 11 and the first low-dropout voltage regulator 12, there is a certain error in the headroom voltage. For example, the voltage control error of the first DC-DC converter 11 is Vos_dcdc, the voltage control error of the first low-dropout voltage regulator 12 is Vos_ldo, and the headroom voltage is expressed as V hr, then the error ratio of the headroom voltage can be expressed as:

[0055]

[0056] Secondly, since the eleventh reference voltage Vref11 and the twelfth reference voltage Vref12 are also reference circuits generated by corresponding voltage generating circuits, and the voltage generating circuits themselves have certain errors when generating reference voltages, the generated eleventh reference voltage Vref11 and the twelfth reference voltage Vref12 are not accurate. Therefore, there will also be certain errors when adjusting the headroom voltage based on the eleventh reference voltage Vref11 and the twelfth reference voltage Vref12. For example, the error of the eleventh reference voltage Vref11 is expressed as Vos_vr1, and the error of the twelfth reference voltage Vref12 is expressed as Vos_vr2. Then, the proportion of the error of the eleventh reference voltage Vref11 and the twelfth reference voltage Vref12 in the headroom voltage can be expressed as:

[0057]

[0058] In addition, due to the process of the resistors themselves, there will be a certain error in the resistance value, which will lead to a mismatch in the resistor voltage divider. The mismatch in the resistor voltage divider will also cause a certain error in the headroom voltage. The mismatch in the voltage divider between the eleventh resistor R11 and the twelfth resistor R12 will cause a certain error in the first output voltage Vo_dcdc. The mismatch in the voltage divider between the thirteenth resistor R13 and the fourteenth resistor R14 will cause a certain error in the second output voltage Vo_1do. The first output voltage Vo_dcdc and the second output voltage Vo_1do will then cause a certain error in the headroom voltage. For example, in this embodiment, the error caused by the mismatch in the voltage divider between the eleventh resistor R11 and the twelfth resistor R12 is expressed as ΔK / K. The larger the value of the voltage divider coefficient K, the greater the error caused to the headroom voltage. The error caused by the mismatch in the resistor voltage divider can be expressed as:

[0059]

[0060] In summary, it can be understood that due to the influence of various factors in the circuit, there is a certain gap between the actual headroom voltage of the first low-dropout (LDO) regulator 12 and the ideal headroom voltage. When the actual headroom voltage is lower than the ideal headroom voltage, the performance of the first LDO regulator 12 is affected, resulting in increased ripple in the second output voltage Vo_ldo output by the first LDO regulator 12 and deterioration in the transient response of the first LDO regulator 12. Considering that the various error factors described above can cause a certain gap between the actual headroom voltage and the ideal headroom voltage, a larger headroom voltage is generally set to reduce the impact of these error factors on the headroom voltage. This further increases the loss of the first LDO regulator 12 and affects the operating efficiency of the first LDO regulator 12.

[0061] In order to overcome the deficiencies in the above-mentioned related technologies, the present application provides a voltage margin adjustment circuit. The voltage margin adjustment circuit is based on the concept of feedback regulation. By real-time acquisition of the input voltage and output voltage of the low-dropout regulator, a current for pulling up or down the feedback voltage is determined according to the difference between the input voltage and the output voltage. Then, the output voltage of the first DC-DC converter is adjusted in real time according to the feedback voltage after being pulled up or down and a preset reference voltage, that is, the input voltage of the low-dropout regulator is feedback-regulated, so that the voltage margin of the low-dropout regulator is always stable at a reasonable set value, thereby ensuring the normal operation of the devices in the circuit without causing waste of electric energy, thereby improving the energy conversion efficiency of the power management module.

[0062] Furthermore, the voltage margin adjustment circuit provided by the present application includes: a voltage margin acquisition circuit, a transconductance amplifier, and a feedback voltage generation circuit, wherein the voltage margin acquisition circuit is used to sample the first output voltage and the second output voltage, and obtain a third voltage based on the difference between the first output voltage and the second output voltage; the third voltage is used to represent the voltage margin of the low-dropout regulator at the current moment; the transconductance amplifier is used to receive the first reference voltage and the third voltage, and obtain a first current based on the first reference voltage and the third voltage; the feedback voltage generation circuit is used to generate a corresponding feedback voltage based on the first current; this is equivalent to real-time sampling of the voltage margin of the low-dropout regulator at the current moment, converting the voltage margin into a first current, and then raising or lowering the feedback voltage according to the magnitude of the first current to adjust the magnitude of the feedback voltage. Finally, the first DC-DC converter adjusts the first output voltage output at the next moment based on the adjusted feedback voltage and the second reference voltage. This achieves dynamic adjustment of the voltage margin of the low-dropout regulator. In this way, even when the input voltage and output voltage of the low-dropout regulator change, the first output voltage of the input of the low-dropout regulator can be dynamically feedback-adjusted, so that the voltage margin of the low-dropout regulator is always stable at a reasonable set value, thereby ensuring the normal operation of the components in the circuit without causing waste of electric energy, thereby improving the energy conversion efficiency of the power management module.

[0063] Among them, the feedback voltage generation includes a current extraction circuit and a voltage divider circuit, the input end of the voltage divider circuit is connected to the output end of the first DC-DC converter, and the output end of the voltage divider circuit is grounded; the current extraction circuit is connected to the first voltage dividing node on the voltage divider circuit, and the first DC-DC converter is connected to the first voltage dividing node or the second voltage dividing node on the voltage divider circuit to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node; wherein, the voltage on the second voltage dividing node is less than the voltage on the first voltage dividing node; the current extraction circuit includes an input end, an output end and a driving end, the input end of the current extraction circuit is connected to the first voltage dividing node on the voltage divider circuit, the output end of the current extraction circuit is grounded, and the driving end of the current extraction circuit is connected to the output end of the transconductance amplifier to receive the first current; the current extraction circuit is used to pull up or down the feedback voltage on the first voltage dividing node or the second voltage dividing node when triggered by the first current.

[0064] Figure 4 This is one of the schematic diagrams of the voltage margin adjustment circuit structure provided in the embodiment of the present application. The voltage margin adjustment circuit is applied to the power management circuit provided in the above embodiments. The power management circuit provided in this embodiment can refer to the above Figure 1 or Figure 3 The power management circuit shown in the figure will not be described here. Figure 4As shown, the voltage margin adjustment circuit provided by this embodiment includes: a voltage margin acquisition circuit 41 , a transconductance amplifier 42 , and a feedback voltage generation circuit 400 .

[0065] Among them, the output end of the voltage margin acquisition circuit 41 is connected to the negative input end of the transconductance amplifier 42, the output end of the transconductance amplifier 42 is connected to the current extraction circuit 43, the input end of the voltage divider circuit 44 is connected to the output end of the first DC-DC converter 11, and the output end of the voltage divider circuit 44 is grounded; the current extraction circuit 43 is connected to the first voltage dividing node on the voltage divider circuit 44, and the first DC-DC converter 11 is connected to the first voltage dividing node or the second voltage dividing node on the voltage divider circuit 44 to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node; wherein, the voltage on the second voltage dividing node is less than the voltage on the first voltage dividing node.

[0066] The voltage headroom acquisition circuit 41 of this embodiment is configured to sample the first output voltage Vo_dcdc and the second output voltage Vo_1do, and obtain a third voltage V3 based on the difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do. The third voltage V3 is used to represent the current voltage headroom of the first low-dropout regulator 12. In other words, the voltage difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do can be used as the current voltage headroom of the first low-dropout regulator 12. Since the third voltage V3 is obtained based on the difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do, and the ratio of the sampling resistors in the voltage headroom acquisition circuit 41 must also be considered, and the ratio of the sampling resistors is proportional to the third voltage V3, the third voltage V3 obtained based on the first output voltage Vo_dcdc and the second output voltage Vo_1do can represent the current voltage headroom of the first low-dropout regulator 12.

[0067] The transconductance amplifier 42 is configured to receive a first reference voltage Vref1 and a third voltage V3, and to generate a first current I1 based on the first reference voltage Vref1 and the third voltage V3. An operational transconductance amplifier (OTA) is an amplifier that converts an input differential voltage into an output current. It is understood that the transconductance amplifier 42 generates the first current I1 based on the difference between the first reference voltage Vref1 and the third voltage V3. The greater the difference between the first reference voltage Vref1 and the third voltage V3, the greater the value of the first current I1. In this embodiment, the first reference voltage Vref1 is set to represent the ideal value of the voltage margin. The greater the voltage margin of the first low-dropout regulator 12 at the current moment, the greater the third voltage V3 output by the voltage margin acquisition circuit 41. The greater the third voltage V3, the smaller the difference between the third voltage V3 and the first reference voltage Vref1, and the smaller the first current I1 output by the transconductance amplifier 42. Conversely, the smaller the voltage margin of the first low-dropout regulator 12 at the current moment, the smaller the third voltage V3 output by the voltage margin acquisition circuit 41. The smaller the third voltage V3, the greater the difference between the third voltage V3 and the first reference voltage Vref1, and the larger the first current I1 output by the transconductance amplifier 42. Therefore, in this embodiment, the current value of the first current I1 is negatively correlated with the voltage value of the third voltage V3.

[0068] The feedback voltage generation 400 includes a current extraction circuit 43 and a voltage divider circuit 44. The input end of the voltage divider circuit 44 is connected to the output end of the first DC-DC converter 11, and the output end of the voltage divider circuit 44 is grounded GND. The current extraction circuit 43 is connected to a first voltage dividing node on the voltage divider circuit 44, and the first DC-DC converter 11 is connected to the first voltage dividing node or the second voltage dividing node on the voltage divider circuit 11 to sample the feedback voltage VFB on the first voltage dividing node or the second voltage dividing node. The voltage on the second voltage dividing node is less than the voltage on the first voltage dividing node. The current extraction circuit 43 includes an input end, an output end, and a driving end. The input end of the current extraction circuit is connected to the first voltage dividing node on the voltage divider circuit, the output end of the current extraction circuit 43 is grounded, and the driving end of the current extraction circuit 43 is connected to the output end of the transconductance amplifier 42 to receive the first current. The current extraction circuit 43 is used to pull up or down the feedback voltage VFB on the first voltage dividing node or the second voltage dividing node when triggered by the first current.

[0069] The current extraction circuit 43 is configured to increase or decrease the feedback voltage at the first voltage-dividing node or the second voltage-dividing node when triggered by the first current I1. Specifically, if the current value of the first current I1 increases compared to the previous moment, the feedback voltage at the first voltage-dividing node or the second voltage-dividing node is decreased; if the current value of the first current I1 increases compared to the previous moment, the feedback voltage at the first voltage-dividing node or the second voltage-dividing node is increased. Therefore, the current extraction circuit 43 can adjust the magnitude of the feedback voltage based on the first current I1.

[0070] The first DC-DC converter 11 is further configured to receive a second reference voltage Vref2 and adjust the first output voltage Vo_dcdc to be output at a next moment based on the feedback voltage and the second reference voltage Vref2. Specifically, the first output voltage feedback adjustment module in the first DC-DC converter 11 can feedback-adjust the first output voltage Vo_dcdc to be output at a next moment based on the feedback voltage and the second reference voltage Vref2 received at the current moment, so that the first output voltage Vo_dcdc input to the first low-dropout regulator 12 is stabilized at a target value, thereby stabilizing the voltage margin formed by the input voltage and output voltage of the first low-dropout regulator 12 at a set value, i.e., stabilizing the voltage margin of the first low-dropout regulator 12 at an ideal value.

[0071] It can be seen that the voltage margin adjustment circuit provided according to this embodiment can dynamically adjust the voltage margin of the first low-voltage difference regulator 12. In this way, even when the input voltage and output voltage of the first low-voltage difference regulator 12 change, the first output voltage output by the first low-voltage difference regulator 12 can be dynamically feedback-adjusted, so that the voltage margin of the low-voltage difference regulator is always stable at a reasonable set value, thereby ensuring the normal operation of the components in the circuit without causing waste of electric energy, thereby improving the energy conversion efficiency of the power management module.

[0072] Please continue to see Figure 4 As shown, the voltage margin acquisition circuit 41 provided in this embodiment includes a first sampling end and a second sampling end. The first sampling end is connected to the output end of the first DC-DC converter 11 to sample the first output voltage Vo_dcdc output by the first DC-DC converter 11, and the second sampling end is connected to the output end of the first low-dropout regulator 12 to sample the second output voltage Vo_1do output by the first low-dropout regulator 12.

[0073] The output of the voltage margin acquisition circuit 41 is connected to the negative input of the transconductance amplifier 42 to output a third voltage V3 to the transconductance amplifier 42. The positive input of the transconductance amplifier V3 is used to receive the first reference voltage Vref1. The current extraction circuit 43 of this embodiment includes an input, an output, and a driving end. The input of the voltage regulation circuit 43 is connected to the first voltage dividing node on the voltage divider circuit 44. The output of the current extraction circuit 43 is grounded. The driving end of the current extraction circuit 43 is connected to the output of the transconductance amplifier 42 to receive the first current I1. The first current I1 is used to drive the current extraction circuit 43 to operate and adjust the voltage on the first voltage dividing node or the second voltage dividing node on the voltage divider circuit 44.

[0074] Among them, the input end of the voltage divider circuit 44 is connected to the voltage output of the first DC-DC converter 11, that is, the voltage at the input end of the voltage divider circuit 44 is the first output voltage Vo_dcdc. The voltage divider circuit 44 can include multiple voltage divider resistors, and the high-voltage end of each voltage divider resistor forms a voltage divider node. The voltage divider resistors form multiple voltage divider nodes, and the voltage at each voltage divider node is different. It can be understood that the multiple voltage divider resistors in the voltage divider circuit 44 have different voltage dividers on their high-voltage ends depending on their resistance values. For a certain voltage divider node, different current values flowing through a certain voltage divider resistor will result in different voltage values on the high-voltage end of the voltage divider resistor. Therefore, the change in the voltage at a certain voltage divider node on the sampling voltage divider circuit 44 can represent the change in the first output voltage Vo_dcdc at the input end of the voltage divider circuit 44. Therefore, when the current extraction circuit 43 is working, it can extract the current value of the sampling voltage divider circuit 44, thereby raising or lowering the feedback voltage on a certain voltage divider node.

[0075] The positive input terminal of the first DC-DC converter 11 is used to receive the second reference voltage Vref2. The negative input terminal of the first DC-DC converter 11 is connected to the first voltage-dividing node on the voltage-dividing circuit 44 to sample the feedback voltage VFB of the first voltage-dividing node. The feedback voltage VFB can represent the change of the first output voltage Vo_dcdc. The second reference voltage Vref2 can represent the set value of the output voltage of the first DC-DC converter 11. The first output voltage feedback regulation module can feedback-regulate the first output voltage Vo_dcdc to be output by the first DC-DC converter 11 at the next moment based on the feedback voltage VFB received at the current moment and the second reference voltage Vref2, so that the first output voltage Vo_dcdc input to the first low-dropout regulator 12 is stabilized at a target value, thereby stabilizing the voltage margin composed of the input voltage and output voltage of the first low-dropout regulator 12 at the set value, that is, stabilizing the voltage margin of the first low-dropout regulator 12 at an ideal value.

[0076] Please continue to see Figure 4 As shown, the voltage margin acquisition circuit 41 provided in this embodiment includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2, and a third transistor Q3; the first end of the first resistor R1 is connected to the output end of the first low-dropout regulator 12, the second end of the first resistor R1 is connected to the first electrode of the first transistor Q1, and the second electrode and control electrode of the first transistor Q1 are both grounded; the first end of the second resistor R2 is connected to the output end of the first DC-DC converter 11, the second end of the second resistor R2 is respectively connected to the first electrode of the second transistor Q2 and the second electrode of the third transistor Q3, the second electrode of the second transistor Q2 and the control electrode of the third transistor Q3 are both grounded, and the first electrode of the third transistor Q3 is grounded through the third resistor R3; the first electrode of the third transistor Q3 is the output end of the voltage margin acquisition circuit. In this embodiment, the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 are all the same.

[0077] In this embodiment, the first transistor Q1 and the second transistor Q2 in the voltage margin acquisition circuit 41 can be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the first transistor Q1 and the second transistor Q2 are PMOS transistors, their first electrode is the source, their second electrode is the drain, and their control electrode is the gate. In other embodiments, the first transistor Q1 and the second transistor Q2 can also be NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0078] The third transistor Q3 in the voltage margin acquisition circuit 41 provided in this embodiment can be an NMOS (N-Metal-Oxide-Semiconductor) transistor. When the third transistor Q3 is an NMOS transistor, its first electrode is a source electrode, its second electrode is a drain electrode, and its control electrode is a gate electrode. In other embodiments, the third transistor Q3 can also be a PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0079] It can be understood that in another embodiment, when the first transistor Q1 and the second transistor Q2 in the voltage margin acquisition circuit 41 adopt NMOS tubes, and the third transistor Q3 adopts a PMOS tube, the relevant circuit structure is deformed as a whole as needed to achieve the same technical purpose as the voltage margin acquisition circuit 41 in this embodiment, which will not be repeated here.

[0080] It can be understood that, according to the voltage headroom acquisition circuit 41 provided in this embodiment, the first resistor R1, the first transistor Q1, the second resistor R2, and the second transistor Q2 constitute a current mirror circuit. Thus, the currents in the branch containing the first resistor R1 and the first transistor Q1 and the branch containing the second resistor R2 and the second transistor Q2 are the same. In other words, the branch containing the first resistor R1 and the first transistor Q1 can be considered to be connected to the first current source IA1, and the branch containing the second resistor R2 and the second transistor Q2 can be considered to be connected to the second current source IA2. The first current source IA1 and the second current source IA2 output the same current.

[0081] It can be understood that, in this embodiment, the branch where the second transistor Q2 and the third transistor Q3 are located forms a voltage differential circuit, and the third voltage V3 output by the source of the third transistor Q3 can be expressed as:

[0082]

[0083] In the above formula (4), ΔV represents the difference between the first output voltage Vo_dcdc and the second output voltage Vo_1do, that is, ΔV represents the voltage margin of the first low-dropout regulator 12 at the current moment, ΔV=Vo_dcdc-Vo_1do; R3 represents the resistance value of the third resistor R3, and R2 represents the resistance value of the second resistor R2.

[0084] According to the above formula (4), since the resistance values of the second resistor R2 and the third resistor R3 are generally constant, the third voltage V3 in this embodiment is proportional to the voltage margin of the first low-dropout voltage regulator 12. That is, as the voltage margin of the first low-dropout voltage regulator 12 at the current moment increases, the voltage value of the third voltage V3 output by the voltage margin acquisition circuit 41 increases, and as the voltage margin of the first low-dropout voltage regulator 12 at the current moment decreases, the voltage value of the third voltage V3 output by the voltage margin acquisition circuit 41 decreases. The current moment in this embodiment refers to the previous moment, which is the moment of the last feedback adjustment of the first DC-DC converter 11, and the next moment is the moment of the next feedback adjustment of the first DC-DC converter 11.

[0085] Please continue to see Figure 4 As shown, the current extraction circuit 43 provided in this embodiment includes a first capacitor C1, a fourth transistor Q4 and a fourth resistor R4; the first end of the first capacitor C1 and the control electrode of the fourth transistor Q4 are both connected to the output end of the transconductance amplifier 42, the second electrode of the fourth transistor Q4 is connected to the first voltage dividing node on the voltage dividing circuit 44, the first electrode of the fourth transistor Q4 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

[0086] The transconductance amplifier 42 receives the first reference voltage Vref1 and the third voltage V3, and integrates the difference between the first reference voltage Vref1 and the third voltage V3 to obtain the first current I1. The greater the difference between the first reference voltage Vref1 and the third voltage V3, the greater the current value of the first current I1. In this embodiment, the first reference voltage Vref1 is set to represent the ideal value of the voltage margin. The greater the voltage margin of the first low-dropout regulator 12 at the current moment, the greater the third voltage V3 output by the voltage margin acquisition circuit 41. The greater the third voltage V3, the smaller the difference between the third voltage V3 and the first reference voltage Vref1, and the smaller the first current I1 output by the transconductance amplifier 42. Conversely, the smaller the voltage margin of the first low-dropout regulator 12 at the current moment, the smaller the third voltage V3 output by the voltage margin acquisition circuit 41. The smaller the third voltage V3, the greater the difference between the third voltage V3 and the first reference voltage Vref1, and the larger the first current I1 output by the transconductance amplifier 42. Therefore, in this embodiment, the current value of the first current I1 and the voltage value of the third voltage V3 are negatively correlated.

[0087] The first current I1 output by the transconductance amplifier 42 charges the first capacitor C1, thereby causing a fourth voltage V4 to be present at the first end of the first capacitor C1. The fourth voltage V4 triggers the fourth transistor Q4 to turn on, thereby causing a third current I3 to flow through the branch path containing the fourth transistor Q4 and the fourth resistor R4. Furthermore, the greater the first current I1 output by the transconductance amplifier 42, the greater the third current I3 in the branch path containing the fourth transistor Q4 and the fourth resistor R4. Conversely, the smaller the first current I1 output by the transconductance amplifier 42, the smaller the third current I3 in the branch path containing the fourth transistor Q4 and the fourth resistor R4.

[0088] The fourth transistor Q4 in the current extraction circuit 43 provided in this embodiment can be an NMOS (N-Metal-Oxide-Semiconductor) transistor. When the fourth transistor Q4 is an NMOS transistor, its first electrode is a source electrode, its second electrode is a drain electrode, and its control electrode is a gate electrode. In other embodiments, the fourth transistor Q4 can also be a PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0089] It is understood that when the branch containing the fourth transistor Q4 and the fourth resistor R4 forms a current path, the third current I3 in the branch containing the fourth transistor Q4 and the fourth resistor R4 will draw current from the sampling voltage divider circuit 44, thereby increasing or decreasing the feedback voltage VFB at a certain voltage divider node. For example, when the third current I3 in the branch containing the fourth transistor Q4 and the fourth resistor R4 increases, more current will be drawn from the voltage divider circuit 44, which is equivalent to the current in the voltage divider circuit 44 being shunted by the current extraction circuit 43, thereby adjusting the current in the voltage divider circuit 44 and further affecting the voltage value on a certain voltage divider resistor in the voltage divider circuit 44.

[0090] In summary, the current extraction circuit 43 can, when triggered by the first current I1, increase or decrease the feedback voltage VFB at a certain voltage-dividing node. Specifically, if the current value of the first current I1 increases compared to the previous moment, the feedback voltage VFB at the first or second voltage-dividing node will be decreased; if the current value of the first current I1 increases compared to the previous moment, the feedback voltage VFB at the first or second voltage-dividing node will be increased. Therefore, the current extraction circuit 43 can adjust the magnitude of the feedback voltage VFB based on the first current I1.

[0091] Please continue to see Figure 4 As shown, the voltage divider circuit 44 provided in this embodiment includes a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, and the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are connected in series in sequence to achieve voltage division. The first end of the fifth resistor R5 is the input end of the voltage divider circuit 44, and the first end of the fifth resistor R5 is connected to the output end of the first DC-DC converter 11 to receive the first output voltage Vo_dcdc output by the first DC-DC converter 11. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is grounded. The drain of the fourth transistor Q4 is connected to the second end of the fifth resistor R5.

[0092] It is understandable that the first output voltage Vo_dcdc output by the first DC-DC converter 11 is constantly changing due to feedback regulation. At the current moment, the voltage at the first end of the fifth resistor R5 on the voltage divider circuit 44 is the first output voltage Vo_dcdc. The first output voltage Vo_dcdc is then divided by the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7. In this embodiment, the first end of the sixth resistor R6 is defined as a first voltage dividing node, and the first end of the seventh resistor R7 is defined as a second voltage dividing node. That is, the input end of the current extraction circuit 43 is connected to the first voltage dividing node on the voltage divider circuit 44, and the inverting input end of the first DC-DC converter 11 is connected to the second voltage dividing node on the voltage divider circuit 44. The voltage value of the second voltage dividing node is less than the voltage value at the first voltage dividing node.

[0093] It can be understood that, the greater the third current I3 in the branch where the fourth transistor Q4 and the fourth resistor R4 are located, the greater the current value drawn from the sampling voltage divider circuit 44, the smaller the current value in the branch where the sixth resistor R6 and the seventh resistor R7 are located, and the smaller the divided voltage on the seventh resistor R7, that is, the smaller the voltage value of the feedback voltage VFB collected at the second voltage divider node, and the first output voltage Vo_dcdc output by the first DC-DC converter 11 can be feedback-regulated according to the feedback voltage VFB and the second reference voltage Vref2.

[0094] Please continue to see Figure 4 As shown, based on the above analysis, it can be seen that the voltage headroom adjustment circuit provided in this embodiment includes two voltage adjustment loops. One is to feedback-adjust the magnitude of the feedback voltage VFB of the first DC-DC converter 11 based on the voltage headroom of the first low-dropout regulator 12. The other is to feedback-adjust the first output voltage Vo_dcdc output by the first DC-DC converter 11 based on the feedback voltage VFB and the second reference voltage Vref2, so that the voltage headroom of the first low-dropout regulator 12 is stabilized at an ideal value. In this way, a closed loop of feedback adjustment is formed. When the output voltage and input voltage of the first low-dropout regulator 12 change, the voltage headroom of the first low-dropout regulator 12 can always be stabilized at a reasonable set value. This ensures the normal operation of the components in the circuit without wasting energy, thereby improving the energy conversion efficiency of the power management module.

[0095] Figure 5 For the second schematic diagram of the voltage margin adjustment circuit structure provided in the embodiment of the present application, please refer to Figure 5 As shown, in one embodiment, the voltage margin adjustment circuit further includes a first current limiting circuit 51, which is electrically connected to the current extraction circuit 43; the first current limiting circuit 51 is used to limit the third current I3 on the current extraction circuit 43 to be less than or equal to the first current threshold.

[0096] It is understood that during the initial power-up phase of the power management circuit, when the difference between the first output voltage Vo_dcdc output by the first DC-DC converter 11 and the second output voltage Vo_1do output by the first low-dropout regulator 12 is 0V, i.e., the voltage margin at the current moment is far less than the set headroom voltage, the third voltage V3 is far lower than the first reference voltage Vref1, causing the fourth voltage V4 at the output of the transconductance amplifier 42 to be pulled high, resulting in a large third current I3 in the current extraction circuit 43. This may cause the set voltage value of the first DC-DC converter 11 to be too high. The first current limiting circuit 51 can limit the maximum current of the third current I3 to ensure that the set voltage of the first DC-DC converter 11 remains within the normal range.

[0097] Please continue to see Figure 5 As shown, in one embodiment, the voltage margin adjustment circuit has a second current limiting circuit 52, and the second current limiting circuit 52 is also electrically connected to the current extraction circuit 43; the second current limiting circuit 52 is used to limit the third current on the current extraction circuit 43 to be greater than or equal to the second current threshold.

[0098] It can be understood that when the first output voltage Vo_dcdc output by the first DC-DC converter 11 exceeds the headroom voltage, the third voltage V3 is higher than the first reference voltage Vref1, so that the fourth voltage V4 at the output end of the transconductance amplifier 42 is pulled down, and no current is injected into the voltage divider circuit 44 from the current extraction circuit 43, resulting in the first output voltage Vo_dcdc output by the first DC-DC converter 11 ultimately only reaching the set output of the LDO, which is one headroom voltage away from the expected target. Therefore, a second current limiting circuit 52 is required to limit the minimum current of the third current I3, so that the set output voltage of the first DC-DC converter 11 is raised by a headroom voltage.

[0099] Please continue to see Figure 5 As shown, the first current limiting circuit 51 provided in this embodiment includes a fifth transistor Q5, a sixth transistor Q6, an error amplifier EA and a seventh resistor R7; the control electrode and the second electrode of the fifth transistor Q5 are both used to receive the first bias current Istart, and the first electrode of the fifth transistor Q5 is grounded through the seventh resistor R7; the positive input terminal of the error amplifier EA is connected to the second electrode of the fifth transistor Q5, and the reverse input terminal of the error amplifier EA is connected to the output terminal of the transconductance amplifier 42; the output terminal of the error amplifier EA is connected to the control electrode of the sixth transistor Q6, the first electrode of the sixth transistor Q6 is used to receive the power supply voltage VCC, and the second electrode of the sixth transistor Q6 is also connected to the output terminal of the transconductance amplifier 42.

[0100] The fifth transistor Q5 in the first current limiting circuit 51 provided in this embodiment can be an NMOS (N-Metal-Oxide-Semiconductor) tube. When the fifth transistor Q5 is an NMOS tube, its first electrode is a source electrode, its second electrode is a drain electrode, and its control electrode is a gate electrode. The sixth transistor Q6 in the first current limiting circuit 51 provided in this embodiment can be a PMOS (P-Metal-Oxide-Semiconductor) tube. When the sixth transistor Q6 is a PMOS tube, its first electrode is a source electrode, its second electrode is a drain electrode, and its control electrode is a gate electrode.

[0101] It is understandable that the fifth transistor Q5 , the sixth transistor Q6 , the error amplifier EA and the seventh resistor R7 form a current mirror circuit, thereby limiting the third current I3 in the current extraction circuit 43 to be less than or equal to the first bias current Istart.

[0102] Please continue to see Figure 5 As shown, the second current limiting circuit 52 provided in this embodiment specifically includes a seventh transistor Q7 and an eighth transistor Q8; the control electrode of the seventh transistor Q7, the second electrode of the seventh transistor Q7, and the control electrode of the eighth transistor Q8 are all used to receive the second bias current Ilimit, and the first electrode of the seventh transistor Q7 is grounded; the second electrode of the eighth transistor Q8 is connected to the second end of the fourth resistor R4, the first end of the fourth resistor R4 is connected to the first electrode of the fourth transistor Q4, and the first electrode of the eighth transistor Q8 is grounded.

[0103] Among them, the seventh transistor Q7 and the eighth transistor Q8 in the second current limiting circuit 52 provided in this embodiment can adopt NMOS (N-Metal-Oxide-Semiconductor) tubes. When the seventh transistor Q7 and the eighth transistor Q8 adopt NMOS tubes, their first pole is the source, their second pole is the drain, and their control pole is the gate.

[0104] It can be understood that the current mirror circuit composed of the seventh transistor Q7 and the eighth transistor Q8 can clamp the third current I3 on the current extraction circuit 43 to be no less than the second bias current Ilimit. When the first low-dropout regulator 12 is powered on, the second current limiting circuit 52 can be turned off.

[0105] Please combine Figure 4 and Figure 5 As shown, an analysis of the error of the headroom voltage adjusted by the voltage margin adjustment circuit provided in this embodiment shows that the circuit as a whole satisfies the following relationship:

[0106]

[0107] Since ΔV represents the voltage margin of the first low-dropout regulator 12 at the current moment, when the resistance values of the second resistor R2 and the third resistor R3 are the same, that is, when R2=R3, the voltage margin of the first low-dropout regulator 12 can be equal to the set value; in other words, assuming that the ideal setting of the voltage margin of the first low-dropout regulator 12 is V hr , then the first reference voltage Vref1 is set to V hr *R3 / R2, which can make the voltage margin of the first low dropout regulator 12 equal to the set value.

[0108] It can be seen that according to the voltage margin adjustment circuit provided in this embodiment, the accuracy of the headroom voltage can be made independent of the output accuracy of the first low-dropout regulator 12 and the first DC-DC converter 11. The headroom voltage error is currently mainly caused by the mismatch of the circuit itself. Assuming that the sampling error of the voltage margin acquisition circuit 41 is Vos_s and the integration error of the transconductance amplifier 42 is Vos_gm, the error ratio of the two to the voltage margin can be expressed as:

[0109]

[0110] Assuming that the error introduced by the first reference voltage Vref1 and the second reference voltage Vref2 in this embodiment is Vos_vr, the ratio of the error to the voltage margin error can be expressed as:

[0111]

[0112] Assuming that the error caused by the resistance mismatch between the second resistor R2 and the third resistor R3 due to the production process in this embodiment is Δh, the proportion of the error to the voltage margin error can be expressed as:

[0113]

[0114] From the above analysis, it can be seen that in this embodiment, setting the second resistor R2 and the third resistor R3 to have the same resistance value can make the above errors smaller than the errors introduced in the related art, thereby making the adjustment of the voltage margin more accurate.

[0115] An embodiment of the present application also provides a power management circuit, which includes the above-mentioned first DC-DC converter 11 and the first low-voltage dropout regulator 12. The first DC-DC converter 11 and the first low-voltage dropout regulator 12, the first DC-DC converter 11 is used to receive an input voltage VIN and perform voltage conversion on the input voltage VIN to obtain a first output voltage, and the first low-voltage dropout regulator 12 is used to process the first output voltage to obtain a second output voltage; in addition, the power management circuit also includes a voltage margin adjustment circuit as provided in the above-mentioned embodiments.

[0116] The working principle and technical effects of the power management circuit provided in this embodiment can be referred to the above embodiments and will not be repeated here.

[0117] An embodiment of the present application further provides a chip, which includes the voltage margin adjustment circuit provided in the above embodiments.

[0118] An embodiment of the present application further provides an electronic device, which includes the voltage margin adjustment circuit provided by the above embodiments; or the electronic device includes the chip provided by the above embodiments.

[0119] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A voltage margin adjustment circuit, applied to a power management circuit, comprising a first DC-DC converter and a low-dropout voltage regulator, wherein the first DC-DC converter and the low-dropout voltage regulator are electrically connected, the first DC-DC converter being configured to receive an input voltage and perform voltage conversion on the input voltage to obtain a first output voltage, and the low-dropout voltage regulator being configured to process the first output voltage to obtain a second output voltage; characterized in that: The voltage margin adjustment circuit includes: a voltage margin acquisition circuit, a transconductance amplifier and a feedback voltage generation circuit; The voltage margin acquisition circuit is configured to sample the first output voltage and the second output voltage, and obtain a third voltage according to a difference between the first output voltage and the second output voltage; the third voltage is used to represent the voltage margin of the low dropout regulator at a current moment; The transconductance amplifier is configured to receive a first reference voltage and a third voltage, and obtain a first current according to the first reference voltage and the third voltage; The feedback voltage generating circuit is configured to generate a corresponding feedback voltage according to the first current; The first DC-DC converter is further configured to receive a second reference voltage and adjust the first output voltage to be output at a next moment according to the feedback voltage and the second reference voltage.

2. The voltage margin adjustment circuit according to claim 1, wherein: The voltage margin acquisition circuit includes a first sampling terminal and a second sampling terminal, the first sampling terminal is connected to the output terminal of the first DC-DC converter to sample the first output voltage, and the second sampling terminal is connected to the output terminal of the low-dropout regulator to sample the second output voltage; The output end of the voltage margin acquisition circuit is connected to the negative input end of the transconductance amplifier to output the third voltage to the transconductance amplifier, and the positive input end of the transconductance amplifier is used to receive the first reference voltage; The feedback voltage generation includes a current extraction circuit and a voltage divider circuit, wherein the input end of the voltage divider circuit is connected to the output end of the first DC-DC converter, and the output end of the voltage divider circuit is grounded; the current extraction circuit is connected to a first voltage dividing node on the voltage divider circuit, and the first DC-DC converter is connected to the first voltage dividing node or the second voltage dividing node on the voltage divider circuit to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node; wherein the voltage on the second voltage dividing node is less than the voltage on the first voltage dividing node; The current extraction circuit includes an input end, an output end, and a driving end, wherein the input end of the current extraction circuit is connected to the first voltage dividing node on the voltage dividing circuit, the output end of the current extraction circuit is grounded, and the driving end of the current extraction circuit is connected to the output end of the transconductance amplifier to receive the first current; The current extraction circuit is configured to pull up or pull down the feedback voltage on the first voltage dividing node or the second voltage dividing node when triggered by the first current; The positive input terminal of the first DC-DC converter is used to receive the second reference voltage, and the negative input terminal of the first DC-DC converter is connected to the first voltage dividing node or the second voltage dividing node on the voltage dividing circuit to sample the feedback voltage on the first voltage dividing node or the second voltage dividing node.

3. The voltage margin adjustment circuit according to claim 2, wherein: The voltage margin adjustment circuit further includes a first current limiting circuit, wherein the first current limiting circuit is connected to the current extraction circuit; The first current limiting circuit is used to limit the third current on the current extraction circuit to be less than or equal to a first current threshold.

4. The voltage margin adjustment circuit according to claim 3, wherein: The voltage margin adjustment circuit further includes a second current limiting circuit, wherein the second current limiting circuit is connected to the current extraction circuit; The second current limiting circuit is used to limit the third current on the current extraction circuit to be greater than or equal to a second current threshold.

5. The voltage margin adjustment circuit according to claim 2, wherein: The voltage margin acquisition circuit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor and a third transistor; A first end of the first resistor is connected to the output end of the low-dropout regulator, a second end of the first resistor is connected to the first electrode of the first transistor, and a second electrode and a control electrode of the first transistor are both grounded; A first end of the second resistor is connected to the output end of the first DC-DC converter, a second end of the second resistor is connected to the first electrode of the second transistor and the second electrode of the third transistor, respectively, the second electrode of the second transistor and the control electrode of the third transistor are both grounded, and the first electrode of the third transistor is grounded via the third resistor; the first electrode of the third transistor is the output end of the voltage margin acquisition circuit; The resistance values of the first resistor, the second resistor and the third resistor are all the same.

6. The voltage margin adjustment circuit according to claim 4, characterized in that: The current extraction circuit includes a first capacitor, a fourth transistor and a fourth resistor; The first end of the first capacitor and the control electrode of the fourth transistor are both connected to the output end of the transconductance amplifier, the second electrode of the fourth transistor is connected to the first voltage dividing node on the voltage dividing circuit, and the first electrode of the fourth transistor is grounded through the fourth resistor.

7. The voltage margin adjustment circuit according to claim 6, wherein: The voltage divider circuit includes a fifth resistor, a sixth resistor and a seventh resistor; A first end of the fifth resistor is connected to the output end of the first DC-DC converter, a second end of the fifth resistor is connected to the first end of the sixth resistor, a second end of the sixth resistor is connected to the first end of the seventh resistor, and a second end of the seventh resistor is grounded.

8. The voltage margin adjustment circuit according to claim 3, wherein: The first current limiting circuit includes a fifth transistor, a sixth transistor, an error amplifier and a seventh resistor; The control electrode and the second electrode of the fifth transistor are both used to receive a first bias current, and the first electrode of the fifth transistor is grounded through the seventh resistor; the positive input terminal of the error amplifier is connected to the second electrode of the fifth transistor, and the reverse input terminal of the error amplifier is connected to the output terminal of the transconductance amplifier; the output terminal of the error amplifier is connected to the control electrode of the sixth transistor, the first electrode of the sixth transistor is used to receive a power supply voltage, and the second electrode of the sixth transistor is connected to the output terminal of the transconductance amplifier.

9. The voltage margin adjustment circuit according to claim 6, wherein: The second current limiting circuit includes a seventh transistor and an eighth transistor; The control electrode of the seventh transistor, the second electrode of the seventh transistor, and the control electrode of the eighth transistor are all used to receive a second bias current, and the first electrode of the seventh transistor is grounded; the second electrode of the eighth transistor is connected to the second end of the fourth resistor, the first end of the fourth resistor is connected to the first electrode of the fourth transistor, and the first electrode of the eighth transistor is grounded.

10. A power management circuit, characterized in that: The power management circuit includes a first DC-DC converter and a low-voltage dropout regulator, the first DC-DC converter and the low-voltage dropout regulator are electrically connected, the first DC-DC converter is used to receive an input voltage and perform voltage conversion on the input voltage to obtain a first output voltage, and the low-voltage dropout regulator is used to process the first output voltage to obtain a second output voltage; The power management circuit further includes a voltage margin adjustment circuit as described in any one of claims 1-9.

11. A chip, characterized in that: The chip includes the voltage margin adjustment circuit according to any one of claims 1 to 9.

12. An electronic device, characterized in that: The electronic device includes the voltage margin adjustment circuit according to any one of claims 1 to 9; or the electronic device includes the chip according to claim 11.

Images