CDR circuit capable of rapidly tracking spread spectrum clock

Abstract

The invention relates to the technical field of electronic oscillators, in particular to a CDR circuit capable of rapidly tracking a spread spectrum clock. Comprising an analog front end (AFE) used for carrying out equalization amplification on a reference clock signal, a baseband phase detector (BBPD) used for detecting a phase difference between the reference clock signal and a local clock signal CLK2 and generating a phase error signal, and a charge pump CPPL with a phase leading function and used for receiving the phase error signal and generating a control voltage VCTRL, the local clock oscillator ICO is used for providing a stable local clock signal CLK2 and feeding back the stable local clock signal CLK2 to the baseband phase detector BBPD, and the phase error signal is coupled to the control voltage VCTRL or the tuning voltage VRING of the input end of the local clock oscillator ICO through a capacitor C. The BBPD outputs a lead-lag signal, alternating current is coupled to a potential on the VCTRL, pre-charging and pre-discharging are formed, and the response capability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic oscillators, and in particular to a CDR circuit for rapidly tracking a spread spectrum clock. Background Art

[0002] In modern high-speed serial communication systems, clock and data recovery (CDR) circuits are core modules for ensuring reliable data transmission. The CDR's primary function is to extract a clock signal from the received data stream and use it to sample and recover the data. However, with increasing communication speeds and increasingly stringent electromagnetic compatibility (EMC) requirements, spread spectrum clocking (SSC) technology has been widely used to reduce electromagnetic interference (EMI). SSC reduces EMI by modulating the clock signal at a low frequency to disperse the spectral energy. While SSC effectively reduces EMI, the frequency modulation it introduces places higher demands on the performance of the CDR circuit.

[0003] Traditional dual-ring CDR architecture such as Figure 1 As shown, the circuit comprises a frequency loop and a phase loop. The frequency loop includes a phase frequency detector (PFD), a frequency loop charge pump (CP_FL), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a divider (DIVIDER); the phase loop includes a phase detector (PD), a charge pump (CP), a low-pass filter (LPF), and a current-controlled oscillator (ICO). To improve phase path alignment (PPA), ensuring the correct phase relationship between the data sampling clock and the data signal, some modules, including the LPF and VCO, can be reused. However, traditional CDR circuits often suffer from issues such as limited SSC spread spectrum support and slow tracking speed when tracking SSC signals, making them difficult to meet the requirements of high-speed communication systems. Summary of the Invention

[0004] In order to solve the problem that the existing CDR is slow in tracking SSC signals and cannot meet the requirements of high-speed communication, the present invention provides a CDR circuit that can quickly track the spread spectrum clock. The baseband phase detector BBPD outputs the lead and lag signals, which are AC-coupled to the control voltage VCTRL to form a pre-charge and discharge, thereby improving the response capability.

[0005] The present invention provides a CDR circuit for fast tracking of a spread-spectrum clock. The circuit comprises, in sequence, an analog front-end (AFE) for performing balanced amplification on a reference clock signal; a baseband phase detector (BBPD) for detecting the phase difference between the reference clock signal and a local clock signal (CLK2) and generating a phase error signal; a phase-leading charge pump (CP_PL) for receiving the phase error signal and generating a control voltage (VCTRL); and a local clock oscillator (ICO) for providing a stable local clock signal (CLK2) and feeding it back to the baseband phase detector (BBPD). The phase error signal is coupled to the control voltage (VCTRL) or a tuning voltage (VRING) at the input of the local clock oscillator (ICO) via a capacitor (C). The capacitor couples the lead and lag signals to a voltage, forming a pre-charge / discharge circuit, thereby improving the tracking speed, stability, and energy efficiency of the CDR circuit for SSC signals.

[0006] Furthermore, the analog front end (AFE) has an input terminal DATA_IN for receiving a data stream (Link Training) or a reference clock signal, and an output terminal DIN for outputting an amplified and filtered reference clock signal to a baseband phase detector (BBPD). The AFE performs preliminary processing on the input signal to improve signal quality and meet subsequent processing requirements.

[0007] Furthermore, the phase error signal is divided into an early signal and a late signal. The early signal and the late signal are respectively coupled to the control voltage VCTRL or the tuning voltage VRING at the input of the local clock oscillator ICO through capacitors C. They are used to adjust the frequency of the voltage-controlled oscillator VCO.

[0008] Furthermore, the control voltage VCTRL is divided into a positive control voltage VCTRL_P and a negative control voltage VCTRL_I. Capacitor C includes capacitors C1, C2, C3, and C4. The early and late signals Early and Late are coupled to the positive control voltage VCTRL_P via capacitors C1 and C2, respectively. The early and late signals Late are coupled to the negative control voltage VCTRL_I via capacitors C3 and C4, respectively. This improves the fast response to low-frequency SSC.

[0009] Furthermore, a low-pass filter LPF is connected between the charge pump CP_PL and the control voltage VCTRL to filter out high-frequency noise and generate a smooth control voltage VCTRL. It is used to smooth the output of the charge pump CP_PL to generate the control voltage VCTRL.

[0010] Furthermore, the low-pass filter LPF includes resistors Rz1 and Rz2, and capacitors Cp1 and Cp2. Resistors Rz1 and Rz2 are connected in series between the positive control voltage VCTRL_P and the negative control voltage VCTRL_I, while capacitors Cp1 and Cp2 are connected in parallel between the control voltage VCTRL and ground. This is used to smooth and stabilize the control voltage.

[0011] Furthermore, a voltage-to-current converter V2I is connected between the control voltage VCTRL and the local clock oscillator ICO, for converting the control voltage VCTRL into a control current and driving the local clock oscillator ICO. It is used to convert a voltage signal into a current signal.

[0012] Furthermore, the tuning voltage VRING is the input voltage of the local clock oscillator ICO. Capacitor C includes capacitors C1 and C2. The early signal Early and the late signal Late are coupled to the tuning voltage VRING via capacitors C1 and C2, respectively. By bypassing the delay caused by the low-pass filter LPF, the VCO's response speed can be significantly improved.

[0013] Furthermore, the local clock oscillator ICO feeds the local clock signal CLK2 to the baseband phase detector BBPD, which is then connected to the phase interpolator PI. The phase transcoding of the phase interpolator is further adjusted by the adaptive control circuit, thereby achieving a fast tracking response to the SSC.

[0014] The beneficial effects of the present invention are: The present invention provides a CDR circuit for rapidly tracking a spread-spectrum clock. A baseband phase detector (BBPD) outputs lead and lag signals, which are AC-coupled to a control voltage to form a pre-charge / discharge circuit, thereby improving responsiveness. No additional power consumption is required for bandwidth compensation, thereby reducing the power consumption of the CDR circuit in rapidly responding to SSC operations. The circuit is applicable to a variety of SSC modulation modes (such as triangle wave modulation and sine wave modulation) and can be used for different communication protocols and standards. Some module circuits (such as the LPF and VCO) can be reused, and adjustment can be made so that CP_PL and CP_FL control the same charge pump CP through logic gates for switching use, thereby improving area advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts. Figure 1 This is a diagram of the traditional dual-ring CDR architecture; Figure 2 is a schematic diagram of embodiment 1; Figure 3 is a schematic diagram of embodiment 2; Figure 4 is a schematic diagram of embodiment 3; DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0017] like Figure 1 The figure shows a schematic diagram of a traditional dual-loop CDR, comprising a frequency loop and a phase loop. The frequency loop includes a phase frequency detector (PFD), a frequency loop charge pump (CP_FL), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a divider (DIVIDER). The phase loop includes a phase detector (PD), a charge pump (CP), a low-pass filter (LPF), a voltage-to-current converter (V2I), and a local clock oscillator (ICO). To improve phase path alignment (PPA) and ensure the correct phase relationship between the data sampling clock and the data signal for accurate data recovery, some modules, including the LPF and VCO, can be reused. The frequency loop is used for frequency tracking. After the VCO oscillation frequency is increased to near the desired data recovery clock frequency, the phase loop is switched to recover the clock signal from the data stream.

[0018] Example 1, as Figure 2 As shown in the figure, in order to improve the fast response capability, a CDR circuit that can quickly track the spread spectrum clock is designed, including an analog front end AFE, a baseband phase detector BBPD, a charge pump CP_PL with phase leading, and a local clock oscillator ICO.

[0019] The analog front end (AFE) has an input terminal DATA_IN and an output terminal DIN. The input terminal DATA_IN is used to receive a data stream Link Training or a reference clock signal. The output terminal DIN is used to output the amplified and filtered reference clock signal to the baseband phase detector (BBPD). The AFE is used to perform balanced amplification on the reference clock signal to meet the capture range of the CDR. The baseband phase detector (BBPD) is used to detect the phase difference between the reference clock signal and the local clock signal CLK2 and generate an advance signal Early and a lag signal Late. The charge pump CP_PL is used to receive the phase error signal and generate a positive control voltage VCTRL_P and a negative control voltage VCTRL_I. The local clock oscillator (ICO) is used to provide a stable local clock signal CLK2 and feed it back to the baseband phase detector (BBPD). The advance signal Early and the lag signal Late are coupled to the positive control voltage VCTRL_P via capacitors C1 and C2, respectively. The advance signal Early and the lag signal Late are coupled to the negative control voltage VCTRL_I via capacitors C3 and C4, respectively.

[0020] A low-pass filter (LPF) is connected between the charge pump CP_PL and the control voltage VCTRL to filter out high-frequency noise and generate a smooth control voltage VCTRL. Specifically, the low-pass filter (LPF) includes resistors Rz1 and Rz2, and capacitors Cp1 and Cp2. Resistors Rz1 and Rz2 are connected in series between the positive control voltage VCTRL_P and the negative control voltage VCTRL_I. Capacitors Cp1 and Cp2 are connected in parallel between the control voltage VCTRL and ground.

[0021] A voltage-to-current converter V2I is also connected between the control voltage VCTRL and the local clock oscillator ICO. This converter converts the control voltage VCTRL into a control current that drives the local clock oscillator ICO. The voltage-to-current converter V2I receives the voltage control signals (VCTRL_P and VCTRL_I) from the charge pump CP_PL and converts them into current signals to drive the VCO, ensuring that the VCO can accurately adjust its output frequency based on the phase error signal of the input data stream.

[0022] The above-mentioned CDR steps are as follows: Step 1: The CDR circuit receives the data stream Link Training or reference clock and performs frequency lock; Step 2: After the CDR locks the frequency, it switches the phase loop, receives the input data stream, generates the advance signal Early and the lag signal Late through the baseband phase detector BBPD, and controls the charge pump CP_PL to charge and discharge the low-pass filter LPF, thereby controlling the VCO output frequency to adjust with the input data phase difference; Step 3: The advance and lag signals output by the baseband phase detector BBPD are directly coupled to VCTRL_P through C1 and C2, and directly coupled to VCTRL_I through C3 and C4, thereby improving the fast response to low-frequency SSC.

[0023] In traditional phase loops, the power supply domain of advanced processes is relatively low. To ensure power supply rejection and the accuracy of the current mirror, the gate width of the charge pump (CP) output switch is typically increased, thereby limiting the charge and discharge time. In spread spectrum with higher modulation frequencies, frequency deviation is large and accompanied by frequency modulation, while the original current (ICP) remains unchanged. This results in the limited bandwidth being unable to quickly respond to frequency deviations, and in more serious cases, can lead to loss of lock. Therefore, by using the lead and lag signals of the baseband phase detector (BBPD) output and AC coupling (AC coupling) the potential on VCTRL, a pre-charge and discharge is created to improve responsiveness.

[0024] Example 2, as Figure 3 As shown, the difference from the first embodiment is that the early signal Early and the late signal Late are directly coupled to VRING of the VCO through capacitors C1 and C2 respectively. Since the delay of the low-pass filter LPF is skipped, the VCO response adjustment can be improved faster.

[0025] Example 3, as Figure 4 As shown, the difference from the first embodiment lies in the inclusion of a phase interpolator PI in the loop from the local clock oscillator ICO to the baseband phase detector BBPD, which feeds the local clock signal CLK2. In this architecture, the phase interpolator PI can be used to couple the lead / lag signals to the control voltage VCTRL, combined with a lead / lag pulse width comparison and counting, to further adjust the phase transcoding of the phase interpolator through an adaptive control circuit, thereby achieving a fast tracking response to SSC.

[0026] The Early and Late signals are coupled to the control voltage VCTRL and a phase interpolator (PI) is used to further improve eye diagram quality while ensuring fast SSC tracking. Due to the spread spectrum modulation of the input signal, the Early and Late signals output by the BBPD can be compared and counted. As positive and negative frequency offsets change, the probability of Early and Late occurrences also changes accordingly. Using a finite state machine (FSM) and an SSC tracking enhancement module, the phase interpolator's PI phase transcoding is adjusted via an adaptive control circuit, further enhancing the CDR's fast SSC tracking response.

[0027] The above description is only illustrative of the present invention and not restrictive. Those skilled in the art will understand that many modifications, changes or equivalents may be made without departing from the spirit and scope defined by the appended claims, but all of them will fall within the scope of protection of the present invention.

Claims

1. A CDR circuit for rapidly tracking a spread spectrum clock, characterized by: Included in sequence The analog front end (AFE) is used to perform balanced amplification on the reference clock signal to meet the capture range of the CDR. The baseband phase detector BBPD is used to detect the phase difference between the reference clock signal and the local clock signal CLK2 and generate a phase error signal. a charge pump CP_PL with phase lead, which receives the phase error signal and generates the control voltage VCTRL, and The local clock oscillator ICO is used to provide a stable local clock signal CLK2 and feed it back to the baseband phase detector BBPD. The phase error signal is coupled to the control voltage VCTRL or the tuning voltage VRING at the input terminal of the local clock oscillator ICO through the capacitor C.

2. The CDR circuit for fast tracking a spread spectrum clock according to claim 1, wherein: The analog front end AFE has an input terminal DATA_IN and an output terminal DIN. The input terminal DATA_IN is used to receive a data stream LinkTraining or a reference clock signal. The output terminal DIN is used to output the amplified and filtered reference clock signal to the baseband phase detector BBPD.

3. The CDR circuit for fast tracking a spread spectrum clock according to claim 1, wherein: The phase error signal is divided into an early signal and a late signal. The early signal and the late signal are respectively coupled to the control voltage VCTRL or the tuning voltage VRING of the input terminal of the local clock oscillator ICO through a capacitor C.

4. The CDR circuit for fast tracking a spread spectrum clock according to claim 3, wherein: The control voltage VCTRL is divided into a positive control voltage VCTRL_P and a negative control voltage VCTRL_I. The capacitor C includes capacitors C1, C2, C3, and C4. The early signal and the late signal are coupled to the positive control voltage VCTRL_P through capacitors C1 and C2, respectively. The early signal and the late signal are coupled to the negative control voltage VCTRL_I through capacitors C3 and C4, respectively.

5. The CDR circuit for fast tracking a spread spectrum clock according to claim 4, wherein: A low-pass filter LPF is connected between the charge pump CP_PL and the control voltage VCTRL to filter out high-frequency noise and generate a smooth control voltage VCTRL.

6. The CDR circuit for fast tracking a spread spectrum clock according to claim 5, wherein: The low-pass filter LPF includes a resistor Rz1, a resistor Rz2, a capacitor Cp1 and a capacitor Cp2. The resistor Rz1 and the resistor Rz2 are connected in series between the positive control voltage VCTRL_P and the negative control voltage VCTRL_I. The capacitor Cp1 and the capacitor Cp2 are connected in parallel between the control voltage VCTRL and ground.

7. The CDR circuit for fast tracking a spread spectrum clock according to claim 3, wherein: A voltage-to-current converter V2I is connected between the control voltage VCTRL and the local clock oscillator ICO, for converting the control voltage VCTRL into a control current and driving the local clock oscillator ICO.

8. The CDR circuit for fast tracking a spread spectrum clock according to claim 7, wherein: The tuning voltage VRING is the input voltage of the local clock oscillator ICO. The capacitor C includes a capacitor C1 and a capacitor C2. The early signal Early and the late signal Late are coupled to the tuning voltage VRING through the capacitor C1 and the capacitor C2, respectively.

9. The CDR circuit for fast tracking a spread spectrum clock according to claim 1, wherein: The local clock oscillator ICO feeds back the local clock signal CLK2 to the baseband phase detector BBPD, and a phase interpolator PI is connected to the loop.

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