Silicon oxide filled GST phase change shallow trench pixel-level electronic control metasurface structure and processing method thereof

Abstract

The invention relates to a silicon oxide filled GST phase change shallow trench pixel-level electronic control metasurface structure and a processing method thereof. The metasurface structure comprises a silicon substrate, a silicon oxide layer and a top ITO electrode from bottom to top. A shallow trench is arranged in the silicon oxide layer, and a bottom layer ITO electrode and a GST nano column are deposited in the shallow trench from bottom to top; the GST nanorod is made of a GST phase change material and is connected with the bottom layer ITO electrode and the top layer ITO electrode; the bottom layer ITO electrode and the top layer ITO electrode are arranged in an orthogonal mode. According to the method, the problem of phase change structure damage caused in high-temperature deposition and plasma etching processes is solved, meanwhile, the process complexity and the process stability are optimized, and the metasurface machining cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of micro-nano photonics, and particularly relates to a silicon oxide-filled GST (Ge2Sb2Te5) phase-change shallow groove pixel-level electrically controlled metasurface structure and a processing method thereof. Background Art

[0002] As optoelectronic chips develop towards high density and multifunctionality, near-infrared dynamic optical control technology has put forward higher requirements on the process compatibility, control accuracy and reliability of metasurface devices.

[0003] In the existing technology, the electrically controlled metasurface process mainly includes the following steps: 1. Phase-change material processing: GST thin films are sputtered at high substrate temperatures, and the GST layer is etched using fluorine- or chlorine-based plasmas to form isolation trenches. High-temperature sputtering can directly damage pre-integrated CMOS circuits on the silicon substrate, complicating the process compatibility of metasurface devices. Fluorine / chlorine-based plasma etching can also cause chemical damage to the GST sidewalls (e.g., Te volatilization), forming an amorphous-grain boundary mixed phase that reduces optical response consistency. Etching also reduces the surface flatness of the GST pillars, creating interface defects between the ITO (indium tin oxide (In2O3:SnO2 = 9:1)) electrode and the GST material, significantly increasing optical loss.

[0004] 2. Spacer filling layer processing: The isolation trenches are filled using chemical vapor deposition (CVD) and planarized using chemical mechanical polishing (CMP). High-temperature deposition induces stress mismatch between the GST and silicon oxide interfaces, creating microcracks that significantly reduce the reliability of the metasurface. Furthermore, achieving precise nanoscale control using CMP is difficult and results in low yield.

[0005] 3. Electrode processing technology: Traditional electrode designs are mostly global drive modes, using a full-surface sputtering electrode process. This causes all GST units to share the same electrical signal, making it impossible to achieve independent pixel-level control. At the same time, continuous layers introduce parasitic capacitance, causing electrical signal coupling between adjacent units.

[0006] Therefore, there is currently no suitable low-cost, low-optical-loss, high-stability pixel-level electrically controlled metasurface structure process method to solve the problems of the existing electrically controlled metasurface process lacking comprehensive considerations, ignoring the problem of chemical damage to the side walls of the structure caused by the etching process; the problem of interface stress mismatch caused by high-temperature deposition filling; the problem of multiple exposure, etching, and polishing processes increasing process complexity; and the problem of the whole-surface sputtering electrode limiting the freedom of dynamic control. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure and a processing method thereof, so as to reduce process damage to the metasurface, reduce the cost of metasurface processing, and realize pixel-level electrical control.

[0008] The present invention provides a silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, wherein the metasurface structure comprises, from bottom to top, a silicon substrate, a silicon oxide layer, and a top ITO electrode; shallow trenches are provided in the silicon oxide layer, and bottom ITO electrodes and GST nanocolumns are deposited in the shallow trenches from bottom to top; the GST nanocolumns are made of GST phase-change material and connected to the bottom ITO electrode and the top ITO electrode; the bottom ITO electrode and the top ITO electrode are arranged orthogonally.

[0009] The present invention also provides a method for processing the silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, comprising the following steps: S1. Processing of silicon oxide layer A silicon oxide layer is deposited on the surface of a silicon substrate using chemical vapor deposition (CVD), and in-situ plasma activation is used to optimize the interfacial bonding strength. A positive photoresist is then spin-coated on the surface of the silicon oxide layer and patterned using an electron beam exposure system to form an underlying circular hole array structure. Shallow trenches are then formed using reactive ion etching (RIE), completing the processing of the silicon oxide layer. S2. Processing of bottom ITO electrodes An ITO film is deposited on the surface of a silicon substrate using a magnetron sputtering process. The silicon substrate is then immersed in a degumming solution, and an ultrasonic-assisted lift-off process is used to remove the redundant ITO film outside the shallow trenches, achieving electrode patterning and completing the processing of the underlying ITO electrode. S3. Fabrication of GST Nanopillars A silicon oxide layer is deposited on the surface of the silicon substrate using the same process as step S1, and a positive photoresist is spin-coated on the surface of the silicon oxide layer, followed by overlay exposure to form a top circular hole array structure, and then shallow trenches are etched. Subsequently, a low-damage magnetron sputtering process is used to deposit GST phase change material into the shallow trenches, and a lift-off process is performed to remove redundant GST phase change material outside the shallow trenches, thereby completing the processing of GST nanopillars. S4. Processing of top ITO electrode Repeat the ITO electrode processing process described in step S2 to prepare an orthogonally arranged top layer of ITO electrodes on the surface of the silicon substrate, thereby obtaining a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

[0010] Preferably, in step S1 , electron beam exposure-reactive plasma etching is used to perform patterning pretreatment on the silicon substrate.

[0011] Preferably, the thickness of the silicon oxide layer in step S1 is 40-60 nm.

[0012] Preferably, the optimization of interfacial bonding strength through in-situ plasma activation technology described in step S1 is specifically performed by subjecting the silicon substrate on which the silicon oxide layer is deposited to an oxygen plasma treatment process, wherein the high-energy oxygen plasma generated by glow discharge undergoes a physical and chemical reaction with the substrate surface, thereby generating a high density of hydroxyl groups in situ on the surface. This hydrophilic modification process effectively reduces the surface free energy, significantly reducing the contact angle between the photoresist and the substrate, thereby enhancing the wettability and spreadability of the photoresist on the substrate surface, and ensuring the thickness uniformity and surface flatness of the photoresist film during the coating process.

[0013] Preferably, the thickness of the positive photoresist in step S1 is 150-200 nm.

[0014] Preferably, the acceleration voltage of the electron beam exposure system in step S1 is 50-150 KV.

[0015] Preferably, the diameter of the circular holes of the bottom circular hole array in step S1 is 200-1000 nm, and the array period error is ≤±5 nm.

[0016] Preferably, the depth of the shallow trench in step S1 is 40-60 nm.

[0017] Preferably, the chamber temperature of the magnetron sputtering process in step S2 is less than 150° C., and the sputtering power is 5-20 W.

[0018] Preferably, the thickness of the ITO film in step S2 is 40-60 nm.

[0019] Preferably, the degumming solution in step S2 includes but is not limited to an N-methylpyrrolidone (NMP)-based degumming solution.

[0020] Preferably, the overlapping accuracy of the top circular hole array in step S3 and the bottom circular hole array in step S1 is ≤10 nm.

[0021] Preferably, the chamber temperature of the low-damage magnetron sputtering process in step S3 is less than 150° C., and the sputtering power is 5-10 W.

[0022] Preferably, the GST phase change material in step S3 is Ge2Sb2Te5 phase change material.

[0023] Preferably, the thickness tolerance of the GST phase change material deposited in the shallow trench in step S3 is ±1 nm.

[0024] Preferably, the top ITO electrode in step S4 is perpendicular to the bottom ITO electrode in step S2, and the error of the intersection spacing is ≤20 nm.

[0025] The metasurface structure of the present invention consists of a periodic Si-ITO-GST nanopillar-ITO array on a silicon substrate, with silicon oxide filling the gaps between the arrays to achieve a design without isolation grooves. Compared with conventional metasurface structures, the metasurface structure of the present invention enables independent addressing of pixel-level electronic control units, significantly improving the dynamic control capability of near-infrared light fields. Through a low-temperature deposition-stripping process, the process complexity is reduced and the introduction of interface defects is avoided, significantly reducing the preparation cost and optical loss of the metasurface structure. This metasurface structure can be applied to the field of near-infrared dynamic imaging, providing technical support for the integration and functional reconstruction of optoelectronic chips.

[0026] Beneficial effects

[0027] The present invention provides a pixel-level electrically controlled metasurface structure and a processing method thereof, which optimizes the phase change structure damage problem caused by high-temperature deposition and plasma etching processes, while optimizing process complexity and process stability, and reducing the metasurface processing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 3D and sectional views of the super surface structure of the present invention.

[0029] Figure 2 This is a flow chart of the processing method of the super surface structure of the present invention.

[0030] Figure 3 This is a SEM image of the silicon oxide layer after processing in the embodiment.

[0031] Figure 4 This is the SEM image of the GST nanocolumns after processing in the embodiment.

[0032] Figure 5 This is a SEM image of the top ITO electrode after processing in the embodiment.

[0033] Reference numerals: 1-silicon substrate, 2-silicon oxide layer, 3-bottom ITO electrode, 4-GST nanorods, 5-top ITO electrode, 6-positive photoresist. DETAILED DESCRIPTION

[0034] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0035] Example

[0036] This embodiment provides a silicon oxide filled GST phase change shallow trench pixel-level electrically controlled metasurface structure, the three-dimensional and cross-sectional views of which are shown in FIG. Figure 1 As shown, the metasurface structure includes a silicon substrate 1, a silicon oxide layer 2 and a top ITO electrode 5 from bottom to top; a shallow groove is provided in the silicon oxide layer 2, and a bottom ITO electrode 3 and a GST nanocolumn 4 are deposited in the shallow groove from bottom to top; the GST nanocolumn 4 is made of GST phase change material and is connected to the bottom ITO electrode 3 and the top ITO electrode 5; the bottom ITO electrode 3 and the top ITO electrode 5 are arranged orthogonally.

[0037] The processing method flow chart of the above-mentioned super surface structure is as follows: Figure 2 As shown, the specific steps include: S1. Processing of silicon oxide layer 2 (1) Providing a silicon substrate 1, and performing patterning pretreatment on the silicon substrate 1 by electron beam exposure-reactive plasma etching; (2) A silicon oxide layer 2 with a thickness of 40-60 nm is deposited on the surface of the silicon substrate 1 using a CVD process, and the interface bonding strength is optimized by in-situ plasma activation technology; (3) A positive photoresist 6 with a thickness of 150-200 nm is spin-coated on the surface of the silicon oxide layer 2; then, an electron beam exposure system (acceleration voltage 100 kV) is used for patterning to form a bottom circular hole array structure with a diameter of 200-1000 nm (periodic error ≤±5 nm); and a shallow trench with a depth of 40-60 nm is created through RIE process, thereby completing the processing of the silicon oxide layer 2. The bottom surface roughness of the shallow trench is <1 nm (AFM detection), and the side wall verticality is >88°. Its morphology is as follows: Figure 3 As shown, there is no burr defect on the edge; S2. Processing of bottom ITO electrode 3 (4) Depositing an ITO film with a thickness of 40-60 nm on the surface of the silicon substrate 1 by a magnetron sputtering process at a chamber temperature of <150°C; (5) The silicon substrate 1 is then immersed in an N-methylpyrrolidone-based degumming solution, and the redundant ITO film outside the shallow groove is peeled off by an ultrasonic-assisted lift-off process to achieve electrode patterning, thereby completing the processing of the bottom ITO electrode 3, and its morphology is as follows: Figure 4 As shown; S3. Processing of GST Nanopillars 4 (6) Depositing a silicon oxide layer 2 with a thickness of 40-60 nm on the surface of the silicon substrate 1 using the same CVD process as in step (2); (7) Spin-coat a 150-200 nm thick positive photoresist 6 on the surface of the silicon oxide layer 2 using the same process as step (3), overlay exposure to form a top circular hole array structure with an overlap accuracy of ≤10 nm with the bottom circular hole array, and form a shallow trench with a depth of 40-60 nm by RIE etching; (8) Using a low-damage magnetron sputtering process (chamber temperature <150°C, sputtering power 5-10 W) to deposit GST phase change material into shallow trenches (thickness tolerance ±1 nm); (9) The same process as step (3) is used to lift-off the redundant GST phase change material outside the shallow groove, thereby completing the processing of the GST nanocolumn 4. The morphology after peeling is as follows Figure 5 As shown; S4. Processing of the top ITO electrode 5 (10) Repeat the ITO electrode processing technology of steps (4)-(5) to prepare an orthogonally arranged top ITO electrode 5 on the surface of the silicon substrate 1 (perpendicular to the bottom ITO electrode 3, with an intersection spacing error of ≤20 nm), thereby obtaining a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

[0038] The present invention's method for processing a silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure provides a stable, independent electrically controlled environment without damaging the phase-change material structure. The lift-off process for preparing the metasurface phase-change unit and electrode materials reduces process complexity while minimizing optical losses caused by defects between stacked materials.

Claims

1. A silicon oxide filled GST phase change shallow trench pixel-level electrically controlled metasurface structure, characterized in that: The metasurface structure includes a silicon substrate, a silicon oxide layer and a top ITO electrode from bottom to top; a shallow groove is provided in the silicon oxide layer, and a bottom ITO electrode and GST nanopillars are deposited in the shallow groove from bottom to top; the GST nanopillars are made of GST phase change material and are connected to the bottom ITO electrode and the top ITO electrode; the bottom ITO electrode and the top ITO electrode are arranged orthogonally.

2. A method for processing a silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, characterized in that: The following steps are involved: S1. Processing of silicon oxide layer A silicon oxide layer is deposited on the surface of a silicon substrate using chemical vapor deposition, and in-situ plasma activation technology is used to optimize the interfacial bonding strength. A positive photoresist is then spin-coated on the surface of the silicon oxide layer and patterned using an electron beam exposure system to form an underlying circular hole array structure. Then, a shallow trench is formed by etching using a reactive ion etching process, thereby completing the processing of the silicon oxide layer; S2. Processing of bottom ITO electrodes An ITO film is deposited on the surface of a silicon substrate using a magnetron sputtering process. The silicon substrate is then immersed in a degumming solution, and an ultrasonic-assisted lift-off process is used to remove the redundant ITO film outside the shallow trenches, achieving electrode patterning and completing the processing of the underlying ITO electrode. S3. Fabrication of GST Nanopillars A silicon oxide layer is deposited on the surface of the silicon substrate using the same process as step S1, and a positive photoresist is spin-coated on the surface of the silicon oxide layer, followed by overlay exposure to form a top circular hole array structure, and then shallow trenches are etched. Subsequently, a low-damage magnetron sputtering process is used to deposit GST phase change material into the shallow trenches, and a lift-off process is performed to remove redundant GST phase change material outside the shallow trenches, thereby completing the processing of GST nanopillars. S4. Processing of top ITO electrode Repeat the processing technology of the bottom ITO electrode described in step S2 to prepare an orthogonally arranged top ITO electrode on the surface of the silicon substrate, thereby obtaining a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

3. The processing method according to claim 2, characterized in that: In step S1, electron beam exposure-reactive plasma etching is used to perform patterning pretreatment on the silicon substrate.

4. The processing method according to claim 2, wherein: The thickness of the silicon oxide layer in step S1 is 40-60 nm.

5. The processing method according to claim 2, characterized in that The thickness of the positive photoresist in step S1 is 150-200 nm; the acceleration voltage of the electron beam exposure system is 50-150 KV.

6. The processing method according to claim 2, wherein: The diameter of the circular holes of the bottom circular hole array in step S1 is 200-1000 nm, and the array period error is ≤±5 nm; the depth of the shallow groove in step S1 is 40-60 nm.

7. The processing method according to claim 2, wherein: In step S2, the chamber temperature of the magnetron sputtering process is less than 150° C., and the sputtering power is 5-20 W; the thickness of the ITO film is 40-60 nm.

8. The processing method according to claim 2, wherein: The overlapping accuracy of the top circular hole array in step S3 and the bottom circular hole array in step S1 is ≤10 nm.

9. The processing method according to claim 2, wherein: The chamber temperature of the low-damage magnetron sputtering process in step S3 is less than 150° C., and the sputtering power is 5-10 W. The thickness tolerance of the GST phase change material deposited in the shallow trench in step S3 is ±1 nm.

10. The processing method according to claim 2, wherein: The top ITO electrode in step S4 is perpendicular to the bottom ITO electrode in step S2, and the intersection spacing error is ≤20 nm.

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