Silicon controlled rectifier for core particle electrostatic pulse rapid clamping and preparation method thereof

Abstract

The invention discloses a silicon controlled rectifier for core particle electrostatic pulse rapid clamping. The silicon controlled rectifier comprises a substrate P-Sub, a first DN-Well region, a second DN-Well region, a first P-Well region, a second P-Well region, a first N-Well region, a second N-Well region, a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth N + injection region, a third P + injection region, a fourth P + injection region, a fifth P + injection region, a sixth P + injection region and a second polysilicon gate. According to the invention, a silicon controlled rectifier structure with self-gain and rapid electrostatic pulse clamping is formed, and the protection level of chip core particle bonding electrostatic discharge can be improved; a polysilicon gate is controlled to open a channel, current is injected to conduct a parasitic NPN triode, and a low-trigger silicon controlled rectifier is further coupled, so that an electrostatic protection structure with a multi-channel parallel path is formed, the current discharge capacity of the device per unit area is remarkably enhanced, and the purpose of realizing rapid clamping of electrostatic voltage in a core particle is achieved.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection of three-dimensional integrated circuit semiconductor devices, and in particular to a thyristor rectifier for fast clamping of electrostatic pulses of core particles and a preparation method thereof. Background Art

[0002] As semiconductor processing enters the deep submicron era, electrostatic discharge (ESD) protection has become a critical bottleneck in chip die bonding reliability. According to statistics, ESD strikes account for as much as 58% of chip failures, with die bonding in 3D integrated circuits being one of the most vulnerable links. Traditional ESD protection structures struggle to achieve fast response times within nanoseconds at the nanometer scale. However, silicon-controlled rectifiers (SCRs), with their fast ESD pulse clamping properties, can stabilize transient voltages within a few nanoseconds to a safe threshold. This fast voltage clamping capability, combined with the SCR's positive feedback effect, the low on-resistance of N-type field-effect transistors, and the self-gain of NPN transistors, enables high fault currents. This effectively prevents metal melting and gate oxide breakdown at the bond interface caused by charge accumulation and thermal contact, significantly improving the ESD tolerance of the die bonding process. Currently, optimizing the synergistic effect of fast clamping and high fault current within a limited area has become a core challenge in ESD design for 3D integrated circuits.

[0003] Currently, the ESD protection performance of traditional silicon-controlled rectifiers (SCRs) in the field of three-dimensional integrated circuits (3D ICs) faces significant challenges. Core issues include: slow turn-on speeds leading to delayed response, making them incapable of handling fast-rising ESD pulses; excessive on-resistance causing significant voltage overshoot, increasing the risk of breakdown at the die-to-die bond interface; and uncontrollable ESD current paths, which can easily trigger latch-up. While existing improvements have lowered on-resistance through nested structures, these approaches fail to fundamentally optimize the latch-up positive feedback mechanism created by parasitic PNP / NPN transistors, lacking the additional self-gain effect. Furthermore, these improvements often come at the expense of area, severely limiting their application prospects in advanced 3D IC die packaging.

[0004] The structure and equivalent circuit of the traditional unidirectional silicon controlled rectifier are as follows: Figure 1As shown, this device exhibits significant drawbacks in ESD protection for 3D integrated circuit die bonding: its triggering mechanism relies on the avalanche breakdown effect between the N-Well and P-Well. Due to the low concentrations of the two wells, its breakdown voltage is high, making it impractical for direct application in the aforementioned scenario. As a conventional unidirectional thyristor rectifier gradually turns on, the conduction path must sequentially turn on the parasitic PNP transistor formed by the P+ injection region, N-Well region, P-Well region, and P+ injection region, and the parasitic NPN transistor formed by the N+ injection region, N-Well region, P-Well region, and N+ injection region, thereby creating a positive feedback effect for the thyristor. However, this positive feedback mechanism still lacks the additional self-gain effect, resulting in a limited current discharge capability for the electrostatic pulse path, a high on-resistance, and a low failure current. Under the high-intensity, fast ESD pulses encountered by die bonding, this serial triggering mechanism results in excessively high local current density, which can easily lead to thermal failure. In addition, its single-path lateral conductive path is difficult to adapt to the multi-dimensional ESD protection requirements of the vertical bonding interface, significantly increasing the chip bonding reliability risk of three-dimensional integrated circuits. Summary of the Invention

[0005] The present invention aims to solve one of the technical problems existing in the related art at least to a certain extent.

[0006] The purpose of the present invention is to provide a thyristor rectifier structure for fast clamping of electrostatic pulses of core particles with simple structure, small occupied area, fast response speed and strong antistatic ability, and to provide a manufacturing method thereof.

[0007] In order to achieve the above-mentioned object, the present invention provides a thyristor rectifier for fast clamping of electrostatic pulses of core particles, comprising: a substrate P-Sub; The substrate P-Sub is provided with a first DN-Well area, a second DN-Well area and a second P-Well area; The first DN-Well region is divided into two layers, the lower layer is provided with the first N-Well region and the first P-Well region from left to right, and the upper layer is provided with the first field oxygen isolation region, the first N+ injection region, the second field oxygen isolation region, the first P+ injection region, the third field oxygen isolation region, the second N+ injection region, the first polysilicon gate, the third N+ injection region, the fourth field oxygen isolation region, the second P+ injection region and the fifth field oxygen isolation region from left to right; The second DN-Well region is divided into two layers, the lower layer is provided with a second N-Well region, and the upper layer is provided with a fifth field oxygen isolation region, a fourth N+ implantation region, a sixth field oxygen isolation region and a second polysilicon gate from left to right; The second P-Well region is provided with a second polysilicon gate, a fifth N+ implantation region, a third P+ implantation region, a seventh field oxygen isolation region, a sixth N+ implantation region and an eighth field oxygen isolation region from left to right; The first N+ implantation region and the first P+ implantation region serve as the anode of the device; the third N+ implantation region, the second P+ implantation region and the fourth N+ implantation region are connected; the fifth N+ implantation region and the third P+ implantation region are connected; the second polysilicon gate serves as the gate of the device; the first polysilicon gate and the sixth N+ implantation region serve as the cathode of the device; When the chip core is bonded, the fast electrostatic pulse generated reaches the anode of the device, the gate is applied with a positive voltage, and the cathode of the device is grounded, the parasitic PNP transistor composed of the first N+ injection region, the first N-Well region, the first P+ injection region, the first P-Well region, and the second P+ injection region; the parasitic NPN1 transistor composed of the first P-Well region, the first N+ injection region, the first N-Well region, and the third N+ injection region; the fourth N+ injection region, the second N-Well region, the second DN-Well region, the second polysilicon gate, and the substrate P-Su b. An NMOS transistor composed of the second P-Well region and the fifth N+ injection region, a parasitic NPN2 transistor composed of the third P+ injection region, the substrate P-Sub, the second P-Well region, the fourth N+ injection region, the second N-Well region, the second DN-Well region, and the sixth N+ injection region, and a parasitic D1 diode composed of the third P+ injection region, the substrate P-Sub, the second P-Well region, and the sixth N+ injection region; the base region of the PNP transistor and the collector region of the NPN1 transistor are connected through the parasitic resistance R of the first N-Well region. N1 The base region of the NPN1 transistor and the collector region of the PNP transistor are connected through the parasitic resistance R P1 The drain of the NMOS transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, the collector region of the NPN2 transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, and the base region of the NPN2 transistor and the drain of the NMOS transistor are connected through the parasitic resistance R of the third P+ injection region and the second P-Well region. P2 , the sixth N+ implantation region, and the parasitic D1 diode are connected.

[0008] Preferably, the first N-Well region is adjacent to the first P-Well region and spans the middle of the second N+ implantation region.

[0009] Preferably, the left and right sides of the fifth field oxygen isolation region are respectively adjacent to the right side of the second P+ implantation region and the left side of the fourth N+ implantation region.

[0010] Preferably, the left and right sides of the second polysilicon gate are adjacent to the right side of the sixth field oxygen isolation region and the left side of the fifth N+ injection region respectively; the left and right sides of the second polysilicon gate span the right edge of the second DN-Well region and the left edge of the second P-Well region respectively; the fifth N+ injection region is adjacent to the third P+ injection region.

[0011] Preferably, the invention further comprises first to sixth metal layers and first to third metal connection layers, wherein the first to third metal connection layers are respectively provided with first to third metal through holes; The first N+ injection region and the first P+ injection region are connected to the first metal layer and the second metal layer respectively. The first metal layer and the second metal layer are connected to the first metal connection layer respectively through the first metal through-hole and serve as anodes of the device; The third N+ injection region, the second P+ injection region and the fourth N+ injection region are connected to the fourth metal layer; the fifth N+ injection region and the third P+ injection region are connected to the sixth metal layer; The second polysilicon gate is connected to the fifth metal layer, and the fifth metal layer is connected to the second metal connection layer through the second metal through-hole and serves as the gate of the device; The first polysilicon gate is connected to the third metal layer, the sixth N+ implantation region is connected to the third metal layer, and the third metal layer is connected to the third metal connection layer through the third metal through-hole as a cathode of the device.

[0012] In one aspect, the present invention provides a method for preparing a silicon controlled rectifier for fast clamping of electrostatic pulses of core particles, comprising the following steps: S1, forming a first DN-Well region and a second DN-Well region in the substrate P-Sub from left to right; S2. By photolithography, the first to eighth field oxygen isolation regions are formed on the substrate P-Sub from left to right: S3. Forming a first N-Well region and a first P-Well region in the first DN-Well region, forming a second N-Well region in the second DN-Well region, and forming a second P-Well region in the P-Sub region by photolithography; S4, forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second DN-Well region, the substrate P-Sub, and the second P-Well region; S5. Forming a first N+ implantation region, a first P+ implantation region, a second N+ implantation region, a third N+ implantation region, and a second P+ implantation region in the first N-Well region and the first P-Well region by photolithography; S6, forming a fourth N+ implantation region in the second N-Well region; S7, forming a fifth N+ implantation region, a third P+ implantation region, and a sixth N+ implantation region in the second P-Well region; S8. Connect the first N+ injection region and the first P+ injection region and use them as the anode of the device; connect the third N+ injection region, the second P+ injection region, and the fourth N+ injection region; connect the fifth N+ injection region and the third P+ injection region; use the second polysilicon gate as the gate of the device; connect the first polysilicon gate and the sixth N+ injection region and use them as the cathode of the device.

[0013] Preferably, the following steps are included between step S1 and step S2: first, a layer of silicon dioxide film is formed by thermal oxidation, and then a layer of silicon nitride is deposited; photoresist is evenly applied on the wafer, and the photoresist is exposed and developed to form shallow trench isolation STI; then the silicon nitride, silicon dioxide and isolation shallow trench are etched to remove the photoresist layer, and a layer of silicon dioxide is deposited, and then chemical mechanical polishing is performed until the silicon nitride film layer is reached, and the silicon nitride film layer is etched away.

[0014] Preferably, step S2 is specifically as follows: using field oxygen LOCOS isolation technology, using thermal oxidation method to grow a silicon dioxide thin film layer as a buffer layer, then using chemical vapor deposition LPCVD technology to deposit silicon nitride, applying photoresist on the wafer, and using photolithography technology to define the first to eighth field oxygen isolation regions; using reactive ion etching to remove the silicon nitride, and then performing field area injection to prevent the field area from being opened.

[0015] Preferably, the preparation method of the first N-Well region 301 and the second N-Well region 302 in step S3 is: applying a photoresist on the wafer, then implanting high-energy phosphorus ions to form a local N-type region, removing the photoresist layer, and then performing an annealing process to repair the crystal damage on the silicon surface caused by the ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using an RTP process; The preparation method of the first P-Well area 401 and the second P-Well area 402 is: apply photoresist on the wafer, then implant high-energy boron ions to form a local P-type area, and remove the photoresist; then perform annealing to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and use the RTP process to eliminate further diffusion of impurities.

[0016] Preferably, step S4 is specifically as follows: growth of a sacrificial oxide layer to capture defects on the silicon surface, growth of a gate oxide layer to serve as a gate insulating layer of the transistor, deposition of a first polysilicon gate and a second polysilicon gate using chemical vapor deposition (LPCVD) technology, photoresist molding, polysilicon etching, requiring precise acquisition of the specific shape of the polysilicon from the photoresist, and removal of the photoresist layer; polysilicon oxidation to buffer and isolate the polysilicon and the silicon nitride formed in subsequent steps, deposition of a layer of silicon nitride using chemical vapor deposition (LPCVD) technology, etching of the silicon nitride to leave isolation side walls, and precise positioning of ion implantation in the source and drain regions of the transistor.

[0017] Beneficial effects: (1) The present invention constitutes a thyristor rectifier structure for fast clamping of electrostatic pulses of core particles, which has an additional self-gain effect of the NPN transistor and a parallel channel path of the NMOS tube; that is, the drain of the NMOS tube and the collector of the parasitic NPN2 transistor are connected to the N+ injection region and the P+ injection region of the low-trigger thyristor rectifier; thereby, the channel path of the NMOS tube and the self-gain path of the parasitic NPN transistor are coupled on the basis of the positive feedback mechanism of the low-trigger thyristor rectifier, which significantly enhances the current discharge capability of the device and reduces the on-resistance, thereby achieving the purpose of increasing its failure current.

[0018] (2) The present invention uses a parasitic PNP transistor, two parasitic NPN transistors, and an NMOS transistor to form a thyristor structure with fast electrostatic pulse clamping and self-gain. Based on the above mechanism, the channel current of the NMOS transistor is used to achieve a fast response to the electrostatic pulse; multi-path current coupling is used to significantly improve the overcurrent per unit area of the device, and it is compatible with multi-dimensional electrostatic protection in the horizontal and vertical directions. Therefore, this type of structure can better protect the chip reliability during the bonding of three-dimensional integrated circuit core particles and always maintain a low reverse leakage current. In addition, in order to optimize the anti-latch capability of the above structure, the positive feedback effect and self-gain can be suppressed by increasing the lateral dimensions of the two polysilicon gates, thereby obtaining a higher holding voltage and the failure current will not be significantly reduced.

[0019] (3) The present invention has a simple structure and occupies a small area. The structure of the thyristor rectifier for fast clamping of electrostatic pulses of the chip is fully compatible with the standard CMOS process, does not use masks other than the standard process, and does not affect the chip bonding process of the three-dimensional integrated circuit. It can enable the thyristor device to have the ability to fast clamp electrostatic pulses and a high protection level, effectively protect the integrity of the signal transmission during chip chip bonding, and improve its reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The cross-sectional view and equivalent circuit diagram of the traditional unidirectional silicon controlled rectifier structure; Figure 2A cross-sectional view and circuit connection diagram of a silicon controlled rectifier structure for fast clamping of electrostatic pulses of a core particle in an embodiment of the present invention; Figure 3 Schematic diagram of a three-dimensional parasitic structure of a silicon controlled rectifier structure for fast clamping of electrostatic pulses of a core particle in an embodiment of the present invention; Figure 4 The equivalent circuit of the silicon controlled rectifier structure for fast clamping of electrostatic pulses of the core particles in the embodiment of the present invention is the ESD current release path; Figure 5 It is a top view of the structure of a thyristor rectifier for fast clamping of electrostatic pulses of a core in an embodiment of the present invention.

[0021] Wherein: 101 - substrate P-Sub region, 201 - first DN-Well region, 202 - second DN-Well region, 301 - first N-Well region, 302 - second N-Well region, 401 - first P-Well region, 402 - second P-Well region, 501 - first N+ implantation region, 502 - second N+ implantation region, 503 - third N+ implantation region, 504 - fourth N+ implantation region, 505 - fifth N+ implantation region, 506 - sixth N+ implantation region, 601 - first P+ implantation region, 602 - second P+ implantation region, 603 - third P+ implantation region, 701 - first polysilicon gate, 702 - second polysilicon gate , 801-first field oxygen isolation region, 802-second field oxygen isolation region, 803-third field oxygen isolation region, 804-fourth field oxygen isolation region, 805-fifth field oxygen isolation region, 806-sixth field oxygen isolation region, 807-seventh field oxygen isolation region, 808-eighth field oxygen isolation region, 901-first metal layer, 902-second metal layer, 903-third metal layer, 904-fourth metal layer, 905-fifth metal layer, 906-sixth metal layer, 1001-first metal connection layer, 1002-second metal connection layer, 1003-third metal connection layer, 1101-first metal through hole, 1102-second metal through hole, 1103-third metal through hole. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments, and they should not be understood as limitations on the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be understood that the terms used are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0023] Example 1: Figure 1 - Figure 5 As shown, the present invention provides a thyristor for fast clamping of electrostatic pulses of a core particle, comprising a substrate P-Sub region 101; a first DN-Well region 201, a second DN-Well region 202, and a second P-Well region 402 are provided in the substrate P-Sub region 101; a first N-Well region 301, a first P-Well region 401, a first field oxygen isolation region 801, a first N+ injection region 501, a second N-Well region 202, and a second P-Well region 402 are provided in the first DN-Well region 201 from bottom to top and from left to right. The second field oxygen isolation region 802, the first P+ implantation region 601, the third field oxygen isolation region 803, the second N+ implantation region 502, the first polysilicon gate 701, the third N+ implantation region 503, the fourth field oxygen isolation region 804, the second P+ implantation region 602, and the fifth field oxygen isolation region 805; wherein the first N-Well region 301 is adjacent to the first P-Well region 401 and spans the middle of the second N+ implantation region 502; the left side of the fifth field oxygen isolation region 805 is adjacent to the right side of the second P+ implantation region 602; the second The DN-Well region 202 is provided with a second N-Well region 302, a fifth field oxygen isolation region 805, a fourth N+ implant region 504, a sixth field oxygen isolation region 806, and a second polysilicon gate 702 from bottom to top and from left to right. The right side of the fifth field oxygen isolation region 805 is adjacent to the left side of the fourth N+ implant region 504. The left side of the second polysilicon gate 702 is adjacent to the right side of the sixth field oxygen isolation region 806. The left side of the second polysilicon gate 702 spans the right edge of the second DN-Well region 202. The second P-Well region 402 is provided with a second polysilicon gate 702, a fifth N+ injection region 505, a third P+ injection region 603, a seventh field oxygen isolation region 807, a sixth N+ injection region 506, and an eighth field oxygen isolation region 808 from left to right; wherein the right side of the second polysilicon gate 702 spans the left edge of the second P-Well region 402; the right side of the second polysilicon gate 702 is adjacent to the left side of the fifth N+ injection region 505; and the fifth N+ injection region 505 is adjacent to the third P+ injection region 603.

[0024] The first N+ injection region 501 is connected to the first metal layer 901 through a contact hole, and the first P+ injection region 601 is connected to the second metal layer 902 through a contact hole. A first metal through-hole 1101 is provided on the first metal connection layer 1001. The first metal layer 901 and the second metal layer 902 are connected to the first metal connection layer 1001 through the first metal through-hole 1101 and serve as the anode of the device.

[0025] The third N+ injection region 503, the second P+ injection region 602, and the fourth N+ injection region 504 are connected to the fourth metal layer 904 through contact holes; the fifth N+ injection region 505 and the third P+ injection region 603 are connected to the sixth metal layer 906 through contact holes.

[0026] The second polysilicon gate 702 is connected to the fifth metal layer 905 through a contact hole. A second metal through-hole 1102 is provided on the second metal connection layer 1002. The fifth metal layer 905 is connected to the second metal connection layer 1002 through the second metal through-hole 1102, serving as the gate of the device. The first polysilicon gate 701 is connected to the third metal layer 903 through a contact hole, and a third metal through-hole 1103 is provided on the third metal connection layer 1003, and the third metal layer 903 is connected to the third metal connection layer 1003 through the third metal through-hole 1103; the sixth N+ injection region 506 is connected to the third metal layer 903 through a contact hole, and the third metal layer 903 is connected to the third metal connection layer 1003 through the third metal through-hole 1103, serving as the cathode of the device.

[0027] The present invention constitutes a thyristor rectifier structure for fast clamping of electrostatic pulses of core particles, which has an additional self-gain effect of NPN transistor and a parallel channel path of NMOS tube; that is, the drain of NMOS tube and the collector of parasitic NPN2 transistor are connected to the N+ injection area and P+ injection area of low trigger thyristor rectifier, such as Figure 2 and Figure 3 As shown. Based on the positive feedback mechanism of the low-trigger thyristor rectifier, the channel path of the NMOS tube and the self-gain path of the parasitic NPN transistor are coupled, which significantly enhances the current discharge capability of the device and reduces the on-resistance, thereby achieving the purpose of increasing its failure current. The present invention uses a parasitic PNP transistor, two parasitic NPN transistors, and an NMOS tube to form a thyristor structure with electrostatic pulse fast clamping and self-gain, as shown. Figure 4 and Figure 5 Specifically: When the chip core is bonded, the fast electrostatic pulse generated reaches the anode of the device, the gate is applied with a positive voltage, and the cathode of the device is grounded, the first DN-Well area 201, the first N-Well area 301, the second N+ injection area 502 and the first P-Well area 401 undergo avalanche breakdown, and then the parasitic PNP transistor composed of the first N+ injection area 501, the first N-Well area 301, the first P+ injection area 601, the first P-Well area 401, and the second P+ injection area 602 is turned on; the parasitic NPN1 transistor composed of the first P-Well area 401, the first N+ injection area 501, the first N-Well area 301, and the third N+ injection area 503 is turned on; the fourth N+ injection area 504, the second N-Well area 30 2. An NMOS transistor consisting of the second DN-Well region 202, the second polysilicon gate 702, the substrate P-Sub region 101, the second P-Well region 402, and the fifth N+ injection region 505; a parasitic NPN2 transistor consisting of the third P+ injection region 603, the substrate P-Sub region 101, the second P-Well region 402, the fourth N+ injection region 504, the second N-Well region 302, the second DN-Well region 202, and the sixth N+ injection region 506; a parasitic D1 diode consisting of the third P+ injection region 603, the substrate P-Sub region 101, the second P-Well region 402, and the sixth N+ injection region 506; connecting the base region of the PNP transistor and the collector region of the NPN1 transistor through the parasitic resistor R of the first P-Well region N1 The base region of the NPN1 transistor and the collector region of the PNP transistor are connected through the parasitic resistance R P1 The drain of the NMOS transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, the collector region of the NPN2 transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, and the base region of the NPN2 transistor and the drain of the NMOS transistor are connected through the third P+ injection region 603 and the parasitic resistance R P2, the sixth N+ injection region 506, and the parasitic D1 diode are connected; based on the above mechanism, the channel current of the NMOS tube is used to achieve a rapid response to the electrostatic pulse; multi-path current coupling is adopted to significantly improve the overcurrent per unit area of the device, and to be compatible with multi-dimensional electrostatic protection in the horizontal and vertical directions, thereby forming a thyristor structure with multi-channel parallel paths, significantly enhancing the current discharge capacity per unit area of the device, and achieving the purpose of achieving rapid electrostatic voltage clamping in the core particle. Therefore, this type of structure can better protect the chip reliability during the bonding of the three-dimensional integrated circuit core particles, and always maintain a low reverse leakage current. In addition, for the optimization of the anti-latch capability of the above structure, the positive feedback effect and self-gain can be suppressed by increasing the lateral dimensions of the two polysilicon gates, thereby obtaining a higher holding voltage, and the failure current will not be significantly reduced.

[0028] Example 2, another aspect of the present invention provides a method for preparing a thyristor rectifier for fast clamping of electrostatic pulses of core particles, comprising the following steps: Step 1: forming a first DN-Well region 201 and a second DN-Well region 202 in the substrate P-Sub region 101. Specifically: The first DN-Well region 201, the second DN-Well region 202, and the second P-Well region 402 are formed in the substrate P-Sub region 101. A silicon dioxide film is then formed using thermal oxidation to mitigate stress damage caused by the silicon nitride formed in subsequent process steps. A layer of silicon nitride is deposited using LPCVD to serve as a stop layer for CMP in subsequent process steps.

[0029] Photoresist is evenly applied to the wafer, exposed, and developed. This step is used to define shallow trench isolation (STI). The silicon nitride, silicon dioxide, and isolation trenches are then etched to remove the photoresist layer. A layer of silicon dioxide is deposited using LPCVD, followed by chemical mechanical polishing until the silicon nitride film layer is reached. This layer is then removed using hot phosphoric acid wet etching.

[0030] Step 2: By photolithography, a first field oxygen isolation region 801, a second field oxygen isolation region 802, a third field oxygen isolation region 803, a fourth field oxygen isolation region 804, a fifth field oxygen isolation region 805, a sixth field oxygen isolation region 806, a seventh field oxygen isolation region 807, and an eighth field oxygen isolation region 808 are formed on the substrate P-Sub region 101. Specifically: Using LOCOS isolation technology, a silicon dioxide film layer is grown using thermal oxidation as a buffer layer. Silicon nitride is then deposited using LPCVD. Photoresist is then applied to the wafer, and photolithography is used to define the first LOCOS isolation region 801, the second LOCOS isolation region 802, the third LOCOS isolation region 803, the fourth LOCOS isolation region 804, the fifth LOCOS isolation region 805, the sixth LOCOS isolation region 806, the seventh LOCOS isolation region 807, and the eighth LOCOS isolation region 808. Reactive ions then etch away the silicon nitride on the first LOCOS isolation region 801, the second LOCOS isolation region 802, the third LOCOS isolation region 803, the fourth LOCOS isolation region 804, the fifth LOCOS isolation region 805, the sixth LOCOS isolation region 806, the seventh LOCOS isolation region 807, and the eighth LOCOS isolation region 808. Field implantation is then performed to prevent field turn-on.

[0031] Step 3: By photolithography, a first N-Well region 301 and a first P-Well region 401 are formed in the first DN-Well region 201, a second N-Well region 302 is formed in the second DN-Well region 202, and a second P-Well region 402 is formed in the P-Sub region 101. Specifically: A photoresist is coated on the wafer to define the first N-Well region 301 and the second N-Well region 302 , and then high-energy phosphorus ions are implanted to form a local N-type region, and the photoresist layer is removed.

[0032] A photoresist is coated on the wafer to define the first P-Well region 401 and the second P-Well region 402 , and then high-energy boron ions are implanted to form a local P-type region, and the photoresist is removed.

[0033] The first N-Well region 301, the first P-Well region 401, the second N-Well region 302, and the second P-Well region 402 are annealed to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using the RTP process.

[0034] Step 4: Form a first polysilicon gate 701 in the first P-Well region 401, and form a second polysilicon gate 702 in the second DN-Well region 202, the substrate P-Sub region 101, and the second P-Well region 402. Specifically: The growth of a sacrificial oxide layer is used to capture defects on the silicon surface. The gate oxide layer is grown to serve as the gate insulation layer of the transistor. The first polysilicon gate 701 and the second polysilicon gate 702 are deposited using chemical vapor deposition (LPCVD) technology. Photoresist is formed and polysilicon is etched. It is required to accurately obtain the specific shape of the polysilicon from the photoresist, and the photoresist layer is removed. Polysilicon oxidation is used to buffer and isolate the polysilicon and the silicon nitride formed in subsequent steps. A layer of silicon nitride is deposited using chemical vapor deposition (LPCVD) technology. The silicon nitride is etched to leave isolation sidewalls, and ion implantation in the source and drain regions of the transistor is precisely positioned.

[0035] Step 5: By photolithography, a first N+ implantation region 501, a first P+ implantation region 601, a second N+ implantation region 502, a third N+ implantation region 503, and a second P+ implantation region 602 are formed in the first N-Well region 301 and the first P-Well region 401; Step 6: Form a fourth N+ implantation region 504 in the second N-Well region 302 by photolithography; Step seven: forming a fifth N+ implantation region 505 , a third P+ implantation region 603 , and a sixth N+ implantation region 506 in the second P-Well region 402 by photolithography.

[0036] Specifically: Photoresist forming is used to control ion implantation, shallow depth, heavily doped boron ion implantation, remove the photoresist layer, and form the first P+ implantation area 601, the second P+ implantation area 602, and the third P+ implantation area 603.

[0037] Photoresist forming is used to control ion injection, shallow depth, heavily doped arsenic ion injection, remove the photoresist layer, and form the first N+ injection area 501, the second N+ injection area 502, the third N+ injection area 503, the fourth N+ injection area 504, the fifth N+ injection area 505, and the sixth N+ injection area 506.

[0038] Step 8: Connect the first N+ injection region and the first P+ injection region and use them as the anode of the device; connect the third N+ injection region, the second P+ injection region, and the fourth N+ injection region; connect the fifth N+ injection region and the third P+ injection region; use the second polysilicon gate as the gate of the device; connect the first polysilicon gate and the sixth N+ injection region and use them as the cathode of the device.

[0039] In summary, the present invention demonstrates a simple structure and a small footprint. The resulting thyristor structure for fast electrostatic pulse clamping of die is fully compatible with standard CMOS processes, requiring no masks beyond those used in standard processes and without interfering with the die bonding process of three-dimensional integrated circuits. This allows the thyristor device to possess fast electrostatic pulse clamping capabilities and a high level of protection, effectively protecting the integrity of signal transmission during die bonding and improving its reliability and stability.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A silicon controlled rectifier for fast clamping of electrostatic pulses of core particles, characterized in that: include: Substrate P-Sub; The substrate P-Sub is provided with a first DN-Well area, a second DN-Well area and a second P-Well area; The first DN-Well region is divided into two layers, the lower layer is provided with the first N-Well region and the first P-Well region from left to right, and the upper layer is provided with the first field oxygen isolation region, the first N+ injection region, the second field oxygen isolation region, the first P+ injection region, the third field oxygen isolation region, the second N+ injection region, the first polysilicon gate, the third N+ injection region, the fourth field oxygen isolation region, the second P+ injection region and the fifth field oxygen isolation region from left to right; The second DN-Well region is divided into two layers, the lower layer is provided with a second N-Well region, and the upper layer is provided with a fifth field oxygen isolation region, a fourth N+ implantation region, a sixth field oxygen isolation region and a second polysilicon gate from left to right; The second P-Well region is provided with a second polysilicon gate, a fifth N+ implantation region, a third P+ implantation region, a seventh field oxygen isolation region, a sixth N+ implantation region and an eighth field oxygen isolation region from left to right; The first N+ implantation region and the first P+ implantation region serve as the anode of the device; the third N+ implantation region, the second P+ implantation region and the fourth N+ implantation region are connected; the fifth N+ implantation region and the third P+ implantation region are connected; the second polysilicon gate serves as the gate of the device; the first polysilicon gate and the sixth N+ implantation region serve as the cathode of the device; When the chip core is bonded, the fast electrostatic pulse generated reaches the anode of the device, the gate is applied with a positive voltage, and the cathode of the device is grounded, the parasitic PNP transistor composed of the first N+ injection region, the first N-Well region, the first P+ injection region, the first P-Well region, and the second P+ injection region; the parasitic NPN1 transistor composed of the first P-Well region, the first N+ injection region, the first N-Well region, and the third N+ injection region; the fourth N+ injection region, the second N-Well region, the second DN-Well region, the second polysilicon gate, and the substrate P-Su b. An NMOS transistor composed of the second P-Well region and the fifth N+ injection region, a parasitic NPN2 transistor composed of the third P+ injection region, the substrate P-Sub, the second P-Well region, the fourth N+ injection region, the second N-Well region, the second DN-Well region, and the sixth N+ injection region, and a parasitic D1 diode composed of the third P+ injection region, the substrate P-Sub, the second P-Well region, and the sixth N+ injection region; the base region of the PNP transistor and the collector region of the NPN1 transistor are connected through the parasitic resistance R of the first N-Well region. N1 The base region of the NPN1 transistor and the collector region of the PNP transistor are connected through the parasitic resistance R P1 The drain of the NMOS transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, the collector region of the NPN2 transistor is connected to the collector region of the PNP transistor and the emitter region of the NPN1 transistor, and the base region of the NPN2 transistor and the drain of the NMOS transistor are connected through the parasitic resistance R of the third P+ injection region and the second P-Well region. P2 , the sixth N+ implantation region, and the parasitic D1 diode are connected.

2. The silicon controlled rectifier for fast clamping of electrostatic pulses of a core according to claim 1, characterized in that: The first N-Well region is adjacent to the first P-Well region and spans the middle of the second N+ implantation region.

3. The silicon controlled rectifier for fast clamping of electrostatic pulses of a core according to claim 2, characterized in that: The left and right sides of the fifth field oxygen isolation region are respectively adjacent to the right side of the second P+ implantation region and the left side of the fourth N+ implantation region.

4. The silicon controlled rectifier for fast clamping of electrostatic pulses of a core according to claim 3, characterized in that: The left and right sides of the second polysilicon gate are adjacent to the right side of the sixth field oxygen isolation region and the left side of the fifth N+ injection region respectively; the left and right sides of the second polysilicon gate span the right edge of the second DN-Well region and the left edge of the second P-Well region respectively; the fifth N+ injection region is adjacent to the third P+ injection region.

5. The silicon controlled rectifier for fast clamping of electrostatic pulses of a core according to claim 4, characterized in that: The invention also includes first to sixth metal layers and first to third metal connection layers, wherein the first to third metal connection layers are respectively provided with first to third metal through holes; The first N+ injection region and the first P+ injection region are connected to the first metal layer and the second metal layer respectively. The first metal layer and the second metal layer are connected to the first metal connection layer respectively through the first metal through-hole and serve as anodes of the device; The third N+ injection region, the second P+ injection region and the fourth N+ injection region are connected to the fourth metal layer; the fifth N+ injection region and the third P+ injection region are connected to the sixth metal layer; The second polysilicon gate is connected to the fifth metal layer, and the fifth metal layer is connected to the second metal connection layer through the second metal through-hole and serves as the gate of the device; The first polysilicon gate is connected to the third metal layer, the sixth N+ implantation region is connected to the third metal layer, and the third metal layer is connected to the third metal connection layer through the third metal through-hole as a cathode of the device.

6. A method for preparing a thyristor rectifier for fast clamping of core electrostatic pulses according to any one of claims 1 to 5, characterized in that: The steps include: S1, forming a first DN-Well region and a second DN-Well region in the substrate P-Sub from left to right; S2. By photolithography, the first to eighth field oxygen isolation regions are formed on the substrate P-Sub from left to right: S3. Forming a first N-Well region and a first P-Well region in the first DN-Well region, forming a second N-Well region in the second DN-Well region, and forming a second P-Well region in the P-Sub region by photolithography; S4, forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second DN-Well region, the substrate P-Sub, and the second P-Well region; S5. Forming a first N+ implantation region, a first P+ implantation region, a second N+ implantation region, a third N+ implantation region, and a second P+ implantation region in the first N-Well region and the first P-Well region by photolithography; S6, forming a fourth N+ implantation region in the second N-Well region; S7, forming a fifth N+ implantation region, a third P+ implantation region, and a sixth N+ implantation region in the second P-Well region; S8. Connect the first N+ injection region and the first P+ injection region and use them as the anode of the device; connect the third N+ injection region, the second P+ injection region, and the fourth N+ injection region; connect the fifth N+ injection region and the third P+ injection region; use the second polysilicon gate as the gate of the device; connect the first polysilicon gate and the sixth N+ injection region and use them as the cathode of the device.

7. The method for preparing a thyristor rectifier for fast core electrostatic pulse clamping according to claim 6, characterized in that: The steps between step S1 and step S2 include the following: first, forming a silicon dioxide film by thermal oxidation, and then depositing a silicon nitride layer; evenly applying photoresist on the wafer, exposing and developing the photoresist, and forming shallow trench isolation (STI); Then, the silicon nitride, silicon dioxide and isolation shallow grooves are etched to remove the photoresist layer, and a layer of silicon dioxide is deposited. After that, chemical mechanical polishing is performed until the silicon nitride film layer is reached, and the silicon nitride film layer is etched away.

8. The method for preparing a thyristor rectifier for fast core electrostatic pulse clamping according to claim 7, characterized in that: Step S2 is specifically as follows: using field oxygen LOCOS isolation technology, using thermal oxidation method to grow a silicon dioxide thin film layer as a buffer layer, then using chemical vapor deposition LPCVD technology to deposit silicon nitride, applying photoresist on the wafer, and using photolithography technology to define the first to eighth field oxygen isolation regions; using reactive ion etching to remove the silicon nitride, and then performing field area injection to prevent the field area from being opened.

9. The method for preparing a thyristor rectifier for fast core electrostatic pulse clamping according to claim 8, characterized in that: In step S3, the preparation method of the first N-Well region 301 and the second N-Well region 302 is as follows: a photoresist is coated on the wafer, and then high-energy phosphorus ions are implanted to form a local N-type region, the photoresist layer is removed, and then an annealing process is performed to repair the crystal damage on the silicon surface caused by the ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using an RTP process; The preparation method of the first P-Well area 401 and the second P-Well area 402 is: apply photoresist on the wafer, then implant high-energy boron ions to form a local P-type area, and remove the photoresist; then perform annealing to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and use the RTP process to eliminate further diffusion of impurities.

10. The method for preparing a thyristor rectifier for fast core electrostatic pulse clamping according to claim 9, characterized in that: Step S4 specifically includes: growth of a sacrificial oxide layer to capture defects on the silicon surface, growth of a gate oxide layer to serve as a gate insulating layer for the transistor, deposition of a first polysilicon gate and a second polysilicon gate using chemical vapor deposition (LPCVD) technology, photoresist molding, polysilicon etching, requiring precise acquisition of the specific shape of the polysilicon from the photoresist, and removal of the photoresist layer; polysilicon oxidation to buffer and isolate the polysilicon and the silicon nitride formed in subsequent steps, deposition of a layer of silicon nitride using chemical vapor deposition (LPCVD) technology, etching of the silicon nitride to leave isolation sidewalls, and precise positioning of ion implantation in the source and drain regions of the transistor.

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