TOPCon solar cell and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a TOPCon solar cell and a preparation method thereof. The preparation method comprises the steps of front surface texturing, boron diffusion, removal of BSG + alkali polishing, deposition of a back surface insulating layer, local grooving on the insulating layer, deposition of a tunneling oxide layer and a polycrystalline silicon layer in sequence in a local grooving area, phosphorus diffusion, removal of PSG + RCA, deposition of a passivation layer and an anti-reflection film layer, and silk-screen printing. According to the method, the insulating layer is deposited on the back surface of the silicon wafer, local grooving is carried out, the oxide layer / polycrystalline silicon layer and the printing electrode are tunneled in the grooving area, non-contact passivation is reserved, meanwhile, the carrier transmission path is optimized, the recombination loss is reduced, the passivation performance of the battery prepared through the method can be further optimized, and the service life of the battery is prolonged. The conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TOPCon solar cell and a preparation method thereof. Background Art

[0002] TOPCon solar cells (Tunnel Oxide Passivated Contact) are a new generation of high-efficiency crystalline silicon solar cell technology. With its unique back-side passivated contact structure, it has quickly become a mainstream technology in the photovoltaic industry. Its core innovation lies in the preparation of an ultra-thin tunnel oxide layer (1-2 nm) on the back of the silicon wafer. ) and a doped polysilicon layer (80-150 nm) composite structure: On the one hand, the tunneling oxide layer enables efficient carrier transport (electrons or holes) through the quantum tunneling effect. At the same time, its extremely low interface defect state density significantly reduces the recombination velocity on the back side of the silicon wafer, significantly improving the minority carrier lifetime. On the other hand, the doped polysilicon layer acts as a selective contact layer, forming a high-low junction through Fermi-level pinning, effectively blocking the diffusion of minority carriers (such as holes in N-type TOPCon solar cells) to the metal electrode. This enables the cell's open-circuit voltage (Voc) to exceed 720 mV and a fill factor (FF) exceeding 83%. Compared to the previous generation PERC technology, TOPCon solar cells achieve an average increase in photoelectric conversion efficiency (η) of 1.5%-2.0%, making them one of the most efficient crystalline silicon cell technologies currently in mass production.

[0003] Although TOPCon solar technology has achieved industrial breakthroughs, its traditional full-contact structure has the following problems: 1) Long-wave parasitic absorption. The high refractive index of polysilicon leads to a decrease in the reflectivity of incident light. The absorption coefficient of the polysilicon layer to near-infrared light (>1000 nm) is low. ) is 3-5 times that of silicon materials, resulting in the penetration depth of photons in this band in the polysilicon layer being less than 50nm, unable to reach the silicon wafer substrate to participate in photoelectric conversion, thereby limiting the improvement of the battery short-circuit current (Jsc); 2) Interface recombination is intensified, and the defect state density (Dit) at the interface between the polysilicon layer and the silver paste electrode is as high as , causing the contact resistance (Rc) to decrease from the ideal value ( ) rise to , while shortening the minority carrier lifetime (τeff) from 800 μs to 550 μs; 3) The lateral resistance loss is significant. The carriers in the polysilicon layer of the traditional structure need to be transmitted laterally to the electrode contact point, and the long path causes resistance loss.

[0004] The current industrial efficiency of TOPCon solar cells has reached a theoretical bottleneck of 28.7%. Further improvement requires overcoming the inherent contradictions of the full-area structure. Existing technologies have attempted to alleviate these issues by reducing the thickness of the polysilicon layer or optimizing the doping concentration. However, thicknesses below 100 nm can lead to reduced reliability of the tunneling oxide layer (increased pinhole density), while high doping concentrations ( ) will cause lattice distortion and aggravate recombination. Therefore, it is urgent to develop a TOPCon solar cell structure that can achieve synergistic optimization of optical and electrical performance without sacrificing passivation performance. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a TOPCon solar cell and a preparation method thereof, which realizes the coordinated optimization of optical and electrical properties.

[0006] In one aspect, the present invention provides a method for preparing TOPCon solar energy, which comprises:

[0007] (1) Take an N-type silicon wafer and perform front surface texturing;

[0008] (2) Boron diffusion on the textured surface;

[0009] (3) After removing the borosilicate glass layer on the back and sides of the silicon wafer, polishing the back;

[0010] (4) Depositing an insulating layer on the polished back surface;

[0011] (5) Locally groove the insulating layer using a laser, and then clean the silicon wafer to remove the damaged layer and the side insulating layer in the grooved area;

[0012] (6) In-situ treatment of the silicon backside using hydrogen plasma, followed by sequential deposition of a tunneling oxide layer and a polysilicon layer;

[0013] (7) diffusing phosphorus in the polysilicon layer;

[0014] (8) removing the phosphosilicate glass layer on the back and side surfaces of the silicon wafer, and removing the insulating layer and borosilicate glass layer on the front surface;

[0015] (9) depositing a passivation layer and an anti-reflection film layer on the back side of the silicon wafer in sequence;

[0016] (10) Screen printing electrodes in the local grooved area.

[0017] Preferably, the width of the groove area is 50-800 μm, the side wall roughness is less than 10 nm, and the width of the electrode is 10-40 μm.

[0018] Preferably, the local grooving is performed by laser grooving, with a laser wavelength of 300-600 nm, a laser power of 40-50 W, a scanning speed of 35 m / s, and a spot size of 100-400 μm.

[0019] Preferably, after the local grooving, the grooving area is further cleaned with a mixed acid of HF and HNO3 to remove residues; the HF concentration is 1-5 mol / L.

[0020] Preferably, the insulating layer is a silicon oxide, aluminum oxide or silicon nitride layer, and the thickness of the insulating layer is 10-200 nm.

[0021] Preferably, the polishing liquid for the back alkali polishing uses an alkali solution with a concentration of 5 to 20 mol / L and a polishing additive, and the alkali solution is NaOH and / or KOH.

[0022] Preferably, the tunnel oxide layer has a thickness of 1-2 nm, and the polysilicon layer has a thickness of 60-200 nm.

[0023] Preferably, the passivation layer is an Al2O3 passivation layer deposited by atomic deposition method, with a thickness of 1-5 nm.

[0024] Preferably, the anti-reflection film layer is a silicon nitride thin film layer deposited by PECVD method, with a thickness of 50-150 nm.

[0025] Preferably, after the screen printing of the electrodes, sintering and light injection treatment are performed.

[0026] Preferably, the electrode is Ag.

[0027] Preferably, the screen printing electrode and sintering are specifically as follows: firstly, a metal grid line is printed in a local grooved area on the back of the TOPCon solar cell using Ag paste, and then sintered at 780-850° C. for 20-60 seconds.

[0028] Preferably, the light injection treatment uses a light intensity of 20-40 suns and a light duration of 10-20 seconds.

[0029] In one aspect, the present invention further provides a TOPCon solar cell produced by the above method for producing a TOPCon solar cell.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] (1) An insulating layer is introduced on the back of the silicon substrate, and a local groove design is used to retain the complete insulating layer in the non-contact area, achieving high-density interface passivation, suppressing carrier surface recombination, and maintaining a high open-circuit voltage. At the same time, since the insulating layer is retained only in the non-contact area, the optical loss caused by parasitic absorption can be greatly reduced compared to the full-area contact technology. Grooving is performed in the contact area, and a tunneling oxide layer and a polysilicon layer are deposited in the grooved area, overcoming the lateral transmission loss defect, shortening the carrier transmission path, and thus reducing current loss; at the same time, since the tunneling oxide layer and the polysilicon layer are deposited in the grooved area, a lateral doping concentration gradient is formed on the back of the silicon substrate, constructing a low-resistance carrier channel, thereby improving the fill factor. The simultaneous optimization of the battery optical utilization rate and the battery conversion rate is achieved.

[0032] (2) In the early stage of the process, an insulating layer is introduced on the back of the silicon substrate. Combined with the local grooving process, when phosphorus diffuses, the grooves formed in the grooving area allow phosphorus to directly contact the substrate, resulting in a larger doping depth and concentration. However, the non-contact area has a relatively low doping concentration due to the barrier of the insulating layer introduced on the back of the silicon substrate, which achieves the purpose of differentiating the doping concentration.

[0033] (3) The slotted area is formed into a micron-scale contact window through laser micromachining technology, which can ensure the precise alignment of the electrode and the slot, avoiding the electrode covering the non-slotted area and damaging the passivation layer, and preventing the carrier collection efficiency from decreasing due to excessive spacing, thereby achieving the coordinated optimization of contact resistance and recombination loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and, therefore, should not be regarded as limiting the scope. For those skilled in the art, other relevant drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a flow chart of the preparation of the TOPCon solar cell of the present invention;

[0036] Figure 2 It is a schematic structural diagram of the TOPCon solar cell of the present invention.

[0037] Among them, 1. anti-reflection layer, 2. passivation layer, 3. boron-doped layer, 4. silicon substrate, 5. insulating layer, 6. tunneling oxide layer, 7. phosphorus-doped layer, 8. metal gate line. DETAILED DESCRIPTION

[0038] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0039] like Figure 1 As shown, the method for preparing a TOPCon solar cell of the present invention comprises the following steps:

[0040] (1) Texturing: Clean the N-type silicon substrate and texturing the front side with alkaline solution;

[0041] (2) Boron diffusion: Boron diffusion is performed on the textured surface using BCl3 or BBr3 thermal diffusion method;

[0042] (3) BSG removal + alkaline polishing: After removing the borosilicate glass layer on the back of the silicon wafer with HF solution, the back of the silicon substrate is alkaline polished with NaOH solution and polishing additives, and then cleaned with pure water after polishing;

[0043] (4) Back side insulating layer deposition: using CVD or ALD to deposit an insulating layer on the back side of the alkali polished silicon substrate. The insulating layer is one or more of SiO2, Al2O3, and SiNx. The thickness of the insulating layer is 10~200nm.

[0044] (5) Local grooving: Use laser to locally groove the above-mentioned insulating layer to remove part of the insulating layer. The number of local grooves is the same as the number of back electrodes. The width W of the groove area is 50~800μm, and the local groove area is cleaned with HF;

[0045] (6) Tunneling oxide layer + polysilicon deposition: The back side of the silicon is treated in situ with hydrogen plasma, and then the tunneling oxide layer and polysilicon layer are deposited in the local groove area in sequence using LPCVD, PECVD or sputtering. The thickness of the tunneling oxide layer is 1~2nm, and the thickness of the polysilicon layer is 60~200nm.

[0046] (7) Phosphorus diffusion: Phosphorus diffusion is performed in the polysilicon layer using POCl3 vapor at a temperature of 800°C to form a shallow junction. Dopants are activated by rapid annealing (10s) at 900°C. Laser-induced doping is used in the groove area with an energy density of 1.2-1.8 J / cm² and a phosphorus doping concentration of 1×10 20 ~5×10 20 atoms / cm³, the phosphorus doping concentration in the non-groove area is 1×10 19 ~5×10 19 atoms / cm³, achieving a balance between low-resistance conduction in the contact area and efficient composite suppression in the passivation area.

[0047] (8) PSG+RCA removal: Use HF solution to remove the phosphosilicate glass layer on the back and sides of the silicon wafer, and remove the borosilicate glass layer and insulating layer on the front of the silicon wafer;

[0048] (9) Deposition of passivation layer and anti-reflection film: A passivation layer is deposited on the velvet surface and back of the silicon wafer by atomic deposition method. The passivation layer is Al2O3 with a thickness of 1~5nm; an anti-reflection film is deposited on the passivation layer by PECVD method. The anti-reflection film is a silicon nitride thin film layer with a thickness of 50~150nm;

[0049] (10) Screen printing: First, use Ag paste to print the metal grid lines in the local groove area on the back of the TOPCon solar cell, then sinter at 780~850℃ for 20~60s; then perform light injection under a light intensity of 20~40s and a light duration of 10~20s.

[0050] like Figure 2 As shown, the TOPCon cell prepared by the above method includes a silicon substrate 1, a velvet surface 2, a boron diffusion layer 3, a front passivation layer 4 and a front anti-reflection film layer 5 arranged in sequence from the inside to the outside on the front side of the substrate, an insulating layer 6 with multiple grooved areas arranged in sequence from the inside to the outside on the back side of the substrate, a tunneling oxide layer 7, a polysilicon layer 8, a PN junction 9, a back passivation layer 10, a back anti-reflection film layer 11 and an electrode 12 arranged in the grooved area.

[0051] The TOPCon solar cell and its preparation method in this embodiment are reviewed in detail below through examples and comparative examples.

[0052] Example 1

[0053] A TOPCon solar cell comprises an N-type silicon substrate, a velvet surface, a boron diffusion layer, a front passivation layer, and a front anti-reflection film layer sequentially arranged on the front side of the substrate from the inside to the outside, an insulating layer having multiple grooved regions sequentially arranged on the back side of the substrate from the inside to the outside, a tunneling oxide layer, a polysilicon layer, a PN junction, a back passivation layer, a back anti-reflection film layer, and an Ag electrode arranged in the grooved region; the front passivation layer has a thickness of 3 nm, the front anti-reflection film layer has a thickness of 100 nm, the grooved region has a width of 100 μm, the tunneling oxide layer has a thickness of 2 nm, the polysilicon layer has a thickness of 100 nm, the Al2O3 back passivation layer has a thickness of 3 nm, the silicon nitride back anti-reflection film layer has a thickness of 100 nm, and the Ag electrode has a width of 20 μm; the insulating layer is a single Al2O3 layer with a thickness of 15 nm.

[0054] The preparation method of the TOPCon battery comprises the following steps:

[0055] Step 1: Clean the N-type silicon substrate with a thickness of 150 μm and texturize the front side with NaOH solution;

[0056] Step 2: Use BBr3 thermal diffusion method to diffuse boron on the textured surface. The diffusion temperature is 950~1000℃ and the square resistance is 300~400℃. ;

[0057] Step 3: After removing the borosilicate glass layer on the back of the silicon wafer with an HF solution, the back of the silicon substrate is alkaline polished with a NaOH solution and a polishing additive, and then rinsed with pure water after polishing;

[0058] Step 4: Using ALD to deposit an insulating layer on the back of the alkali-polished silicon substrate, the insulating layer is a single layer of Al2O3 with a thickness of 10nm;

[0059] Step 5: Using a laser with a wavelength of 355 nm, a laser power of 45 W, a scanning speed of 35 m / s, and a spot size of 100 μm, locally groove the above-mentioned insulating layer to remove part of the insulating layer. The number of local grooves is the same as the number of back electrodes, and the width W1 of the groove area is 100 μm. The local groove area is then cleaned with HF.

[0060] Step 6: Using LPCVD to deposit a tunnel oxide layer and a polysilicon layer in the local groove area, the tunnel oxide layer has a thickness of 2 nm and the polysilicon layer has a thickness of 100 nm;

[0061] Step 7: Phosphorus diffusion is performed on the polysilicon layer using POCl3 vapor at 800°C, and rapid annealing (10s) is performed at 900°C to activate the dopant. Laser-induced doping is used in the groove area with an energy density of 1.5 J / cm² and a phosphorus doping concentration of 3×10 20 atom / cm³, the phosphorus doping concentration in the non-groove area is 3×10 19 atom / cm³;

[0062] Step 8: Use HF solution to remove the phosphosilicate glass layer on the back and sides of the silicon wafer, and remove the borosilicate glass layer and insulating layer on the front of the silicon wafer;

[0063] Step 9: A passivation layer is deposited on the velvet surface and back of the silicon wafer using the atomic deposition method. The passivation layer is Al2O3 with a thickness of 1-5nm. An anti-reflection film is deposited on the passivation layer using the PECVD method. The anti-reflection film is a silicon nitride thin film layer with a thickness of 100nm.

[0064] Step 10: First, use Ag paste to print a 20μm wide metal grid line in the local groove area on the back of the TOPCon solar cell, then sinter it at 800℃ for 50s; then perform light injection under a light intensity of 30sun and a light duration of 20s.

[0065] Example 2

[0066] A TOPCon solar cell comprises an N-type silicon substrate, a velvet surface, a boron diffusion layer, a front passivation layer and a front anti-reflection film layer arranged in sequence from the inside to the outside on the front side of the substrate, an insulating layer having a plurality of grooved regions arranged in sequence from the inside to the outside on the back side of the substrate, a tunneling oxide layer, a polysilicon layer, a PN junction, a back passivation layer, a back anti-reflection film layer and an Ag electrode arranged in the grooved region; the front passivation layer has a thickness of 5nm, the front anti-reflection film layer has a thickness of 150nm, the grooved region has a width of 50μm, the tunneling oxide layer has a thickness of 1nm, the polysilicon layer has a thickness of 200nm, the Al2O3 back passivation layer has a thickness of 5nm, the silicon nitride back anti-reflection film layer has a thickness of 150nm, and the Ag electrode has a width of 10μm; the insulating layer is a single layer , with a thickness of 5nm.

[0067] The preparation method of the TOPCon battery comprises the following steps:

[0068] Step 1: Clean the N-type silicon substrate with a thickness of 150 μm and texturize the front side with NaOH solution;

[0069] Step 2: Use BBr3 thermal diffusion method to diffuse boron into the textured surface. The diffusion temperature is 950~1000℃ and the sheet resistance is ;

[0070] Step 3: After removing the borosilicate glass layer on the back of the silicon wafer with an HF solution, the back of the silicon substrate is alkaline polished with a NaOH solution and a polishing additive, and then rinsed with pure water after polishing;

[0071] Step 4: Use CVD to deposit an insulating layer on the back of the alkaline polished silicon substrate. The insulating layer is a single layer. , thickness is 5nm;

[0072] Step 5: Using a laser with a wavelength of 355 nm, a frequency of 80 kHz, a scanning speed of 35 m / s, and a spot size of 50 μm, the insulating layer is partially grooved to remove part of the insulating layer. The number of local grooves is the same as the number of back electrodes, and the width W1 of the groove area is 50 μm. The local groove area is then cleaned with HF.

[0073] Step 6: Using PECVD to deposit a tunnel oxide layer and a polysilicon layer in the local groove area, the tunnel oxide layer has a thickness of 1 nm and the polysilicon layer has a thickness of 200 nm;

[0074] Step 7: Phosphorus diffusion is performed on the polysilicon layer using POCl3 vapor at 800°C, and rapid annealing (10s) is performed at 900°C to activate the dopant. Laser-induced doping is used in the groove area with an energy density of 1.2 J / cm² and a phosphorus doping concentration of 1×10 20 atoms / cm³, the phosphorus doping concentration in the non-groove area is 1×10 19 atom / cm³;

[0075] Step 8: Use HF solution to remove the phosphosilicate glass layer on the back and sides of the silicon wafer, and remove the borosilicate glass layer and insulating layer on the front of the silicon wafer;

[0076] Step 9: A passivation layer is deposited on the velvet surface and back of the silicon wafer using the atomic deposition method. The passivation layer is Al2O3 with a thickness of 5nm. An anti-reflection film is deposited on the passivation layer using the PECVD method. The anti-reflection film is a silicon nitride thin film layer with a thickness of 150nm.

[0077] Step 10: First, use Ag paste to print a 10μm wide metal grid line in the local groove area on the back of the TOPCon solar cell, then sinter it at 780℃ for 60s; then perform light injection under a light intensity of 20s and a light duration of 20s.

[0078] Example 3

[0079] A TOPCon solar cell comprises an N-type silicon substrate, a velvet surface, a boron diffusion layer, a front passivation layer, and a front anti-reflection film layer sequentially arranged on the front side of the substrate from the inside out, an insulating layer having multiple grooved regions sequentially arranged on the back side of the substrate from the inside out, a tunneling oxide layer, a polysilicon layer, a PN junction, a back passivation layer, a back anti-reflection film layer, and an Ag electrode arranged in the grooved region; the front passivation layer has a thickness of 1 nm, the front anti-reflection film layer has a thickness of 50 nm, the grooved region has a width of 500 μm, the tunneling oxide layer has a thickness of 1.5 nm, the polysilicon layer has a thickness of 50 nm, the Al2O3 back passivation layer has a thickness of 1 nm, the silicon nitride back anti-reflection film layer has a thickness of 50 nm, and the Ag electrode has a width of 40 μm; the insulating layer is a single layer of SiNx with a thickness of 80 nm.

[0080] The preparation method of the TOPCon battery comprises the following steps:

[0081] Step 1: Clean the N-type silicon substrate with a thickness of 150 μm and texturize the front side with NaOH solution;

[0082] Step 2: Use BCl3 thermal diffusion method to diffuse boron into the textured surface. The diffusion temperature is 950~1000℃ and the sheet resistance is ;

[0083] Step 3: After removing the borosilicate glass layer on the back of the silicon wafer with an HF solution, the back of the silicon substrate is alkaline polished with a NaOH solution and a polishing additive, and then rinsed with pure water after polishing;

[0084] Step 4: Deposit an insulating layer on the back of the alkali-polished silicon substrate using a CVD method. The insulating layer 6 is a single layer of SiNx with a thickness of 80 nm.

[0085] Step 5: Using a laser with a wavelength of 355 nm, a frequency of 100 kHz, a scanning speed of 35 m / s, and a spot size of 15 μm, the insulating layer is partially grooved to remove part of the insulating layer. The number of local grooves is the same as the number of back electrodes, and the width W1 of the groove area is 500 μm. The local groove area is then cleaned with HF.

[0086] Step 6: Depositing a tunnel oxide layer and a polysilicon layer in the local grooved area in sequence by sputtering, wherein the thickness of the tunnel oxide layer is 1.5 nm and the thickness of the polysilicon layer is 50 nm;

[0087] Step 7: Phosphorus diffusion is performed on the polysilicon layer using POCl3 vapor at 800°C, and rapid annealing (10s) is performed at 900°C to activate the dopant. Laser-induced doping is used in the groove area with an energy density of 1.8 J / cm² and a phosphorus doping concentration of 5×10 20 atoms / cm³, the phosphorus doping concentration in the non-groove area is 5×10 19 atom / cm³;

[0088] Step 8: Use HF solution to remove the phosphosilicate glass layer on the back and sides of the silicon wafer, and remove the borosilicate glass layer and insulating layer on the front of the silicon wafer;

[0089] Step 9: A passivation layer is deposited on the velvet surface and back of the silicon wafer using the atomic deposition method. The passivation layer is Al2O3 with a thickness of 1nm. An anti-reflection film is deposited on the passivation layer using the PECVD method. The anti-reflection film is a silicon nitride thin film layer with a thickness of 50nm.

[0090] Step 10: First, use Ag paste to print a 40μm wide metal grid line in the local groove area on the back of the TOPCon solar cell, then sinter it at 850℃ for 20s; then perform light injection under a light intensity of 40sun and a light duration of 10s.

[0091] Example 4

[0092] The structure and preparation method of the TOPCon solar cell in this embodiment are basically the same as those in Example 1, except that the insulating layer is 2 nm thick. Stacked with 80nm SiNx, the laser grooving wavelength is 532nm and the frequency is 120kHz; the width of the grooving area is 80μm and the metal electrode width is 25μm.

[0093] Example 5

[0094] The structure and preparation method of the TOPCon solar cell in this embodiment are basically the same as those in Example 1. The difference is that the insulating layer is composed of 5nm Al2O3 and 50nm SiN x The laser grooving wavelength is 355nm and the frequency is 80kHz. The width of the grooving area is 800μm and the width of the metal electrode is 40μm.

[0095] Comparative Example 1

[0096] Compared with embodiment 1, the difference is that the back insulating layer is fully covered.

[0097] The TOPCon cells prepared in Examples 1-5 and Comparative Example 1 were tested for performance, specifically the cell conversion efficiency (Eta), open-circuit voltage (Uoc), current (Isc), and fill factor (FF). Eta (efficiency) represents the ratio of solar energy converted to electrical energy by the cell. The test results are shown in Table 1.

[0098] Table 1

[0099]

[0100] The test results comparing Examples 1-5 and Comparative Example 1 in Table 1 demonstrate that the process employed by the present invention, which deposits an insulating layer on the backside of the silicon wafer, performs localized grooves, and forms a tunneling oxide layer, polysilicon layer, and printed electrodes in the grooved areas, significantly improves the cell conversion efficiency of TOPCcon cells. Compared to the conventional process in Comparative Example 1, the average cell conversion efficiency of Examples 1-5 increased by 0.2%. This is attributed to the fact that the present invention retains passivation in the non-contact area. By depositing a dense insulating layer on the ungrooved area of the backside of the silicon wafer, it effectively passivates the dangling bonds on the silicon wafer surface, isolating them from the outside world and significantly reducing the surface state density. This reduces the probability of carrier recombination at the surface, potentially improving cell efficiency. Furthermore, the tunneling oxide layer and polysilicon layer are formed in the grooved areas along the carrier transmission path, creating an orderly "contact-non-contact" distribution. The tunneling oxide layer is extremely thin, allowing carriers to pass through it via quantum tunneling and enter the polysilicon layer. The polysilicon layer has good electrical conductivity and provides an efficient transmission channel for carriers. The insulating layer in the ungrooved area prevents the disordered diffusion of carriers and guides them to be directionally transmitted along the tunneling oxide layer and polysilicon layer in the grooved area, avoiding the loss of carriers in non-essential areas, allowing carriers to converge more efficiently at the electrodes, thereby improving the carrier collection efficiency. In addition, the present invention reduces the contact area between the metal and the silicon wafer by limiting the preparation of the electrode to the grooved area, reduces the contamination of the silicon wafer by metal impurities, and also avoids the lattice distortion caused by large-area contact, further suppressing the recombination of carriers. This effectively improves the battery conversion rate.

[0101] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in this field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a TOPCon solar cell, characterized in that: include: (1) Take an N-type silicon wafer and perform front surface texturing; (2) Boron diffusion on the textured surface; (3) After removing the borosilicate glass layer on the back and sides of the silicon wafer, polishing the back; (4) Depositing an insulating layer on the polished back surface; (5) Locally groove the insulating layer using a laser, and then clean the silicon wafer to remove the damaged layer and the side insulating layer in the grooved area; (6) In-situ treatment of the silicon backside using hydrogen plasma, followed by sequential deposition of a tunneling oxide layer and a polysilicon layer; (7) diffusing phosphorus in the polysilicon layer; (8) removing the phosphosilicate glass layer on the back and side surfaces of the silicon wafer, and removing the insulating layer and borosilicate glass layer on the front surface; (9) depositing a passivation layer and an anti-reflection film layer on the back side of the silicon wafer in sequence; (10) Screen printing electrodes in the local grooved area.

2. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The width of the groove area is 50-800 μm, the side wall roughness is less than 10 nm, and the width of the electrode is 10-40 μm.

3. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The local grooving is performed by laser grooving, with a laser wavelength of 300-600 nm, a laser power of 40-50 W, a scanning speed of 35 m / s, and a spot size of 100-400 μm.

4. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The insulating layer is one of silicon oxide, aluminum oxide and silicon nitride, and the thickness of the insulating layer is 10-200 nm.

5. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: After the local grooving, the grooving area is cleaned with a mixed acid of HF and HNO3.

6. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The thickness of the tunnel oxide layer is 1-2 nm, and the thickness of the polysilicon layer is 60-200 nm.

7. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The passivation layer is an Al2O3 passivation layer deposited by atomic deposition method, with a thickness of 1-5 nm.

8. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The anti-reflection film layer is a silicon nitride thin film layer deposited by PECVD method, with a thickness of 50-150nm.

9. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: After the screen printing of the electrodes, sintering and light injection treatments are performed.

10. A TOPCon solar cell, characterized in that: The TOPCon solar cell is prepared by the preparation method according to any one of claims 1 to 9.

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