A Deep Learning-Based VLSI Circuit Layout Optimization Method and System

Abstract

This invention discloses a deep learning-based VLSI circuit layout optimization method and system in the field of integrated circuit technology. The method includes the following steps: abstracting a large-scale integrated circuit into a hypergraph structure; receiving the hypergraph structure; generating a node embedding matrix using a hypergraph neural network; optimizing the segmentation loss function through unsupervised training to obtain a probability distribution matrix; determining the segmented subsets based on the probability distribution matrix; mapping each subset to a physical layout unit; generating the physical region layout of the chip according to area balance constraints and timing constraints; providing constraint feedback on the physical layout results; and dynamically adjusting the parameters of the segmentation loss function until all physical constraints are met. This invention can be used for the layout of very large-scale integrated circuits, providing an optimization method and means for providing high-quality VLSI circuit layout solutions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a VLSI circuit layout optimization method and system based on deep learning. Background Technology

[0002] As semiconductor processes move into the nanoscale, the design complexity of very large-scale integrated circuits (VLSI) is increasing exponentially. Circuit layout, as a key aspect of physical design, directly affects the timing convergence, power efficiency, and manufacturing cost of chips.

[0003] Current VLSI circuit placement methods abstract large-scale integrated circuits into a hypergraph structure, where vertices represent logic units, logic gates, registers, input / output ports, etc., and hyperedges represent the electrical connections between multiple logic units. Based on hypergraph modeling, existing placement methods employ hypergraph partitioning algorithms, aiming to divide the VLSI circuit into multiple sub-modules while minimizing the number of cut edges, thereby reducing the increased latency and routing complexity caused by cross-module transmission. The result of the hypergraph partitioning algorithm is the primary basis for circuit placement. As a core step in the VLSI circuit placement process, current hypergraph partitioning techniques mainly employ a multi-level heuristic algorithm. This multi-level heuristic hypergraph partitioning algorithm reduces the number of cut edges between blocks after placement through an iterative process of coarsening-initial partitioning-refining. However, at advanced process nodes, the surge in circuit size, the increased proportion of multi-pin hyperedges, and the superposition of complex physical constraints make traditional heuristic algorithms prone to getting trapped in local optima when dealing with VLSI circuits with complex hypergraph structures. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] Therefore, the purpose of this invention is to provide a VLSI circuit layout optimization method and system based on deep learning to solve the problems mentioned in the background art.

[0006] To address the aforementioned technical problems, according to one aspect of the present invention, the present invention provides the following technical solution:

[0007] A deep learning-based VLSI circuit layout optimization method, the steps of which are as follows:

[0008] S1. Abstracting large-scale integrated circuits into a hypergraph structure. Among them, hypergraph structure It includes a set of nodes V and a set of superedges E. The set of nodes V corresponds to the logic units, registers and input / output ports in the circuit, and the set of superedges E represents the electrical connection relationship between multiple nodes.

[0009] S2, Receiver Hypergraph Structure The node embedding matrix is ​​generated using a hypergraph neural network (HGNN), and the segmentation loss function is optimized through unsupervised training, resulting in the node set V being divided into n subsets. The probability distribution matrix X;

[0010] S3. Determine the segmented subsets based on the probability distribution matrix X, and map each subset to a physical layout unit. Generate the physical region layout of the chip according to the area balance constraint and timing constraint.

[0011] S4. Perform constraint feedback on the physical layout results and dynamically adjust the parameters of the segmentation loss function until all physical constraints are met.

[0012] As a preferred embodiment of the deep learning-based VLSI circuit layout optimization method described in this invention, in step S2, the loss function includes a hyperedge cutting loss term and a balance constraint term, specifically expressed as follows: ;

[0013] Among them, the super-edge cutting loss term The normalized cross-partition superedge number loss is calculated as follows:

[0014] ;

[0015] in, This indicates that for each superedge The cutting loss is normalized to prevent large hyperedges from dominating the loss function. The average contribution of each node is amortized, making the penalties for hyperedges of different sizes comparable.

[0016] Indicates statistical superedge The sum of the probabilities of all nodes being assigned to different partitions. It is a node The one-hot encoded vector;

[0017] Represented as a measure Whether to stay in the same partition is determined by element-wise multiplication of the dimensions of each partition using the Hadamard product. If all nodes are assigned to the same partition k, the product is 1; otherwise, it is 0.

[0018] Balance constraints The variance loss for the number of nodes in each subset is calculated as follows:

[0019] ;

[0020] Where |Pk| represents the actual number of nodes in the k-th partition, i.e., the number of logic units, and |v| represents the total number of nodes. In the VLSI domain, |v| represents the total number of logic units in the circuit.

[0021] As a preferred embodiment of the deep learning-based VLSI circuit layout optimization method described in this invention, the Hypergraph Neural Network (HGNN) employs a multi-layer convolutional structure. The layer convolution operation is defined as:

[0022]

[0023] in, and These are diagonal matrices representing the degree of nodes and the degree of hyperedges, respectively. H For the hypergraph incidence matrix, The `diag()` function represents the weight of the hyperedge, constructing a diagonal matrix where only the main diagonal elements are non-zero, and the remaining elements are 0. Indicates the superedge The number of nodes included. Indicates the first Layer model parameters.

[0024] As a preferred embodiment of the deep learning-based VLSI circuit layout optimization method described in this invention, the embedding matrix output by the hypergraph neural network is converted into a probability distribution matrix X through the Softmax function.

[0025] As a preferred embodiment of the deep learning-based VLSI circuit layout optimization method described in this invention, in step S3, the physical layout unit increases the weight parameter during layout. Strengthen the penalty for slicing across high-speed buses in different partitions, and balance the distribution of high-power modules by adjusting the weight parameter β.

[0026] In a preferred embodiment of the deep learning-based VLSI circuit layout optimization method described in this invention, step S4 includes constraint feedback that includes detecting abnormal heat distribution or wiring congestion, and dynamically adjusting parameters based on the detection results. The values ​​of β and β.

[0027] A deep learning-based VLSI circuit layout optimization system, comprising:

[0028] Hypergraph modeling unit, used to abstract large-scale integrated circuits into a hypergraph structure. Generate a node set V, a hyperedge set E, and an association matrix H;

[0029] The hypergraph segmentation unit, including the hypergraph neural network, is used to learn the node embedding matrix and optimize the segmentation loss function, and outputs the probability distribution matrix X of node partitioning;

[0030] Physical layout units are used to map the partitioned subsets to chip physical regions and integrate area constraints and timing constraints.

[0031] A constraint feedback unit is used to detect layout violations and adjust the parameters of the segmentation loss function.

[0032] As a preferred embodiment of the deep learning-based VLSI circuit layout optimization system described in this invention, the hypergraph segmentation unit includes a hypergraph embedding module and a hypergraph partitioning module.

[0033] The hypergraph embedding module uses a hypergraph neural network structure to learn the embedding matrix of a hypergraph, given a hypergraph. and the correlation matrix Randomly generate node feature matrix And input it into the hypergraph neural network to obtain the node embedding matrix. Then, the nodes are embedded into the matrix using the softmax function. Transform into a probability distribution matrix ;

[0034] The hypergraph partitioning module optimizes the segmentation loss function and trains the probability distribution matrix through unsupervised training. Convergence occurs, resulting in the node set V being divided into n subsets. The probability distribution matrix X.

[0035] Compared with existing technologies, the advantages of this invention are as follows: This invention partitions VLSI circuits using an end-to-end hypergraph neural network architecture, incorporating the collaborative optimization of partitioning and placement into a unified framework, thus avoiding redundant computations from multiple iterations in traditional methods. This integrated process fully demonstrates the advantages of this invention across the entire VLSI design chain: the minimum cut objective in the partitioning stage reduces the routing complexity in the placement stage, while the physical constraints of placement feedback (such as heat distribution and congestion hotspots) enhance the generalization ability of the partitioning model, ultimately significantly shortening the chip design cycle while ensuring timing convergence. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0037] Figure 1 This is a system block diagram of a VLSI circuit layout optimization system based on deep learning according to the present invention.

[0038] Figure 2 This is a flowchart of a deep learning-based VLSI circuit layout optimization system according to the present invention. Detailed Implementation

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] This invention proposes a deep learning-based VLSI circuit placement optimization system to provide a solution to the hypergraph segmentation problem with fewer cut edges and better balance in large-scale integrated circuit design scenarios. The deep learning-based VLSI circuit placement optimization system of this invention consists of four units: a hypergraph modeling unit, a hypergraph segmentation unit, a physical placement unit, and a constraint feedback unit.

[0041] like Figure 1 As shown, the flow of this deep learning-based VLSI circuit layout optimization system is described as follows: It begins with two input nodes in the upper left corner: "Circuit Data" and "Physical Constraints." Both serve as the starting point for the design. "Circuit Data" contains raw information such as gate-level netlists and process library parameters, while "Physical Constraints" covers manufacturing requirements such as area thresholds and wiring density rules. Both first enter the "Hypergraph Construction" module of the hypergraph modeling unit, mapping logic gates in the circuit to hypergraph nodes and multi-pin networks (such as clock signal lines) to hyperedges, forming the initial hypergraph topology. The flow then enters the "Hypergraph Attributes" module, generating an association matrix H, a node degree matrix, and a hyperedge degree matrix, providing structured input for subsequent neural network processing.

[0042] The core component of the process is the hypergraph segmentation unit, which utilizes its "HGNN" (Hypergraph Embedding) and "Hypergraph Partitioning" modules. Here, the Hypergraph Neural Network (HGNN) learns node embeddings through multiple convolutional operations, progressively mapping the node feature matrix into a probability distribution matrix. This represents the probability that each logic gate belongs to a different subgraph. During the partitioning phase, the algorithm generates multiple "subgraphs" by optimizing the edge-cutting loss (minimizing the number of cross-partition hyperedges) and balance constraints (balancing subgraph size). These subgraphs are passed to the "physical placement" unit, which maps the partitioning results to physical regions on the chip plane. Then, through "constraint feedback," the violation information (abnormal heat distribution) detected during the placement phase is passed back to the hypergraph partitioning module of the hypergraph segmentation unit, adjusting the hyperparameters in the loss function. (e.g., increasing the cutting penalty coefficient for critical superedges) and Adjustments are then made. Finally, a comprehensive evaluation is conducted through "violation detection" to determine whether the layout meets all physical constraints. If violations are found, a feedback loop is triggered until a solution that conforms to the manufacturing rules is output.

[0043] The entire process, through an end-to-end architecture design, achieves a seamless connection from circuit description to physical implementation. Meanwhile, the efficient matrix operations in the hypergraph attributeization stage lay the foundation for subsequent GPU acceleration.

[0044] The following is combined with Figures 1-2 The present invention provides a detailed description of the hypergraph modeling unit, hypergraph segmentation unit, physical layout unit, and constraint feedback unit.

[0045] The hypergraph modeling unit maps VLSI circuits to hypergraph structures. Its input data needs to obtain the following information from the original circuit: gate-level netlist (the circuit topology basis describing logic gates, standard cells and their connection relationships), physical constraints (such as layout constraints such as fixed-position I / O ports and macrocells, partition area thresholds, wiring layer density rules, etc.), and process library information (providing process parameters such as area, power consumption, and drive capability of standard cells). These three types of data together define the physical structure, design rules and cell characteristics of the circuit, providing underlying support for hypergraph modeling.

[0046] In hypergraph modeling, VLSI circuits are abstracted into a structured representation of nodes and hyperedges: nodes correspond to physical modules such as logic units, logic gates, registers, and input / output ports; hyperedges correspond to electrical networks. This modeling transforms circuit entities and their connections into a hypergraph structure. Subsequent hypergraph segmentation units input this hypergraph structure into a hypergraph neural network for hypergraph segmentation.

[0047] The task of the hypergraph segmentation unit is to segment the hypergraph structure output by the hypergraph modeling unit and ensure that the segmentation algorithm optimizes manufacturing costs while satisfying practical process constraints (such as area balance and time convergence). The hypergraph segmentation unit has three inputs: the hypergraph structure... ; predefined node sets Disjoint subsets Number of Similar to the Hypergraph Neural Network (HGNN), the implementation process of the hypergraph segmentation unit in this invention consists of two steps: hypergraph embedding and hypergraph partitioning. In the first step, hypergraph embedding, the hypergraph structure is... The input is fed into a hypergraph neural network (HGNN), and the HGNN output indicates which node belongs to which network? probability distribution matrix In the second step of hypergraph partitioning, the loss function representing the number of cut edges in the hypergraph, as proposed in this patent, is optimized by training an HGNN, so that... The solution eventually converges to an approximate solution to the hypergraph partitioning problem. The partitioned... Each sub-graph is the input to the physical layout. The physical layout unit maps the logical partitioning result to physical regions on the chip plane.

[0048] like Figure 2 As shown, the hypergraph segmentation unit is divided into a hypergraph embedding module and a hypergraph partitioning module. These two parts will be described in detail below.

[0049] Hypergraph Embedding Module: A Hypergraph , is defined as a series of nodes and a series of hyper-edges , where each superedge yes A subset, a hypergraph It can be represented as an index matrix , among which when hour, ,otherwise First, randomly generate the node feature matrix. It is then input into a hypergraph neural network to output a node embedding matrix. ,Right now Each node belongs to The probability distribution matrix.

[0050] Specifically, the hypergraph embedding submodule uses a hypergraph neural network structure to learn the embedding matrix of the hypergraph, given a hypergraph. and the correlation matrix Randomly generate node feature matrix And input it into the hypergraph neural network to obtain the node embedding matrix, the hypergraph neural network's first... The construction of the convolutional layers is shown below:

[0051] (1)

[0052] The hypergraph embedding module uses graph structures to learn the node embedding matrix and generates the node embedding matrix using softmax. probability distribution matrix In the model The A row can represent each node Belongs to block The probability of.

[0053] in, It is the first The embedding matrix generated by the convolutional layers, It is a non-linear activation function, such as ReLU, for a vertex Its degree is defined as Similarly, the edge The degree is defined as . and A diagonal matrix used to represent vertex degree and edge degree respectively. The `diag()` function represents the weight of the hyperedge, constructing a diagonal matrix where only the main diagonal elements are non-zero, and the remaining elements are 0. Indicates the superedge The number of nodes included. Indicates the first Layer model parameters, Indicates model parameters.

[0054] Will After being input into the aforementioned hypergraph neural network, the output matrix is ​​processed by the softmax function. Transform into a probability distribution matrix, generate a probability matrix .

[0055] Hypergraph Partitioning Module: Input the hypergraph partitioning module, train it using the loss function defined by the hypergraph partitioning module, and enable it to... convergence.

[0056] The definition of the hypergraph partitioning problem is: given a hypergraph The aim is to combine the node set Divide into disjoint subsets The number of nodes in these subsets should be as similar as possible, while minimizing the number of cut edges (cut edges are defined as super edges that span multiple partitioned subgraphs).

[0057] because But in reality The values ​​of the elements in the middle are between 0 and 1, that is... Therefore, the following loss function is defined, which consists of two parts: the hyperedge cutting loss and the balance constraint. The hyperedge cutting loss is determined by the weight parameters. Weighted polynomial terms The number of cross-partition hyperedges is measured to force highly connected nodes to be assigned to the same partition to reduce routing delay. Balance constraints are implemented using weighted parameters. Weighted variance form Directly through the allocation matrix The columns and the expected value of the number of partition nodes are calculated, and then minimized. This forces nodes within the same hyperedge to be assigned to the same block. Ultimately, the partitioned result is n sub-hypergraphs, which correspond to the partitioned sub-circuit modules.

[0058] The loss function is: (2)

[0059] in Indicates the number of cut edges:

[0060] (3)

[0061] Normalization term: For each superedge The cutting loss is normalized to prevent large hyperedges (with a large number of nodes) from dominating the loss function. The average contribution of each node is amortized, making the penalties for hyperedges of different sizes comparable.

[0062] Summation term: Statistical hyperedge The sum of the probabilities of all nodes being assigned to each partition. It is a node The one-hot encoded vector.

[0063] Polynomial terms: measure Whether to remain in the same partition. The Hadamard product is used to perform element-wise product of the dimensions of each partition. If all nodes are assigned to the same partition k, the product is 1; otherwise, it is 0.

[0064] Difference: The degree of cutting of the hyperedge is quantified by the difference between the summation term and the polynomial. Ideally, all nodes are in the same partition and the difference is 0, so no penalty is generated. If the difference is greater than 0, it means that multiple nodes are not in the same partition, and a positive penalty is generated.

[0065] Balance constraints:

[0066] (4)

[0067] Where |Pk| represents the actual number of nodes in the k-th partition, i.e., the number of logic units, and |v| represents the total number of nodes. In the VLSI domain, |v| represents the total number of logic units in the circuit.

[0068] This loss function makes the trained probability matrix... Convergence, the probability matrix obtained after convergence This means Each node belongs to The probability of this is the solution to the hypergraph partitioning problem.

[0069] The loss function consists of two parts: the hyperedge cutting loss and the balance constraint. The hyperedge cutting loss is determined by... Weighted polynomial terms The number of cross-partition hyperedges is measured to force highly connected nodes to be assigned to the same partition to reduce routing delays. Balance constraints are employed. Weighted variance form Directly through the allocation matrix The columns and the expected value of the number of partition nodes are calculated, and then minimized. This forces nodes within the same hyperedge to be assigned to the same block. Ultimately, the partitioned result is n sub-hypergraphs, which correspond to the partitioned sub-circuit modules.

[0070] The physical placement unit receives the partitioning results from the hypergraph partitioning unit and completes the physical placement, forming a complete design chain from hypergraph modeling and VLSI circuit partitioning to physical placement. In the physical placement stage, the partitioned sub-modules... These are mapped to physical regions on the chip plane. The area of ​​each submodule is calculated based on process library parameters (such as logic gate area) to ensure compliance with area threshold constraints in manufacturing rules. For I / O ports and macrocells in fixed locations, the algorithm uses them as placement anchors to constrain the placement range of adjacent submodules, avoiding re-partitioning due to location conflicts.

[0071] Layout strategies adjust parameters (Segmentation loss weighting) penalizes cross-partition superedges (such as high-speed buses and multi-pin interconnects), forcing highly interconnected modules to be clustered together, reducing wiring length and signal delay; by adjusting parameters This forces a balanced area distribution across all zones, preventing overheating issues caused by excessive concentration of high-power modules. The two mechanisms work together to balance performance, power consumption, and heat distribution, ultimately achieving a multi-objective optimized physical layout design. For example, high... The value will bundle the CPU with the nearest memory controller to reduce bus slicing, while high This value forces high-power clusters to disperse in order to equalize chip temperature.

[0072] Although the present invention has been described above with reference to embodiments, various modifications can be made and components can be replaced with equivalents without departing from the scope of the invention. In particular, as long as there is no structural conflict, the features in the disclosed embodiments can be combined with each other in any manner. The lack of an exhaustive description of these combinations in this specification is merely for the sake of brevity and resource conservation. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A VLSI circuit layout optimization method based on deep learning, characterized in that, The steps are as follows: S1. Abstracting large-scale integrated circuits into a hypergraph structure. Among them, hypergraph structure It includes a set of nodes V and a set of superedges E. The set of nodes V corresponds to the logic units, registers and input / output ports in the circuit, and the set of superedges E represents the electrical connection relationship between multiple nodes. S2, Receiver Hypergraph Structure The node embedding matrix is ​​generated using a hypergraph neural network (HGNN), and the segmentation loss function is optimized through unsupervised training, resulting in the node set V being divided into n subsets. The probability distribution matrix X; S3. Determine the segmented subsets based on the probability distribution matrix X, and map each subset to a physical layout unit. Generate the physical region layout of the chip according to the area balance constraint and timing constraint. S4. Perform constraint feedback on the physical layout results and dynamically adjust the parameters of the segmentation loss function until all physical constraints are met. In step S2, the loss function includes a hyperedge cutting loss term and a balance constraint term, specifically expressed as follows: ; Among them, the super-edge cutting loss term The normalized cross-partition superedge number loss is calculated as follows: ； in, This indicates that for each superedge The cutting loss is normalized to avoid large hyperedges dominating the loss function; the average contribution of each node is amortized, making the penalties for hyperedges of different sizes comparable; Indicates statistical superedge The sum of the probabilities of all nodes being assigned to different partitions. It is a node The one-hot encoded vector; Represented as a measure Whether to stay in the same partition is determined by element-wise multiplication of the dimensions of each partition using the Hadamard product. If all nodes are assigned to the same partition k, the product is 1; otherwise, it is 0. Balance constraints The variance loss for the number of nodes in each subset is calculated as follows: ； Where |Pk| represents the actual number of nodes in the k-th partition, i.e., the number of logic units, and |v| represents the total number of nodes. In the VLSI domain, |v| represents the total number of logic units in the circuit. In step S3, the physical layout unit increases the weight parameter during layout. Strengthen the penalty for cutting across high-speed buses in different partitions, and balance the distribution of high-power modules by adjusting the weight parameter β; In step S4, constraint feedback includes detecting abnormal heat distribution or wiring congestion, and dynamically adjusting parameters based on the detection results. The values ​​of β and β.

2. The VLSI circuit layout optimization method based on deep learning according to claim 1, characterized in that, The hypergraph neural network HGNN employs a multi-layer convolutional structure, the first... The layer convolution operation is defined as: ； in, and These are diagonal matrices representing the degree of nodes and the degree of hyperedges, respectively. H For the hypergraph incidence matrix, The `diag()` function represents the weight of the hyperedge, constructing a diagonal matrix where only the main diagonal elements are non-zero, and the remaining elements are 0. Indicates the superedge The number of nodes included. Indicates the first Layer model parameters.

3. The VLSI circuit layout optimization method based on deep learning according to claim 2, characterized in that, The embedding matrix output by the hypergraph neural network is converted into a probability distribution matrix X using the Softmax function.

4. A VLSI circuit layout optimization system based on deep learning, characterized in that, include: Hypergraph modeling unit, used to abstract large-scale integrated circuits into a hypergraph structure. Among them, hypergraph structure It includes a set of nodes V and a set of superedges E. The set of nodes V corresponds to the logic units, registers and input / output ports in the circuit, and the set of superedges E represents the electrical connection relationship between multiple nodes. Hypergraph segmentation unit, including a hypergraph neural network, is used to receive the hypergraph structure. The node embedding matrix is ​​generated using a hypergraph neural network (HGNN), and the segmentation loss function is optimized through unsupervised training, resulting in the node set V being divided into n subsets. The probability distribution matrix X is given by the loss function, which includes a hyperedge cutting loss term and a balance constraint term, specifically expressed as follows: ; Among them, the super-edge cutting loss term The normalized cross-partition superedge number loss is calculated as follows: ； in, This indicates that for each superedge The cutting loss is normalized to avoid large hyperedges dominating the loss function; the average contribution of each node is amortized, making the penalties for hyperedges of different sizes comparable; Indicates statistical superedge The sum of the probabilities of all nodes being assigned to different partitions. It is a node The one-hot encoded vector; Represented as a measure Whether to stay in the same partition is determined by element-wise multiplication of the dimensions of each partition using the Hadamard product. If all nodes are assigned to the same partition k, the product is 1; otherwise, it is 0. Balance constraints The variance loss for the number of nodes in each subset is calculated as follows: ； Where |Pk| represents the actual number of nodes in the k-th partition, i.e., the number of logic units, and |v| represents the total number of nodes. In the VLSI domain, |v| represents the total number of logic units in the circuit. The physical layout unit determines the segmented subsets based on the probability distribution matrix X, maps each subset to a physical layout unit, and generates the physical region layout of the chip according to area balance constraints and timing constraints. The physical layout unit increases the weighting parameters during the layout process. Strengthen the penalty for cutting across high-speed buses in different partitions, and balance the distribution of high-power modules by adjusting the weight parameter β; The constraint feedback unit is used to provide constraint feedback on the physical layout results, dynamically adjusting the parameters of the segmentation loss function until all physical constraints are met. The constraint feedback includes detecting abnormal heat distribution or wiring congestion, and dynamically adjusting the parameters based on the detection results. The values ​​of β and β.

5. The VLSI circuit layout optimization system based on deep learning according to claim 4, characterized in that, The hypergraph segmentation unit includes a hypergraph embedding module and a hypergraph partitioning module; The hypergraph embedding module uses a hypergraph neural network structure to learn the embedding matrix of a hypergraph, given a hypergraph. and the correlation matrix Randomly generate node feature matrix And input it into the hypergraph neural network to obtain the node embedding matrix. Then, the nodes are embedded into the matrix using the softmax function. Transform into a probability distribution matrix ; The hypergraph partitioning module optimizes the segmentation loss function and trains the probability distribution matrix through unsupervised training. Convergence occurs, resulting in the node set V being divided into n subsets. The probability distribution matrix X.

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