Semiconductor memory device and memory system including same

Abstract

A semiconductor memory device includes: a memory cell array including a first memory cell group; a first parallel bit test circuit configured to output a first fail signal based on each of a plurality of memory cells included in the first memory cell group being defective, and outputs a first pass signal based on at least one of the plurality of memory cells included in the first memory cell group having no defect; and a first latch circuit configured to selectively latch an output of the first parallel bit test circuit. The first latch circuit is configured to latch an output of the first parallel bit test circuit in response to the first parallel bit test circuit outputting the first pass signal. The plurality of memory cells included in the first memory cell group are respectively connected to different word lines and to the same bit line.

Description

Technical Field

[0001] One or more example embodiments of the present disclosure relate to a semiconductor memory device and a memory system including the same. Background Art

[0002] Semiconductor memory devices can be divided into non-volatile memory devices such as flash memory and volatile memory devices such as dynamic random access memory (DRAM). Due to their relatively low price, volatile memory devices such as DRAM can be used to store large amounts of data (e.g., system memory). The memory cell array of a DRAM may include multiple word lines and multiple bit lines, and memory cells may be formed at the intersection of the word lines and bit lines.

[0003] As DRAM capacities increase, built-in parallel bit testing within the DRAM is being implemented to reduce testing time. While it is possible to determine whether each DRAM memory cell is defective using parallel bit testing, the yield rate of DRAM chip production may decrease as single-bit defects increase. Therefore, a non-single-bit defect determination method is needed that excludes single-bit defects and only determines a word line or bit line as defective when multiple memory cells connected to the corresponding word line or bit line are determined to be defective. Summary of the Invention

[0004] One or more example embodiments of the present disclosure provide a semiconductor memory device in which non-single-bit defects can be screened.

[0005] One or more example embodiments of the present disclosure provide a memory system capable of screening a semiconductor memory device for non-single-bit defects.

[0006] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] According to one aspect of an example embodiment of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device including: a memory cell array, the memory cell array including a first memory cell group; a first parallel bit test circuit, the first parallel bit test circuit configured to determine whether each of a plurality of memory cells included in the first memory cell group is defective, the first parallel bit test circuit configured to output a first fail signal based on each of the plurality of memory cells included in the first memory cell group being defective, and configured to output a first pass signal based on at least one of the plurality of memory cells included in the first memory cell group being non-defective; and a first latch circuit configured to selectively latch an output of the first parallel bit test circuit, wherein the first latch circuit is configured to latch the output of the first parallel bit test circuit in response to the first parallel bit test circuit outputting the first pass signal, wherein the plurality of memory cells included in the first memory cell group are each connected to a different word line, and wherein the plurality of memory cells included in the first memory cell group are connected to the same bit line.

[0008] According to one aspect of an example embodiment of the present disclosure, a semiconductor memory device is provided, comprising: a memory cell array including a memory cell group; a parallel bit test circuit configured to determine whether each of a plurality of memory cells included in the memory cell group is defective, output a fail signal based on the fact that each of the plurality of memory cells included in the memory cell group is defective, and output a pass signal based on the fact that at least one of the plurality of memory cells included in the memory cell group is not defective; and a latch circuit configured to selectively latch an output of the parallel bit test circuit, wherein the latch circuit is configured to latch the output of the parallel bit test circuit in response to the parallel bit test circuit outputting the pass signal, wherein the plurality of memory cells included in the memory cell group are respectively connected to different bit lines, and wherein the plurality of memory cells included in the memory cell group are connected to the same word line.

[0009] According to one aspect of an example embodiment of the present disclosure, a memory system is provided, the memory system including: a semiconductor memory device; a test device configured to test the semiconductor memory device; and a memory controller configured to control operation of the semiconductor memory device, wherein the semiconductor memory device includes a memory cell array, the memory cell array including a plurality of memory cells; a parallel bit test circuit configured to determine whether each of the plurality of memory cells is defective, the parallel bit test circuit configured to output a fail signal based on each of the plurality of memory cells being defective, and configured to output a pass signal based on at least one of the plurality of memory cells being non-defective; and a latch circuit configured to selectively latch an output of the parallel bit test circuit, wherein the latch circuit is configured to latch the output of the parallel bit test circuit in response to the parallel bit test circuit outputting the pass signal, wherein the plurality of memory cells are respectively connected to different word lines, and wherein the plurality of memory cells are connected to the same bit line.

[0010] It should be noted that the effects of the present disclosure are not limited to the above-described effects, and other effects of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a diagram illustrating a memory system according to some example embodiments.

[0012] Figure 2 is a diagram illustrating a schematic configuration of a memory system according to some example embodiments.

[0013] Figure 3 is a diagram illustrating a schematic configuration of a memory system according to some example embodiments.

[0014] Figure 4 It shows Figures 1 to 3 A diagram showing the configuration of a semiconductor memory device.

[0015] Figure 5 It shows Figure 4 A diagram of an example of a memory cell in a semiconductor memory device.

[0016] Figure 6 It shows Figure 4 An exemplary diagram of a portion of a semiconductor memory device.

[0017] Figure 7 is a diagram illustrating a method according to some example embodiments Figure 6 Diagram of the data control circuit.

[0018] Figure 8 It shows Figure 7 A diagram of the configuration of one of the unit control circuits in the data control circuit.

[0019] Figure 9 It shows Figure 7 An example diagram of a latch circuit.

[0020] Figure 10 is an example diagram of a latch circuit according to some other example embodiments.

[0021] Figure 11 and Figure 12 are diagrams for describing operations of a semiconductor memory device according to some example embodiments.

[0022] Figure 13 and Figure 14 are diagrams for describing operations of a semiconductor memory device according to some other example embodiments.

[0023] Figure 15 is a diagram illustrating bit lines that are subjects of a parallel bit test according to some example embodiments.

[0024] Figure 16 is a diagram illustrating storage in accordance with some example embodiments Figure 15 A timing diagram of a read operation of the test pattern data in the memory cell.

[0025] Figure 17 is a structural diagram illustrating a semiconductor memory device according to some example embodiments.

[0026] Figure 18 is a diagram illustrating a memory system to which a semiconductor memory device is applied according to some example embodiments.

[0027] Figure 19 is a diagram illustrating a computing system equipped with a semiconductor memory device according to some example embodiments.

[0028] Figure 20 is a block diagram illustrating an example of applying a semiconductor memory device to a computing system according to some example embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, a semiconductor memory device and a memory system including the same according to some example embodiments will be described with reference to the accompanying drawings.

[0030] Figure 1is a diagram illustrating a memory system according to some example embodiments.

[0031] refer to Figure 1 , the memory system 10 may include a host 15, a memory controller 100, and a plurality of memory devices 200a to 200k.

[0032] The host 15 may communicate with the memory controller 100 and / or the plurality of semiconductor memory devices 200 a to 200 k using an interface protocol such as, for example, Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Furthermore, the interface protocol between the host 15 and the memory controller 100 and / or the plurality of semiconductor memory devices 200 a to 200 k is not limited to the above examples and may be one of other interface protocols, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0033] The memory controller 100 may generally control the operations of the plurality of semiconductor memory devices 200 a to 200 k and may control overall data exchange between the host 15 and the semiconductor memory devices 200 a to 200 k. For example, the memory controller 100 may control the semiconductor memory devices 200 a to 200 k according to a request from the host 15 to write or read data.

[0034] Furthermore, the memory controller 100 may control operations of the semiconductor memory devices 200 a to 200 k by applying operation commands for controlling the semiconductor memory devices 200 a to 200 k.

[0035] Depending on the example embodiment, each of the semiconductor memory devices 200a to 200k may be a volatile memory such as a dynamic random access memory (DRAM) having dynamic memory cells. However, the example embodiment is not limited thereto, and each of the semiconductor memory devices 200a to 200k may be, for example, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and / or a ferroelectric random access memory (FRAM) including resistive memory cells, and may be a non-volatile memory such as a flash memory. In the following description, a case in which each of the semiconductor memory devices 200a to 200k is implemented using DRAM will be described as an example.

[0036] Figure 2 is a diagram illustrating a schematic configuration of a memory system according to some example embodiments.

[0037] exist Figure 2 In this section, we will only describe Figure 1 A semiconductor memory device 200a corresponding to the memory controller 100 in the memory system 10 is taken as an example. However, the following description can be applied to Figure 1 Any one of the semiconductor memory devices 200b to 200k included in the memory system 10.

[0038] refer to Figure 2 , the memory controller 100 and the semiconductor memory device 200a may be connected to each other via corresponding command pins 101 and 201 and address pins 102 and 202, respectively. The command pins 101 and 201 may be used to transmit and / or receive a command signal CMD via a command transmission line TL1, and the address pins 102 and 202 may be used to transmit and / or receive an address signal ADDR via an address transmission line TL2.

[0039] The memory system 10 can operate in either a normal mode or a test mode. When the memory system 10 operates in the normal mode, the memory controller 100 can write the main data DTA into the semiconductor memory device 200a. In this case, the main data DTA may be data that the host 15 has requested to be written into the semiconductor memory device 200a.

[0040] When the memory system 10 operates in the test mode, the host 15 may be implemented as a test device for testing the semiconductor memory device 200 a. In this case, the memory controller 100 may test the semiconductor memory device 200 a by writing test pattern data TP to the semiconductor memory device 200 a according to a request from the host 15 implemented as a test device and then reading the data written to the semiconductor memory device 200 a.

[0041] The memory controller 100 and the semiconductor memory device 200a may be connected to each other via corresponding data pins 103 and 203, respectively. The data pins 103 and 203 may be used to transmit and / or receive main data DTA via the data transmission line TL3 in normal mode. Furthermore, the data pins 103 and 203 may be used to provide test pattern data TP to the semiconductor memory device 200a in test mode, and may provide test result data MTR to the memory controller 100. To this end, the memory controller 100 may include a built-in self-test (BIST) 110 that generates the test pattern data TP and receives the test result data MTR in test mode.

[0042] Figure 3 is a diagram illustrating a schematic configuration of a memory system according to some example embodiments.

[0043] Figure 3The memory system 10A may correspond to Figure 1 and Figure 2 The memory system 10, and Figure 3 It shows Figure 1 and Figure 2 The host 15 in FIG. 1 is implemented as a test device 15A and the memory system 10A operates in a test mode state.

[0044] refer to Figure 3 In the test mode, the test device 15A may apply a command CMD indicating the test mode to the semiconductor memory device 200a through the command pin 201, and may apply an address to be tested ADDR to the semiconductor memory device 200a through the address pin 202. In addition, the test device 15A may apply test pattern data TP to the semiconductor memory device 200a, and receive test result data MTR from the semiconductor memory device 200a through the data pin 203.

[0045] The semiconductor memory device 200a may include a parallel bit test (PBT) circuit 500. The parallel bit test circuit 500 may perform a parallel bit test operation. Here, the parallel bit test operation may include a test operation to determine whether the semiconductor memory device 200a is defective or non-defective by writing test pattern data TP into memory cells of the semiconductor memory device 200a and then comparing data read from the memory cells.

[0046] Figure 4 It shows Figures 1 to 3 A diagram showing the configuration of a semiconductor memory device.

[0047] refer to Figure 4 The semiconductor memory device 200a may include a control logic 210, an address register 220, a memory bank control logic 230, a refresh counter 297, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier 285, an input / output gating circuit 290, a data control circuit 400, and a data input / output buffer 299.

[0048] The memory cell array 300 may include first to fourth memory bank arrays 310, 320, 330, and 340. In addition, the row decoder 260 may include first to fourth memory bank row decoders 260a, 260b, 260c, and 260d, respectively, connected to the first to fourth memory bank arrays 310 to 340, and the column decoder 270 may include first to fourth memory bank column decoders 270a, 270b, 270c, and 270d, respectively, connected to the first to fourth memory bank arrays 310 to 340. The sense amplifier 285 may include first bank sense amplifiers 285a, 285b, 285c, and 285d, respectively, connected to the first to fourth memory bank arrays 310 to 340. The first to fourth memory bank arrays 310 to 340, the first to fourth memory bank sense amplifiers 285a to 285d, the first to fourth memory bank column decoders 270a to 270d, and the first to fourth memory bank row decoders 260a, 260b, 260c and 260d may configure the first to fourth memory banks, respectively.

[0049] Each of the first to fourth memory bank arrays 310 to 340 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC formed at points where the plurality of word lines WL and the plurality of bit lines BL intersect. Figure 4 An example of a semiconductor memory device 200 a including four memory banks is shown, but the semiconductor memory device 200 a may include any number of memory banks depending on example embodiments.

[0050] The address register 220 can be read from the memory controller 100 (e.g. Figure 1 ) receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0051] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, the bank row decoder corresponding to the bank address BANK_ADDR among the first to fourth bank row decoders 260a to 260d may be activated, and the bank column decoder corresponding to the bank address BANK_ADDR among the first to fourth bank column decoders 270a to 270d may be activated.

[0052] The refresh counter 297 may generate a refresh row address REF_ADDR for refreshing a memory cell row included in the memory cell array 300 under the control of the control logic 210 .

[0053] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 297. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 260a to 260d, respectively.

[0054] The bank row decoders among the first to fourth bank row decoders 260a to 260d activated by the bank control logic 230 may decode the row address RA output from the row address multiplexer 240 and activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0055] The column address latch 250 may receive a column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. Furthermore, the column address latch 250 may gradually increment the received column address COL_ADDR in a burst mode. The column address latch 250 may apply the temporarily stored or gradually incremented column address COL_ADDR to the first to fourth bank column decoders 270a to 270d, respectively.

[0056] The bank column decoders among the first to fourth bank column decoders 270 a to 270 d activated by the bank control logic 230 may activate sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 290 .

[0057] The input / output gating circuit 290 may include input data mask logic, a read data latch for storing data output from the first memory array 310 to the fourth memory array 340, a write driver for writing data to the first memory array 310 to the fourth memory array 340, and a switch circuit for gating input and output data.

[0058] Data to be read from one of the first to fourth bank arrays 310 to 340 can be sensed by a sense amplifier corresponding to the one bank array and stored in a read data latch. The data stored in the read data latch can be provided to the memory controller 100 through the data control circuit 400 and the data input / output buffer 299. Data DTA to be written to one of the first to fourth bank arrays 310 to 340 can be provided from the memory controller 100 to the data input / output buffer 299. The data DTA provided to the data input / output buffer 299 can be written to the memory cell array 300 through the data control circuit 400 and the input / output gating circuit 290.

[0059] In the test mode, the data input / output buffer 299 may receive test pattern data TP provided from the outside and provide the test pattern data TP to the input / output gating circuit 290 through the data control circuit 400. In the test mode, the input / output gating circuit 290 may write the test pattern data TP to a target page of the memory cell array 300, read the test pattern data TP from the target page, and provide the read test pattern data TP to the data control circuit 400 as test result data.

[0060] In the test mode, the data control circuit 400 can sequentially read test result data from each of the plurality of memory cells. The data control circuit 400 may include a parallel bit test circuit 500. The parallel bit test circuit 500 can sequentially compare the bits of the read test result data to determine whether the bits in the test result data are identical. Based on the determination result, the parallel bit test circuit 500 can determine whether each of the plurality of memory cells has failed (i.e., is defective) or passed (i.e., is non-defective).

[0061] The data control circuit 400 can output the merged test result data MTR based on whether each of the multiple memory cells determined by the parallel bit test circuit 500 has failed or passed. For example, only when each of the multiple memory cells connected to a word line or a bit line has failed, the data control circuit 400 can determine that the entirety of the corresponding word line or the corresponding bit line is defective. Therefore, the data control circuit 400 can determine the merged test result data MTR by determining whether a word line or a bit line (i.e., not a single bit) connected to the multiple memory cells is defective, rather than whether a memory cell (i.e., a single bit) is defective. Thereafter, the data control circuit 400 can provide the merged test result data MTR to the memory controller 100 or the test device 15A (e.g., a memory controller 100) through the data input / output buffer 299. Figure 3 shown).

[0062] The control logic 210 may control the operation of the semiconductor memory device 200a. For example, the control logic 210 may generate a control signal so that the semiconductor memory device 200a performs a write operation or a read operation. The control logic 210 may include a command decoder 211 for decoding a command CMD received from the memory controller 100, and a mode register 212 for setting an operation mode of the semiconductor memory device 200a.

[0063] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding the write enable signal WE, the row address strobe signal RAS, the column address strobe signal CAS, and / or the chip select signal CS. Specifically, the control logic 210 may generate a mode signal MS indicating an operating mode of the semiconductor memory device 200a and a control signal CTL for controlling the input / output gating circuit 290 by decoding the command CMD. The control logic 210 may provide the mode signal MS to the data input / output buffer 299 and the data control circuit 400.

[0064] Figure 5 It shows Figure 4 A diagram of an example of a memory cell in a semiconductor memory device.

[0065] refer to Figure 5 , memory cell MC may include a cell capacitor CC and a transistor CT. Transistor CT may be a selection element that connects or blocks cell capacitor CC from bit line BL depending on the voltage of word line WL. Transistor CT may be connected between cell capacitor CC and word line WL and bit line BL, and cell capacitor CC may be connected between transistor CT and a plate voltage.

[0066] Figure 6 It shows Figure 4 An exemplary diagram of a portion of a semiconductor memory device.

[0067] exist Figure 6 In FIG, a first memory bank array 310, an input / output gating circuit 290 and a data control circuit 400 are shown. Figure 6 In the figure, only Figure 4 The first memory bank array 310 among the first to fourth memory bank arrays 310 to 340 included in the memory cell array 300 is shown, but the same description may be applied to the second to fourth memory bank arrays 320 to 340.

[0068] refer to Figure 6, the first memory bank array 310 may include a normal cell array NCA and a redundant cell array RCA. The normal cell array NCA may include a plurality of first memory blocks MB0 to MB15 (indicated by reference numerals 311, 312, and 313, respectively), and the redundant cell array RCA may include at least one second memory block 314. The first memory blocks 311, 312, and 313 may be blocks that determine the storage capacity of the semiconductor memory device 200a. The second memory block 314 may be a redundant repair block. For example, when it is determined that a memory cell included in the first memory blocks 311, 312, and 313 is defective, the memory cell may be repaired by replacing the memory cell determined to be defective with a memory cell included in the second memory block 314. A memory cell that cannot be repaired even by using a redundant repair block may ultimately be determined to be defective.

[0069] Each of the first memory blocks 311 , 312 , and 313 may include a plurality of first memory cells arranged in rows and columns, and the second memory block 314 may also include a plurality of second memory cells arranged in rows and columns.

[0070] The rows of each of the first memory blocks 311, 312, and 313 may include, for example, 8K word lines WL, and the columns of each of the first memory blocks 311, 312, and 313 may include, for example, 1K bit lines BL. In some example embodiments, the memory cells connected to the intersections of the word lines WL and the bit lines BL may be configured as dynamic memory cells. Figure 6 , for convenience of explanation, word lines WL1 to WL4 among 8K word lines WL are shown.

[0071] The input / output gating circuit 290 may include a plurality of switch circuits 291 to 294 connected to the first memory blocks 311, 312, and 313 and the second memory block 314, respectively. In the semiconductor memory device 200a, bit lines BL corresponding to a burst length may be accessed simultaneously to support a burst length indicating the maximum number of accessible column positions. For example, the burst length of the semiconductor memory device 200a may be set to 8. Accordingly, each bit line BL may be connected to a column selection unit connected to each of the 128 column selection signals, and one column selection unit may select 8 bit lines BL at the same time.

[0072] The data control circuit 400 can be connected to the switch circuits 291 to 294 via each of the corresponding first data lines GIO[0:127] and second data lines EDBIO[0:7]. In response to the mode signal MS, the data control circuit 400 can sequentially read the test pattern data stored in each of the plurality of memory cells in the first memory blocks 311, 312, and 313 as test result data in a test mode. The data control circuit 400 can then determine whether the test result data is identical by sequentially comparing the bits of the read test result data. Based on the comparison, the data control circuit 400 can then output merged test result data MTR indicating whether a word line (or a bit line) is defective (i.e., not whether a single bit is defective).

[0073] The data control circuit 400 may write data from the memory controller 100 (eg, Figure 1 The data DTA received by the memory controller 100 or the test device 15A (as shown in FIG. 1 ) is written into the target page of the first memory blocks 311, 312, and 313, and the data DTA can be read from the target page in the first memory blocks 311, 312, and 313 in a read operation in a normal mode. The data control circuit 400 can write data from the memory controller 100 or the test device 15A (as shown in FIG. 1 ) in a write operation in a test mode. Figure 3 The test pattern data TP received by the first memory blocks 311, 312 and 313 is written into the target pages of the first memory blocks 311, 312 and 313, and the test result data can be read from each target page in the first memory blocks 311, 312 and 313 in the read operation of the test mode. It can be determined whether the test result data are the same by sequentially comparing the bits of the test result data read from each target page in the first memory blocks 311, 312 and 313, and based on the comparison, the merged test result data MTR indicating whether non-single bits are defective can be output.

[0074] Figure 7 is a diagram illustrating a method according to some example embodiments Figure 6 In the following, reference will be made to the data control circuit diagram. Figure 6 and Figure 7 Describe the operation of the data control circuit.

[0075] Assume that the test result data TR11 to TR18 are from Figure 6The first storage cell of the first memory block 311 shown is read from the first storage cell connected to the word line WL1, the test result data TR21 to TR28 are read from the first storage cell of the first memory block 311 connected to the word line WL2, the test result data TR31 to TR38 are read from the first storage cell of the first memory block 311 connected to the word line WL3, and the test result data TR41 to TR48 are read from the first storage cell of the first memory block 311 connected to the word line WL4.

[0076] However, the direction of reading the test pattern data stored in each memory cell of the first memory block 311 as the test result data is not limited to the word line WL direction. Therefore, in another example embodiment, the test pattern data stored in the first memory cell of the first memory block 311 may be read in the bit line BL direction as the test result data. Figure 13 An example embodiment of reading test pattern data stored in the first memory cell of the first memory block 311 in the bit line BL direction is described.

[0077] The data control circuit 400 may include a plurality of unit control circuits 410 to 440. The unit control circuits 410 to 440 may sequentially compare each of the input bits TR11 to TR18, TR21 to TR28, TR31 to TR38, and TR41 to TR48 in response to a mode signal MS, and may output merged test result data MTR1 to MTR4 based on the comparison results, respectively.

[0078] Figure 8 It shows Figure 7 A diagram of the configuration of one of the unit control circuits in the data control circuit.

[0079] Despite Figure 8 , the configuration of the unit control circuit 410 is shown in FIG. 4 , but the configuration of each of the unit control circuits 420 to 440 may also be substantially the same as that of the unit control circuit 410 .

[0080] refer to Figure 8 , the cell control circuit 410 may include a path selector 411 , a parallel bit test circuit 500 , and a latch circuit 600 .

[0081] In response to the mode signal MS, in the normal mode, the path selector 411 may provide the data DTA read from the plurality of memory cells to the data input / output buffer 299 (eg, Figure 4). In addition, in the test mode, the path selector 411 may provide the input bits TR11 to TR18 corresponding to the test result data to the parallel bit test circuit 500 through the second path R2.

[0082] The parallel bit test circuit 500 may include an exclusive OR (XOR) or exclusive NOR (XNOR) logic circuit. The parallel bit test circuit 500 may write the same test pattern data to multiple memory cells and then perform a comparison operation using the XOR or XNOR logic circuit when reading the test pattern data as test result data. The parallel bit test circuit 500 may output a signal S1 as the result of the comparison operation.

[0083] The parallel bit test circuit 500 can determine whether each of the plurality of memory cells is defective and output the determination result as a signal S1. Based on the test result data TR11 to TR18, the parallel bit test circuit 500 can output the signal S1 of a logic low level when determining that each of the plurality of memory cells passes, and can output the signal S2 of a logic high level when determining that each of the memory cells fails.

[0084] The latch circuit 600 may perform a latch operation in response to a reset signal RST and a signal S1 received from the parallel bit test circuit 500. The latch circuit 600 may selectively latch the output S1 of the parallel bit test circuit 500. For example, the latch circuit 600 may latch the output of the parallel bit test circuit 500 only when the signal S1 output from the parallel bit test circuit 500 is at a logic low level indicating a pass determination, and may not latch the parallel bit test circuit 500 when the signal S1 output from the parallel bit test circuit 500 is at a logic high level indicating a fail determination.

[0085] exist Figure 8 , the unit control circuit 410 in the read operation is described. The unit control circuit 410 can provide data DTA to the first memory blocks 311, 312 and 313 (eg, Figure 6 ), and the test pattern data TP may be provided to the target pages of the first memory blocks 311, 312, 313 in a write operation of the test mode.

[0086] Figure 9 It shows Figure 7 An example diagram of a latch circuit.

[0087] refer to Figure 9, the latch circuit 600 can be based on a set-reset (SR) latch. The latch circuit 600 may include an inverter INV1, a logic gate G1, a logic gate G2, and an inverter INV2. The inverter INV1 may output a signal S3 by inverting the reset signal RST. The signal S3 may be input to the logic gate G2. The signal S4 at the node N1 may be input to the logic gate G2. The logic gate G2 may perform a NAND operation on the signals S3 and S4 and output a signal S5. The output S1 of the parallel bit test circuit 500 and the output signal S5 of the logic gate G2 may be input to the logic gate G1. In this way, the logic gates G1 and G2 may be cross-coupled to form an SR latch. The signal S5 output from the logic gate G2 may be input to the inverter INV2, and the inverter INV2 may output the signal S2 by inverting the signal S5.

[0088] When the parallel bit test circuit 500 makes a pass determination for a particular memory cell, the signal S1 input to the logic gate G1 may be at a logic low level. Furthermore, when the reset signal RST input to the inverter INV1 is at a logic low level, the inverter INV1 may output a signal S3 at a logic high level. In this case, the signal S5 output from the logic gate G2 may be at a logic low level. The inverter INV2 may output a signal S2 at a logic high level that is an inverted version of the signal S5 at a logic low level. In this manner, when the output of the parallel bit test circuit 500 corresponds to a pass determination, the latch circuit 600 may latch the output S1 of the parallel bit test circuit 500.

[0089] When the parallel bit test circuit 500 makes a failed determination, the signal S1 input to the logic gate G1 may be at a logic high level. When the reset signal RST input to the inverter INV1 is at a logic low level, the inverter INV1 may output a signal S3 at a logic high level. In this case, the logic level of the signal S5 output from the logic gate G2 maintains the previous state.

[0090] In another example embodiment, when the parallel bit test circuit 500 makes a fail determination for a particular memory cell, such that the signal S1 input to the logic gate G1 is at a logic high level, and the reset signal RST input to the inverter INV1 is at a logic high level, the inverter INV1 may output a signal S3 at a logic low level. In this case, the signal S5 output from the logic gate G2 may be at a logic high level. The inverter INV2 may output a signal S2 at a logic low level that is an inverted version of the signal S5 at a logic high level. In this way, when the output of the parallel bit test circuit 500 corresponds to a fail determination, the latch circuit 600 may not latch the output signal S1 of the parallel bit test circuit 500.

[0091] In this way, once the signal S1 indicating that a specific memory cell has passed the determination is input from the parallel bit test circuit 500 to the latch circuit 600, even if the signal S2 indicating that a memory cell other than the specific memory cell has failed the determination is input from the parallel bit test circuit 500, the latch circuit 600 can maintain the state of outputting the signal S2 at a logic high level until the latch circuit 600 is reset.

[0092] Figure 10 is an example diagram of a latch circuit according to some other example embodiments.

[0093] refer to Figure 10 , the latch circuit 600A can be based on a set-reset (SR) latch. The latch circuit 600A can include inverters INV3, INV4, INV5, and INV6, and logic gates G3 to G10. Inverter INV3 can output signal S6 by inverting signal S1. In this case, signal S1 can be a signal output from the parallel bit test circuit 500 and can be a signal indicating whether a pass or fail determination is made for each memory cell. Logic gate G3 can perform an exclusive OR operation on signal S6 and signal S7 and output signal S8. In this case, signal S8 can always be at a logic high level. Inverter INV4 can output signal S9 by inverting signal S8 output from logic gate G3. When signal S1 output from the parallel bit test circuit 500 is at a logic low level (i.e., when a pass determination is made for the memory cell), signal S9 at node N2 can be at a logic high level. In contrast, when the signal S1 output from the parallel bit test circuit 500 is at a logic high level (ie, when a fail determination is made on the memory cell), the signal S9 of the node N2 may be at a logic low level.

[0094] The reset signal RST and the output signal S10 of the logic gate G4 can be input to the logic gate G5. The logic gate G5 can perform a NOR operation on the reset signal RST and the signal S10 and output a signal S11. The logic gate G4 can perform a NOR operation on the signal S9 at the node N2 and the output signal S11 of the logic gate G5 and output a signal S10. In this way, the logic gates G4 and G5 can be cross-coupled to form an SR latch.

[0095] Logic gate G6 can perform a NAND operation on output signals S1 and S10 of parallel bit test circuit 500 and output signal S12. Logic gate G7 can perform a NOR operation on output signals S1 and S11 of parallel bit test circuit 500 and output signal S13. Inverter INV5 can output signal S14 at a logic low level by inverting signal S7 at a logic high level. Logic gate G8 can perform an AND operation on signal S12 at a logic high level and signal S7 and output signal S15. Logic gate G9 can perform an AND operation on signal S14 at a logic low level and signal S13 and output signal S16. Logic gate G10 can perform a NOR operation on signal S15 and signal S16 and output signal S17. Inverter INV6 can output signal S2 by inverting signal S17.

[0096] When the parallel bit test circuit 500 makes a pass determination for a particular memory cell, the signal S9 at node N2 may be at a logic high level. Furthermore, when the reset signal RST input to the logic gate G5 is at a logic low level, the logic gate G5 may output a logic high signal S11, and the logic gate G4 may output a logic low signal S10. Furthermore, the logic gate G7 may perform a NOR operation on the logic low signal S1 and the logic high signal S11, and output a logic low signal S13. The logic gate G6 may perform a NAND operation on the logic low signal S1 and the logic low signal S10, and output a logic high signal S12. Thereafter, the logic gate G8 may perform an AND operation on the logic high signal S7 and the logic high signal S12, and output a logic high signal S15. The logic gate G9 may perform an AND operation on the logic low signal S14 and the logic low signal S13, and output a logic low signal S16. Thereafter, the logic gate G10 performs a NOR operation on the logic high signal S15 and the logic low signal S16 and outputs a logic low signal S17. The inverter INV6 inverts the logic low signal S17 to output a logic high signal S2. Thus, when the output of the parallel bit test circuit 500 corresponds to a pass determination, the latch circuit 600A latches the output S1 of the parallel bit test circuit 500.

[0097] Conversely, when the parallel bit test circuit 500 determines that a particular memory cell has failed (i.e., when the signal S9 at node N2 is at a logic low level) and the reset signal RST input to the logic gate G5 is at a logic low level, the logic level of the signal S2 output by the inverter INV6 is maintained at the previous state. Furthermore, when the parallel bit test circuit 500 determines that a particular memory cell has failed (i.e., when the signal S9 at node N2 is at a logic low level) and the reset signal RST input to the logic gate G5 is at a logic high level, the inverter INV6 may output the signal S2 at a logic low level. In this manner, when the output of the parallel bit test circuit 500 corresponds to a failed determination, the latch circuit 600A may not latch the output signal S1 of the parallel bit test circuit 500.

[0098] Figure 11 and Figure 12 are diagrams for describing operations of a semiconductor memory device according to some example embodiments.

[0099] Figure 11 is a diagram showing a semiconductor memory device 200a ( Figure 4 ) of the memory cell array 300 ( Figure 4 For ease of explanation, Figure 11 and Figure 12 Only word lines WL0 to WL3 and bit lines BL0 to BL3 of the multiple word lines and bit lines of the memory cell array 300 are shown. Memory cells MC1 to MC16 connected to the intersections of word lines WL0 to WL3 and bit lines BL0 to BL3 can be configured as dynamic memory cells. In the parallel bit test mode of the parallel bit test circuit 500, after writing the same data (i.e., test pattern data TP) to N (a natural number of 2 or more) memory cells, the N bits of data can be read simultaneously. The read N bits of data can be compared with each other by a comparator included in the parallel bit test circuit 500 to determine whether they pass (or "match") or fail (or "mismatch"). Depending on this pass (P) / fail (F), "1" / "0" can be output as test result data.

[0100] In some example embodiments, the parallel bit test mode of the parallel bit test circuit 500 may be performed on a word line basis. For example, when determining whether a word line to which multiple memory cells are connected (i.e., not a single bit) is defective, rather than determining whether a single memory cell (i.e., a single bit) is defective, a defect in the word line may be determined by outputting merged test result data MTR of the multiple memory cells connected to the word line.

[0101] For example, Figure 11 and Figure 12As shown, when there are a plurality of memory cells MC1 to MC16 connected to word lines WL0 to WL4 and bit lines BL0 to BL4, respectively, the parallel bit test circuit 500 can determine whether each of the plurality of memory cells MC1 to MC16 has passed or failed, and output test result data. In this case, when a pass determination is made for all the plurality of memory cells MC1 to MC4 connected to word line WL0, the data control circuit 400 (e.g., Figure 4 As shown, the data control circuit 400 may output the merged test result data MTR1′ indicating a pass for the word line WL0. Similarly, when a pass determination is made for all of the plurality of memory cells MC9 to MC12 connected to the word line WL2, the data control circuit 400 may output the merged test result data MTR3′ indicating a pass for the word line WL2.

[0102] On the other hand, when a pass determination is made for at least one of the plurality of memory cells MC5 to MC8 connected to the word line WL1, the data control circuit 400 may output the merged test result data MTR2′ indicating a pass for the entire corresponding word line WL1. Figure 11 and Figure 12 As shown, even if a fail determination is made for memory cells MC6 and MC8, a pass determination can be made for the entire corresponding word line WL1 because a pass determination is made for memory cells MC5 and MC7 connected to the same word line WL1. In addition, when a fail determination is made for all of the plurality of memory cells MC13 to MC16 connected to word line WL3, the data control circuit 400 can output the merged test result data MTR4' indicating a fail for word line WL3.

[0103] Therefore, when a pass determination is made for even one of the plurality of memory cells connected to a word line, the data control circuit 400 can make a pass determination for the entire corresponding word line. That is, only when a fail determination is made for the plurality of memory cells connected to the word line, can the data control circuit 400 make a fail determination for the entire corresponding word line.

[0104] Therefore, the data control circuit 400 can use the parallel bit test method to determine whether each of the plurality of memory cells connected to a word line is defective, and can use the AND operation method to determine whether the entire word line is defective. In this way, single bit defects can be excluded and non-single bit defects of the entire word line can be determined.

[0105] Figure 13 and Figure 14 are diagrams for describing operations of a semiconductor memory device according to some other example embodiments.

[0106] although Figure 11 and Figure 12 A case where the parallel bit test mode of the parallel bit test circuit 500 is performed on a word line basis, ie, a case where word line defects of a memory cell array are determined, is described, but example embodiments are not limited thereto.

[0107] For example, reference Figure 13 and 14 When a pass determination is made for all the multiple memory cells MC1' to MC4' connected to the bit line BL0, the data control circuit 400 can output the merged test result data MTR1" indicating that the bit line BL0 has passed. Similarly, when a pass determination is made for all the multiple memory cells MC9' to MC12' connected to the bit line BL2, the data control circuit 400 can output the merged test result data MTR3" indicating that the bit line BL2 has passed.

[0108] On the other hand, when a pass determination is made for at least one of the plurality of memory cells MC5' to MC8' connected to the bit line BL1, the data control circuit 400 may output the merged test result data MTR2' indicating that the entire corresponding bit line BL1 has passed. Figure 13 As shown, even if a fail determination is made for memory cells MC6' and MC8', a pass process can be performed for the entire bit line BL1 because a pass determination is made for memory cells MC5' and MC8' connected to the same bit line BL1. In addition, when a fail determination is made for all of the plurality of memory cells MC13' to MC16' connected to the bit line BL3, the data control circuit 400 can output the merged test result data MTR4' indicating a fail for the bit line BL3.

[0109] Therefore, when a pass determination is made for even one memory cell among the plurality of memory cells connected to the bit line, the data control circuit 400 can make a pass determination for the entire corresponding bit line. In other words, only when a fail determination is made for all the plurality of memory cells connected to the bit line, can the data control circuit 400 make a fail determination for the entire corresponding bit line.

[0110] In this manner, the data control circuit 400 can use a parallel bit test method to determine whether each of a plurality of memory cells connected to a bit line is defective, and can use an AND operation method to determine whether the entire corresponding bit line is defective. In this manner, single bit defects can be excluded, and non-single bit defects of the entire bit line can be determined.

[0111] As an example, Figures 11 to 14The case where the entire word line or the entire bit line is determined to be defective when a failure determination is made for each memory cell connected to the word line or the bit line is described, but example embodiments are not limited thereto. In another example embodiment, when determining whether a word line or a bit line is defective, only memory cells at predetermined addresses among a plurality of memory cells connected to the word line or the bit line may be considered. For example, referring to Figure 13 , when determining whether the entire bit line BL1 is defective, only memory cells MC6' and MC8' corresponding to some of the memory cells MC5' to MC8' connected to the bit line BL1 may be considered. In this case, even if a pass determination is made for each of the memory cells MC5' and MC7' connected to the bit line BL1, a fail determination may be made for the entire bit line BL1 because a fail determination is made for all of the memory cells MC6' and MC8' at the predetermined addresses.

[0112] In this manner, when determining whether a word line or a bit line among a plurality of memory cells connected to the word line or the bit line has a non-single bit defect, the memory cells at the predetermined address considered may form a memory cell group. Hereinafter, the description of determining whether the entirety of a word line or a bit line is defective may include determining whether the entirety of the memory cell group including the memory cell at the predetermined address is defective.

[0113] Figure 15 is a diagram illustrating bit lines that are subjects of a parallel bit test according to some example embodiments. Figure 16 is a diagram illustrating reading a data file stored in a memory according to some example embodiments. Figure 15 A timing diagram of a read operation of the test pattern data in the memory cell.

[0114] In the following, as an example, reference will be made to Figure 15 and Figure 16 The following describes the case of reading test pattern data stored in memory cells MC(n) to MC(n+4) connected to bit line BL(n). Parallel bit test circuit 500 can make a pass or fail determination for each of memory cells MC(n) to MC(n+4) through a parallel bit test operation. The following describes an example in which parallel bit test circuit 500 determines a fail for memory cells MC(n) and MC(n+2), and a pass for memory cells MC(n+1), MC(n+3), and MC(n+4).

[0115] refer to Figure 16 , in the test mode, at time point t1, the memory controller 100 ( Figure 2 ) may apply an active command ACT(m) for the word line WL(m) to the semiconductor memory device 200 a ( Figure 2). In response to the activation command ACT(m), the word line WL(m) may be activated. After activating the word line WL(m), at time point t2, the memory controller 100 may apply a read command RD(m) for the word line WL to the semiconductor memory device 200a. In response to the read command RD(m) being applied to the semiconductor memory device 200a, the logic level of the command / address signal CA11 applied to the semiconductor memory device 200a may transition from the first logic level L to the second logic level H at time point t3. After the command / address signal CA11 applied to the semiconductor memory device 200a switches once, the logic level of the command / address signal CA11 may transition back to the first logic level L.

[0116] In response to a read command RD(m) applied to the semiconductor memory device 200a, the parallel bit test circuit 500 (eg Figure 2 As shown in FIG, the memory cell MC(n) can be determined whether it is passed (i.e., normal) or failed (i.e., defective) by reading the data stored in the memory cell MC(n) connected to the bit line BL(n) and the word line WL(m), and a signal S1 (as shown in FIG, 4 ) indicating the determination result can be sent to the memory cell MC(n). Figure 8 As shown) is sent to the latch circuit 600 (as shown Figure 8 ). The latch circuit 600 may latch the output of the parallel bit test circuit 500 when a pass signal is received from the parallel bit test circuit 500, and may not latch the output of the parallel bit test circuit 500 when a fail signal is received from the parallel bit test circuit 500.

[0117] When the parallel bit test circuit 500 makes a failure determination on the memory cell MC(n), the latch circuit 600 may output a signal S2 of a logic low level. In this case, the latch circuit 600 may not latch the output of the parallel bit test circuit 500 .

[0118] Furthermore, in response to application of the read command RD(m) for the word line WL(m) at the time point t2 and subsequent application of the command / address signal CA11 of the second logic level H to the semiconductor memory device 200 a at the time point t3 , the data read from the memory cell MC(n) (i.e., data including information on whether the memory cell MC(n) is defective) may not be immediately provided to the test device 15A (e.g., Figure 3 Thereafter, at time point t4, the bit lines of the memory cells connected to the word line WL(m) may be precharged.

[0119] Thereafter, at time t5, the memory controller 100 may apply an activation command ACT(m+1) for word line WL(m+1) to the semiconductor memory device 200a. In response to the activation command ACT(m+1), word line WL(m+1) may be activated. After word line WL(m+1) is activated, at time t6, the memory controller 100 may apply a read command RD(m+1) for word line WL(m+1) to the semiconductor memory device 200a. In response to the read command RD(m+1) applied to the semiconductor memory device 200a, the logic level of the command / address signal CA11 applied to the semiconductor memory device 200a may transition from the first logic level L to the second logic level H.

[0120] In response to a read command RD(m+1) applied to semiconductor memory device 200a, parallel bit test circuit 500 may read the data stored in memory cell MC(n+1) and determine a pass on memory cell MC(n+1). Therefore, parallel bit test circuit 500 may transmit a pass signal to latch circuit 600, and latch circuit 600 may output signal S2, which is a logic high signal, at time t8. In this case, latch circuit 600 may latch the output of parallel bit test circuit 500.

[0121] In addition, in response to the application of the read command RD(m+1) for word line WL(m+1) at time point t6 and the subsequent application of the command / address signal CA11 of the second logic level H to the semiconductor memory device 200a at time point t7, the data read from the memory cell MC(n+1) (i.e., data including information on whether the memory cell MC(n+1) is defective) may not be immediately provided to the test device 15A. Thereafter, at time point t9, the bit line of the memory cell connected to the word line WL(m+1) may be precharged.

[0122] Thereafter, at time t10, the memory controller 100 may apply an active command ACT(m+2) for word line WL(m+2) to the semiconductor memory device 200a. In response to the active command ACT(m+2), word line WL(m+2) may be activated. After word line WL(m+2) is activated, at time t11, the memory controller 100 may apply a read command RD(m+2) for word line WL(m+2) to the semiconductor memory device 200a. In response to the read command RD(m+2) applied to the semiconductor memory device 200a, the logic level of the command / address signal CA11 applied to the semiconductor memory device 200a may transition from a first logic level L to a second logic level H at time t12.

[0123] In response to the read command RD(m+2) applied to the semiconductor memory device 200a, the parallel bit test circuit 500 can make a failure determination on the memory cell MC(n+2) by reading the data stored in the memory cell MC. Therefore, the parallel bit test circuit 500 can send a failure signal to the latch circuit 600. In this case, as shown in FIG. Figure 9 As described above, even if the latch circuit 600 receives the fail signal from the parallel bit test circuit 500 , the latch circuit 600 may maintain a state in which the latch circuit 600 outputs the signal S2 of a logic high level.

[0124] In addition, in response to the application of the read command RD(m+2) for the word line WL(m+2) at time point t11 ​​and the subsequent application of the command / address signal CA11 of the second logic level H to the semiconductor memory device 200a at time point t12, the data read from the memory cell MC(n+2) (i.e., data including information on whether the memory cell MC(n+2) is defective) may not be immediately provided to the test device 15A. Thereafter, at time point t13, the bit line of the memory cell connected to the word line WL(m+2) may be precharged.

[0125] Subsequently, at time t14, an activation command ACT(m+3) for word line WL(m+3) may be applied to semiconductor memory device 200a, and accordingly, word line WL(m+2) may be activated. Subsequently, at time t15, a read command RD(m+3) for word line WL(m+3) may be applied to semiconductor memory device 200a, and in response, parallel bit test circuit 500 may read the data stored in memory cell MC(n+3) and perform a pass determination on memory cell MC(n+3). Consequently, parallel bit test circuit 500 may transmit a pass signal to latch circuit 600, and latch circuit 600 may continuously output a signal S2 at a logic high level.

[0126] In addition, in response to the application of the read command RD(m+3) for the word line WL(m+3) at time point t15 and the subsequent application of the command / address signal CA11 of the second logic level H to the semiconductor memory device 200a at time point t16, the data read from the memory cell MC(n+3) (i.e., data including information on whether the memory cell MC(n+3) is defective) may not be immediately provided to the test device 15A. Thereafter, at time point t17, the bit line of the memory cell connected to the word line WL(m+3) may be precharged.

[0127] Thereafter, at time t18, the memory controller 100 may apply an activate command ACT(m+4) for word line WL(m+4) to the semiconductor memory device 200a. In response to the activate command ACT(m+4), word line WL(m+4) may be activated. After word line WL(m+4) is activated, at time t19, the memory controller 100 may apply a read command RD(m+4) for word line WL(n+3) to the semiconductor memory device 200a.

[0128] Even if a read command RD(m+4) is applied to the semiconductor memory device 200a, the command / address signal CA11 applied to the semiconductor memory device 200a may continue to maintain the first logic level L. In this manner, in response to the read command RM(m+4) applied to the semiconductor memory device 200a, but the logic level of the command / address signal CA11 applied to the semiconductor device 200a is the first logic level L, the memory controller 100 may transmit a read enable signal RD_EN of a logic high level to the semiconductor memory device 200a. Therefore, the logic level of the read enable signal RD_EN applied to the semiconductor memory device 200a may transition from the first logic level L to the second logic level H at time t20.

[0129] In this manner, in response to the application of the read enable signal RD_EN at a logic high level to the semiconductor memory device 200a, the combined test result data MTR can be output from the semiconductor memory device 200a at time t21. The combined test result data MTR can include information regarding whether the entire bit line BL(n) passes or fails. Even when a pass determination is made from one of the memory cells MC(n) to MC(n+4) connected to the bit line BL(n) (i.e., when the signal S2 is at the second logic level at time t20 when the read enable signal RD_EN at a logic high level is applied to the semiconductor memory device 200a), the test result data MTR can include information that the entire bit line BL(n) passes.

[0130] In another example embodiment, when a failure determination is made for all memory cells MC(n) to MC(n+4) connected to bit line BL(n), signal S2 is maintained at the first logic level L. In this case, test result data MTR output from semiconductor memory device 200a may include information that the entire bit line BL(n) failed. Test result data MTR output from semiconductor memory device 200a may be transmitted to test device 15A.

[0131] Figure 17 is a structural diagram illustrating a semiconductor memory device according to some example embodiments.

[0132] like Figure 17 As shown, the semiconductor memory device 700 may include a plurality of semiconductor layers LA1 to LAp (p is a natural number of 3 or greater). Assume that the lowest semiconductor layer LA1 is a master chip, and the remaining semiconductor layers LA2 to LAp are slave chips. Figure 2 The semiconductor memory device 200a described may correspond to any one of the semiconductor layers LA2 to LAp. The plurality of semiconductor layers LA1 to LAp may transmit and receive signals to and from each other through silicon vias TSV, and the main chip LA1 may communicate with an external memory controller 100 (e.g., a memory controller 100) through a conductive device formed on its outer surface. Figure 1 The configuration and operation of the semiconductor memory device 700 will be described below using the first semiconductor layer 710 as a master chip and the p-th semiconductor layer 720 as an example of a slave chip.

[0133] The first semiconductor layer 710 may include various peripheral circuits for driving a memory region 721 provided in the slave chip. For example, the first semiconductor layer 710 may include a row driver 7101 (X driver) for driving a memory word line, a column driver 7102 (Y driver) for driving a memory bit line, a data input / output unit 7103 for controlling data input / output, a command buffer 7104 for receiving a command CMD from the outside and buffering the command CMD, and an address buffer 7105 for receiving an address from the outside and buffering the address. The memory region may include a first memory block and a second memory block, as shown in FIG. Figure 6 As stated.

[0134] In addition, the first semiconductor layer 710 may further include a control logic 7107 . The control logic 7107 may control access to the memory area 721 based on a command and address signal provided from the memory controller 100 , and may generate a control signal for accessing the memory area 721 .

[0135] The p-th semiconductor layer 720 may include a data control circuit 722 for testing memory cells included in the memory region 721 in a test mode. The data control circuit 722 may correspond to a reference signal. Figures 4 to 16 The data control circuit 400 is described. Figures 4 to 16 As described above, the data control circuit 722 can sequentially read the test result data from each of the plurality of memory cells connected to one word line (or one bit line) of the memory area 721 in the test mode and sequentially compare the read test result data to the memory controller 100 or the test device 15A (e.g., Figure 3) provides the combined test result data MTR indicating whether all word lines (or bit lines) have failed. The memory controller 100 or the test device 15A can screen (or identify) non-single bit defects based on the test result data MTR.

[0136] Figure 18 is a diagram illustrating a memory system to which a semiconductor memory device is applied according to some example embodiments.

[0137] refer to Figure 18 , the memory system 800 may include a memory module 810 and a memory controller 820. The memory module 810 may include at least one semiconductor memory device (DRAM) 830 mounted on a module board. The semiconductor memory device 830 may be implemented as Figure 2 The semiconductor memory device 200a is configured as a semiconductor memory device 830. For example, the semiconductor memory device 830 may be implemented as a DRAM chip. Furthermore, each semiconductor memory device 830 may include multiple semiconductor chips stacked one on top of the other. In this case, the semiconductor chips may include at least one master chip 831 and at least one slave chip 832. Signals may be transmitted between the stacked semiconductor chips using through-silicon vias (TSVs).

[0138] Each of the master chip 831 and the slave chip 832 may include Figure 2 The semiconductor memory device 200a is shown in FIG. Therefore, the semiconductor memory device 830 can sequentially read test result data from each of a plurality of memory cells connected to a word line (or a bit line) in a test mode and sequentially compare the read test result data to provide the built-in test circuit 850 of the memory controller 820 with merged test result data MTR indicating whether a word line (or a bit line) is defective. The built-in test circuit 850 can screen for non-single bit defects based on the merged test result data MTR.

[0139] The memory module 810 can communicate with the memory controller 820 through a system bus. Data DTA, commands / addresses CMD / ADDR, a clock signal CLK, etc. can be transmitted and received between the memory module 810 and the memory controller 820 through the system bus.

[0140] Figure 19 is a diagram illustrating a computing system equipped with a semiconductor memory device according to some example embodiments.

[0141] refer to Figure 19The computing system 900 may be installed in a mobile device or a desktop computer. The computing system 900 may include a memory system 910 electrically connected to a system bus 905, a central processing unit (CPU) 920, a random access memory (RAM) 930, a user interface 940, and a modem 950 such as a baseband chipset. The computing system 900 may also include an application chipset, a camera image processor (CIS), input / output devices, and the like.

[0142] The user interface 940 may be an interface for sending data to and / or receiving data from a communication network. The user interface 940 may be wired or wireless and may include an antenna or a wired or wireless transceiver. Data provided through the user interface 940 or the modem 950 or data processed by the central processing unit 920 may be stored in the memory system 910.

[0143] The memory system 910 may include a semiconductor memory device 912 and a memory controller 911. The memory controller 911 may include a built-in test device 913. The semiconductor memory device 912 stores data processed by the central processing unit 920 or data input from the external device. In a test mode, the semiconductor memory device 912 may sequentially read test result data from multiple memory cells connected to a word line (or a bit line) and sequentially compare the read test result data. The semiconductor memory device 912 may then provide the built-in test device 913 of the memory controller 911 with merged test result data MTR indicating whether a word line (or a bit line) is defective. The built-in test device 913 may determine whether to repair the memory cell based on the merged test result data MTR.

[0144] When the computing system 900 is a device that performs wireless communications, the computing system 900 may be used in communication systems such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Multiple Access (NADC), and CDMA2000. The computing system 900 may be installed on an information processing device such as a personal digital assistant (PDA), a portable computer, a web tablet, a digital camera, a portable media player (PMP), a mobile phone, a wireless phone, or a laptop computer.

[0145] Figure 20 is a block diagram illustrating an example of applying a semiconductor memory device to a computing system according to some example embodiments.

[0146] refer to Figure 20, the computing system 1000 includes a processor 1010, an input / output hub 1020, an input / output controller hub 1030, at least one memory module 1040, and a graphics card 1050. Depending on the example embodiment, the computing system 1000 can be any computing system, such as a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, etc.

[0147] The processor 1010 can perform various computing functions, such as specific calculations or tasks. For example, the processor 1010 can be a microprocessor or a central processing unit (CPU). According to exemplary embodiments, the processor 1010 can include one processor core (single core) or multiple processor cores (multi-core). For example, the processor 1010 can include multiple cores, such as dual cores, quad cores, or hexa cores. In addition, Figure 20 Computing system 1000 is shown as including one processor 1010, but according to example embodiments, computing system 1000 may include multiple processors. Furthermore, depending on example embodiments, processor 1010 may also include internal or external cache memory. Processor 1010 may include a memory controller 1011 that controls the operation of memory module 1040. Memory controller 1011 included in processor 1010 may be referred to as an integrated memory controller (IMC). The memory interface between memory controller 1011 and memory module 1040 may be implemented as a single channel including multiple signal lines, or as multiple channels. Furthermore, one or more memory modules 1040 may be connected to each channel. Depending on example embodiments, memory controller 1011 may be located within input / output hub 1020. Input / output hub 1020 including memory controller 1011 may be referred to as a memory controller hub (MCH).

[0148] Memory module 1040 may include multiple semiconductor memory devices that store data provided by memory controller 1011. Each semiconductor memory device can determine whether a test result for each of the multiple memory cells is a pass or fail by sequentially reading test result data from multiple memory cells connected to a word line (or a bit line) in a test mode and sequentially comparing the read test result data. Based on the determination result, the device can provide memory controller 1011 with merged test result data MTR containing information on whether the entire word line (or the entire bit line) is defective. Memory controller 1011 can screen the semiconductor memory devices for non-single-bit defects based on the merged test result data MTR.

[0149] The input / output hub 1020 can manage data transfer between devices such as the graphics card 1050 and the processor 1010. The input / output hub 1020 can be connected to the processor 1010 through various types of interfaces. For example, the input / output hub 1020 and the processor 1010 can be connected through various standard interfaces, such as the front-side bus (FSB), the system bus, HyperTransport, Lightning Data Transfer (LDT), Quick Path Interconnect (QPI), and the Common System Interface (CSI). Figure 20 The computing system 1000 is shown to include one input / output hub 1020 , but depending on the example implementation, the computing system 1000 may include multiple input / output hubs.

[0150] The I / O hub 1020 may provide various interfaces between devices, such as an Accelerated Graphics Port (AGP) interface, a Peripheral Component Express (PCIe) interface, a Communication Streaming Architecture (CSA) interface, and the like.

[0151] The graphics card 1050 may be connected to the input / output hub 1020 via AGP or PCIe. The graphics card 1050 may control a display device for displaying images. The graphics card 1050 may include an internal processor and an internal semiconductor memory device for image data processing. Depending on the exemplary embodiment, the input / output hub 1020 may include a graphics device having the graphics card 1050 located outside the input / output hub 1020 or inside the input / output hub 1020 instead of the graphics card 1050. The graphics device included in the input / output hub 1020 may be referred to as integrated graphics. In addition, the input / output hub 1020 including a memory controller and a graphics device may be referred to as a graphics and memory controller hub (GMCH).

[0152] The I / O controller hub 1030 can perform data buffering and interface arbitration to enable various system interfaces to operate efficiently. The I / O controller hub 1030 can be connected to the I / O hub 1020 via an internal bus. For example, the I / O hub 1020 and the I / O controller hub 1030 can be connected via a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), PCIe, etc.

[0153] The input / output controller hub 1030 may provide various interfaces with peripheral devices. For example, the input / output controller hub 1030 may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general-purpose input / output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.

[0154] Although the present disclosure has been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A semiconductor memory device, comprising: a memory cell array, the memory cell array comprising a first memory cell group; a first parallel bit test circuit configured to determine whether each of a plurality of memory cells included in the first memory cell group is defective, the first parallel bit test circuit configured to output a first fail signal based on each of the plurality of memory cells included in the first memory cell group being defective, and the first parallel bit test circuit configured to output a first pass signal based on at least one of the plurality of memory cells included in the first memory cell group being non-defective; as well as a first latch circuit configured to selectively latch an output of the first parallel bit test circuit; The first latch circuit is configured to latch the output of the first parallel bit test circuit in response to the first parallel bit test circuit outputting the first pass signal. The plurality of memory cells included in the first memory cell group are respectively connected to different word lines, and The plurality of memory cells included in the first memory cell group are connected to the same bit line.

2. The semiconductor memory device according to claim 1, wherein The first latch circuit comprises: a first inverter configured to output a first signal by inverting a reset signal; a first logic gate configured to perform a NAND operation on the first signal and a second signal of the first node to output a third signal; a second logic gate configured to output the second signal by performing a NAND operation on the output of the first parallel bit test circuit and the third signal; and a second inverter configured to output a fourth signal by inverting the third signal.

3. The semiconductor memory device according to claim 1, wherein The first latch circuit is based on a set-reset latch, and Wherein, the first latch circuit includes: a first inverter configured to output a first signal by inverting a reset signal; a first NAND gate configured to generate a third signal based on the first signal and the second signal; a second NAND gate configured to form the set-reset latch by cross-coupling with the first NAND gate and to generate the second signal by receiving the output of the first parallel bit test circuit and the third signal; and a second inverter configured to output a fourth signal by inverting the third signal.

4. The semiconductor memory device according to claim 1, wherein The memory cell array further includes a second memory cell group, and Wherein, the semiconductor memory device further includes: a second parallel bit test circuit configured to determine whether each of a plurality of memory cells included in the second memory cell group is defective, the second parallel bit test circuit configured to output a second fail signal based on each of the plurality of memory cells included in the second memory cell group being defective, and the second parallel bit test circuit configured to output a second pass signal based on at least one of the plurality of memory cells included in the second memory cell group being non-defective; and a second latch circuit configured to selectively latch an output of the second parallel bit test circuit, The second latch circuit is configured to latch the output of the second parallel bit test circuit in response to the second parallel bit test circuit outputting the second pass signal. The plurality of memory cells included in the second memory cell group are respectively connected to different word lines, and The plurality of memory cells included in the second memory cell group are connected to the same bit line.

5. The semiconductor memory device according to claim 1, wherein The first latch circuit comprises: a first inverter configured to output a first signal by inverting an output of the first parallel bit test circuit; a first logic gate configured to perform an exclusive OR operation on the first signal and the second signal to output a third signal; and a second inverter configured to output a fourth signal by inverting the third signal, wherein the second signal is at a logic high level, and Wherein, the first latch circuit is based on a set-reset latch.

6. The semiconductor memory device according to claim 5, wherein The first latch circuit further includes: a second logic gate configured to perform a NOR operation on the reset signal and the fifth signal of the first node to output a sixth signal; a third logic gate configured to form the set-reset latch by cross-coupling with the second logic gate and output the fifth signal by performing a NOR operation on the fourth signal and the sixth signal; a fourth logic gate configured to output a seventh signal by performing a NOR operation on the sixth signal and an output of the first parallel bit test circuit; a fifth logic gate configured to output an eighth signal by performing a NAND operation on the fifth signal and an output of the first parallel bit test circuit; a third inverter configured to output a ninth signal by inverting the second signal, a sixth logic gate configured to output a tenth signal by performing an AND operation on the seventh signal and the ninth signal; a seventh logic gate configured to output an eleventh signal by performing an AND operation on the second signal and the eighth signal; an eighth logic gate configured to output a twelfth signal by performing a NOR operation on the tenth signal and the eleventh signal; and a fourth inverter configured to output a thirteenth signal by inverting the twelfth signal.

7. The semiconductor memory device according to claim 1, wherein The first storage unit group includes a first storage unit and a second storage unit, wherein the first latch circuit is configured to output a signal having a second logic level different from the first logic level in response to the first parallel bit test circuit outputting a first fail signal having a first logic level as a result of determining whether the first memory cell is defective at a first point in time, and Wherein, the first latch circuit is configured to output the signal having the first logic level in response to the first parallel bit test circuit outputting the first pass signal having the second logic level as a result of determining whether the second storage unit is defective at a second time point after the first time point.

8. The semiconductor memory device according to claim 7, wherein The first storage unit group further includes a third storage unit, and Wherein, the first latch circuit is configured to output the signal having the first logic level in response to the first parallel bit test circuit outputting the first fail signal having the first logic level at a third time point after the second time point as a result of determining whether the third storage unit is defective.

9. A semiconductor memory device, comprising: a memory cell array, the memory cell array comprising memory cell groups; a parallel bit test circuit configured to determine whether each of a plurality of memory cells included in the memory cell group is defective, the parallel bit test circuit configured to output a fail signal based on each of the plurality of memory cells included in the memory cell group being defective, and the parallel bit test circuit configured to output a pass signal based on at least one of the plurality of memory cells included in the memory cell group being non-defective; as well as a latch circuit configured to selectively latch an output of the parallel bit test circuit, wherein the latch circuit is configured to latch the output of the parallel bit test circuit in response to the parallel bit test circuit outputting the pass signal, The plurality of memory cells included in the memory cell group are respectively connected to different bit lines, and The plurality of memory cells included in the memory cell group are connected to the same word line.

10. The semiconductor memory device according to claim 9, wherein The latch circuit comprises: a first inverter configured to output a first signal by inverting a reset signal; a first logic gate configured to perform a NAND operation on the first signal and a second signal of the first node to output a third signal; a second logic gate configured to output the second signal by performing a NAND operation on the output of the parallel bit test circuit and the third signal; and a second inverter configured to output a fourth signal by inverting the third signal.

11. The semiconductor memory device according to claim 9, wherein The latch circuit is based on a set-reset latch, and Wherein, the latch circuit includes: a first inverter configured to output a first signal by inverting a reset signal; a first logic gate configured to perform a NAND operation on the first signal and the second signal to generate a third signal; a second logic gate configured to form the set-reset latch by cross-coupling with the first logic gate and to generate the second signal by performing a NAND operation on the output of the parallel bit test circuit and the third signal; and a second inverter configured to output a fourth signal by inverting the third signal.

12. The semiconductor memory device according to claim 9, wherein The memory cell group includes a first memory cell connected to a first word line and a first bit line, and a second memory cell connected to the first word line and a second bit line different from the first bit line, wherein the latch circuit is configured to output a signal having a second logic level different from the first logic level in response to the parallel bit test circuit outputting the fail signal having a first logic level as a result of determining whether the first memory cell is defective at a first point in time, and Wherein, the latch circuit is configured to output the signal having the first logic level in response to the parallel bit test circuit outputting the pass signal having the second logic level as a result of determining whether the second storage unit is defective at a second time point after the first time point.

13. The semiconductor memory device according to claim 12, wherein The memory cell group further includes a third memory cell connected to the first word line and a third bit line different from the first bit line and the second bit line, and Wherein, the latch circuit is configured to output the signal having the first logic level in response to the parallel bit test circuit outputting the fail signal having the first logic level as a result of determining whether the third storage unit is defective at a third time point after the second time point.

14. A memory system, comprising: semiconductor memory devices; a testing device configured to test the semiconductor memory device; as well as a memory controller configured to control operations of the semiconductor memory device, Wherein, the semiconductor memory device comprises: a memory cell array, the memory cell array comprising a plurality of memory cells; a parallel bit test circuit configured to determine whether each of the plurality of memory cells is defective, output a fail signal based on whether each of the plurality of memory cells is defective, and output a pass signal based on whether at least one of the plurality of memory cells is not defective; and a latch circuit configured to selectively latch an output of the parallel bit test circuit, wherein the latch circuit is configured to latch the output of the parallel bit test circuit in response to the parallel bit test circuit outputting the pass signal, The plurality of memory cells are connected to different word lines respectively, and The plurality of memory cells are connected to the same bit line.

15. The memory system according to claim 14, wherein: The memory controller is configured to apply at least one command to control the operation of the semiconductor memory device, The plurality of memory cells include a first memory cell and a second memory cell, the first memory cell is connected to a first word line and a first bit line, and the second memory cell is connected to the first bit line and a second word line different from the first word line. wherein, in response to the memory controller applying a first activation command for the first word line to the semiconductor memory device, the first word line is activated at a first time point, and In response to the memory controller applying a first read command to the semiconductor memory device after the first time point, a command / address signal having a first logic level is applied to the semiconductor memory device at a second time point after the first time point.

16. The memory system according to claim 15, wherein: In response to the memory controller applying a second active command to the semiconductor memory device after the second time point, the second word line is activated at a third time point after the second time point, and In which, in response to the memory controller applying a second read command to the semiconductor memory device after the third time point, a command / address signal having a second logic level different from the first logic level is applied to the semiconductor memory device at a fourth time point after the third time point.

17. The memory system according to claim 15, wherein: The memory controller is configured to not transmit a read enable signal to the semiconductor memory device in response to the command / address signal having the first logic level being applied to the semiconductor memory device at the second time point.

18. The memory system according to claim 16, wherein: The memory controller is configured to transmit a read enable signal to the semiconductor memory device in response to the command / address signal having the second logic level being applied to the semiconductor memory device at the fourth time point.

19. The memory system of claim 18, wherein: The memory controller is configured to transmit data read from the first memory cell and the second memory cell to the test device in response to the read enable signal being applied to the semiconductor memory device.

20. The memory system of claim 15, wherein: The memory controller is configured not to transfer data read from the first memory cell to the test device in response to the first read command being applied to the semiconductor memory device and the command / address signal having the first logic level being applied to the semiconductor memory device.

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