Sense amplifier circuit and data readout method

Abstract

The present application relates to the field of semiconductor circuit design, and relates to a sense amplifier circuit and a data readout method, comprising: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; a first control MOS transistor for providing a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor for providing a bias voltage to the second PMOS transistor according to a control signal; a first offset cancellation MOS transistor for electrically connecting an initial bit line to a first complementary readout bit line according to the offset cancellation signal; and a second offset cancellation MOS transistor for electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal. Stable gate voltages are provided to the first and second PMOS transistors respectively via the first and second control MOS transistors, thereby stably eliminating offset noise in the sense amplifier circuit and avoiding voltage fluctuations on the bit lines and complementary bit lines.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and more particularly to a sensing amplifier circuit and a data readout method. Background Art

[0002] Dynamic Random Access Memory (DRAM) writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line. In DRAM, when a read operation or refresh operation is performed, the read amplifier reads and amplifies the voltage difference between the bit line and the complementary bit line.

[0003] The semiconductor devices that make up the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. These different device characteristics can cause offset noise in the sense amplifier, which can reduce the effective read margin of the sense amplifier and degrade DRAM performance.

[0004] The applicant has discovered that in the current process of eliminating DRAM offset noise, the bit line and the complementary read bit line are electrically connected, and the complementary bit line and the read bit line are electrically connected, and the offset noise is canceled by the voltage difference between the bit line and the complementary bit line. However, because the gate of the PMOS transistor in the sense amplifier circuit is connected to the read bit line and the complementary read bit line respectively, it is easy to cause voltage fluctuations on the read bit line and the complementary read bit line, thereby affecting the voltage of the bit line and the complementary bit line, reducing the accuracy of DRAM reading, and degrading DRAM performance.

[0005] Therefore, how to stably eliminate the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line is an urgent problem to be solved. Summary of the Invention

[0006] Embodiments of the present application relate to a sense amplifier circuit and a data readout method, providing a sense amplifier circuit to stably eliminate offset noise in the sense amplifier circuit while avoiding voltage fluctuations on a bit line and a complementary bit line.

[0007] The present application provides a sensing amplifier circuit, which is arranged between adjacent memory arrays, and includes: a first PMOS transistor, whose gate is connected to a second readout bit line, whose drain is connected to a first complementary readout bit line, and whose source is connected to a first signal terminal; a first NMOS transistor, whose gate is connected to an initial bit line, whose drain is connected to the first complementary readout bit line, and whose source is connected to a second signal terminal, wherein the initial bit line is connected to one memory array in the adjacent memory arrays; a second PMOS transistor, whose gate is connected to the second complementary readout bit line, whose drain is connected to the first readout bit line, and whose source is connected to the first signal terminal; a second NMOS transistor, whose gate is connected to the initial complementary bit line, whose drain is connected to the first readout bit line, and whose source is connected to the second signal terminal, wherein the initial complementary bit line is connected to another memory array in the adjacent memory arrays; the first signal terminal is used to receive a first level signal, and the second signal terminal is used to receive a second level signal; a first control M An OS transistor, whose source is connected to the second readout bit line, whose gate is used to receive a control signal, and whose drain is used to receive a bias voltage, is used to provide a bias voltage to the first PMOS transistor according to the control signal; a second control MOS transistor, whose source is connected to the second complementary readout bit line, whose gate is used to receive a control signal, and whose drain is used to receive a bias voltage, is used to provide a bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor, whose source is connected to the initial bit line, whose drain is connected to the first complementary readout bit line, whose gate is used to receive an offset cancellation signal, is used to electrically connect the initial bit line with the first complementary readout bit line according to the offset cancellation signal; a second offset cancellation MOS transistor, whose source is connected to the initial complementary bit line, whose drain is connected to the first readout bit line, whose gate is used to receive an offset cancellation signal, is used to electrically connect the initial complementary bit line with the first readout bit line according to the offset cancellation signal.

[0008] The present application also provides a data readout method, applicable to the above-mentioned sensing amplifier circuit, comprising: a precharge phase, an offset cancellation phase, a charge sharing phase, a sensing amplifier phase, and a reset phase, which are sequentially executed. During the precharge phase and the reset phase, an initial bit line, a first sensing bit line, a second sensing bit line, an initial complementary bit line, a first complementary sensing bit line, and a second complementary sensing bit line in the sensing amplifier circuit are precharged to a precharge voltage. During the offset cancellation phase, a bias voltage is provided to a first PMOS transistor and a second PMOS transistor in the sensing amplifier circuit to eliminate device differences between the first PMOS transistor and the second PMOS transistor, and simultaneously eliminate device differences between the first NMOS transistor and the second NMOS transistor. During the charge sharing phase, a voltage of a target memory cell is read to the initial bit line, and a voltage of a target complementary memory cell is read to the initial complementary bit line. During the sensing amplifier phase, a voltage of the initial bit line and the initial complementary bit line that is higher than the precharge voltage is pulled up to a voltage corresponding to a first level signal, and a voltage that is lower than the precharge voltage is pulled down to a voltage corresponding to a second level signal.

[0009] When the first control MOS transistor and the second control MOS transistor are turned on based on the control signal, a bias voltage is provided to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The first PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first complementary read bit line, and the first level signal is transmitted to the first complementary read bit line. The second PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first read bit line, and the first level signal is transmitted to the first read bit line, thereby achieving offset cancellation of the PMOS transistor; when the first offset cancellation MOS transistor and the second offset cancellation MOS transistor are turned on based on the offset cancellation signal, the initial bit line is electrically connected to the first complementary read bit line and shares a voltage, the initial complementary bit line is electrically connected to the first read bit line and shares a voltage, and the initial bit line is electrically connected to the first read bit line and shares a voltage. The voltage of the initial complementary bit line is used as the gate voltage of the first NMOS transistor to turn on the first NMOS transistor, the second signal terminal is electrically connected to the first complementary read bit line, the second level signal is transmitted to the first complementary read bit line, the voltage of the initial complementary bit line is used as the gate voltage of the second NMOS transistor to turn on the second NMOS transistor, the second signal terminal is electrically connected to the first read bit line, and the second level signal is transmitted to the first read bit line, thereby achieving offset cancellation of the NMOS transistor; because the first PMOS transistor and the second PMOS transistor are turned on based on the stable bias voltage, that is, the voltage of the first read bit line and the first complementary read bit line is kept stable, the voltage of the initial bit line and the initial complementary bit line is further stabilized, so as to avoid voltage fluctuation on the bit line and the complementary bit line, and stably eliminate offset noise in the sense amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the circuit structure of a sensing amplifier circuit provided in one embodiment of the present application;

[0011] Figure 2 A timing diagram of a data readout method provided in another embodiment of the present application;

[0012] Figures 3 to 8 FIG. 1 is a schematic structural diagram of a sensing amplifier circuit corresponding to each step in a data readout method according to another embodiment of the present application. DETAILED DESCRIPTION

[0013] Currently, in the process of eliminating DRAM offset noise, the bit line and the complementary read bit line are electrically connected, and the complementary bit line and the read bit line are electrically connected. The offset noise is offset by the voltage difference between the bit line and the complementary bit line. However, because the gate of the PMOS transistor in the sense amplifier circuit is connected to the read bit line and the complementary read bit line respectively, it is easy to cause voltage fluctuations on the read bit line and the complementary read bit line. This affects the voltage of the bit line and the complementary bit line, reduces the accuracy of DRAM reading, and degrades DRAM performance. Therefore, how to stably eliminate offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line is a current problem that needs to be solved.

[0014] An embodiment of the present application provides a sensing amplifier circuit, which is arranged between adjacent memory arrays, and includes: a first PMOS transistor, whose gate is connected to a second readout bit line, whose drain is connected to a first complementary readout bit line, and whose source is connected to a first signal terminal; a first NMOS transistor, whose gate is connected to an initial bit line, whose drain is connected to the first complementary readout bit line, and whose source is connected to a second signal terminal, wherein the initial bit line is connected to one memory array in the adjacent memory arrays; a second PMOS transistor, whose gate is connected to the second complementary readout bit line, whose drain is connected to the first readout bit line, and whose source is connected to the first signal terminal; a second NMOS transistor, whose gate is connected to the initial complementary bit line, whose drain is connected to the first readout bit line, and whose source is connected to the second signal terminal, wherein the initial complementary bit line is connected to another memory array in the adjacent memory arrays; the first signal terminal is used to receive a first level signal, and the second signal terminal is used to receive a second level signal; a first control M An OS transistor, whose source is connected to the second readout bit line, whose gate is used to receive a control signal, and whose drain is used to receive a bias voltage, is used to provide a bias voltage to the first PMOS transistor according to the control signal; a second control MOS transistor, whose source is connected to the second complementary readout bit line, whose gate is used to receive a control signal, and whose drain is used to receive a bias voltage, is used to provide a bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor, whose source is connected to the initial bit line, whose drain is connected to the first complementary readout bit line, whose gate is used to receive an offset cancellation signal, is used to electrically connect the initial bit line with the first complementary readout bit line according to the offset cancellation signal; a second offset cancellation MOS transistor, whose source is connected to the initial complementary bit line, whose drain is connected to the first readout bit line, whose gate is used to receive an offset cancellation signal, is used to electrically connect the initial complementary bit line with the first readout bit line according to the offset cancellation signal.

[0015] Those skilled in the art will appreciate that, in the various embodiments of this application, many technical details are provided to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0016] Figure 1 This is a schematic diagram of the circuit structure of the sensing amplifier circuit provided in this embodiment. The sensing amplifier circuits provided in various embodiments of the present application are further described in detail below in conjunction with the accompanying drawings, as follows:

[0017] refer to Figure 1 , a sensing amplifier circuit, disposed between adjacent memory arrays 400, comprising:

[0018] The first PMOS tube <p1>The gate is connected to the second readout bit line ISABL, the drain is connected to the first complementary readout bit line SABLB, and the source is connected to the first signal terminal; wherein the first signal terminal is used to receive a first level signal (Positive Cell Storing Signal, PCS).

[0019] The first NMOS tube <n1>The gate is connected to the initial bit line BL, the drain is connected to the first complementary readout bit line SABLB, and the source is connected to the second signal terminal; wherein the second signal terminal is used to receive a second level signal Negative Cell Storing Signal, NCS).

[0020] In this embodiment, the voltage of the first level signal PCS is greater than the voltage of the second level signal NCS, that is, the first level signal PCS is a high level corresponding to logic "1", and the second level signal NCS is a low level corresponding to logic "0".

[0021] The second PMOS tube <p2>The gate is connected to the second complementary read bit line ISABLB, the drain is connected to the first read bit line SABL, and the source is connected to the first signal terminal.

[0022] The second NMOS tube <n2>The gate is connected to the initial complementary bit line BLB, the drain is connected to the first readout bit line SABL, and the source is connected to the second signal terminal.

[0023] Regarding the initial bit line BL and the initial complementary bit line BLB, the initial bit line BL is connected to the memory cells of one memory array 400 in the adjacent memory arrays 400 , and the initial complementary bit line is connected to the memory cells of the other memory array 400 in the adjacent memory array 400 .

[0024] In this embodiment, reference Figure 1 The initial bit line BL passes through the first switch tube <01> Connected to the first storage unit, the initial complementary bit line BLB passes through the second switch tube <02> Connect a second storage unit.

[0025] For the first switch <01> and the second switch tube <02> , the first switch tube <01> The gate is connected to the word line WL, the source is connected to the initial bit line BL, the drain is connected to the first storage unit, and the second switch is connected to the first storage unit. <02> The gate is connected to the word line WL, the source is connected to the initial complementary BLB, and the drain is connected to the second memory cell.

[0026] Among them, the word line WL is used to be turned on based on the row selection signal. When the word line WL is turned on, the switch tube connected to the word line WL is turned on, and the charge of the storage unit is shared to the initial bit line BL or the initial complementary bit line BLB. The initial bit line BL or the initial complementary bit line BLB is turned on based on the column selection signal. When the initial bit line BL or the initial complementary bit line BLB is turned on, the memory reads out the data.

[0027] The first control MOS tube <11> The source is connected to the second readout bit line ISABL, the gate is used to receive the control signal, and the drain is used to receive the bias voltage V BIAS , used to control the first PMOS tube according to the control signal <p1>Provide bias voltage V BIAS .

[0028] Second control MOS tube <12> The source is connected to the second complementary read bit line ISABLB, the gate is used to receive the control signal, and the drain is used to receive the bias voltage V BIAS , used to control the first NMOS transistor according to the control signal <n1>Provide bias voltage V BIAS .

[0029] The first offset cancellation MOS tube <31> The source is connected to the initial bit line BL, the drain is connected to the first complementary read bit line SABLB, and the gate is used to receive an offset cancellation signal (OC) and to electrically connect the initial bit line BL to the first complementary read bit line SABLB according to the offset cancellation signal OC.

[0030] Second offset cancellation MOS tube <32> The source is connected to the initial complementary bit line BLB, the drain is connected to the first readout bit line SABL, and the gate is used to receive the offset cancellation signal OC and to electrically connect the initial complementary bit line BLB to the first readout bit line SABL according to the offset cancellation signal OC.

[0031] When the first control MOS tube <11> and the second control MOS tube <12> After the control signal is turned on, the first PMOS tube <p1>The gate and the second PMOS tube <p2>The gate provides a bias voltage V BIAS , the first PMOS tube <p1>Based on the bias voltage V BIAS The first signal terminal is electrically connected to the first complementary readout bit line SABLB, the first level signal PCS is transmitted to the first complementary readout bit line SABLB, and the second PMOS transistor <p2>Based on the bias voltage V BIAS The first signal terminal is electrically connected to the first readout bit line SABL, and the first level signal PCS is transmitted to the first readout bit line SABL, thereby achieving the offset elimination of the PMOS tube; when the first offset elimination MOS tube <31> and the second offset cancellation MOS tube <32> After the offset cancellation signal OC is turned on, the initial bit line BL is electrically connected to the first complementary read bit line SABLB and shares a voltage. The initial complementary bit line BLB is electrically connected to the first read bit line SABL and shares a voltage. The voltage of the initial bit line BL serves as the first NMOS transistor. <n1>The gate voltage turns on the first NMOS transistor <n1>The second signal terminal is electrically connected to the first complementary read bit line SABLB, and the second level signal NCS is transmitted to the first complementary read bit line SABLB. The voltage of the initial complementary bit line BL is used as the voltage of the second NMOS transistor. <n2>The gate voltage turns on the second NMOS transistor <n2>, the second signal end is electrically connected to the first readout bit line SABL, and the second level signal NCS is transmitted to the first readout bit line SABL, thereby achieving offset elimination of the NMOS tube; since the first PMOS tube <p1>and the second PMOS tube <p2>Based on a stable bias voltage V BIAS The first sensing bit line SABL and the first complementary sensing bit line SABLB are turned on, that is, the voltage of the first sensing bit line SABL and the first complementary sensing bit line SABLB is kept stable, and the voltage of the initial bit line BL and the initial complementary bit line BLB is further stabilized to avoid voltage fluctuations on the bit line and the complementary bit line, and stably eliminate offset noise in the sense amplifier circuit.

[0032] In one example, the control signal is the same as the offset cancellation signal OC, that is, the first control MOS transistor <11> , the second control MOS tube <12> , the first offset cancellation MOS tube <31> and the second offset cancellation MOS tube <32> By setting the control signal to be the same as the offset cancellation signal OC, the first control MOS tube is synchronously controlled. <11> , the second control MOS tube <12> , the first offset cancellation MOS tube <31> and the second offset cancellation MOS tube <32> , thereby achieving offset cancellation of the sense amplifier circuit, such as Figure 1 The circuit shown.

[0033] In one example, the control signal includes a first control signal and a second control signal, wherein the first control MOS transistor <11> Based on the first control signal being turned on, the second control MOS tube <12> Based on the second control signal, the first control MOS tube is turned on. <11> Based on the first control signal, the first PMOS transistor <p1>Provide bias voltage V BIAS ; Second control MOS tube <12> Based on the second control signal <p2>Provide bias voltage V BIAS Through different control signals and the separate control of the first control unit and the second control unit, the control module 100 is further precisely controlled. <11> and the second control MOS tube <12> The individual control of the sense amplifier circuit can be further realized by further precise control.

[0034] In one example, the first control MOS tube <11> and the second control MOS tube <12> It can also be realized by only one MOS tube, that is, the first PMOS tube is simultaneously supplied with power by the same MOS tube. <p1>and the second PMOS tube <p2>Provide bias voltage V BIAS The bias voltage V is provided by the same control unit. BIAS , so as to reduce the layout area of ​​the sensing amplifier circuit structure, which is beneficial to improving the integration of the memory.

[0035] In this embodiment, the sense amplifier circuit further includes: a first isolation unit 201, having one end connected to the first sense bit line SABL and the other end connected to the second sense bit line ISABL, and being configured to electrically connect the first sense bit line SABL and the second sense bit line ISABL according to a first isolation signal (Isolation Signal 1, ISO1); and a second isolation unit 202, having one end connected to the first complementary sense bit line SABLB and the other end connected to the second complementary sense bit line ISABLB, and being configured to electrically connect the first complementary sense bit line SABLB and the second complementary sense bit line ISABLB according to the first isolation signal (Isolation Signal 1, ISO1).

[0036] Specifically, the first isolation unit 201 includes a first isolation MOS transistor <21> , the first isolation MOS tube <21> The source is connected to the first readout bit line SABL, the drain is connected to the second readout bit line ISABL, and the gate is used to receive the first isolation signal ISO1; the second isolation unit 202 includes a second isolation MOS transistor <22> , the second isolation MOS tube <22> The source is connected to the first complementary read bit line SABLB, the drain is connected to the second complementary read bit line ISABLB, and the gate is used to receive the first isolation signal ISO1.

[0037] The sensing amplifier circuit provides a first isolation signal ISO1 in the precharge phase to precharge the second read bit line ISABL and the second complementary read bit line ISABLB. In the sensing amplifier phase, the first isolation signal ISO1 is provided to enable the first PMOS transistor to <p1>The gate of the first PMOS transistor is connected to the first read bit line SABL. <p1>The gate of is connected to the first complementary read bit line SABLB.

[0038] At this time, for the first PMOS tube <p1>and the first NMOS tube <n1>, since the first PMOS tube <p1>Gate and first NMOS tube <n1>The connection relationship of the gate is the same, that is, based on the different levels of the second read bit line ISABL, the first PMOS transistor <p1>Or the first NMOS tube <n1>When turned on, the first PMOS tube <p1>and the first NMOS tube <n1>There is only one MOS tube that is turned on; for the second PMOS tube <p2>and the second NMOS tube <n2>, since the second PMOS tube <p2>Gate and second NMOS tube <n2>The connection relationship of the gate is the same, that is, based on the different levels of the second complementary bit line ISABLB, the second PMOS transistor <p2>Or the second NMOS tube <n2>When turned on, the second PMOS tube <p2>and the second NMOS tube <n2>There is only one conducting MOS tube in the circuit.

[0039] Specifically, when the second PMOS tube <p2>After being turned on, the first signal terminal is connected to the first readout bit line SABL, thereby pulling the first readout bit line SABL high to the first level signal PCS, and then pulling the initial bit line BL high to the first level signal PCS, so that the data read out of the memory through the initial bit line BL is a high level corresponding to the logic "1" of the first level signal PCS; when the first NMOS transistor <n1>After being turned on, the second signal terminal is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB down to the second level signal NCS, and then pulling the initial complementary bit line BLB down to the second level signal NCS, so that the data read out of the memory through the initial complementary bit line BLB is the low level of the second level signal NCS corresponding to the logic "0"; when the first PMOS transistor <p1>After being turned on, the first signal terminal is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB high to the first level signal PCS, and then pulling the initial complementary bit line BLB high to the first level signal PCS, so that the data read out of the memory through the initial complementary bit line BLB is a high level corresponding to the first level signal PCS logic "1"; when the second NMOS transistor <n2>After being turned on, the second signal terminal is connected to the first read bit line SABL, thereby pulling the first read bit line SABL down to the second level signal NCS, and then pulling the initial bit line BL down to the second level signal NCS, so that the data read out of the memory through the initial bit line BL is the low level of the second level signal NCS corresponding to the logic "0".

[0040] In this embodiment, the sense amplifier circuit further includes: a third isolation unit 203, having one end connected to the initial bit line BL and the other end connected to the first readout bit line SABL, and being configured to electrically connect the initial bit line BL to the first readout bit line SABL according to a second isolation signal (Isolation Signal 2, ISO2); and a fourth isolation unit 204, having one end connected to the initial complementary bit line BLB and the other end connected to the first complementary readout bit line SABLB, and being configured to electrically connect the initial complementary bit line BLB to the first complementary readout bit line SABLB according to the second isolation signal (Isolation Signal 2, ISO2).

[0041] The third isolation unit 203 includes a third isolation MOS transistor <23> , the third isolation MOS tube <23> The source is connected to the initial bit line BL, the drain is connected to the first readout bit line SABL, and the gate is used to receive the second isolation signal (Isolation Signal 2, ISO2). The fourth isolation unit 204 includes a fourth isolation MOS transistor <24> , the fourth isolation MOS tube <24> The source is connected to the initial complementary bit line BLB, the drain is connected to the first complementary readout bit line SABLB, and the gate is used to receive a second isolation signal (IsolationSignal 2, ISO2).

[0042] The sense amplifier circuit provides a second isolation signal ISO2 during the offset cancellation phase and the amplification phase to achieve charge sharing between the initial bit line BL and the first readout bit line SABL, and between the initial complementary bit line BLB and the first complementary bit line SABLB.

[0043] In this embodiment, the sense amplifier circuit further includes an equalizing unit 401 having one end connected to the first sense bit line SABL and the other end connected to the first complementary sense bit line SABLB, and configured to equalize the voltage of the first sense bit line SABL and the voltage of the first complementary sense bit line SABLB according to an equalizing signal (EQ).

[0044] Specifically, the balancing unit 401 includes a balancing MOS tube <41> The source is connected to the first read bit line SABL, the drain is connected to the first complementary read bit line SABLB, and the gate is used to receive the equalization signal EQ.

[0045] It should be noted that the specific connection methods of the "source" and "drain" defined in the above-mentioned transistors do not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be adopted.

[0046] When the first control MOS transistor and the second control MOS transistor are turned on based on the control signal, a bias voltage is provided to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The first PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first complementary read bit line, and the first level signal is transmitted to the first complementary read bit line. The second PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first read bit line, and the first level signal is transmitted to the first read bit line, thereby achieving offset cancellation of the PMOS transistor; when the first offset cancellation MOS transistor and the second offset cancellation MOS transistor are turned on based on the offset cancellation signal, the initial bit line is electrically connected to the first complementary read bit line and shares a voltage, the initial complementary bit line is electrically connected to the first read bit line and shares a voltage, and the initial bit line is electrically connected to the first read bit line and shares a voltage. The voltage of the initial complementary bit line is used as the gate voltage of the first NMOS transistor to turn on the first NMOS transistor, the second signal terminal is electrically connected to the first complementary read bit line, the second level signal is transmitted to the first complementary read bit line, the voltage of the initial complementary bit line is used as the gate voltage of the second NMOS transistor to turn on the second NMOS transistor, the second signal terminal is electrically connected to the first read bit line, and the second level signal is transmitted to the first read bit line, thereby achieving offset cancellation of the NMOS transistor; because the first PMOS transistor and the second PMOS transistor are turned on based on the stable bias voltage, that is, the voltage of the first read bit line and the first complementary read bit line is kept stable, the voltage of the initial bit line and the initial complementary bit line is further stabilized, so as to avoid voltage fluctuation on the bit line and the complementary bit line, and stably eliminate offset noise in the sense amplifier circuit.

[0047] It should be noted that, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems raised by this application, but this does not mean that there are no other units in this embodiment; ordinary technicians in this field can understand that the above-mentioned embodiments are specific embodiments for implementing this application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

[0048] Another embodiment of the present application provides a data readout method, applied to the above-mentioned sensing amplifier circuit, comprising: a precharge phase, an offset cancellation phase, a charge sharing phase, a sensing amplifier phase, and a reset phase, which are sequentially executed. During the precharge phase and the reset phase, an initial bit line, a first sensing bit line, a second sensing bit line, an initial complementary bit line, a first complementary sensing bit line, and a second complementary sensing bit line in the sensing amplifier circuit are precharged to a precharge voltage. During the offset cancellation phase, a bias voltage is provided to a first PMOS transistor and a second PMOS transistor in the sensing amplifier circuit to eliminate device differences between the first PMOS transistor and the second PMOS transistor, and simultaneously eliminate device differences between the first NMOS transistor and the second NMOS transistor. During the charge sharing phase, a voltage of a target memory cell is read to the initial bit line, and a voltage of a target complementary memory cell is read to the initial complementary bit line. During the sensing amplifier phase, voltages of the initial bit line and the initial complementary bit line that are higher than the precharge voltage are pulled up to a voltage corresponding to a first level signal, and voltages that are lower than the precharge voltage are pulled down to a voltage corresponding to a second level signal.

[0049] Figure 2 A timing diagram of the data reading method provided in this embodiment, Figures 3 to 8 The structure diagram of the sensing amplifier circuit corresponding to each step in the data readout method of this embodiment is as follows:

[0050] refer to Figure 2 The data readout method includes: a pre-charging stage, an offset elimination stage, a charge sharing stage, a sensing amplification stage and a reset stage which are executed in sequence.

[0051] Among them, the pre-charge stage is Figure 2 The offset elimination phase is t0~t1. Figure 2 The charge sharing phase is t1~t2. Figure 2 t2~t3 in the sensing and amplification stage is Figure 2 The reset phase is t3 to t5. Figure 2 t5~t6 in.

[0052] refer to Figure 1 、 Figure 2 The t0~t1 part in Figure 3 , for the precharge stage, including: precharging the initial bit line BL, the first read bit line SABL, the second read bit line ISABL, the first complementary read bit line SABLB and the second complementary read bit line ISABLB in the sense amplifier circuit to a precharge voltage.

[0053] Specifically, the first isolation signal ISO1 is provided to turn on the first isolation MOS transistor. <21> To electrically connect the first read bit line SABL to the second read bit line ISABL, and provide the first isolation signal ISO1 to turn on the second isolation MOS transistor <22> , so that the first complementary read bit line SABLB is electrically connected to the second complementary read bit line ISABLB.

[0054] Provide the second isolation signal ISO2 to turn on the third isolation MOS tube <23> To electrically connect the initial bit line BL to the first read bit line SABL, and provide the second isolation signal ISO2 to turn on the fourth isolation MOS transistor <24> , so that the initial complementary bit line BLB is electrically connected to the first complementary readout bit line SABLB.

[0055] A precharge signal is provided to precharge the initial bit line BL and the initial complementary bit line BLB to a preset voltage, or to precharge the first read bit line SABL and the first complementary read bit line SABLB to a precharge voltage.

[0056] In one example, the precharge voltage is 1 / 2 the stored internal power supply voltage.

[0057] In one example, during the precharge phase, an equalization signal EQ is further provided to electrically connect the first sensing bit line SABL to the first complementary sensing bit line SABLB.

[0058] By electrically connecting the first read bit line SABL to the second read bit line ISABL, the first complementary read bit line SABLB to the second complementary read bit line ISABLB, the initial bit line BL to the first read bit line SABL, and the initial complementary bit line BLB to the first complementary read bit line SABLB, one of the initial bit line BL, the first read bit line SABL, the second read bit line ISABL, the first complementary read bit line SABLB, and the second complementary read bit line ISABLB is precharged, thereby completing the overall precharging of the initial bit line BL, the first read bit line SABL, the second read bit line ISABL, the first complementary read bit line SABLB, and the second complementary read bit line ISABLB.

[0059] refer to Figure 1 、 Figure 2 The t1~t2 part in Figure 4 It can be seen that the offset elimination stage includes: sending the first PMOS transistor of the sensing amplifier circuit to ... <p1>and the second PMOS tube <p2>Provide bias voltage V BIAS , to eliminate the first PMOS tube <p1>and the second PMOS tube <p2>device differences and eliminate the first NMOS transistor <n1>and the second NMOS tube <n2>The difference between the devices.

[0060] Specifically, a first level signal PCS is provided to the first signal terminal, and a second level signal NCS is provided to the second signal terminal.

[0061] To the first PMOS tube <p1>The gate and the second PMOS tube <p2>The gate is biased by the same voltage V BIAS , the first PMOS tube <p1>The voltage of the first complementary readout bit line SABLB is adjusted based on the first level signal PCS, and the second PMOS transistor <p2>The voltage of the first sensing bit line SABL is adjusted based on the second level signal NCS.

[0062] Specifically, when the first control MOS tube <11> and the second control MOS tube <12> After the control signal is turned on, the first PMOS tube <p1>The gate and the second PMOS tube <p2>The gate provides a bias voltage V BIAS , the first PMOS tube <p1>Based on the bias voltage V BIAS The first signal terminal is electrically connected to the first complementary read bit line SABLB, the first level signal PCS is transmitted to the first complementary read bit line SABLB, and the second PMOS transistor <p2>Based on the bias voltage V BIAS The first signal terminal is electrically connected to the first readout bit line SABL, and the first level signal PCS is transmitted to the first readout bit line SABL.

[0063] Due to factors such as the formation process, the first PMOS tube <p1>and the second PMOS tube <p2>The device difference is that the first PMOS tube <p1>and the second PMOS tube <p2>The threshold voltage of the first PMOS tube is different. <p1>and the second PMOS tube <p2>Based on the bias voltage V BIAS After being turned on, there is a difference between the voltage of the first sensing bit line SABL and the voltage of the first complementary sensing bit line SABLB.

[0064] Provides an offset cancellation signal OC to electrically connect the initial bit line BL to the first complementary read bit line SABLB, and to electrically connect the initial complementary bit line BLB to the first read bit line SABL. The first NMOS transistor <n1>The voltage of the first complementary readout bit line SABLB is adjusted based on the voltage of the initial bit line BL, and the second NMOS transistor <n2>The voltage of the first sensing bit line SABL is adjusted based on the voltage of the initial complementary bit line BLB.

[0065] When the first offset elimination MOS tube <31> and the second offset cancellation MOS tube <32> After the offset cancellation signal OC is turned on, the initial bit line BL is electrically connected to the first complementary read bit line SABLB and shares a voltage, and the initial complementary bit line BLB is electrically connected to the first read bit line SABL and shares a voltage, so that there is a difference between the initial bit line BL and the initial complementary bit line BLB, thereby achieving offset cancellation of the PMOS tube.

[0066] The voltage of the initial bit line BL is used as the voltage of the first NMOS transistor <n1>The gate voltage turns on the first NMOS transistor <n1>The second signal terminal is electrically connected to the first complementary read bit line SABLB, and the second level signal NCS is transmitted to the first complementary read bit line SABLB. The voltage of the initial complementary bit line BL is used as the voltage of the second NMOS transistor. <n2>The gate voltage turns on the second NMOS transistor <n2>, the second signal end is electrically connected to the first readout bit line SABL, and the second level signal NCS is transmitted to the first readout bit line SABL.

[0067] Due to factors such as the formation process, the first NMOS tube <n1>and the second NMOS tube <n2>The device difference is that the first NMOS tube <n1>and the second NMOS tube <n2>The threshold voltage of the first NMOS tube is different. <n1>and the second NMOS tube <n2>After the first sensing bit line SABL is turned on, the voltage difference between the first sensing bit line SABL and the first complementary sensing bit line SABLB changes.

[0068] When the first offset elimination MOS tube <31> and the second offset cancellation MOS tube <32> After the offset cancellation signal OC is turned on, the initial bit line BL is electrically connected to the first complementary read bit line SABLB and shares a voltage, and the initial complementary bit line BLB is electrically connected to the first read bit line SABL and shares a voltage, thereby synchronizing the voltage difference between the first read bit line SABL and the first complementary read bit line SABLB to the initial bit line BL and the initial complementary bit line BLB, thereby achieving offset cancellation of the NMOS tube.

[0069] Since the first PMOS tube <p1>and the second PMOS tube <p2>Based on a stable bias voltage V BIAS The first sensing bit line SABL and the first complementary sensing bit line SABLB are turned on, that is, the voltage of the first sensing bit line SABL and the first complementary sensing bit line SABLB is kept stable, and the voltage of the initial bit line BL and the initial complementary bit line BLB is further stabilized to avoid voltage fluctuations on the bit line and the complementary bit line, and stably eliminate offset noise in the sense amplifier circuit.

[0070] refer to Figure 1 、 Figure 2 The t2~t3 part in the Figure 5 It can be seen that the charge sharing phase includes: reading the voltage of the target memory cell to the initial bit line BL, and reading the voltage of the target complementary memory cell to the initial complementary bit line.

[0071] Specifically, the bit selection signal WL is provided to read the voltage of the target memory cell to the initial bit line BL, and to read the voltage of the target complementary memory cell to the initial complementary bit line BLB.

[0072] Provide the first isolation signal ISO1 to turn on the first isolation MOS tube <21> , so that the first read bit line SABL is electrically connected to the second read bit line ISABL, so as to synchronize the voltage of the first read bit line SABL to the second read bit line ISABL; provide a first isolation signal ISO1 to turn on the second isolation MOS transistor <22> The first complementary read bit line SABLB is electrically connected to the second complementary read bit line ISABLB, and the voltage of the first complementary read bit line SABLB is synchronized to the voltage of the second complementary read bit line ISABLB.

[0073] During the charge sharing phase, the second isolation signal ISO2 is not provided. At this time, the initial bit line BL is not electrically connected to the first read bit line SABL, and the initial complementary bit line BLB is not electrically connected to the first complementary read bit line SABLB. During this phase, an equalization signal EQ can also be provided to synchronize the voltages of the first read bit line SABL and the first complementary read bit line SABLB to ensure the accuracy of subsequent data reading.

[0074] refer to Figure 1 、 Figure 2 The t3 to t5 part of Figure 6 and Figure 7 It can be seen that in the sensing amplification stage, the voltage higher than the precharge voltage in the initial bit line BL and the initial complementary bit line BLB is pulled up to the voltage corresponding to the first level signal PCS, and the voltage lower than the precharge voltage is pulled down to the voltage corresponding to the second level signal NCS.

[0075] Specifically, the sensing and amplification phase includes a pre-sensing phase and an amplification phase.

[0076] refer to Figure 1 、 Figure 2 The t3~t4 part in the Figure 6 It can be seen that in the pre-sensing stage, the voltage of the initial bit line BL is read to the first and second read bit lines SABL and ISABL, and the voltage of the initial complementary bit line BLB is read to the first and second complementary read bit lines SABLB and ISABLB.

[0077] Specifically, the second isolation signal ISO2 is provided to turn on the third isolation MOS transistor. <23> , so that the initial bit line BL is electrically connected to the first read bit line SABL, so as to read the voltage of the initial bit line BL to the first read bit line SABL, and provide the second isolation signal ISO2 to turn on the fourth isolation MOS transistor <24> , the initial complementary bit line BLB is electrically connected to the first complementary read bit line SABLB, so that the voltage of the initial complementary bit line BLB is read to the first complementary read bit line SABLB.

[0078] Provide the first isolation signal ISO1 to turn on the first isolation MOS tube <21> , so that the first read bit line SABL is electrically connected to the second read bit line ISABL to synchronize the voltage of the first read bit line SABL to the second read bit line ISABL; provide a first isolation signal ISO1 to turn on the second isolation MOS transistor <22> , electrically connecting the first complementary read bit line SABLB to the second complementary read bit line ISABLB, so as to synchronize the voltage of the first complementary read bit line SABLB to the second complementary read bit line ISABLB.

[0079] refer to Figure 1 、 Figure 2 The t4~t5 part in the Figure 7 It can be seen that for the amplification stage, the voltage higher than the pre-charge voltage in the first read bit line SABL and the first complementary read bit line SABLB is pulled up to the voltage corresponding to the first level signal PCS, and the voltage lower than the pre-charge voltage is pulled down to the voltage corresponding to the second level signal NCS, and the voltage of the first read bit line SABL is synchronized to the initial bit line BL, and the voltage of the first complementary read bit line SABLB is synchronized to the initial complementary bit line BLB.

[0080] Specifically, a first isolation signal ISO1, a first level signal PCS and a second level signal NCS are provided to pull a voltage higher than the pre-charge voltage up to a voltage corresponding to the first level signal PCS, and to pull a voltage lower than the pre-charge voltage down to a voltage corresponding to the second level signal NCS.

[0081] At this time, for the first PMOS tube <p1>and the first NMOS tube <n1>, since the first PMOS tube <p1>Gate and first NMOS tube <n1>The connection relationship of the gate is the same, that is, based on the different levels of the second read bit line ISABL, the first PMOS transistor <p1>Or the first NMOS tube <n1>When turned on, the first PMOS tube <p1>and the first NMOS tube <n1>There is only one MOS tube that is turned on; for the second PMOS tube <p2>and the second NMOS tube <n2>, since the second PMOS tube <p2>Gate and second NMOS tube <n2>The connection relationship of the gate is the same, that is, based on the different levels of the second complementary bit line ISABLB, the second PMOS transistor <p2>Or the second NMOS tube <n2>When turned on, the second PMOS tube <p2>and the second NMOS tube <n2>There is only one conducting MOS tube in the circuit.

[0082] Specifically, when the first PMOS tube <p1>After being turned on, the first signal terminal is connected to the first readout bit line SABL, thereby pulling the first readout bit line SABL high to the first level signal PCS, and then pulling the initial bit line BL high to the first level signal PCS, so that the data read out of the memory through the initial bit line BL is a high level corresponding to the logic "1" of the first level signal PCS; when the first NMOS transistor <n1>After being turned on, the second signal terminal is connected to the first read bit line SABL, thereby pulling the first read bit line SABL down to the second level signal NCS, and then pulling the initial bit line BL down to the second level signal NCS, so that the data read out of the memory through the initial bit line BL is the low level of the second level signal NCS corresponding to the logic "0"; when the second PMOS transistor <p2>After being turned on, the first signal terminal is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB high to the first level signal PCS, and then pulling the initial complementary bit line BLB high to the first level signal PCS, so that the data read out of the memory through the initial complementary bit line BLB is a high level corresponding to the first level signal PCS logic "1"; when the second NMOS transistor <n2>After being turned on, the second signal end is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB down to the second level signal NCS, and then pulling the initial complementary bit line BLB down to the second level signal NCS, so that the data read out of the memory through the initial complementary bit line BLB is the low level of the second level signal NCS corresponding to the logic "0".

[0083] A second isolation signal ISO2 is provided to synchronize the voltage of the first read bit line SABL to the initial bit line BL and to synchronize the voltage of the first complementary read bit line SABLB to the initial complementary bit line BLB.

[0084] refer to Figure 1 、 Figure 2 The t5~t6 part in the Figure 8 It can be seen that, for the reset stage, that is, the reset stage after the amplification is completed, its signal timing and circuit structure are the same as those in the pre-charge stage, and will not be described in detail in this embodiment.

[0085] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects achieved in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0086] The above division of the readout stages is only for clarity of description. During implementation, they can be combined into one readout stage or some readout stages can be split and decomposed into multiple readout stages. As long as the timing change of the control signal is the same, they are all within the scope of protection of this patent; adding insignificant modifications or introducing insignificant designs to the readout stage without changing the core design of the readout stage are all within the scope of protection of this patent; ordinary technicians in this field can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

[0087] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A sensing amplifier circuit, arranged between adjacent memory arrays, characterized in that: include: a first PMOS transistor, whose gate is connected to the second readout bit line, whose drain is connected to the first complementary readout bit line, and whose source is connected to the first signal terminal; a first NMOS transistor, having a gate connected to an initial bit line, a drain connected to the first complementary readout bit line, and a source connected to a second signal terminal, wherein the initial bit line is connected to one of the adjacent memory arrays; a second PMOS transistor, whose gate is connected to the second complementary readout bit line, whose drain is connected to the first readout bit line, and whose source is connected to the first signal terminal; a second NMOS transistor, having a gate connected to an initial complementary bit line, a drain connected to the first readout bit line, and a source connected to the second signal terminal, wherein the initial complementary bit line is connected to another adjacent memory array; The first signal end is used to receive a first level signal, and the second signal end is used to receive a second level signal; a first control MOS transistor, whose source is connected to the second readout bit line, whose gate is used to receive a control signal, and whose drain is used to receive a bias voltage, and is used to provide a bias voltage to the first PMOS transistor according to the control signal; a second control MOS transistor, whose source is connected to the second complementary read bit line, whose gate is used to receive the control signal, and whose drain is used to receive the bias voltage, and is used to provide the bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor, having a source connected to the initial bit line, a drain connected to the first complementary read bit line, and a gate for receiving an offset cancellation signal and electrically connecting the initial bit line to the first complementary read bit line according to the offset cancellation signal; a second offset cancellation MOS transistor, having a source connected to the initial complementary bit line, a drain connected to the first readout bit line, and a gate for receiving the offset cancellation signal and electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal; The control signal is the same as the offset cancellation signal.

2. The sensing amplifier circuit according to claim 1, wherein: Also includes: a first isolation unit, one end of which is connected to the first read bit line and the other end of which is connected to the second read bit line, for electrically connecting the first read bit line and the second read bit line according to a first isolation signal; The second isolation unit has one end connected to the first complementary read bit line and the other end connected to the second complementary read bit line, and is used to electrically connect the first complementary read bit line and the second complementary read bit line according to the first isolation signal.

3. The sensing amplifier circuit according to claim 2, wherein: The first isolation unit includes a first isolation MOS transistor, and the second isolation unit includes a second isolation MOS transistor; The source of the first isolation MOS transistor is connected to the first readout bit line, the drain is connected to the second readout bit line, and the gate is used to receive the first isolation signal; The source of the second isolation MOS transistor is connected to the first complementary readout bit line, the drain is connected to the second complementary readout bit line, and the gate is used to receive the first isolation signal.

4. The sensing amplifier circuit according to claim 1, wherein: Also includes: a third isolation unit, one end of which is connected to the initial bit line and the other end of which is connected to the first read bit line, and is used to electrically connect the initial bit line to the first read bit line according to a second isolation signal; A fourth isolation unit has one end connected to the initial complementary bit line and the other end connected to the first complementary readout bit line, and is configured to electrically connect the initial complementary bit line to the first complementary readout bit line according to the second isolation signal.

5. The sensing amplifier circuit according to claim 4, wherein: The third isolation unit includes a third isolation MOS transistor, and the fourth isolation unit includes a fourth isolation MOS transistor. The source of the third isolation MOS transistor is connected to the initial bit line, the drain is connected to the first readout bit line, and the gate is used to receive the second isolation signal; The source of the fourth isolation MOS transistor is connected to the initial complementary bit line, the drain is connected to the first complementary readout bit line, and the gate is used to receive the second isolation signal.

6. The sensing amplifier circuit according to claim 1, wherein: Also includes: An equalization unit has one end connected to the first read bit line and the other end connected to the first complementary read bit line, and is used to make the voltage of the first read bit line the same as the voltage of the first complementary read bit line according to an equalization signal.

7. The sensing amplifier circuit according to claim 6, wherein: The equalization unit includes an equalization MOS transistor, a source of the equalization MOS transistor is connected to the first readout bit line, a drain is connected to the first complementary readout bit line, and a gate is used to receive the equalization signal.

8. A data reading method, applied to the sensing amplifier circuit according to any one of claims 1 to 7, characterized in that: include: The pre-charge phase, offset cancellation phase, charge sharing phase, sense amplification phase and reset phase are executed sequentially; During the precharge phase and the reset phase, the initial bit line, the first read bit line, the second read bit line, the initial complementary bit line, the first complementary read bit line, and the second complementary read bit line in the sense amplifier circuit are precharged to a precharge voltage; In the offset cancellation phase, bias voltages are provided to the first PMOS transistor and the second PMOS transistor of the sense amplifier circuit to eliminate device differences between the first PMOS transistor and the second PMOS transistor, and simultaneously eliminate device differences between the first NMOS transistor and the second NMOS transistor; In the charge sharing phase, the voltage of the target memory cell is read out to the initial bit line, and the voltage of the target complementary memory cell is read out to the initial complementary bit line; In the sensing amplification stage, the voltage of the initial bit line and the initial complementary bit line that is higher than the precharge voltage is pulled up to the voltage corresponding to the first level signal, and the voltage that is lower than the precharge voltage is pulled down to the voltage corresponding to the second level signal.

9. The data reading method according to claim 8, wherein: Precharging the initial bit line, the first readout bit line, the second readout bit line, the initial complementary bit line, the first complementary readout bit line, and the second complementary readout bit line in the sense amplifier circuit to a precharge voltage includes: providing a precharge signal to precharge the initial bit line and the initial complementary bit line to a preset voltage, or to precharge the first read bit line and the first complementary read bit line to a precharge voltage; providing a first isolation signal to electrically connect the first sense bit line to the second sense bit line and to electrically connect the first complementary sense bit line to the second complementary sense bit line; A second isolation signal is provided to electrically couple the initial bit line to the first sense bit line and to electrically couple the initial complementary bit line to the first complementary sense bit line.

10. The data reading method according to claim 8, wherein: Providing a bias voltage to the first PMOS transistor and the second PMOS transistor of the sensing amplifier circuit includes: providing a first level signal to the first signal terminal and providing a second level signal to the second signal terminal; providing the same bias voltage to the gate of the first PMOS transistor and the gate of the second PMOS transistor, so that the first PMOS transistor adjusts the voltage of the first complementary read bit line based on the first level signal, and causes the second PMOS transistor to adjust the voltage of the first read bit line based on the second level signal; An offset cancellation signal is provided to electrically connect the initial bit line to the first read bit line and to electrically connect the initial complementary bit line to the first complementary read bit line. The first NMOS transistor adjusts the voltage of the first complementary read bit line based on the voltage of the initial bit line, and the second NMOS transistor adjusts the voltage of the first read bit line based on the voltage of the initial complementary bit line.

11. The data reading method according to claim 8, wherein: The method of reading the voltage of the target memory cell to the initial bit line and reading the voltage of the target complementary memory cell to the initial complementary bit line during the charge sharing phase includes: providing a bit selection signal to read the voltage of the target memory cell to the initial bit line and to read the voltage of the target complementary memory cell to the initial complementary bit line; A first isolation signal is provided to synchronize the voltage of the first sense bit line to the second sense bit line and to synchronize the voltage of the first complementary sense bit line to the second complementary sense bit line.

12. The data reading method according to claim 8, wherein: The sensing and amplification stage includes: a pre-sensing stage and an amplification stage performed in sequence; In the pre-sensing phase, the voltage of the initial bit line is read out to the first readout bit line and the second readout bit line, and the voltage of the initial complementary bit line is read out to the first complementary readout bit line and the second complementary readout bit line; In the amplification stage, the voltage of the first read bit line and the first complementary read bit line that is higher than the pre-charge voltage is pulled up to the voltage corresponding to the first level signal, and the voltage that is lower than the pre-charge voltage is pulled down to the voltage corresponding to the second level signal, and the voltage of the first read bit line is synchronized to the initial bit line, and the voltage of the first complementary read bit line is synchronized to the initial complementary bit line.

13. The data reading method according to claim 12, wherein: The step of sensing the voltage of the initial bit line to the first complementary read bit line and the second complementary read bit line, and sensing the voltage of the initial complementary bit line to the first read bit line and the second read bit line, comprises: providing a second isolation signal to sense the voltage of the initial bit line to the first sense bit line and to sense the voltage of the initial complementary bit line to the first complementary sense bit line; A first isolation signal is provided to synchronize the voltage of the first sense bit line to the second sense bit line and to synchronize the voltage of the first complementary sense bit line to the second complementary sense bit line.

14. The data reading method according to claim 12, wherein: The step of pulling up the voltage of the first read bit line and the first complementary read bit line, which is higher than the precharge voltage, to a voltage corresponding to the first level signal, and pulling down the voltage of the first read bit line and the first complementary read bit line, to a voltage corresponding to the second level signal, and synchronizing the voltage of the first read bit line to the initial complementary bit line, and synchronizing the voltage of the first complementary read bit line to the initial bit line, comprises: Providing a first isolation signal, the first level signal, and the second level signal, pulling a voltage higher than the pre-charge voltage up to a voltage corresponding to the first level signal, and pulling a voltage lower than the pre-charge voltage down to a voltage corresponding to the second level signal; A second isolation signal is provided to synchronize the voltage of the first read bit line to the initial bit line and synchronize the voltage of the first complementary read bit line to the initial complementary bit line.

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