Ultrathin body array transistor for 4F2

Abstract

The present technique includes a vertical cell array transistor (VCAT) including bit lines arranged in a first horizontal direction and word lines arranged in a second horizontal direction. The array includes channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that the bit lines intersect source / drain regions of the plurality of channels and the word lines intersect gate regions of the plurality of channels. The array includes a channel having at least one source / drain region and a channel body disposed between a first end and a second end. The array includes a channel body having a thickness greater than or about 5% less than a thickness of at least a portion of the at least one source / drain region.

Description

[0001] Cross-reference to related applications

[0002] This application, entitled "ULTRA-THIN BODY ARRAYTRANSISTOR FOR 4F", is to be filed on September 20, 2023. 2 (for 4F) 2 The benefit and priority of U.S. Patent Application No. 63 / 584,065, entitled "Ultra-thin Main Array Transistor", are hereby incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally describes 4F 2 Design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a 4F array with improved buoyancy effect. 2 Memory array. Background Technology

[0004] With advancements in computing technology, computing devices are becoming smaller and more powerful. Correspondingly, there is a need to increase storage devices and memory to meet the programming and computational requirements of these devices. By increasing the number of storage cells with smaller geometries, storage capacity can be increased while simultaneously reducing device size.

[0005] Over time, dynamic random access memory (DRAM) architectures have continued to shrink. For example, the DRAM cell architecture of one transistor and one capacitor (1T-1C) has been successfully scaled down from 8F. 2 Size reduced to 6F 2 Dimensions (where F is the minimum feature size). From 6F 2 Go to 4F 2 Further design modifications could help to further increase the area density. In 4F 2 In DRAM designs, memory nodes (capacitors) and bit lines are located at the top and bottom of the vertical cell transistors, completely isolating the channel from the bulk. The floating body effect is relevant to current 8F DRAM designs. 2 Or 6F 2 For DRAM cell structures, there are no issues due to the main channel connections, but for 4F... 2 For DRAM, this arrangement makes the floating body effect a major technical challenge. Therefore, improvements in this field are needed. Summary of the Invention

[0006] This technology generally relates to vertical cell array transistors (VCATs) and methods of forming such transistors. A VCAT may include one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels extending in a vertical direction substantially orthogonal to the first and second horizontal directions, such that one or more word lines intersect the gate regions of one or more channels. In a VCAT, the one or more channels have at least one source / drain region at a first end, a second end, or both the first and second ends, and a channel body disposed between the first and second ends. The channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the at least one source / drain region.

[0007] In one embodiment, the VCAT includes one or more channels comprising a first source / drain region at a first end and a second source / drain region at a second end, wherein the channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the first and second source / drain regions. Additionally or alternatively, in one embodiment, at least a portion of the source / drain region has a thickness greater than the second portion of the source / drain region. In a further embodiment, at least 20% or about 20% of the at least one source / drain region has a thickness greater than the thickness of the channel body. Furthermore, in one embodiment, at least one source / drain region has a contact end and an internal end, wherein the contact end has a thickness greater than the thickness of the channel body. In one embodiment, the internal end of at least one source / drain region has a thickness substantially equal to the thickness of the channel body. In more embodiments, the channel body has a thickness greater than or about 10% less than the thickness of at least a portion of the first and second source / drain regions. Furthermore, in one embodiment, the channel body has a thickness less than 11 nm. In this embodiment, the channel body has a thickness of less than or about 10 nm.

[0008] This technology also generally relates to vertical cell array transistors, including multiple bit lines arranged in a first horizontal direction, multiple word lines arranged in a second horizontal direction, and multiple channels extending in a vertical direction substantially orthogonal to the first and second horizontal directions, such that the multiple word lines intersect the gate regions of the multiple channels. Each of the multiple channels has a first source / drain region at a first end, a second source / drain region at a second end, and a channel body disposed between the first end and the second end. The channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the first source / drain region and the second source / drain region.

[0009] This technology also generally relates to methods for forming vertical cell array transistors. The method includes etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels. The method includes depositing a first protective dielectric material in a shallow trench isolation adjacent to a first source / drain region at a first end of a vertically extending channel. The method includes depositing a sacrificial dielectric material over the first protective dielectric material. The method further includes depositing a second protective dielectric material over a sacrificial dielectric material adjacent to a second source / drain region at a second end of a vertically extending channel. The method includes removing the sacrificial material and reducing the thickness of one or more channel bodies of the vertically extending channels, wherein the channel bodies are disposed between the first source / drain region and the second source / drain region.

[0010] In one embodiment, the method includes etching a second protective dielectric material to form a support mesh. Additionally or alternatively, the method includes reducing the thickness of a portion of the first source / drain region, the second source / drain region, or a combination thereof. In a further embodiment, the first protective dielectric material is deposited from a first end to a height substantially coplanar with or less than the top surface of the first source / drain region. In more embodiments, a sacrificial dielectric material is deposited from the top surface of the first protective dielectric material to a height greater than or substantially coplanar with the bottom surface of the second source / drain region. In another embodiment, the second protective dielectric material is deposited to extend from a height greater than or substantially coplanar with the bottom surface of the second source / drain region to a second end of a vertically extending channel. In more embodiments, the method further includes removing the first and second protective dielectric materials, and depositing a gate dielectric layer and gate metal around the periphery of one or more shallow trench isolations. Furthermore, in one embodiment, the thickness of the channel body is reduced by more than 5% or about 5%. In a further embodiment, reducing the thickness of the channel body includes selective silicon etching, oxidation, and wet etching, or a combination thereof. In another embodiment, the method includes: wherein the sacrificial dielectric material comprises a material that can be selectively etched without etching the first protective dielectric material and the second protective dielectric material.

[0011] Compared to traditional systems and technologies, this technology offers numerous advantages. For example, the process and system can distribute cavities across multiple channels holistically, thereby reducing the cavitation effect. Furthermore, the process and system can significantly reduce 4F. 2 Hole accumulation in the body of the DRAM device. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying drawings. Attached Figure Description

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the accompanying drawings.

[0013] Figure 1A A top plan view of an exemplary processing chamber according to an embodiment of the present technology is shown.

[0014] Figure 1B Showing the traditional 4F 2 Top view of the memory array.

[0015] Figure 1C Showing the traditional 4F 2 Perspective view of the memory array.

[0016] Figure 2 Selected operations in the formation method according to an embodiment of the present technology are shown.

[0017] Figure 3A A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, which is filled with dielectric material after shallow trench isolation is formed.

[0018] Figure 3B A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, which is patterned for the formation of a second shallow trench isolation.

[0019] Figure 3C A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, having a protective dielectric surrounding a first source / drain region.

[0020] Figure 3D A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, having sacrificial spacers in shallow trench isolation.

[0021] Figure 3E A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, having a second protective dielectric with a supporting grid pattern surrounding a second source / drain region.

[0022] Figure 3F A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, having a second protective dielectric etched to expose sacrificial spacers.

[0023] Figure 3G A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, wherein sacrificial spacers are removed.

[0024] Figure 3H A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, having a thinned channel.

[0025] Figure 3IA perspective view of a semiconductor structure according to an embodiment of the present technology is shown, wherein the first and second protective dielectric materials are removed.

[0026] Figure 3J A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, wherein word lines are etched, shallow trench isolation is filled, and source / drain regions are formed.

[0027] Figure 3K A perspective view of a semiconductor structure according to an embodiment of the present technology is shown, in which bit line contacts are formed.

[0028] The accompanying drawings include multiple figures for illustrative purposes. It should be understood that these figures are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, the accompanying drawings include multiple figures for illustrative purposes and may not include all aspects or information compared to a true representation, and may also include exaggerated material for illustrative purposes.

[0029] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by letters following the reference numerals to differentiate between similar parts. If only the first reference numeral is used in the description, the description applies to any similar part having the same first reference numeral, regardless of the letters used. Detailed Implementation

[0030] Historically, DRAM chip bit density has increased by approximately 25% per node. However, in recent generations, this node-wise increase has slowed to around 20%, primarily due to the challenges posed by expanding cell area. Modern DRAM technology's cell design architecture has consistently been based on 6F. 2 Geometry, where "F" is the minimum feature size for a specific technology node. For example, 6F... 2 Convert to 4F 2 The cell architecture can increase the bit density of the same technology node by 33%. Furthermore, compared to 6F... 2 Compared to 4F 2 The patterning difficulty of DRAM has been greatly reduced. This is at least partly due to the fact that in 4F... 2 In DRAM designs, capacitors and bit lines are located at the ends of vertical cell transistors, rather than as in 6F. 2 They are arranged closely on the same side, like DRAM.

[0031] However, 4F 2 DRAM design also presents its own challenges. For example, 4F 2Memory cells have transistor channels positioned between the bit lines and the capacitor layer, without a common substrate connecting the channels, causing these transistors to exhibit a floating body effect. For example, it is believed that traditional 4F... 2 DRAM devices can experience off-leakage issues. Off-leakage is caused by the floating body effect, for example, due to channel isolation, 4F... 2 Holes accumulate in the body of a DRAM device. Electron-hole pairs form in the semiconductor channel due to interband tunneling. While electrons can flow into the n-type source or drain regions of the transistor, holes cannot. For 4F without substrate bonding... 2 In DRAM devices, holes have no path to leave the channel and accumulate continuously. Therefore, the floating body effect can lead to channel activation without gate activation, which ultimately translates to leakage current from capacitors or the data memory side of the device. Some have attempted to provide body connectivity using buried body contact schemes. However, this approach can result in the gate overlapping with the source / drain junction edge, leading to undesirable gate-induced drain leakage or limiting scalability to smaller sizes.

[0032] Furthermore, some have attempted to reduce the buoyancy effect by decreasing the width of the channel body. For example, a channel body with reduced thickness allows for an interface suitable for minority carrier recombination. However, this approach also results in a smaller source / drain region thickness and therefore a smaller contact area, causing the thickness or width of the source / drain region to fall below a critical value. Attempts to widen the source / drain region have proven difficult to achieve due to the complex epitaxial growth and photolithography steps required, leading to inconsistent and inefficient results.

[0033] This technology overcomes these and other problems by providing a vertical channel array transistor (VCAT) with a reduced channel body width, and eliminates the need to grow or add source / drain regions to the channel. In other words, this technology surprisingly discovers that by utilizing one or more protective dielectric materials, the source / drain regions (or planned source / drain regions) can be protected, allowing for a reduction in channel body thickness without reducing the thickness or width of all or part of the source / drain regions. Therefore, a VCAT according to this technology can have source / drain regions formed at or above the critical dimensions necessary for the contact width, while also exhibiting a channel body with a width smaller than the source / drain regions. Furthermore, this technology provides methods and systems for providing such a VCAT that do not require complex processing steps such as photolithography and / or epitaxial growth of doped materials. Moreover, this technology also finds that a support mesh can be utilized during processing to further protect the semiconductor, which can be particularly beneficial for high aspect ratio features and devices incorporating such features.

[0034] Although the remaining disclosures will routinely specify the transistors used to form vertical cell arrays (VCATs) (such as 4F... 2 While this disclosure describes specific deposition and etching processes for DRAM devices, it is readily understood that these systems and methods are equally applicable to other DRAM devices, including gate-all-around and Schottky barrier VCAT devices, other devices affected by the floating body effect and their orientation, and the processes used to form such devices. Therefore, this technology should not be considered limited to use with these specific devices or systems. Before making additional changes and adjustments to the device according to embodiments of this technology, this disclosure will discuss a possible semiconductor device that may include one or more components utilizing one or more channels according to embodiments of this technology.

[0035] Figure 1AA top plan view of a multi-chamber processing system 100 is shown. The multi-chamber processing system 100 can be specifically configured to implement aspects or operations of some embodiments according to the present technology. The multi-chamber processing system 100 can be configured to perform one or more manufacturing processes on a single substrate (e.g., any number of semiconductor substrates) to form a semiconductor device. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer loading locks 110 and 112 (and possibly dual-wafer loading locks), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. Processing chambers 122 and 124 may be attached to buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108, facilitating transfer between robots 126 and 128. Platforms 102 and 104 may be open to both the transfer chambers and buffer chambers, or the platforms may be selectively isolated from or sealed to allow for different operating pressures to be maintained between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, for example, for orientation or measurement operations.

[0036] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any means or combination of means configured to perform the operations described below. Therefore, the computer system 130 may be a controller or controller array and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, performs the operations described in the methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in semiconductor structure fabrication. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a variety of substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0037] Figure 1B and Figure 1C Showing the traditional 4F 2Top and perspective views of a memory array 150. The memory array 150 may include multiple word lines 152 disposed in a first layer on a substrate. The word lines 152 may be conductive traces for selecting memory cells in the memory array 150. The memory array 150 may also include multiple bit lines 154 disposed in a second layer on the substrate. The multiple bit lines may be conductive traces for selecting memory cells in the memory array 150. Activating one of the multiple bit lines 154 and one of the multiple word lines 152 selects a single cell in the memory array 150. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having word lines 152 may be formed over the second layer having bit lines 154 such that the two layers do not intersect.

[0038] Multiple vertical memory cells can be arranged at the intersection of multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or a vertical column transistor. The channel material of the transistor may be formed from a single-crystal silicon pillar or from any other substrate discussed in detail below. Such a silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell can be operated by storing charge on the vertical capacitor 156 to indicate the saved memory state. However, although Figure 1B and Figure 1C The illustration depicts the arrangement of vertical transistors and capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" can be within approximately 10° of orthogonality, for example, less than or approximately 7.5°, for example, less than or approximately 5°, for example, less than or approximately 2.5°, for example, less than or approximately 1°, or any range or value between the two; "generally" can be used to similarly vary "vertical," "horizontal," etc.). It should be understood that other orientations may be considered in this technique. For example, in one embodiment, capacitors and vertical transistors may be spaced in alternating rows offset by half the distance between the vertical transistors. That is, in one embodiment, the first row of memory cells may be regularly spaced along a line in a first direction, and the second row of memory cells may also be regularly spaced along a line in the first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, aligned approximately halfway between the vertical transistors and capacitors in the first row. Figure 1B and Figure 1C Compared to the square pattern shown, this pattern can be called a "honeycomb" or "hexagonal pattern". Therefore, it should be understood that this technique can utilize any suitable orientation.

[0039] To characterize this conventional 4F... 2 The size of the unit cell region 166 of the memory array is very useful. For example, the capacitor footprint region 158 can be defined as a circular region surrounding each vertical capacitor 156. The capacitor footprint region 158 can include the horizontal cross-sectional area of ​​the capacitor until the cross-sectional area contacts the capacitor region of the adjacent memory cell. Assume that the word line spacing 162 of the multiple word lines 152 and the bit line spacing 164 of the multiple bit lines 154 can be defined as 2F. Thus, the total cross-sectional area of ​​the unit cell region 166 is 4F. 2 .

[0040] Figure 2 Exemplary operations in method 200 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formations, but these operations are not critical to the present technology or may be performed by easily understood alternative methods. Furthermore, while the method may be described vertically as a formation method, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0041] Method 200 may include additional operations prior to initiating the listed operations. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The previous processing operations may be performed in a chamber in which method 200 is performed, or the processing operations may be performed in one or more other processing chambers before the substrate is transported to the semiconductor processing chamber in which method 200 is performed. In any case, method 200 may optionally include transporting the semiconductor substrate to a processing region of the semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include the components described above. The substrate may be deposited on a substrate support / transfer platform, which may be a base, such as substrate support 104, and may reside in a processing region of the chamber, such as the processing region of processing chamber 120 described above. Method 200 describes... Figures 3A-3K The operations illustrated herein will be described in conjunction with the operations of method 200. It should be understood that... Figures 3A-3K Only partial schematic diagrams are shown. The semiconductor substrate may include further components and alternative components of any size or configuration shown in the diagram, which may still benefit from various aspects of the present technology.

[0042] Method 200 may or may not involve optional operations to develop the semiconductor structure to a specific manufacturing operation. It should be understood that method 200 can be performed on any number of semiconductor structures 300 or substrates 302, such as... Figures 3A-3K As shown, an exemplary structure is included, on which selectively deposited materials can be formed. (As illustrated...) Figure 3A As shown, substrate 302 can be any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing.

[0043] In an embodiment, structure 300 may be a semiconductor substrate, including a bulk substrate, an epitaxial growth substrate, and / or a silicon-on-insulator wafer. As used herein, the term "semiconductor substrate" refers to a substrate whose entire substrate is made of semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, semiconductor substrate 300 comprises semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, substrate 302 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which substrates may be formed are described herein, any material that can serve as the basis for the construction of passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is within the spirit and scope of this disclosure.

[0044] In implementations, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In implementations, the substrate can be doped using any suitable process, such as ion implantation. As used herein, the term "n-type" refers to a semiconductor produced during manufacturing by doping an electron donor element into an intrinsic semiconductor. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). Compared to an n-type semiconductor, a p-type semiconductor has a greater hole concentration than an electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0045] like Figure 3A As shown, a structure 300 is provided, comprising a substrate 302 having undergone source / drain 304 formation and shallow trench isolation 308 formation, and a first dielectric material 306 filled within the shallow trench isolation 308. However, it should be understood that in this embodiment, the first source / drain regions 304 may also be formed after the front-side processing is completed. Furthermore, two or more sidewalls 305 are formed between the respective first shallow trench isolations 308, wherein the illustrated sidewalls 305 are spaced in horizontally extending rows generally perpendicular to the word line direction in this embodiment. However, as those skilled in the art will understand, in this embodiment, the shallow trench isolation may first be cut in a direction generally parallel to the word line direction. In this embodiment, the dielectric material 306 may be any one or more of the dielectric materials discussed herein, such as silicon oxide or silicon nitride, or may be a low-k dielectric, or a combination thereof.

[0046] In an implementation, when the source / drain 304 is formed as part of a front-end processing, the formation may include one or more ion implantations followed by an annealing process. The implantation process may be a single implantation or may include a series of multiple implantations. When using multiple implantations, each implantation may utilize the same ions or different ions. However, it should be understood that the source / drain region 304 can be formed by any suitable processing procedure. The method may include providing a semiconductor structure having a first source / drain region 304 for multiple vertical channels and forming multiple word lines in contact with the first source / drain region. Generally, the process can progressively form each stage of the transistor based on a previously completed stage.

[0047] In an implementation, the source / drain region 304 and the channel body 348 (before thinning) may have a thickness t greater than 11 nm, for example greater than or about 12 nm, for example greater than or about 13 nm, for example greater than or about 14 nm, for example greater than or about 15 nm, for example greater than or about 16 nm, for example greater than or about 17 nm, for example greater than or about 18 nm, for example greater than or about 18 nm, for example greater than or about 19 nm, for example greater than or about 20 nm, for example greater than or about 21 nm, for example greater than or about 22 nm, for example greater than or about 23 nm, for example greater than or about 24 nm, or for example about 40 nm or less, for example about 35 nm or less, for example about 30 nm or less, for example about 25 nm or less, or any range or value between the two.

[0048] Furthermore, while various deposition and filling processes will be described, it should be understood that, in embodiments, semiconductor structures can be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124, configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or similar chambers. Therefore, unless specifically stated otherwise, it should be understood that any one or more of the above methods known in the art may be employed. Similarly, semiconductor structures can be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0049] Nevertheless, in operation 201, method 200 may include forming such as Figure 3A The first shallow trench isolation and the second shallow trench isolation 346 are shown. For example, in one embodiment, the substrate 302 can be loaded into loading locks 110, 112 and transferred to a processing chamber (e.g., processing chamber 114) by robots 126, 128, wherein the semiconductor structure 300 can undergo mask 340 formation and second shallow trench isolation 346 formation at operation 201, which may also be referred to herein as word line trench formation, since the second shallow trench isolation 346 can extend in a generally horizontal direction generally parallel to the word line direction. For example, Figure 3BA forming mask 340 is shown, which can be any patterned mask known in the art, and in an embodiment, the sidewalls 305 are etched into channels 348 by etching in a direction extending substantially perpendicular to the first horizontal direction in a second horizontal direction using the mask 340. That is, as discussed above with respect to the formation of shallow trench isolation 308 between sidewalls 305, isolation between channels 348 can be formed using a pattern or mask 340 defining a second shallow trench isolation 346, in this embodiment, the channels 348 extending parallel to or in the plane of the word lines, formed by an etching process. The resulting channels 348 can have a uniform or non-uniform width, and / or a width substantially equal to that of the sidewalls 305. The second shallow trench isolation 346 can serve to isolate adjacent channels 348. Therefore, as Figure 3A and Figure 3B As shown, a semiconductor structure 300 including first and second shallow trench isolations can be provided, wherein the first shallow trench isolation may include a deposited or filled dielectric material as described above. It should be understood that the substrate may be transferred between each operation step or only between a portion of the operation steps, since some operation steps may be performed in the same processing chamber.

[0050] like Figure 3C As shown, at operation 202, a first protective dielectric material 350 may be formed at a first end 314 adjacent to one or more corresponding word line trenches 346 in a row extending along a second horizontal direction (e.g., such that the gate dielectric material 350 is substantially parallel to the word line direction). The first protective dielectric material 350 may be any one or more dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials known in the art, formed using any filling method discussed above and known in the art. Although silicon oxide or silicon nitride will be discussed periodically as dielectric and / or spacer materials in the following description, it should be understood that any number of dielectric materials may be used in embodiments of the present technology, and the present technology should not be limited to any particular dielectric material that can form features. However, as will be discussed in detail below, it should be understood that other materials may also be used at operation 202.

[0051] Despite the above method, the first protective dielectric material 350 can be deposited at a height that extends from the first end 314 of the corresponding shallow trench isolation 346 to a height h that is substantially coplanar with or lower than the top surface 316 of the source / drain region 304. That is, in the embodiment, the first protective dielectric material 350 can be deposited at a height h to protect some or all of the first source / drain region 304 from one or more etching processes. Therefore, in an embodiment, the first protective dielectric material 350 can be deposited at a height that can be at least about 20% of the distance between the first end 314 of the shallow trench isolation 346 and the top surface 316 of the first source / drain region 304, for example, greater than or about 30%, greater than or about 40%, greater than or about 50%, greater than or about 60%, greater than or about 70%, greater than or about 75%, greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 95%, greater than or about 99%, or less than or about 99.9%, less than or about 99%, less than or about 95%, less than or about 90%, less than or about 85%, less than or about 80%, less than or about 75%, or any range or value between the two. In this way, all or a portion of the width of the source / drain region 304 can be maintained during one or more etching processes.

[0052] Operation 202 may also include depositing a sacrificial dielectric material 352 over the first protective dielectric material 350. Figure 3D In this embodiment, the sacrificial dielectric material 352 is shown deposited directly over the first protective dielectric material 350. However, in other embodiments, one or more layers may exist between the first protective dielectric material 350 and the sacrificial dielectric material 352. The sacrificial dielectric material can be any oxide, patterning material (such as a carbon-containing patterning material), or a combination thereof, as well as other sacrificial materials known in the art. That is, in other embodiments, the sacrificial dielectric material 352 may be selected to be easily etchable while preserving the first protective dielectric material 350 and the second protective dielectric material 354.

[0053] Nevertheless, the sacrificial dielectric material 352 can be deposited at a height h2, which extends from the top surface 318 (e.g., the inner surface) of the first protective dielectric material to the top surface 312 of the shallow trench isolation 346 and the second source / drain region 324 (e.g., the inner surface). Figure 3J and Figure 3KA height between the coplanar planes of the bottom surface 320 of the second source / drain region 324 (as shown) (or the planned source / drain region). In this way, all or part of the second source / drain region 324 (or the planned second source / drain region) can be protected during the thinning operation of the channel body 348 or other etching processes. Therefore, in an embodiment, the sacrificial dielectric material 352 can be deposited at a height that extends at least about 10%, for example greater than or about 15%, for example greater than or about 20%, for example greater than or about 25%, for example greater than or about 30%, for example greater than or about 35%, for example greater than or about 40%, for example greater than or about 45%, for example greater than or about 50%, or for example less than or about 75%, or for example less than or about 70%, for example less than or about 65%, for example less than or about 60%, for example less than or about 55%, for example less than or about 50%, for example less than or about 45%, for example less than or about 40%, or any range or value between the two. However, in an embodiment, the sacrificial dielectric material 352 can be deposited to a height that is substantially coplanar with the bottom surface 320 of the second source / drain region 324. In this way, all or part of the width of the source / drain region 324 can be maintained during one or more etching processes.

[0054] Operation 202 may also include depositing a second protective dielectric material 354 over the sacrificial dielectric material 354. Figure 3E In this embodiment, the second protective dielectric material 354 is shown deposited directly over the sacrificial dielectric material 352. However, in some embodiments, one or more layers may exist between the second protective dielectric material 354 and the sacrificial dielectric material 352. The second protective dielectric material 354 can be any one or more dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials known in the art, formed using any filling method discussed above and known in the art. However, as will be discussed in detail below, it should be understood that other materials may also be used in operation 202. Furthermore, in some embodiments, the first protective dielectric material 350 and the second protective dielectric material 354 can be the same or separate different materials selected from one or more of the aforementioned dielectric materials. Nevertheless, in some embodiments, the first protective dielectric material 350 and the second protective dielectric material 354 may be selected to be retained during the etching of the sacrificial dielectric material 352. Therefore, in the embodiments, the first protective dielectric material 350 and / or the second protective dielectric material 354 may be materials that are selective for the sacrificial material 352.

[0055] Despite the selection of the aforementioned material, the second protective dielectric material 354 is typically deposited on the upper surface of the sacrificial material. Furthermore, the second protective dielectric material may typically be deposited to exhibit a height that protects all or part of the second source / drain region 324. Therefore, in an embodiment, the second protective dielectric material 354 may extend from the top surface 322 of the sacrificial dielectric material to the top surface 312 of the shallow trench isolation 346. In an embodiment, the height h3 of the second protective dielectric material 354 may extend from the height between the top surface 312 and the top surface 316 of the source / drain region 304 to the top surface 312. That is, in an embodiment, the second protective dielectric material 354 may be deposited at a height h3 to protect some or all of the second source / drain region 324 from one or more etching processes. Therefore, in this embodiment, the second protective dielectric material 354 can be deposited at least about 40% of the height of the distance from the bottom surface 320 of the second source / drain region 324 to the top surface 312 of the shallow trench isolation 346, for example, greater than or about 50%, greater than or about 60%, greater than or about 70%, greater than or about 75%, greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 95%, greater than or about 99%, or less than or about 99.9%, less than or about 99%, less than or about 95%, less than or about 90%, less than or about 85%, less than or about 80%, less than or about 75%, or any range or value between the two. In this way, all or part of the width of the source / drain region 304 can be maintained during one or more etching processes. However, in this embodiment, the second protective dielectric material 354 can be deposited over the adjacent channel and thus extend over the top surface 312 before the trench is formed.

[0056] In other words, the first protective dielectric material 350 and the second protective dielectric material 354 can be discharged from the contact surfaces 326, 328 of their respective source / drain regions (in... Figure 3K (As shown more clearly in the image) extending toward the inner surface of the respective source / drain regions 304, 324, the distance being at least 30% of the height h4 of the respective source / drain region, for example greater than or about 35%, for example greater than or about 40%, for example greater than or about 45%, for example greater than or about 50%, for example greater than or about 55%, for example greater than or about 60%, for example greater than or about 65%, for example greater than or about 70%, for example greater than or about 75%, or less than or about 100%, for example less than or about 95%, for example less than or about 90%, for example less than or about 85%, for example less than or about 80%, or any range or value between the two.

[0057] Regardless of the material chosen, in optional operation 203, a support grid 330 can be formed from the second protective dielectric material 354, which can provide additional structural stability to the semiconductor structure for further etching processes. Figure 3E As shown, a patterned mask 356 (which may be the same as or different from mask 340) may be applied over the second protective dielectric material 354. As illustrated, the mask may be deposited to extend across the semiconductor structure generally parallel to the word line direction to provide additional support for the shallow trench isolation 346 spaced apart in the word line direction. Although four mask 356 patterns are illustrated, it should be clearly understood that more or fewer patterns may be used as needed to provide support while still allowing access to the sacrificial dielectric material 354.

[0058] Nevertheless, after forming the patterned mask 356, as Figure 3F As shown, the exposed portion of the second protective dielectric material 354 can be removed. In embodiments, the exposed portion of the second protective dielectric material 354 can be removed by etching, bottom punching, other methods known in the art, or a combination thereof. As shown, the method used allows the second protective dielectric layer 354 to remain extending in the bit line direction (e.g., generally perpendicular to the word line direction) and surrounding the connection row of the second source / drain region 324, while exposing the sacrificial dielectric material 352 between adjacent rows. However, it should be understood that in embodiments, the second protective dielectric material 354 can be deposited within a shallow trench isolation 346 without the need to form a trench.

[0059] Following operation 202 or optional operation 203, the sacrificial dielectric material 352 can be removed in operation 204, while retaining the first protective dielectric material 350 and the second protective dielectric material 354, as follows. Figure 3G As shown. That is, since the first protective dielectric material 350 and the second protective dielectric material 354 are selective for the sacrificial dielectric material 352, the sacrificial dielectric material 352 can be easily removed using methods known in the art without damaging the channel body 348, the first source / drain region 304, and / or the second source / drain region 324. For example, in embodiments, removal may include selective wet etching, vapor phase etching, plasma etching, etc., to remove the sacrificial film 352.

[0060] like Figure 3HAs shown, after removing the sacrificial dielectric material 352, in operation 205, the thickness of one or more of the channel bodies 348 can be thinned or reduced by etching the exposed sidewalls 305 of the channel bodies 348. In other words, the first source / drain region 304 and the second source / drain region 324 can maintain their initial thickness t, while one or more channel bodies 348 are thinned from the initial thickness t to a second thickness t2. In embodiments, the second thickness t2 can be greater than or less than thickness t by about 5%, for example, greater than or less than about 7.5%, for example, greater than or less than about 10%, for example, greater than or less than about 12.5%, for example, greater than or less than about 15%, for example, greater than or less than about 20%, for example, greater than or less than about 25%, for example, greater than or less than about 30%, for example, greater than or less than about 35%, for example, greater than or less than about 40%, for example, greater than or less than about 45%, for example, greater than or less than about 50%, for example, greater than or less than about 55%, for example, greater than or less than about 60%, for example, greater than or less than about 65%, or any range or value between the two. In an embodiment, a portion of one or more source / drain regions 304, 324 may also be thinned according to the aforementioned amounts. In such an embodiment, the height h4 of the respective source / drain region may be thinned to less than or about 40%, for example less than or about 35%, for example less than or about 30%, for example less than or about 25%, for example less than or about 20%, for example less than or about 15%, for example less than or about 10%, for example less than or about 5%, or any range or value between the two.

[0061] In other words, in the implementation, the second thickness t2 can be less than 11 nm, for example less than or about 10.5 nm, for example less than or about 10 nm, for example less than or about 9.5 nm, for example less than or about 9 nm, for example less than or about 8.5 nm, for example less than or about 8 nm, for example less than or about 7.5 nm, or any range or value between the two.

[0062] In implementations, selective silicon etching can be used to reduce thickness. Alternatively or additionally, depending on the materials selected for the first protective dielectric 350 and the second protective dielectric 354, the silicon of the channel body 348 may be oxidized and wet-etched. Nevertheless, it should be understood that other methods (or combinations of one or more methods) for thinning the channel body 348 may be selected based on selectivity for the channel body 348, but not for the first protective dielectric 350 and the second protective dielectric 354.

[0063] After reducing the thickness of the channel body 348 in operation 205, in operation 206, the first protective dielectric material 350 and the second protective dielectric material 354 can be removed, such as Figure 3IAs shown. Therefore, semiconductor structure 300 can be re-entered into VCAT devices (such as 4F). 2 The normal processing flow of DRAM arrays.

[0064] For example, refer to Figure 3J A gate dielectric 342 may be deposited generally along the outer periphery of the shallow trench isolation 346. The gate dielectric 342 may be any one or more of the aforementioned dielectric materials, and in some embodiments may be an oxide. Furthermore, a gate material 344 may be deposited generally along the outer periphery of the gate dielectric 342 lining the shallow trench isolation 346 over the gate dielectric 342. The gate material may be a material such as a low-resistivity metal, including tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or combinations thereof. Nevertheless, as shown, after depositing the gate dielectric 342 and gate metal 344, the bottom of the gate dielectric 342 and gate metal 344 adjacent to the substrate 302 may be removed, for example by polishing or bottom punching, to isolate adjacent word lines. Additionally, in some embodiments, a fill dielectric 360 may be introduced between adjacent gate metals 344. Nevertheless, a second source / drain region 324 may be formed adjacent to the top surface 312, such as by ion implantation or any other method discussed above with respect to the first source / drain region 304.

[0065] However, in the embodiments, it should be understood that one or both of the first source / drain region 304 and the second source / drain region 324 may also be formed as Schottky contacts. That is, in the embodiments, such contacts as source / drain regions can further reduce minority carrier injection and reduce the floating body effect, thereby further reducing leakage current. For example, metal silicides may be formed as one or more source / drain regions. In such embodiments, the first or second source / drain regions 304, 324 may undergo metallization, such as silicide treatment, to form a metallized interface. For example, a metal layer may be applied to the first or second source / drain regions 304, 324 subsequently exposed to the silicide treatment process. In the embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Therefore, the formed interface may be any one or more of the aforementioned metals and channel materials (such as silicon) as metallized layers. In such examples only, the interface layer may be titanium silicide, molybdenum silicide, hafnium silicide, or a combination thereof. The contacts may also include one or more ion implantations, such as ion implantations of boron, phosphorus, arsenic, or some other material, to create a barrier height greater than or about 0.60 V, and may create barrier heights greater than or about 0.65 V, greater than or about 0.70 V, greater than or about 0.75 V, greater than or about 0.80 V, greater than or about 0.85 V, or higher.

[0066] Despite using different doping methods, the final structure can be as follows: Figure 3K The illustration shows that, surprisingly, this technology allows for the use of a relatively thicker word line metal 344 for thinning the channel body 348 without increasing the spacing of the semiconductor structure. In other words, as shown... Figure 3K As shown, because the body 348 is thinner than the source and drain contacts 324 and 326, a thicker word line material can be formed without contacting adjacent word lines or bearing the risk of short circuits due to lack of isolation. Therefore, the semiconductor structure of this technology not only reduces the floating body effect but also provides lower resistivity.

[0067] Regardless of how or when the source / drain regions 304 and 324 are formed, the semiconductor structure 300 can be re-entered into a vertical cell DRAM array (such as 4F). 2 The DRAM array follows the normal process flow and undergoes one or more further processing steps. For example, the semiconductor structure may undergo contact redistribution, bonding pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure can still exhibit reduced gate floating body effect and / or word line resistivity.

[0068] It should be understood that the specific steps illustrated in the figures provide a method for forming a 4F according to various implementations. 2 A specific method for DRAM arrays. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments may perform the above steps in a different order. Furthermore, each step shown in the figures may include multiple sub-steps, which may be performed in different orders depending on the specific application. Additionally, extra steps may be added or removed depending on the application. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0069] The terms “about,” “approximately,” or “substantially” as used herein are to be interpreted as within the range that a person skilled in the art would expect from the specification.

[0070] In the foregoing description, numerous specific details have been listed for ease of explanation, in order to provide a thorough understanding of the various implementations. However, it will be apparent that some implementations can be carried out without some of these specific details. In other cases, well-known structures and apparatuses are represented in block diagram form.

[0071] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments will provide an advantageous disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of some of the embodiments set forth in the appended claims.

[0072] Specific details have been provided in the foregoing description to offer a thorough understanding of the implementation. However, it is understood that implementations can be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form to avoid obscuring the implementation with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary details to avoid obscuring the implementation.

[0073] Furthermore, it should be noted that each implementation can be described as a process, which may be represented by a flowchart, data flow diagram, structure diagram, or block diagram. While a flowchart may describe operations as a sequential process, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates upon completion of its operations, but there may be additional steps not included in the diagram. A process can correspond to a method, a function, a procedure, a subroutine, a subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0074] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and other media capable of storing, containing, or carrying instructions and / or data. Code segments or machine-executable instructions can represent any combination of procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuitry by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., can be passed, forwarded, or transmitted in any suitable manner, including memory sharing, message passing, token passing, network transmission, etc.

[0075] Furthermore, the implementation can be carried out using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented using software, firmware, middleware, or microcode, the program code or code segments that perform the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0076] In the foregoing description, features have been described with reference to specific embodiments thereof, but it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or in combination. Furthermore, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Therefore, this specification and accompanying drawings should be considered illustrative rather than restrictive.

[0077] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, the methods may be performed in a different order. It should also be understood that the methods described above can be executed by hardware components or implemented as a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or logic circuit programmed with instructions) to execute these methods. These machine-executable instructions may be stored on one or more machine-readable media, such as optical discs or other types of optical discs, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods may also be executed by a combination of hardware and software.

Claims

1. A vertical cell array transistor (VCAT), comprising: One or more bit lines arranged in the first horizontal direction; One or more letter lines arranged in the second horizontal direction; One or more channels extend in a vertical direction that is substantially orthogonal to the first horizontal direction and the second horizontal direction, such that the one or more word lines intersect the gate region of the one or more channels; The one or more channels have at least one source / drain region at a first end, a second end, or both of the first and second ends of the one or more channels, and a channel body disposed between the first end and the second end, wherein the channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the at least one source / drain region.

2. The vertical cell array transistor (VCAT) of claim 1, wherein the one or more channels include a first source / drain region at a first end and a second source / drain region at a second end, wherein the channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the first source / drain region and the second source / drain region.

3. The vertical cell array transistor (VCAT) of claim 1, wherein at least a portion of the at least one source / drain region has a thickness greater than a second portion of the at least one source / drain region.

4. The vertical cell array transistor (VCAT) of claim 1, wherein more than 20% or about 20% of the at least one source / drain region has a thickness greater than the thickness of the channel body.

5. The vertical cell array transistor (VCAT) of claim 4, wherein the at least one source / drain region has a contact end and an internal end, wherein the contact end has a thickness greater than the thickness of the channel body.

6. The vertical cell array transistor (VCAT) of claim 5, wherein the inner terminal has a thickness substantially equal to the thickness of the channel body.

7. The vertical cell array transistor (VCAT) of claim 2, wherein the channel body has a thickness greater than or about 10% less than the thickness of at least a portion of the first source / drain region and the second source / drain region.

8. The vertical cell array transistor (VCAT) of claim 1, wherein the channel body has a thickness of less than 11 nm.

9. The vertical cell array transistor (VCAT) of claim 8, wherein the channel body has a thickness of less than or about 10 nm.

10. A vertical cell array transistor (VCAT), comprising: Multiple bit lines arranged in the first horizontal direction; Multiple letter lines arranged in the second horizontal direction; Multiple channels extend in a vertical direction that is substantially orthogonal to the first horizontal direction and the second horizontal direction, such that the multiple word lines intersect with the gate regions of the multiple channels; Each of the plurality of channels has a first source / drain region at a first end, a second source / drain region at a second end, and a channel body disposed between the first end and the second end, wherein the channel body has a thickness greater than or about 5% less than the thickness of at least a portion of the first source / drain region and the second source / drain region.

11. A method for forming a vertical cell array transistor (VCAT), comprising: The substrate is etched to form one or more shallow trench isolations and multiple vertically extending channels; A first protective dielectric material is deposited in the shallow trench isolation adjacent to the first source / drain region at the first end of the vertically extending channel; A sacrificial dielectric material is deposited on top of the first protective dielectric material; A second protective dielectric material is deposited over the sacrificial dielectric material adjacent to the second source / drain region at the second end of the vertically extended channel; Remove the sacrificial dielectric material; and Reduce the thickness of one or more of the vertically extending channels, wherein the channel body is disposed between the first source / drain region and the second source / drain region.

12. The method of claim 11, further comprising etching the second protective dielectric material to form a support mesh.

13. The method of claim 11, further comprising reducing the thickness of a portion of the first source / drain region, the second source / drain region, or a combination thereof.

14. The method of claim 11, wherein the first protective dielectric material is deposited to extend from the first end to a height or less that is substantially coplanar with the top surface of the first source / drain region.

15. The method of claim 14, wherein the sacrificial dielectric material is deposited to extend from the top surface of the first protective dielectric material to a height greater than the bottom surface of the second source / drain region or to a height substantially coplanar with the bottom surface of the second source / drain region.

16. The method of claim 15, wherein the second protective dielectric material is deposited to extend from a height greater than the bottom surface of the second source / drain region or at a height substantially coplanar with the bottom surface of the second source / drain region to the second end of the vertically extending channel.

17. The method of claim 11, further comprising removing the first protective dielectric material and the second protective dielectric material, and depositing a gate dielectric layer and a gate metal around the periphery of the one or more shallow trench isolations.

18. The method of claim 17, wherein the thickness of the channel body is reduced by more than 5% or about 5%.

19. The method of claim 11, wherein reducing the thickness of the channel body comprises selective silicon etching, oxidation and wet etching, or a combination thereof.

20. The method of claim 12, wherein the sacrificial dielectric material comprises a material that can be selectively etched without etching the first protective dielectric material and the second protective dielectric material.

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