Crystal oscillator device and manufacturing method thereof

Abstract

The invention discloses a crystal oscillator device and a manufacturing method thereof.The crystal oscillator device comprises a glass substrate, an IC chip, a crystal oscillator chip and a cover plate, the glass substrate is provided with a blind groove and a plurality of TGV holes, the TGV holes are filled with metal to be metalized, the IC chip is embedded into the blind groove, the front face and the back face of the glass substrate are each provided with an insulating layer, and the cover plate is arranged on the back face of the glass substrate. The crystal oscillator chip is located between the front face of the glass substrate and the cover plate, and interconnection of the IC chip, the crystal oscillator chip and the cover plate is achieved through metal wiring and TGV hole metallization. Through wafer-level packaging and re-wiring layer processes, routing paths are effectively reduced, an IC chip is embedded into a glass substrate, the packaging size is effectively reduced, miniaturization and integration of a packaging body are achieved, the glass substrate and a cover plate with the whole metalized face are permanently bonded together, the airtightness is improved, the shielding effect is achieved, and the performance and stability of a crystal oscillator device are guaranteed.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer-level packaging, and in particular relates to a crystal oscillator device and a manufacturing method thereof. Background Art

[0002] Crystal oscillator devices are widely used in various electronic products, controlling the operating rhythm of devices and ensuring stable data transmission and communication signals. Different application scenarios require crystal oscillator devices to withstand external electromagnetic interference. Traditionally, crystal oscillator chips are packaged in a ceramic tube package. The chip is connected to the tube pads via wire bonding. The two electrodes of the quartz crystal wafer are bonded to the tube pads with conductive adhesive for interconnection, and then shielded with a metal cover. Wire bonding has the following disadvantages: 1. It takes up a lot of space: Wire bonding increases the package size, hindering product miniaturization and integration. 2. It limits signal transmission performance: Long wire bonds can cause signal delay, attenuation, and interference, affecting the high-frequency performance of the circuit. 3. In harsh environments or with long-term use, wire bonds can break or loosen, affecting the stability and service life of the package. The challenge is to achieve a crystal oscillator package that shortens the interconnect spacing to improve performance, reduces the package size, and provides shielding.

[0003] The invention patent with announcement number CN109937533B proposes a crystal vibration device with a crystal resonator of a sandwich structure. The connection between the IC chip and the crystal resonator is interconnected by wire bonding and bumps to external components such as the tube shell. It takes up a large space and increases the size of the package, which is not conducive to the miniaturization and integration of the product. In addition, the long wire bonding may cause signal delay, attenuation and interference, affecting the high-frequency performance of the circuit. Summary of the Invention

[0004] In order to solve the above-mentioned problems existing in the prior art, the present application provides a crystal oscillator device and a manufacturing method thereof, which realizes interconnection through wafer-level packaging and redistribution layer (RDL) routing technology and buries the IC chip into the glass substrate, effectively reducing the routing path and packaging volume, so as to overcome the shortcomings of the above-mentioned prior art.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A crystal oscillator device, comprising:

[0007] A glass substrate having a front surface and a back surface opposite to each other, a blind groove being formed on the front surface of the glass substrate, and a plurality of TGV holes filled with metal to metalize the TGV holes;

[0008] an IC chip, wherein the IC chip is embedded in the blind groove;

[0009] A crystal oscillator chip and a cover plate, wherein the crystal oscillator chip is located between the front surface of the glass substrate and the cover plate, and the IC chip, the crystal oscillator chip and the cover plate are interconnected through metal wiring and TGV hole metallization.

[0010] Embedding the IC chip in the blind groove of the glass substrate can reduce the package volume and facilitate device miniaturization. The cover plate has a shielding effect and can effectively reduce electromagnetic interference. The precise processing of the blind groove ensures the coplanarity of the IC chip and the glass substrate, providing a foundation for multi-layer stacking. The metal filling of the TGV hole provides an additional heat conduction path, making the heat distribution more uniform.

[0011] Preferably, the cover plate is provided with a groove, and a cover plate metal layer is provided between the groove and a side of the cover plate having the groove, and the side of the cover plate having the groove faces the front side of the glass substrate.

[0012] Preferably, the front surface of the glass substrate further includes a first protective layer and a first passivation layer, and the metal wiring includes a first metal layer and a second metal layer. The first protective layer is disposed between the glass substrate and the crystal oscillator chip to fix the IC chip. The first metal layer is disposed between the first protective layer and the crystal oscillator chip. The first metal layer connects the metallized TGV hole and is connected to the IC chip. The first passivation layer is disposed between the first metal layer and the crystal oscillator chip. The second metal layer is disposed between the first passivation layer and the crystal oscillator chip. The second metal layer connects the first metal layer, the crystal oscillator chip, and the cover plate. The first passivation layer serves as an insulating protection, and chip embedding and through-hole metallization are completed through patch and metallization technology to achieve vertical interconnection.

[0013] Further preferably, an auxiliary layer is provided between the second metal layer and the cover metal layer, and the cover metal layer, the auxiliary layer, the second metal layer and the first passivation layer form a sealed cavity, and the crystal oscillator chip is placed in the sealed cavity. The thickness of the second metal layer in the vertical direction supports the crystal oscillator chip in the sealed cavity, so that the crystal oscillator chip does not contact the cover metal layer and the first passivation layer. The second metal layer, by virtue of its specific thickness in the vertical direction, firmly supports the crystal oscillator chip in the sealed cavity, ensures that the chip is in a predetermined position and maintains a stable working state, and also provides a vibration space for the crystal oscillator chip, which can reduce external electromagnetic interference, improve reliability, and ensure the performance and stability of the crystal oscillator device. The auxiliary layer is used to achieve bonding with the cover metal layer, which is beneficial to improve the connection strength and form a sealed cavity with better sealing.

[0014] Preferably, the IC chip is embedded in the blind groove so that the surface of the IC chip is flush with the front surface of the glass substrate, and the gap between the IC chip and the blind groove wall is filled with insulating material. The IC chip is fixed in the blind groove by the insulating material, providing better physical protection and reducing the impact of external shock or vibration on the chip. The surface of the IC chip is flush with the front surface of the glass substrate, which reduces the stress between the first protective layer and the front surface of the glass substrate, significantly reducing the mechanical stress concentration of the first protective layer at the interface between the glass substrate and the chip surface. It also reduces the stress between the first protective layer and the IC chip surface. The coplanar structure eliminates the height difference in traditional stepped packaging, avoids shear stress in the first protective layer at the interface transition point, and prevents delamination failure.

[0015] Preferably, the metal wiring further includes a third metal layer disposed on the back side of the glass substrate, the third metal layer being connected to the metallized TGV hole, and a metal protective layer disposed on a side of the third metal layer away from the glass substrate. The metal protective layer is used to protect the metal surface of the third metal layer from oxidation and serves as an external solder pad.

[0016] Further preferably, the back surface of the glass substrate further includes a second passivation layer, wherein the thickness of the second passivation layer is greater than the combined thickness of the third metal layer and the metal protective layer, and the second passivation layer covers the gaps between the third metal layers and partially covers the surface of the metal protective layer. The second passivation layer serves as an insulating protection.

[0017] On the other hand, the present application proposes a method for manufacturing a crystal oscillator device, which is used to manufacture the above-mentioned crystal oscillator device, comprising:

[0018] S1: preparing a cover plate with a groove;

[0019] S2: preparing a glass substrate having a blind groove and a plurality of TGV holes, and filling the TGV holes with metal;

[0020] S3: Embedding the IC chip into the blind groove of the glass substrate;

[0021] S4: filling the gap between the IC chip and the blind groove with an insulating material, and forming a first protective layer on the surface of the glass substrate having the blind groove;

[0022] S5: preparing a first metal layer on the first protective layer, wherein the first metal layer connects the TGV hole and the IC chip;

[0023] S6: preparing a first passivation layer covering the first metal layer;

[0024] S7: preparing a second metal layer on the first passivation layer to achieve interconnection with the first metal layer;

[0025] S8: forming a third metal layer on a surface of the glass substrate away from the first protective layer, wherein the third metal layer is connected to the TGV hole;

[0026] S9: forming a second passivation layer on a side of the third metal layer away from the glass substrate, wherein the second passivation layer covers a gap between the third metal layers;

[0027] S10: attaching a crystal oscillator chip to the second metal layer, and connecting the cover plate to the second metal layer by permanent bonding, so that the crystal oscillator chip is located in a sealed cavity surrounded by the first passivation layer, the cover plate and the second metal layer.

[0028] The crystal oscillator device of the present application adopts a wafer-level packaging process, realizes interconnection through the RDL (Redistribution Layer) routing process, buries the IC chip in the glass substrate, and prepares an insulating layer and a passivation layer for protection, effectively reducing the package volume, simplifying the process flow, reducing costs, and realizing miniaturization and integration of the package body.

[0029] Preferably, the step S1 further comprises: plating a cover plate metal layer on the groove and the side of the cover plate having the groove;

[0030] The S8 further includes: plating a metal protective layer on the side of the third metal layer away from the glass substrate; this layer not only provides protection but also facilitates subsequent connection.

[0031] The S10 further includes: preparing an auxiliary layer between the second metal layer and the cover metal layer, so that the crystal oscillator chip is located in a sealed cavity surrounded by the first passivation layer, the cover metal layer, the second metal layer and the auxiliary layer.

[0032] Plating a layer of metal on the side of the cover plate having the groove and on the groove is conducive to connecting the cover plate to the second metal layer through permanent bonding in the subsequent process, forming a sealed cavity for loading the crystal oscillator chip, which can reduce external electromagnetic interference and improve device reliability; plating a metal protective layer on the side of the third metal layer away from the glass substrate is conducive to preventing metal oxidation and serving as an external solder pad for subsequent connection. The auxiliary layer is used to achieve bonding with the metal layer of the cover plate, which is conducive to improving the connection strength and forming a sealed cavity with better sealing.

[0033] Preferably, the step S7 further includes: preparing a temporary bonding adhesive and a carrier above the first protective layer, wherein the temporary bonding adhesive covers the first passivation layer and the second metal layer;

[0034] The step S9 further includes removing the temporary bonding adhesive and the carrier board. During the manufacturing process of the crystal oscillator device, the temporary bonding adhesive and the carrier board provide support and protection, thereby improving the yield rate.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] The present invention provides a crystal oscillator device and a manufacturing method thereof. The device adopts wafer-level packaging and realizes interconnection through an RDL routing process, effectively reducing routing paths. The IC (Integrated Circuit) chip is embedded in a glass substrate, which can effectively reduce the package volume and realize miniaturization and integration of the package body. The glass substrate and the entire metallized cover are permanently bonded together, which not only increases airtightness but also has a shielding effect. It can effectively reduce the characteristic changes caused by electromagnetic interference and external environmental changes, improve reliability, and ensure electronic performance and stability. The structure can improve the interconnection spacing and avoid external electromagnetic interference, meet the requirement of short interconnection between chips, and avoid increasing power consumption or reducing device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings provide further illustration of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many of the intended advantages of the embodiments will be readily apparent as they become better understood by reference to the following detailed description. Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings:

[0038] Figure 1 This is a schematic structural diagram of a crystal oscillator device according to a specific embodiment of the present invention;

[0039] Figure 2 is a flow chart of a method for manufacturing a crystal oscillator device according to a specific embodiment of the present invention;

[0040] Figures 3 to 13 It is a structural schematic diagram of each step of a method for manufacturing a crystal oscillator device according to a specific embodiment of the present invention.

[0041] The meaning of the numbers in the figure are: 1. Cover plate; 101. Cover plate metal layer; 2. Glass substrate; 201. TGV hole; 202. Blind groove; 3. IC chip; 4. First protective layer; 5. First metal layer; 6. First passivation layer; 7. Second metal layer; 8. Crystal oscillator chip; 9. Third metal layer; 901. Metal protective layer; 10. Second passivation layer; 11. Temporary bonding glue; 12. Carrier; 13. Auxiliary layer. DETAILED DESCRIPTION

[0042] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0043] In the description of the present invention, it should be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly stipulated and limited, the terms "installed", "provided with", "sleeved / connected", "connected", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be a direct connection or an indirect connection through an intermediate medium. It can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] To facilitate understanding by those skilled in the art, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0046] Figure 1 A schematic diagram of the structure of a crystal oscillator device according to a specific embodiment of the present application is shown in FIG. Figure 1 As shown, a crystal oscillator device includes a cover plate 1, a glass substrate 2, an IC chip 3 and a crystal oscillator chip 8. The glass substrate 2 has a front and a back surface relative to each other. The cover plate 1 is provided with a groove. The groove and the side of the cover plate with the groove are both provided with a cover plate metal layer 101. The side of the cover plate with the groove faces the front surface of the glass substrate 2. The size of the groove of the cover plate 1 is larger than the size of the crystal oscillator chip 8, that is, the lateral width of the groove is larger than the lateral width of the crystal oscillator chip 8, and the depth of the groove is larger than the height of the crystal oscillator chip 8; a blind groove is opened on the front surface of the glass substrate 2, and the glass substrate 2 further includes a plurality of TGV holes 201. The TGV holes 201 are filled with metal to metalize them. The IC chip 3 is embedded in the blind groove so that the surface of the IC chip 3 is flush with the front surface of the glass substrate. The gap between the IC chip 3 and the blind groove wall is filled with insulating material to fix the IC chip 3.

[0047] In a specific embodiment, the crystal oscillator chip 3 is located between the front surface of the glass substrate 2 and the cover plate 1. The front surface of the glass substrate 2 includes a first protective layer 4, a first metal layer 5, a second metal layer 7 and a first passivation layer 6. The first protective layer 4 is provided on the front surface of the glass substrate 2 and can fix the IC chip 3 embedded in the blind groove of the glass substrate 2. The first metal layer 5 is provided above the first protective layer 4, and the first metal layer 5 fills the gap between the first protective layers 4 and is connected to each metallized TGV hole 201. The first metal layer 5 is connected to the IC chip 3; a first passivation layer 6 is prepared above the first metal layer 5, the first passivation layer 6 covers the first metal layer 5, and the first passivation layer 6 partially contacts the first protective layer 4; on the first passivation layer 6 A second metal layer 7 is prepared, and the second metal layer 7 fills the gap between the first passivation layer 6 and is connected to the first metal layer 5. At the same time, the second metal layer 7 is also connected to the crystal oscillator chip 8, and is connected to the cover metal layer 101 on the cover plate 1 through the auxiliary layer 13; the cover plate 1 and the cover metal layer 101, the second metal layer 7, the auxiliary layer 13 and the first passivation layer 6 form an airtight space, and the crystal oscillator chip 8 is placed in the middle of the airtight space. The crystal oscillator chip 8 is connected to the second metal layer 7, and the second metal layer 7 supports and connects the crystal oscillator chip 8, so that the crystal oscillator chip 8 does not contact the cover metal layer 101 and the first passivation layer 6, and the interconnection of the IC chip 3, the crystal oscillator chip 8 and the cover plate 1 is realized through metal wiring and TGV hole 201 metallization.

[0048] In a specific embodiment, a third metal layer 9 and a second passivation layer 10 are provided on the back of the glass substrate 2. The third metal layer 9 is connected to each metallized TGV hole 201. The second passivation layer 10 fills the gaps between the third metal layers 9 and partially covers the third metal layer 9.

[0049] In a specific embodiment, a metal protective layer 901 is further provided on the lower surface of the third metal layer 9 to prevent metal oxidation and ensure device performance. It also serves as an external pad to facilitate subsequent connections, and the second passivation layer 10 partially covers the metal protective layer 901.

[0050] In a specific embodiment, the material of the metal protection layer 901 is gold, which has good welding performance and is convenient for external wiring or using tin paste solder.

[0051] In a specific embodiment, the thickness of the second passivation layer 10 is greater than the sum of the thicknesses of the third metal layer 9 and the metal protective layer 901. This thickness is conducive to providing an insulation effect that is more suitable for the crystal oscillator device, helping to evenly distribute heat to avoid local overheating, protecting sensitive metal layers, and extending the service life of the device.

[0052] In a specific embodiment, the first metal layer 5 is connected to the third metal layer through the metallized TGV hole. The first metal layer 5, the second metal layer 7, the third metal layer 9 and the multiple metallized TGV holes 201 are interconnected to form the redistribution layer of this embodiment, thereby realizing short-distance interconnection, reducing the overall size and thickness of the device, having better heat dissipation and electrical performance, and having the advantage of miniaturization.

[0053] Optionally, the first metal layer 5, the metal material filling the TGV hole 201 and the metal material used in the third metal layer 9 can all be one or more of gold, copper, nickel, aluminum and tungsten. The material of the second metal layer 7 is copper, and the material used in the metal protective layer 901 is gold, which can achieve high-quality welding. The materials used in the cover metal layer 101 are copper, nickel and gold, of which the position close to the auxiliary layer 13 is gold. The materials of the auxiliary layer 13 are copper, nickel, tin and silver. The second metal layer 7 is directly connected to the crystal oscillator chip 8 to achieve bonding. The second metal layer 7 is connected to the cover metal layer 101 through the auxiliary layer 13. The auxiliary layer 13 and the cover metal layer 101 can achieve bonding between Au (gold) and Sn (tin).

[0054] In a specific embodiment, there are multiple metalized TGV holes 2, including multiple TGV holes 2 near the IC chip 3 and multiple TGV holes 2 away from the IC chip 3. The first portion of the third metal layer 9 is connected to the first metal layer 5 and the second metal layer 7 through the TGV holes 2 near the IC chip, and then connected to the crystal oscillator chip 8 and the IC chip 3. The second portion of the third metal layer 9 is connected to the first metal layer 5 and the second metal layer 7 through the TGV holes 2 away from the IC chip 3, and then connected to the cover metal layer 101 of the cover 1. The layout planning of this structure is conducive to device miniaturization and maximum space utilization. The use of metal wiring ensures the rapid transmission of signals between the oscillator chip 8 and the IC chip 3, shortens the signal path, and cooperates with the cover 1 connected to the metal wiring to enhance the stability of the device, provide shielding effects, and reduce electromagnetic interference, thereby ensuring the high frequency stability of the crystal oscillator device. Even in the face of interference factors such as temperature changes, voltage fluctuations, or mechanical vibrations, it can still provide a stable clock signal.

[0055] In a specific embodiment, there are multiple metalized TGV holes 2 in the glass substrate 2, which together with the first metal layer 5, the second metal layer 7 and the third metal layer 9 form the metal wiring of the embodiment of this application, and together constitute a multi-layer interconnection structure, wherein the second metal layer 7 accurately supports and suspends the crystal oscillator chip 8 in the airtight space through the thickness design in the vertical direction, thereby optimizing the gap between the crystal oscillator chip 8 and the first passivation layer 6, and avoiding the influence of mechanical vibration on the chip performance. The airtight space is enclosed by the cover plate 1 and the cover plate metal layer 101 on the top, and is surrounded by the cover plate 1, the cover plate metal layer 101, the auxiliary layer 13 and the second metal layer 7 on the sides, and is sealed by the first passivation layer 6 on the bottom, forming a complete packaging environment. Through the coordinated optimization of TGV, multi-layer metal interconnection and airtight space design, high-performance packaging of the crystal oscillator chip 8 is achieved, the multi-layer metal interconnection spacing is shortened, the performance is improved while reducing the package size, and it has the advantages of high-frequency signal transmission, excellent thermal management, high reliability and wide applicability, providing key technical support for the miniaturization and integration of next-generation electronic systems.

[0056] In a specific embodiment, the crystal oscillator chip 8 is located directly above the IC chip 3 in the vertical direction, and the connection between the crystal oscillator chip 8 and the IC chip 3 is achieved through metal wiring, and the IC chip is embedded in the blind groove 202 of the glass substrate 2, which can shorten the signal path, reduce signal delay and reflection, and protect the IC chip 3 and the crystal oscillator chip 8 from the risk of frequency drift caused by vibration or other mechanical stress, so that the crystal oscillator chip 8 and the IC chip 3 can work together efficiently and normally.

[0057] Figure 2 A flow chart of a method for manufacturing a crystal oscillator device according to a specific embodiment of the present application is shown. Figure 2 As shown, the manufacturing method for manufacturing a crystal oscillator device in this application is specifically as follows:

[0058] S1: Prepare a cover plate 1 having a groove. Optionally, the cover plate 1 is subjected to laser modification and solution etching, and the grooved cover plate 1 is obtained using TGV technology. A layer of metal is then electroplated on the grooved side of the cover plate 1. This facilitates permanent bonding of the cover plate 1 to the second metal layer 7 in subsequent processes, forming a sealed cavity for mounting the crystal oscillator chip 8, reducing external electromagnetic interference and improving device reliability.

[0059] S2: Prepare a glass substrate 2 having blind trenches 202 and multiple TGV holes 201, and fill the TGV holes 201 with metal. Optionally, laser modification, solution etching, and TGV technology are performed on the glass substrate 2 to obtain a glass substrate 2 having blind trenches 202 and multiple TGV holes 201, and fill the TGV holes 201 with metal. This is a key step in achieving interconnection through the wafer-level packaging RDL routing process, effectively reducing routing paths.

[0060] S3: Embed the IC chip 3 into the blind groove 202 of the glass substrate 2. Alternatively, the IC chip 3 can be attached to the blind groove 202 of the glass substrate 2, with the surface of the IC chip 3 flush with the surface of the glass substrate 2. This saves device packaging space and facilitates the subsequent preparation of the insulating layer.

[0061] S4: Fill the gap between the IC chip 2 and the blind groove 202 with an insulating material, and form a first protective layer 4 on the surface of the glass substrate 2 having the blind groove 202. Optionally, photolithography is used to leave gaps in the first protective layer 4 at the locations of the TGV holes 201 and the electrical connections of the IC chip 3. This improves the stability of the IC chip 3 within the overall device, resisting the effects of external shock or vibration, while also helping to reduce the device size and achieve miniaturized packaging.

[0062] S5: A first metal layer 5 is formed on top of the first protective layer 4. The first metal layer 5 connects the TGV hole 201 and the IC chip 3. Optionally, the first metal layer 5 fills the gaps between the first protective layer 4 to achieve connection with the TGV hole 201 and the IC chip 3. The use of a glass embedded fan-out package integrated RDL process eliminates the need for a substrate and shortens interconnects compared to traditional wire bonding and flip-chip packaging, reducing the overall package size and thickness. This provides better heat dissipation and electrical performance, and offers the advantage of miniaturization.

[0063] S6: Prepare a first passivation layer 6 covering the first metal layer 5. Optionally, a plurality of gaps are left in the first passivation layer 6 by photolithography to facilitate RDL interconnection, ensure signal transmission, and reduce the overall package volume.

[0064] S7: A second metal layer 7 is prepared on top of the first passivation layer 6 to achieve interconnection with the first metal layer 5. Optionally, a layer of temporary bonding glue 11 and a carrier are prepared on top of the second metal layer 7 to achieve front protection during device preparation. At the same time, the back of the glass substrate 2 away from the temporary bonding glue 11 is thinned so that the TGV hole 201 passes through the glass substrate 2, and the metal filled in the TGV hole 201 is exposed on the back of the glass substrate 2. Ensuring that the glass substrate 2 remains stable during the processing to avoid damage or deformation due to mechanical stress helps to achieve finer and higher-density TGV manufacturing, makes vertical signal transmission possible, reduces the need for planar wiring, and is conducive to the miniaturization and lightweight design of electronic equipment.

[0065] S8: A third metal layer 9 is formed on the surface of the glass substrate 2 away from the first protective layer 4. The third metal layer 9 is connected to the TGV hole 201. This completes the RDL routing process, effectively reducing the package volume and achieving miniaturization and integration of the package. Optionally, a metal protective layer 901 is plated on the surface of the third metal layer 9 to protect the surface of the third metal layer 9 from oxidation, thereby ensuring the stability of the device and serving as a pad for subsequent soldering.

[0066] S9: A second passivation layer 10 is formed on a side of the third metal layer 9 away from the glass substrate 2. The second passivation layer 10 covers the gap between the third metal layers 7. Optionally, the thickness of the second passivation layer 10 is greater than the combined thickness of the third metal layer 9 and the metal protective layer 901. This thickness is beneficial for providing an insulation effect more suitable for the crystal oscillator device, helping to evenly distribute heat to avoid local overheating, protecting sensitive metal layers, and extending the service life of the device.

[0067] S10: A crystal oscillator chip 8 is attached to the second metal layer 7, and the cover plate 1 is permanently bonded to the second metal layer 7, so that the crystal oscillator chip 8 is located in the sealed cavity surrounded by the first passivation layer 6, the cover plate 1, and the second metal layer 7. Optionally, the temporary bonding adhesive 11 and the carrier plate 12 are removed, that is, the front protection of the device is removed, to produce a frequency-stable, highly reliable, miniaturized, and highly integrated crystal oscillator device.

[0068] Figures 3 to 12 A schematic diagram showing the structure of each step of a method for manufacturing a crystal oscillator device according to a specific embodiment of the present application is shown below. Figures 3 to 12 The specific manufacturing method of the crystal oscillator device of this application is described as follows:

[0069] like Figure 3 As shown, a cover plate 1 is prepared. The material of the cover plate 1 is glass. The glass cover plate 1 is subjected to laser modification and solution etching to obtain a cover plate 1 with a groove.

[0070] like Figure 4 As shown, a cover metal layer 101 is plated on the side of the cover plate 1 having the groove and on the groove by electroplating to achieve metallization of the glass cover plate 1. This facilitates the connection of the cover plate 1 to the second metal layer 7 by permanent bonding in subsequent processes, forming a sealed cavity for loading the crystal oscillator chip 8, thereby reducing external electromagnetic interference and improving device reliability.

[0071] Optionally, the cover metal layer 101 is made of copper, nickel and gold, wherein the outermost layer is gold.

[0072] like Figure 5As shown, a glass substrate 2 is subjected to laser modification and solution etching to obtain a glass substrate 2 having a blind groove 202. Multiple TGV holes 201 are formed on the glass substrate 2 using TGV (Through Glass Via) technology. Optionally, in a cross-sectional view, the blind groove 202 is located in the middle of the glass substrate 2, and the extension depth of the TGV hole 201 in the glass substrate 2 is greater than the depth of the blind groove 202. This structural arrangement can strengthen the glass substrate 2 to a certain extent, preventing crack propagation or breakage caused by stress concentration, thereby improving the strength of the entire structure.

[0073] like Figure 6 As shown, the TGV hole 201 is filled with metal by electroplating. The metal used can be copper to achieve metallization of the TGV hole 201. Then, the IC chip 3 is embedded in the blind groove 202 of the glass substrate 2. The blind groove 202 of the glass substrate 2 is larger than the IC chip 3. Optionally, a chip mounter is used to attach the IC chip 3 to the blind groove 202. The surface of the IC chip 3 is flush with the surface of the glass substrate 2, which saves device packaging space and facilitates the subsequent preparation of the insulating layer.

[0074] like Figure 7 As shown, a first protective layer 4 is formed on the surface of the glass substrate 2 having the blind groove 202, and the gap between the IC chip 3 and the blind groove 202 is filled with insulating material. The first protective layer 4 fixes the IC chip 3 in the blind groove 202 and plays an insulating protection role.

[0075] In a specific embodiment, insulating material is filled into the gap between the IC chip 3 and the blind groove wall, so that the IC chip 3 is subjected to an inward squeezing force on all sides, and the IC chip 3 is fixed in the blind groove 202, thereby improving the stability of the IC chip 3 in the overall device and resisting the influence of external shock or vibration.

[0076] Optionally, the first protective layer 4 and the insulating material are a photolithographic dry film.

[0077] In a specific embodiment, photolithography is used to leave gaps in the first protective layer 4 at the position of the TGV hole 201 and the position where the IC chip 3 is electrically connected. A first metal layer 5 is prepared above the first protective layer 4 and fills the gaps to achieve connection with the TGV hole 201 and the IC chip 3.

[0078] Optionally, the material of the first metal layer 5 may be one of metal materials such as copper, aluminum, and tungsten.

[0079] like Figure 8As shown, a first passivation layer 6 is prepared, which covers the surface of the first metal layer 5 and the gaps between the metal wires to play a role of insulation protection, and gaps for vertical connection between the metal wires are set by photolithography; a second metal layer 7 is prepared above the first passivation layer 6, and the second metal layer 7 is interconnected with the first metal layer 5; an auxiliary layer 13 is prepared above part of the second metal layer 7, and the auxiliary layer 13 is located above the second metal layer 7 on the outer side of the device and is used to connect the cover plate 1. The glass embedded fan-out package integrated RDL process omits the substrate and shortens the interconnection compared to traditional wire bonding and flip-chip packaging, which can reduce the size and thickness of the overall package, has better heat dissipation and electrical performance, and has the advantage of miniaturization.

[0080] Optionally, the second metal layer 7 is made of copper, and the height of the second metal layer 7 superimposed on the auxiliary layer 13 is consistent with the height of the second metal layer 7 without the auxiliary layer 13 superimposed.

[0081] like Figure 9 As shown, a layer of temporary bonding adhesive 11 is prepared above the second metal layer 7 and the auxiliary layer 13. The temporary bonding adhesive 11 covers the second metal layer 7, the first passivation layer 6, the auxiliary layer 13, and the first protective layer 4. A carrier plate 12 is disposed above the temporary bonding adhesive 11 to protect the front surface of the glass substrate 2. The back surface of the glass substrate 2, away from the temporary bonding adhesive 11, is thinned so that the TGV hole 201 passes through the glass substrate 2, and the metal filled in the TGV hole 201 is exposed on the back surface of the glass substrate 2. This ensures that the glass substrate 2 remains stable during processing, avoiding damage or deformation caused by mechanical stress, facilitates the manufacture of finer and higher-density TGVs, enables vertical signal transmission, reduces the need for planar wiring, and promotes the miniaturization and lightweight design of electronic devices.

[0082] like Figure 10 As shown, a third metal layer 9 is formed on the back of the glass substrate 2, and the third metal layer 9 is interconnected with the metallized TGV hole 201. The RDL routing process is completed, effectively reducing the package volume and realizing miniaturization and integration of the package.

[0083] Optionally, the third metal layer 9 may be made of metal materials such as copper or nickel.

[0084] Optionally, a metal protective layer 901 is plated on the surface of the third metal layer 9. The material of the metal protective layer 901 is gold, which protects the surface of the third metal layer 9 from oxidation, thereby ensuring the stability of the device and achieving high-quality welding.

[0085] like Figure 11As shown, a second passivation layer 10 is prepared on the back of the glass substrate 2. The second passivation layer 10 covers a portion of the third metal layer 9 with the metal protective layer 901 and the gaps between the metal wires. The thickness of the second passivation layer 10 is greater than the thickness of the third metal layer 9 and the metal protective layer 901 superimposed to provide better insulation protection and mechanical support.

[0086] In a specific embodiment, the portion of the third metal layer 9 with the metal protective layer 901 exposed outside the second passivation layer 10 is used to connect external devices to achieve signal transmission and power supply. Through the optimized design of the second passivation layer 10, multiple advantages of high-reliability insulation, excellent mechanical properties and efficient electrical and thermal management are achieved.

[0087] Optionally, the material of the second passivation layer 10 may be an organic material such as resin or polyimide, or an inorganic insulating material such as silicon oxide or silicon nitride.

[0088] like Figure 12 As shown, removing the temporary bonding glue 11 and the carrier 12, that is, removing the front protection, and using a placement machine to stick the crystal oscillator chip 8 on the second metal layer 7 can reduce the signal path length, reduce parasitic inductance and resistance, and improve the integrity of high-frequency signals.

[0089] like Figure 13 As shown, the cover plate 1 is connected to the auxiliary layer 13 near the edge of the glass substrate 2 by permanent bonding, so that the cover plate metal layer 101 forms a closed cavity with the second metal layer 7, the auxiliary layer 13 and the first passivation layer 6, i.e., an airtight space, and the crystal oscillator chip 8 is placed in the closed cavity. The crystal oscillator chip 8 is placed in the closed cavity through the second metal layer 7, and the crystal oscillator chip does not contact the cover plate metal layer 101. The crystal oscillator device and its manufacturing method of the present application can ensure that the signal of the crystal oscillator will not interfere with other circuits on the circuit board, nor will the characteristics be changed due to changes in the external environment, thereby ensuring the performance and stability of the entire electronic device, effectively reducing electromagnetic interference, and improving the reliability of the crystal oscillator device.

[0090] Optionally, the material of the second metal layer 7 is copper, and the material used for the metal protective layer 901 is gold, which can achieve high-quality welding. The materials used for the cover metal layer 101 are copper, nickel and gold, of which the position close to the auxiliary layer 13 is gold, and the materials of the auxiliary layer 13 are copper, nickel, tin and silver. The second metal layer 7 is directly connected to the crystal oscillator chip 8 to achieve bonding, and the second metal layer 7 is connected to the cover metal layer 101 through the auxiliary layer 13. The auxiliary layer 13 and the cover metal layer 101 can achieve bonding between Au (gold) and Sn (tin).

[0091] It should be noted that the crystal oscillator in this application refers to a crystal oscillator.

[0092] This application proposes a crystal oscillator device and its manufacturing method. The required cover plate 1 is prepared, and a groove of the cover plate 1 is formed by TGV (Through Glass Via) technology, and a layer of metal is plated in the groove. The glass substrate 2 uses TGV technology to form TGV holes 201 and blind grooves 202. The IC (Integrated Circuit) chip 3 is embedded and through-hole metallization is completed by patch and metallization technology to achieve vertical interconnection. Two layers of passivation layer and two layers of metal are made on the front to interconnect with the crystal oscillator chip 8. The crystal oscillator chip 8 is attached to the second metal layer 7. The metal layer is thinned on the back to achieve interconnection with the chip on the front. Finally, the glass substrate 2 and the cover plate 1 are bonded together using a permanent bonding method. This can reduce external electromagnetic interference, improve reliability, and ensure electronic performance and stability. The glass embedded fan-out package integrated RDL process eliminates the substrate and can shorten the interconnection compared to traditional wire bonding and flip-chip packaging, reducing the overall size and thickness of the device, having better heat dissipation and electrical performance, and having the advantage of miniaturization. Interconnections are achieved through wafer-level packaging and redistribution layer (RDL) routing processes, effectively reducing routing paths. The IC chip 3 is embedded in the glass substrate 2, effectively reducing the package volume and achieving miniaturization and integration. The glass substrate 2 and the fully metallized cover plate 1 are permanently bonded together, enhancing both airtightness and shielding. This effectively reduces characteristic variations caused by electromagnetic interference and external environmental changes, improving reliability and ensuring device performance and stability. This results in a crystal oscillator device with short overall interconnect spacing, a compact package size, and excellent shielding. This improves the performance of the crystal oscillator device, reduces adverse factors such as signal delay, attenuation, and interference, and optimizes the high-frequency performance of the circuit.

[0093] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A crystal oscillator device, characterized in that: include: A glass substrate having a front surface and a back surface opposite to each other, a blind groove being formed on the front surface of the glass substrate, and a plurality of TGV holes filled with metal to metalize the TGV holes; an IC chip, wherein the IC chip is embedded in the blind groove; A crystal oscillator chip and a cover plate, wherein the crystal oscillator chip is located between the front surface of the glass substrate and the cover plate, and the IC chip, the crystal oscillator chip and the cover plate are interconnected through metal wiring and TGV hole metallization.

2. The crystal oscillator device according to claim 1, wherein: The cover plate is provided with a groove, and a cover plate metal layer is provided between the groove and a side of the cover plate having the groove, and the side of the cover plate having the groove faces the front side of the glass substrate.

3. The crystal oscillator device according to claim 2, wherein: The front side of the glass substrate also includes a first protective layer and a first passivation layer. The metal wiring includes a first metal layer and a second metal layer. The first protective layer is arranged between the glass substrate and the crystal oscillator chip to fix the IC chip. The first metal layer is arranged between the first protective layer and the crystal oscillator chip. The first metal layer is connected to the metallized TGV hole and is connected to the IC chip. The first passivation layer is arranged between the first metal layer and the crystal oscillator chip. The second metal layer is arranged between the first passivation layer and the crystal oscillator chip. The second metal layer connects the first metal layer, the crystal oscillator chip and the cover plate.

4. The crystal oscillator device according to claim 3, characterized in that An auxiliary layer is provided between the second metal layer and the cover metal layer. The cover metal layer, the auxiliary layer, the second metal layer and the first passivation layer form a sealed cavity. The crystal oscillator chip is placed in the sealed cavity. The thickness of the second metal layer in the vertical direction supports the crystal oscillator chip in the sealed cavity so that the crystal oscillator chip does not contact the cover metal layer and the first passivation layer.

5. The crystal oscillator device according to claim 1, wherein: The IC chip is embedded in the blind groove so that the surface of the IC chip is flush with the front surface of the glass substrate, and the gap between the IC chip and the blind groove wall is filled with insulating material.

6. The crystal oscillator device according to claim 1, characterized in that: The metal wiring further includes a third metal layer disposed on the back of the glass substrate, the third metal layer being connected to the metallized TGV hole, and a metal protective layer being disposed on a side of the third metal layer away from the glass substrate.

7. The crystal oscillator device according to claim 6, characterized in that: The back of the glass substrate further includes a second passivation layer, the thickness of which is greater than the superposition thickness of the third metal layer and the metal protective layer. The second passivation layer covers the gaps between the third metal layers and covers a portion of the surface of the metal protective layer.

8. A method for manufacturing a crystal oscillator device, characterized in that: include: S1: preparing a cover plate with a groove; S2: preparing a glass substrate having a blind groove and a plurality of TGV holes, and filling the TGV holes with metal; S3: Embedding the IC chip into the blind groove of the glass substrate; S4: filling the gap between the IC chip and the blind groove with an insulating material, and forming a first protective layer on the surface of the glass substrate having the blind groove; S5: preparing a first metal layer on the first protective layer, wherein the first metal layer connects the TGV hole and the IC chip; S6: preparing a first passivation layer covering the first metal layer; S7: preparing a second metal layer on the first passivation layer to achieve interconnection with the first metal layer; S8: forming a third metal layer on a surface of the glass substrate away from the first protective layer, wherein the third metal layer is connected to the TGV hole; S9: forming a second passivation layer on a side of the third metal layer away from the glass substrate, wherein the second passivation layer covers a gap between the third metal layers; S10: attaching a crystal oscillator chip to the second metal layer, and connecting the cover plate to the second metal layer by permanent bonding, so that the crystal oscillator chip is located in a sealed cavity surrounded by the first passivation layer, the cover plate and the second metal layer.

9. The production method according to claim 8, characterized in that: Said S1 further comprises: plating a cover plate metal layer on said groove and on a side of said cover plate having the groove; The S8 further includes: plating a metal protective layer on a side of the third metal layer away from the glass substrate; The S10 further includes: preparing an auxiliary layer between the second metal layer and the cover metal layer, so that the crystal oscillator chip is located in a sealed cavity surrounded by the first passivation layer, the cover metal layer, the second metal layer and the auxiliary layer.

10. The manufacturing method according to claim 8, characterized in that: The step S7 further includes: preparing a temporary bonding adhesive and a carrier on the first protective layer, wherein the temporary bonding adhesive covers the first passivation layer and the second metal layer; The step S9 further includes removing the temporary bonding adhesive and the carrier board.

Images