Segmented resistor DAC dynamic mismatch calibration circuit for successive approximation type ADC and calibration method of segmented resistor DAC dynamic mismatch calibration circuit

Abstract

The invention discloses a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation type ADC, and the circuit comprises a switched capacitor sampling circuit, the input end of the switched capacitor sampling circuit is connected with a to-be-sampled voltage VIN and an output voltage VDAC of a segmented resistor DAC, and the output end of the switched capacitor sampling circuit is connected with the input end of a comparator module. The output end of the comparator module is connected with the input end of the SAR logic control circuit, the output of the SAR logic control circuit controls the output voltage of the segmented resistor DAC, the output of the SAR logic control circuit is further connected with the input end of the register, and the output end of the register is connected with the DEM averaging module. The invention further discloses a segmented resistor DAC dynamic mismatch calibration method for the successive approximation type ADC. According to the invention, the problem of resistor mismatch in the segmented resistor DAC is solved, and the output precision of the segmented resistor DAC is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital-to-analog converters in analog integrated circuit analog-to-digital converters, and relates to a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation ADC. The present invention also relates to a segmented resistor DAC dynamic mismatch calibration method for a successive approximation ADC. Background Art

[0002] The rapid development of products such as power tools and electric vehicles has spurred research on battery management chips. However, the voltage, temperature, and current involved in battery management are all analog quantities and cannot be processed directly. Therefore, a high-precision analog-to-digital converter (ADC) is required. The accuracy of the digital-to-analog converter (DAC) is a key factor affecting overall ADC accuracy. Resistor-based DACs (DACs) offer the best linearity among all DACs, but current processes can produce significant resistor mismatch, which can severely impact DAC accuracy.

[0003] The successive approximation register ADC (SAR ADC) uses the principle of binary division to continuously compare the sampled voltage with the voltage generated by the DAC, thereby obtaining the binary conversion result of the voltage relative to the ADC quantization range. IN ) and DAC output voltage (V DAC ) for comparison. The analog voltage output by the DAC is determined by the SAR logic control circuit. The initial DAC output voltage V DAC,1 The size is 0.5V ref If the comparator outputs a high level, it means that V in >0.5V ref , then the SAR logic control circuit makes V DAC,2 0.75V ref ; If the comparator output is low, it means V in <0.5V ref , the next time the SAR logic circuit will switch the DAC output voltage to 0.25V ref Taking an L-bit ADC as an example, a quantization process will perform L comparisons. After each comparison, the output result of the comparator is used to select how to approximate the next time, and a 1-bit binary number is generated based on the comparison result. Finally, an L-bit digital code is obtained as the ADC conversion result. The resistor DAC uses the principle of resistor series voltage division to divide the reference voltage into two LThe low-order resistor string in the segmented resistor DAC will fine-tune the coarse-quantized voltage obtained by dividing the high-order resistor string. The voltage divided by each resistor on the low-order resistor string is V REF / 2 L However, due to mismatched resistor values ​​in the voltage divider string, the voltage divider across each resistor deviates from the ideal value, causing mismatch in the ADC conversion process and a dramatic increase in the ADC's integral nonlinearity (INL) and differential nonlinearity (DNL). Existing resistor mismatch calibration methods primarily include laser trimming and fuse trimming. The former requires expensive equipment and complex operations, while the latter is not only costly but also requires an irreversible, single-shot calibration. Summary of the Invention

[0004] The present invention aims to provide a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation ADC, which solves the resistance mismatch problem in the segmented resistor DAC and improves the output accuracy of the segmented resistor DAC.

[0005] Another object of the present invention is to provide a dynamic mismatch calibration method for a segmented resistor DAC of a successive approximation register ADC.

[0006] The first technical solution adopted by the present invention is a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation ADC, comprising a switched capacitor sampling circuit, wherein the input terminals of the switched capacitor sampling circuit are respectively connected to a voltage to be sampled V IN and the output voltage V of the segmented resistor DAC DAC The output end of the switched capacitor sampling circuit is connected to the input end of the comparator module, the output end of the comparator module is connected to the input end of the SAR logic control circuit, the output of the SAR logic control circuit controls the output voltage of the segmented resistor DAC, and the output of the SAR logic control circuit is also connected to the input end of the register, and the output end of the register is connected to the DEM averaging module.

[0007] The first technical solution of the present invention is also characterized in that: The switched capacitor sampling circuit module includes a sampling capacitor Cs, one end of which is connected to switches S1 and S2 respectively, and the other end of which is connected to switch S3; switch S1 is also connected to the voltage to be sampled V IN , switch S2 also connects the segmented resistor DAC output voltage V DAC ; The circuit also includes a switch S3 and a switch S4. One end of the switches S3 and S4 connected in series is connected to the output end of the operational amplifier COMP1. The other end of the switches S3 and S4 connected in series is connected to the inverting input end of the operational amplifier COMP1 and the upper plate of the sampling capacitor Cs. A compensation capacitor C is provided between the switches S3 and S4. LThe non-inverting input of operational amplifier COMP1 is connected to the reference voltage V R .

[0008] The comparator module includes an operational amplifier COMP2, the non-inverting input of the operational amplifier COMP2 is connected to the output of the operational amplifier COMP1, and the inverting input of the operational amplifier COMP2 is connected to the reference voltage V R The non-inverting output of the operational amplifier COMP2 is connected to the non-inverting input of the latch comparator, and the inverting output of the operational amplifier COMP2 is connected to the inverting input of the latch comparator; the output of the latch comparator is connected to the SAR logic control circuit.

[0009] The DEM average module comprises a binary adder module and a binary divider module which are connected in sequence, and the binary adder module is connected to the register.

[0010] The segmented resistor DAC includes a high-order resistor string, the resistance of which is connected to the high-order resistor string by switches S1 to S (2 K +1) connected in series or parallel with a low-level resistor; The low-order resistor string is also included, and the resistors on the low-order resistor string are controlled by switches S1' to S(2 H +1)' the conduction output V DAC .

[0011] The second technical solution adopted by the present invention is a segmented resistor DAC dynamic mismatch calibration method for a successive approximation ADC, which specifically includes the following steps: Step 1: Use the switched capacitor sampling circuit to obtain V IN Voltage value; Step 2: Use the comparator module to compare V IN With V DAC The comparison result is passed to the SAR logic control circuit; Step 3, performing DEM switching by the resistance sequence of the high-order resistor string in the segmented resistor DAC module; Step 4: The SAR logic control circuit controls the segmented resistor DAC output voltage value V according to the level of the comparator output obtained in step 2. DAC ; Step 5: According to V DAC The voltage is compared N×L times, and the obtained N L-bit digital codes are first stored in the register and then input together to the DEM averaging module for averaging, thereby realizing dynamic calibration of the resistance mismatch on the segmented resistor DAC.

[0012] The second technical solution of the present invention is also characterized in that: In step 3, the specific process of switching the resistors on the high resistor string is as follows: first, switch the 2K The resistors are divided into P groups, each containing Q resistors. The ADC switches the order of the high-order resistor string every time it completes a comparison. During switching, the P group resistor string follows a rolling switch from bottom to top, while the Q resistors in the group follow a rolling switch from top to bottom. An L-bit ADC will perform L comparisons per single conversion. A complete ADC that has undergone dynamic mismatch calibration requires N conversions. Therefore, the high-order resistor string needs to be switched N × L times in sequence.

[0013] In step 3, during the high level period of the first clock cycle in the first conversion, switches S1, S3 and S4 are turned on, and the input voltage to be converted V is sampled by the switched capacitor circuit. IN The charge is stored on the sampling capacitor Cs. At this time, the operational amplifier COMP1 is connected in a unity gain negative feedback form. During the low level period of the first clock cycle, the switch S2 is turned on, and the output voltage V DAC Passed to the sampling capacitor Cs, V DAC With input voltage V IN The difference plus the reference voltage V R and V R +V DAC -V in The result is passed to the negative terminal of the operational amplifier COMP1, and the positive terminal of the operational amplifier COMP1 is the reference voltage V R , at this time the operational amplifier COMP1 is used as a comparator for comparison.

[0014] The beneficial effects of the present invention are as follows: 1) The present invention provides a dynamic mismatch calibration method for a segmented resistor DAC used in a successive approximation ADC. This method can calibrate the high-order resistor string of the segmented resistor DAC, significantly improving the mismatch of resistor values ​​and avoiding the complexities of detecting and adjusting the value of a single resistor. The method has a simple structure and is easy to implement.

[0015] 2) The present invention can achieve dynamic calibration without manual intervention. It uses the principle of dynamic element matching to average the mismatch of resistors, thereby improving the reliability of the circuit and the overall accuracy of the DAC and ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of the segmented resistor DAC dynamic mismatch calibration circuit for successive approximation ADC of the present invention; Figure 2 for Figure 1 Schematic diagram of the area division of the resistors on the high-order resistor string in the segmented resistor DAC module; Figure 3 (a) to Figure 3 (b) are Figure 2Schematic diagram of the DEM switching scheme for the high-order resistor string when K=6, P=8, and Q=8, where Figure 3(a) shows the upper and lower connection sequence diagram of the P group of resistor strings, and Figure 3(b) shows the upper and lower connection sequence diagram of the Q resistors in the first group of resistor strings; Figure 4 A schematic diagram of the overall clock of a single dynamic mismatch calibration process of a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation ADC according to the present invention; Figure 5 FIG3 is a timing diagram of the switch conduction sequence of the resistor strings in the P regions. DETAILED DESCRIPTION

[0017] The following describes it in detail with reference to specific implementation methods.

[0018] Example 1 The present invention is used for a segmented resistor DAC dynamic mismatch calibration circuit of a successive approximation ADC, such as Figure 1 As shown, it includes a switched capacitor sampling circuit, a comparator module, a SAR logic control circuit, a segmented resistor DAC using dynamic element matching (DEM) switching, and a DEM averaging module.

[0019] Example 2 The input end of the switched capacitor sampling circuit is connected to the voltage to be sampled V IN , one end is connected to the output voltage V of the segmented resistor DAC DAC The output end of the switched capacitor sampling circuit is connected to the input end of the comparator module, the output end of the comparator module is connected to the SAR logic control circuit, the output of the SAR logic control circuit controls the output voltage of the segmented resistor DAC, and the SAR logic control circuit also transmits the comparator result to the register; the output end of the register is connected to the DEM averaging module, and the final overall result is output by the DEM averaging module.

[0020] Example 3 The switched capacitor sampling and comparison circuit is used to sample the analog voltage V from the front end of the chip. IN And compare it with the analog voltage V output by DAC DAC The comparator's output signal is transmitted to the SAR logic control circuit, whose output is connected to the control terminal of a segmented resistor DAC with DEM switching. The SAR logic control circuit also transmits the comparator's result to a register. Finally, the DEM averaging module averages the results of N analog-to-digital conversions to obtain a digital output value.

[0021] Example 4 The switched capacitor sampling circuit module includes switch S1, switch S2, switch S3, switch S4, sampling capacitor Cs, compensation capacitor C LAnd op amp COMP1. One end of the sampling capacitor Cs is connected to S1 and S2 respectively, and the other end of the sampling capacitor Cs is connected to S3; the other end of the switch S1 is connected to the voltage to be sampled V IN , the other end of S2 is connected to the output voltage V of the segmented resistor DAC DAC One end of the switches S3 and S4 connected in series is connected to the output of COMP1, and the other end of the switches S3 and S4 connected in series is connected to the inverting input of COMP1 and the upper plate of capacitor Cs, so that COMP1 forms a negative feedback loop; compensation capacitor C L It is formed by an NMOS tube with three terminals connected to the source, drain and body, and is connected to the ground between the switch S3 and the switch S4 as a loop compensation capacitor; the positive input terminal of COMP1 is connected to the reference voltage V R connected.

[0022] The output of operational amplifier COMP1 is connected to the non-inverting input of operational amplifier COMP2 of the comparator module, and the inverting input of operational amplifier COMP2 is connected to the reference voltage V R The non-inverting output of the operational amplifier COMP2 is connected to the non-inverting input of the latch comparator, and the inverting output of the operational amplifier COMP2 is connected to the inverting input of the latch comparator; the output of the latch comparator is connected to the SAR logic control circuit.

[0023] The SAR logic control circuit uses successive approximation logic to control the on and off of the switches on the high and low resistance strings of the segmented resistance DAC, and controls the DEM switching of the resistors on the high resistance string; an output of the SAR logic control circuit is also connected to a register to pass the result obtained from the comparator module to the register.

[0024] The output of the register is first connected to the binary adder module of the DEM averaging module, the output of the binary adder module is connected to the binary divider module, and finally the output of the calibrated overall circuit is obtained from the binary divider module.

[0025] like Figure 2 As shown in the figure, the segmented resistance DAC that uses DEM for dynamic calibration consists of a high-bit resistance string, a low-bit resistance string, and a switch. An L-bit DAC can be divided into a K-bit resistance DAC with a high bit. K resistors, and a resistor DAC with the low bit being H, consisting of 2 H The high-order resistor string is composed of a single resistor using switches S1 to S (2 K +1) is connected in parallel with the low resistance string, and the resistance of the low resistance string is controlled by the switch S1' to S(2 H +1)' the conduction output V DAC .

[0026] Example 5 The present invention provides a segmented resistor DAC dynamic mismatch calibration method for a successive approximation ADC, which is implemented using the segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation ADC, and specifically includes the following steps: Step 1: Use the switched capacitor sampling circuit to obtain V IN Voltage value; For an L-bit ADC, in the first clock cycle, switches S1, S3, and S4 are turned on, and the input voltage to be converted V IN The sample is then transferred to capacitor Cs. At the same time, the SAR logic control circuit, segmented resistance DAC module, register, and DEM averaging module are all reset. After the first clock cycle, switches S1, S2, and S3 are always disconnected until the next conversion process begins. At this time, the voltage on the lower plate of capacitor Cs is V IN , the voltage on the upper plate of capacitor Cs is V R , COMP1 is now connected in the form of unity gain negative feedback; Step 2: Use the comparator module to quickly compare V IN With V DAC When the second clock cycle starts, the segmented resistor DAC starts to output V DAC Voltage, the first output V DAC Equal to 0.5V ref ; In the high level of the second clock cycle, switch S2 is turned on, and the voltage on the lower plate of capacitor Cs is equal to V DAC , the upper plate voltage of capacitor Cs is equal to (V DAC +V R -V IN ), in the low level of the second clock cycle, the upper plate voltage of capacitor Cs is equal to the reference voltage V R Comparison is done by the comparator module. If V IN >V DAC , then the comparator outputs a high level, if V IN <V DAC , then the comparator outputs a low level, and the final comparison result is passed to the SAR logic control circuit; Step 3: When the comparator module makes comparison, the resistance sequence of the high-order resistance string in the segmented resistance DAC module is switched by DEM. Before each comparison, the resistance on the high-order resistance string is switched once. The specific switching strategy is to first switch the 2 high-order resistance string to the same resistance. KThe resistors are divided into P groups, each containing Q resistors. The ADC switches the order of the high-order resistor strings each time it completes a comparison. The P group resistor strings follow a bottom-up rolling switch, while the Q resistors in the group follow a top-down rolling switch. An L-bit ADC performs L comparisons per single conversion, and a complete ADC with dynamic mismatch calibration requires N conversions, meaning that the high-order resistor strings need to be switched N × L times. Step 4: Complete the segmented resistor DAC output V after DEM switching DAC The SAR logic control circuit controls the on / off switching of the switches on the output voltage paths of the high-order resistor string and the low-order resistor string in the segmented resistor DAC according to the level of the comparator output obtained in step 2, thereby controlling the output voltage value of the segmented resistor DAC, such as V DAC The output value at the first comparison is 0.5Vref. At this time, the SAR logic control circuit makes S2 on the high-order resistor string in the segmented resistor DAC (K-1) Switch and S(2 (K -1) +1) switch and S(2 H +1)'switch is turned on; Step 5: Applying the DEM dynamic mismatch calibration technique requires a single V IN The voltage is converted N times, and the V output by the DAC in step 4 is DAC The voltages are compared N × L times, and the resulting N L-bit digital codes are first stored in a register and then fed together into a DEM averaging module for averaging. The averaged result is finally output, enabling dynamic calibration of resistor mismatch on the segmented resistor DAC in the SAR ADC.

[0027] In the above-mentioned successive approximation ADC, the quantization process is mainly based on the principle of binary division. First, during the high level period of the first clock cycle in the first conversion, switches S1, S3 and S4 are turned on, and the input voltage to be converted V is sampled by the switched capacitor circuit. IN The charge is stored on the sampling capacitor Cs. At this time, the operational amplifier COMP1 is connected in a unity gain negative feedback form. During the low level period of the first clock cycle, the switch S2 is turned on, and the output voltage V DAC Passed to the sampling capacitor Cs, V DAC With input voltage V IN The difference plus the reference voltage V R The sum (V R +V DAC -V in ), and pass the result to the negative terminal of the operational amplifier COMP1, the positive terminal of the operational amplifier COMP1 is the reference voltage V R, at this time the operational amplifier COMP1 is used as a comparator for comparison.

[0028] Next, the output voltage V COMP Connected to the non-inverting input of the comparator module, the inverting input is the reference voltage V R , the comparator module can quickly compare V IN Voltage and V DAC The voltage is measured and the result is passed to the SAR logic control circuit.

[0029] The analog voltage output by the DAC is determined by the SAR logic control circuit. The initial DAC output voltage V DAC,1 The size is 0.5V ref If the comparator outputs a high level, it means that V in >0.5V ref , then the SAR logic control circuit makes V DAC,2 0.75V ref ; If the comparator output is low, it means V in <0.5V ref , the next time the SAR logic control circuit will switch the DAC output voltage to 0.25V ref If the ADC resolution is L bits, then the above process will be repeated L times for each conversion. After each comparison, the output result of the comparator is used to select the next approximation method, and a 1-bit binary number is generated based on the comparison result, ultimately obtaining an L-bit digital code as the result of one conversion.

[0030] In a segmented resistor DAC, if the resolution is high, the mismatch error between resistors will have a significant impact on the accuracy of the DAC output voltage. Therefore, in order to improve the overall conversion accuracy, the present invention uses a dynamic element matching method to perform dynamic mismatch calibration on the high-order resistor string of the segmented resistor DAC. This method is performed by calibrating the mismatch error between resistors at each DAC output V DAC Before the voltage is applied, the arrangement order of the resistors in the high-order resistor string in the resistor DAC is adjusted to change the effect of the resistor mismatch under a fixed output voltage. IN Perform N analog-to-digital conversions. If the ADC is L-bit, each conversion requires L comparisons and the DAC also generates L outputs. After each DAC output, the high-order resistor string is rearranged according to a specific switching pattern. The conversion is completed, resulting in an L-bit binary code. After N conversions, the N L-bit results are averaged using the DEM to obtain the final conversion result. This solution dynamically averages the resistance mismatch of the high-order resistor string, effectively improving the overall conversion accuracy of the ADC.

[0031] Compared with the traditional resistor DAC, to achieve L bit resolution, the traditional structure requires (2 L -1) resistors, however, the present invention adopts a segmented resistor DAC method with high K bit and low H bit (K+H=L) in parallel, which reduces the number of resistors to (2 K +2 H -1), greatly reducing the circuit area. The segmented resistor DAC first converts the reference voltage V ref Perform coarse quantization, then connect the voltage across a resistor in the high-order resistor string in parallel to the low-order resistor string for fine quantization, and finally the DAC output voltage V DAC The voltage at a specific resistor node in a low-order resistor string. Resistor mismatch in a high-order resistor string has a greater impact on the DAC's output voltage accuracy than in a low-order resistor string. DEM is a calibration method that adjusts the connection relationship of mismatched components or changes their operating frequency to prevent error accumulation, thereby bringing the long-term average output closer to the ideal output.

[0032] Example 6 Figure 1 In the DEM averaging module shown, the ADC performs N analog-to-digital conversions for each input voltage. First, a binary adder adds the N binary code conversion results. Then, a binary divider divides the result by N to obtain the final average value, which is then output.

[0033] like Figure 2 As shown, the DEM calibration strategy in the present invention is to K The resistors are switched sequentially to change the effect of the resistor mismatch on each fixed output voltage, and the different quantization results are averaged to achieve dynamic calibration of the resistor mismatch. IN During analog-to-digital conversion, an L-bit ADC requires the DAC to output L analog voltages, so the high-order resistor string needs to be switched L times in sequence. Therefore, N conversions require a total of N×L sequential switches. The high-order resistor string is a K-bit DAC, consisting of 2 K These resistors are divided into P regions (R C1 to R CP ), each area consists of Q resistors (R M1 to R MQ ). C1 The area contains the resistor R M1 to R MQ Every time the ADC comparator completes a comparison, the order of the high-order resistor string will be switched. INThe voltage signal will undergo N analog-to-digital conversions, and the high-order resistor string will undergo N×L switching.

[0034] Figures 3(a) and 3(b) illustrate a switching scheme for the high-order resistor string of a segmented resistor DAC with K=6, P=8, and Q=8. The DAC consists of a 12-bit structure consisting of a high-order 6-bit resistor string and a low-order 6-bit resistor string connected in parallel. The high-order resistor switching follows the following strategy: the eight regional resistor strings are switched from bottom to top, while the eight sub-resistors within a region are switched from top to bottom. In Figure 3, (a) shows the arrangement of the high-order resistor string regions when P=8, with eight possible arrangements from left to right in columns; (b) shows the arrangement of the sub-resistors within each region when Q=8, with eight possible arrangements from left to right in columns. This strategy ensures that each mismatched resistor has the same probability of being located in any region of the resistor string. In the examples of Figure 3 (a) and Figure 3 (b), it is assumed that each analog voltage to be converted will undergo 4 analog-to-digital conversions, each analog-to-digital conversion requires 12 comparisons, and the DAC needs to output 12 analog voltages. The high-order resistor string needs to be switched 12 times, so there will be a total of 48 switches. If 8 switches are regarded as one cycle, the switching of the high-order resistor string will go through 6 cycles of sequential switching. Then, the DEM average processing is performed on the obtained 4 12-bit digital codes. The specific steps are: First, through the attached Figure 1 The binary adder in the DEM averaging module shown sums the four groups of digital codes, then uses a binary divider to average the DEMs, and finally outputs the final conversion result.

[0035] Figure 4 This is a timing diagram of a single ADC conversion in the present invention. The entire conversion cycle consists of (N × L + 2) clock cycles T, which include a sampling cycle, N × L quantization cycles, and an averaging cycle. The input signal is sampled in the first clock cycle, followed by analog-to-digital conversion every L clock cycles. N analog-to-digital conversions require a total of N × L clock cycles, and the final clock cycle completes the DEM averaging and outputs it.

[0036] Figure 5 The first resistor sequence in the switching scheme of Figure 3 (a) and Figure 3 (b), that is, the timing diagram of the P regional switches being turned on in the arrangement sequence of the first column in Figure 3 (a). According to the design of the present invention, there are 2 high-order resistor strings. K Resistors are connected in series. Each time a switch is made, if the switches on all the resistors in the high-order resistor string are turned on or off at the same time, it may cause the output voltage to be unable to be stably established for a long time. Therefore, to avoid this problem, it is necessary to perform clock non-overlap processing on the switch-on signal so that the resistor strings in the P regions of the high-order resistor string are switched sequentially. In the present invention, the switch control signals correspond to the P regions on the high-order resistor string respectively. When Figure 5 R in CP When the signal is at a high level, the high-order resistor string R CP The resistor string will be switched first, Figure 5 R in C(P-1) The signal is responsible for controlling the R C(P-1) The resistor string is then switched, and so on. There is a △t time interval between each resistor switching to ensure that R Cm to R C1 They can be stably connected in series, thus effectively avoiding the problem of unstable output voltage caused by simultaneous opening of switches.

Claims

1. A segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation register ADC, characterized by: It includes a switched capacitor sampling circuit, the input ends of which are connected to the voltage to be sampled V IN and the output voltage V of the segmented resistor DAC DAC The output end of the switched capacitor sampling circuit is connected to the input end of the comparator module, the output end of the comparator module is connected to the input end of the SAR logic control circuit, the output of the SAR logic control circuit controls the output voltage of the segmented resistor DAC, and the output of the SAR logic control circuit is also connected to the input end of the register, and the output end of the register is connected to the DEM averaging module.

2. The segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation register ADC according to claim 1, wherein: The switch capacitor sampling circuit module includes a sampling capacitor Cs, one end of the sampling capacitor Cs is connected to the switch S1 and the switch S2, and the other end of the sampling capacitor Cs is connected to the switch S3; the switch S1 is also connected to the voltage to be sampled V IN , switch S2 also connects the segmented resistor DAC output voltage V DAC ; The circuit also includes a switch S3 and a switch S4. One end of the switches S3 and S4 connected in series is connected to the output end of the operational amplifier COMP1. The other end of the switches S3 and S4 connected in series is connected to the inverting input end of the operational amplifier COMP1 and the upper plate of the sampling capacitor Cs. A compensation capacitor C is provided between the switches S3 and S4. L The non-inverting input of operational amplifier COMP1 is connected to the reference voltage V R .

3. The segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation register ADC according to claim 2, wherein: The comparator module includes an operational amplifier COMP2, the non-inverting input terminal of the operational amplifier COMP2 is connected to the output terminal of the operational amplifier COMP1, and the inverting input terminal of the operational amplifier COMP2 is connected to the reference voltage V R The non-inverting output of the operational amplifier COMP2 is connected to the non-inverting input of the latch comparator, and the inverting output of the operational amplifier COMP2 is connected to the inverting input of the latch comparator; the output of the latch comparator is connected to the SAR logic control circuit.

4. The segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation register ADC according to claim 3, wherein: The DEM averaging module comprises a binary adder module and a binary divider module which are connected in sequence, and the binary adder module is connected to the register.

5. The segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation register ADC according to claim 4, wherein: The segmented resistor DAC includes a high-order resistor string, the resistance of which is connected to the high-order resistor string by switches S1 to S (2 K +1) connected in series or parallel with a low-level resistor; The low-order resistor string is also included, and the resistors on the low-order resistor string are controlled by switches S1' to S(2 H +1)' the conduction output V DAC .

6. A method for dynamic mismatch calibration of a segmented resistor DAC for a successive approximation register ADC, characterized in that: The specific steps include: Step 1: Use the switched capacitor sampling circuit to obtain V IN Voltage value; Step 2: Use the comparator module to compare V IN With V DAC The comparison result is passed to the SAR logic control circuit; Step 3, performing DEM switching by the resistance sequence of the high-order resistor string in the segmented resistor DAC module; Step 4: The SAR logic control circuit controls the segmented resistor DAC output voltage value V according to the level of the comparator output obtained in step 2. DAC ; Step 5: According to V DAC The voltage is compared N×L times, and the obtained N L-bit digital codes are first stored in the register and then input together to the DEM averaging module for averaging, thereby realizing dynamic calibration of the resistance mismatch on the segmented resistor DAC.

7. The method for dynamic mismatch calibration of a segmented resistor DAC for a successive approximation register ADC according to claim 6, wherein: In step 3, the specific process of switching the resistors on the high resistor string is as follows: first, switch the 2 K The resistors are divided into P groups, each containing Q resistors. The ADC switches the order of the high-order resistor string every time it completes a comparison. During switching, the P group resistor string follows a rolling switch from bottom to top, while the Q resistors in the group follow a rolling switch from top to bottom. An L-bit ADC will perform L comparisons per single conversion. A complete ADC that has undergone dynamic mismatch calibration requires N conversions. Therefore, the high-order resistor string needs to be switched N × L times in sequence.

8. The method for dynamic mismatch calibration of a segmented resistor DAC for a successive approximation register ADC according to claim 7, wherein: In step 3, during the high level period of the first clock cycle in the first conversion, switches S1, S3 and S4 are turned on, and the input voltage to be converted V is sampled by the switched capacitor circuit. IN The charge is stored on the sampling capacitor Cs. At this time, the operational amplifier COMP1 is connected in a unity gain negative feedback form. During the low level period of the first clock cycle, the switch S2 is turned on, and the output voltage V DAC Passed to the sampling capacitor Cs, V DAC With input voltage V IN The difference plus the reference voltage V R and V R +V DAC -V in The result is passed to the negative terminal of the operational amplifier COMP1, and the positive terminal of the operational amplifier COMP1 is the reference voltage V R , at this time the operational amplifier COMP1 is used as a comparator for comparison.

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