Successive approximation analog-to-digital converter based on charge pump with doubled quantization range

Abstract

The application discloses a successive approximation analog-to-digital converter based on charge pump quantization range doubling, which improves the gate voltage bootstrap switch used for sampling and innovatively designs a passive reference voltage boosting circuit, wherein the capacitor in the gate voltage bootstrap switch is divided into two parts, is charged in parallel first and then in series, and can bootstrap the gate voltage of the sampling tube to 2 times of the power supply voltage; the passive reference voltage boosting circuit generates a voltage value of double power supply voltage by charging two capacitors with equal capacitance to the power supply voltage and then connecting them in series at the head and tail, and uses the voltage value as a reference voltage for ADC quantization. The application realizes that the ADC can correctly quantize an input signal with an amplitude of 2 times of the power supply voltage under the condition of low power supply voltage, expands the application range of the low-voltage ADC, meets the collaborative design of the analog circuit and the digital circuit in the ADC under an advanced process node, realizes full dynamic design, eliminates static current, and is also suitable for low-power ADC design.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital converters, and in particular relates to a successive approximation analog-to-digital converter based on doubling the quantization range of a charge pump. Background Art

[0002] ADC (Analog-to-Digital Converter) serves as a bridge between analog signals and digital signals. It can convert continuously changing analog signals in nature into discrete digital signals that can be processed by computers. It is an indispensable circuit module in fields such as communications, artificial intelligence, Internet of Things, and biomedicine.

[0003] With the development of advanced semiconductor processes, manufacturing has reached the nanometer node, allowing circuits to operate at lower voltages, with power supply voltages below 1V. This brings many advantages to digital circuits, such as lower power consumption, higher integration, and smaller area. However, for analog circuits, the design becomes more difficult due to factors such as the intrinsic gain and signal swing of transistors. ADCs, as a representative type of mixed-signal circuit, combine analog and digital circuits. Therefore, the ability to coordinate analog and digital circuits under low-voltage conditions is a key consideration when designing ADCs.

[0004] Among various ADC architectures, the SAR (Successive Approximation Register) ADC, due to its highly digital structure, is well-suited for low-voltage applications. However, it still includes analog circuitry such as sampling switches and reference voltage generation. In existing technology, the paper [Li Junhui. Design of a 10-bit Low-Voltage, Low-Power SAR ADC [D]. Nanjing: Southeast University, 2022] improves the gate voltage bootstrap switch used for sampling, ensuring that the gate voltage of the sampling tube is at the negative supply voltage when the phase is held, thus suppressing sampling distortion caused by subthreshold leakage at low voltages. Based on this, a SAR ADC operating at 0.6V in a 40nm process was designed. The paper [Chi Zhehan. Research and Design of Reference Voltage Circuits in 18-bit, 20MS / s Pipeline ADCs [D]. Jiangsu: Southeast University, 2022] designed a low-temperature-coefficient, high-precision 1.2V reference voltage circuit based on a bandgap reference circuit for capacitor array switching in pipeline ADCs, but this circuit was not optimized for low-voltage design. Reference [Becca. Design of low voltage and current model bandgap reference circuit [D]. Beijing: Beijing Institute of Technology, 2016] Based on the bandgap reference circuit of the folded cascode operational amplifier, a 0.6V stable output reference voltage circuit is designed to support ADC operation at low voltage and is suitable for low power design.

[0005] However, the above-mentioned existing research works mostly focus on how to support the normal operation of analog circuits under low-voltage power supply, but do not consider the problem of reduced ADC quantization range caused by low voltage, which limits the application scenarios of ADC. Summary of the Invention

[0006] In view of the above, the present invention provides a successive approximation analog-to-digital converter based on a charge pump with doubled quantization range, which can solve the problem of reduced maximum input signal quantization range caused by low voltage.

[0007] A successive approximation analog-to-digital converter based on doubling the quantization range of a charge pump, comprising:

[0008] Double gate voltage bootstrap sampling switch circuit for accurate sampling of differential input signals;

[0009] The capacitor array is used to receive the sampled signal and generate a differential residual signal through level switching of the lower plate;

[0010] A passive reference voltage boost circuit based on a charge pump is used to provide double the power supply voltage as a reference voltage for the lower plate of the capacitor array;

[0011] Dynamic comparator, used to compare the differential residual signal and generate N The comparison result is the final output of SARADC. N is the number of bits of SAR ADC;

[0012] The successive approximation control logic module controls the level switching of the lower plate of the capacitor array according to the comparison result, and provides corresponding clock signals for the passive reference voltage boost circuit and the dynamic comparator.

[0013] Furthermore, the passive reference voltage boost circuit includes N A charge pump boost circuit is formed, which is used to provide a reference voltage of double the power supply voltage to the lower plate of the bit capacitor of the corresponding position in the capacitor array. The charge pump boost circuit includes four switches S1~S4 and two capacitors C with equal capacitance. nREF,1 and C nREF,2 , where one end of S1 is connected to the power supply voltage V DD , the other end of S1 is connected to C nREF,1 One end is connected as node A, C nREF,1 The other end of S2 is connected to one end of S4, the other end of S2 is grounded, and the other end of S4 is connected to C nREF,2 One end is connected to the power supply voltage V DD , C nREF,2The other end of is connected to one end of S3 as node B, the other end of S3 is grounded, nodes A and B are connected to the lower plate of the P-end bit capacitor or the lower plate of the N-end bit capacitor of the corresponding position in the capacitor array, the control electrodes of S1~S3 are connected to the clock signal Φ1, and the control electrode of S4 is connected to the clock signal Φ2.

[0014] Furthermore, when the comparison result of the positive phase output of the dynamic comparator is 0, node A is connected to the lower plate of the P-end bit capacitor of the corresponding bit, and node B is connected to the lower plate of the N-end bit capacitor of the corresponding bit; when the comparison result of the positive phase output of the dynamic comparator is 1, node A is connected to the lower plate of the N-end bit capacitor of the corresponding bit, and node B is connected to the lower plate of the P-end bit capacitor of the corresponding bit.

[0015] Furthermore, the clock signals Φ1 and Φ2 are complementary in phase and have a certain dead time, and Φ1 is in phase with the SARADC sampling clock Φ S The switching timing is synchronized.

[0016] Furthermore, the capacitor array adopts CDAC (Capacitive Digital-to-Analog Converter).

[0017] Furthermore, the double gate voltage bootstrap sampling switch circuit includes two double gate voltage bootstrap sampling switches, which are used to sample the positive phase and negative phase input signals respectively. The double gate voltage bootstrap sampling switches include four PMOS transistors M1 to M4, seven NMOS transistors M5 to M11, and two capacitors C1 and C2 with equal capacitance, wherein the source of M1 is connected to the source of M2 and the gate of M5 and is connected to the power supply voltage V DD , the drain of M1 is connected to one end of C1 and the drain of M3, the gate of M1 is connected to the source of M3, the gate of M11, one end of C2 and the drain of M10, the drain of M2 is connected to the other end of C2 and the drain of M4, the gate of M2 is connected to the source of M4, the source of M5, the gate of M7 and the gate of M8, the drain of M5 is connected to the source of M6, the drain of M6 is grounded, the other end of C1 is connected to the drain of M9, the drain of M11, the source of M11 and the source of M7, the source of M9 is connected to the source of M10 and grounded, the drain of M7 is connected to the source of M8 and serves as the input end of the double gate voltage bootstrap sampling switch, the drain of M8 is connected to the upper plate of the bit capacitor at the P end or N end in the capacitor array as the output end of the double gate voltage bootstrap sampling switch, and the control electrodes of M3, M4, M6, M9 and M10 are connected to the clock signal , is the SAR ADC sampling clock Φ S The inverted clock.

[0018] Furthermore, the dynamic comparator includes six PMOS transistors Q4, Q5, Q10, Q11, Q12, Q13 and seven NMOS transistors Q1, Q2, Q3, Q6, Q7, Q8, Q9, wherein the source of Q4 is connected to the source of Q5, the source of Q12 and the source of Q13 and is connected to the power supply voltage V DD , the gate of Q4 is connected to the gate of Q5 and the gate of Q1 and is connected to the clock signal Φ C , the drain of Q4 is connected to the drain of Q2 and the gate of Q10, the drain of Q5 is connected to the drain of Q3 and the gate of Q11, the gate of Q2 is the non-inverting input of the dynamic comparator, the gate of Q3 is the inverting input of the dynamic comparator, the source of Q2 is connected to the source of Q3 and the drain of Q1, the source of Q1 is grounded, the drain of Q12 is connected to the source of Q10, the drain of Q13 is connected to the source of Q11, the gate of Q12 is connected to the gate of Q7, the drain of Q8, the drain of Q9 and the drain of Q11 and serves as the inverting output of the dynamic comparator, the gate of Q13 is connected to the gate of Q8, the drain of Q7, the drain of Q6 and the drain of Q10 and serves as the non-inverting output of the dynamic comparator, the source of Q6 is connected to the source of Q7, the source of Q8 and the source of Q9 and is grounded, and the gate of Q6 is connected to the gate of Q9 and connected to the clock signal , is Φ C The inverted clock.

[0019] Due to the charge sharing effect between capacitors, the actual weight of SAR ADC quantization deviates from the standard binary and needs to be recalculated according to the capacitor structure for the back-end digital-to-analog conversion work of signal reconstruction using the digital code output by SAR ADC. n The calculation expression is as follows:

[0020]

[0021]

[0022] Where: C n is the capacitance value of the nth bit capacitor in the capacitor array, C nREF The capacitor C in the charge pump boost circuit connected to the nth bit capacitor nREF,1 The capacitance value and C nREF =8C n , C k is the capacitance value of the kth bit capacitor in the capacitor array, C kREF =8C k , n is a natural number and 1≤n≤ N .

[0023] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0024] 1. This invention innovatively proposes a passive reference voltage boost circuit based on a charge pump boost circuit. By utilizing the characteristics of the charge pump capacitor stack, the low voltage V DD Boost to 2×V DD , as the reference voltage for quantization by the analog-to-digital converter.

[0025] 2. The present invention innovatively applies a passive reference voltage boost circuit based on a charge pump boost circuit to a successive approximation analog-to-digital converter, and combines it with a double gate voltage bootstrap sampling switch based on a charge pump to achieve the function of doubling the amplitude of the quantized input signal of the analog-to-digital converter.

[0026] 3. The charge pump-based passive reference voltage boost circuit of the present invention has only two capacitors and several switches as overhead, and has fully dynamic operating characteristics, with only dynamic current. Compared with other reference voltage circuits based on bandgap references that have static current, it has lower power consumption and is suitable for low-power analog-to-digital converter designs.

[0027] 4. The present invention does not require additional on-chip generation or off-chip injection of common-mode voltage, and has higher energy efficiency and hardware efficiency compared to other analog-to-digital converters based on common-mode voltage switching strategies.

[0028] 5. The present invention realizes the coordinated design of analog circuits and digital circuits in a low-voltage analog-to-digital converter, and is suitable for the design of low-voltage analog-to-digital converters at advanced process nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the structure of a successive approximation analog-to-digital converter in an embodiment of the present invention.

[0030] Figure 2 Schematic diagram of the charge pump boost circuit structure and switching clock in an embodiment of the present invention.

[0031] Figure 3 Schematic diagram of the double gate voltage bootstrap sampling switch circuit structure and switch clock in an embodiment of the present invention.

[0032] Figure 4 Schematic diagram of switching the lower plate of the CDAC bit capacitor of the passive reference voltage boost circuit in an embodiment of the present invention.

[0033] Figure 5 FIG. 4 is a schematic diagram of the circuit structure of a dynamic comparator in an embodiment of the present invention.

[0034] Figure 62 is a schematic diagram of a spectrum of a digital-to-analog conversion signal when the input signal frequency of the successive approximation analog-to-digital converter is low frequency in an embodiment of the present invention. In the figure, BW represents bandwidth, Fin represents input signal frequency, SNDR represents signal-to-noise and distortion ratio, and SNR represents signal-to-noise ratio.

[0035] Figure 7 Schematic diagram of a digital-to-analog conversion signal spectrum when the input signal frequency of the successive approximation analog-to-digital converter is the Nyquist frequency in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] The invention is based on a successive approximation analog-to-digital converter with doubled charge pump quantization range, comprising a double gate voltage bootstrap sampling switch, N Bit capacitor array, passive reference voltage boost circuit based on charge pump, dynamic comparator and successive approximation control logic module, the charge pump circuit in the passive reference voltage boost circuit converts V DD Boost to 2×V DD , helping to double the quantization range of the successive approximation analog-to-digital converter.

[0038] The upper and lower plates of the two capacitors in the charge pump boost circuit are each charged to V in the Φ1 phase of a set of non-overlapping clocks. DD and GND, connected in series at the beginning and end of the Φ2 phase, so that the upper plate voltage of the entire series capacitor is boosted to 2×V DD , the lower plate remains at GND and is used as a reference level for quantization by the analog-to-digital converter.

[0039] The dual gate voltage bootstrap sampling switch is a traditional gate voltage bootstrap switch with a charge pump boost circuit embedded in it to support a correct sampling amplitude of 2×V DD The passive reference voltage circuit uses a charge pump boost circuit to generate 2×V DD The reference voltage is obtained and connected to the CDAC according to the switching strategy based on the common-mode voltage to complete the voltage switching of each bit capacitor in the CDAC; after the SAR ADC completes the quantization, it outputs the digital result.

[0040] Since the reference voltage is provided by the capacitor rather than the power supply voltage, there is a charge sharing effect between the reference capacitor and the CDAC, which causes the actual weight of the SAR ADC quantization to deviate from the standard binary. It needs to be recalculated according to the CDAC capacitor topology to serve the back-end digital-to-analog conversion work of signal reconstruction using the digital code output by the SAR ADC. n The calculation expression is as follows:

[0041]

[0042]

[0043] Where: C n is the capacitance value of the nth bit capacitor in the capacitor array, C nREF The capacitor C in the charge pump boost circuit connected to the nth bit capacitor nREF,1 The capacitance value and C nREF =8C n , C k is the capacitance value of the kth bit capacitor in the capacitor array, C kREF =8C k , n is a natural number and 1≤n≤ N . Example

[0044] This embodiment realizes a 0.6V powered circuit with a 1.2V input signal quantization amplitude under a 65nm CMOS (Complementary Metal Oxide Semiconductor) process with a standard voltage of 1.2V. N =10-bit successive approximation analog-to-digital converter, its circuit structure is as follows Figure 1 As shown, the capacitor array includes 10 bit capacitors B1 to B10, corresponding to different unit capacitor sizes, and C represents the unit capacitor.

[0045] The charge pump boost circuit structure and switching clock in this embodiment are as follows Figure 2 As shown, it is controlled by a set of non-overlapping clocks Φ1 and Φ2. At Φ1, switches S1, S2 and S3 are turned on, and S4 is turned off, so that the two reference capacitors C nREF,1 and C nREF,2 Charge to V DD =0.6V and GND=0V. At Φ2, switches S1, S2 and S3 are disconnected, and S4 is turned on, which turns C nREF,1 The upper plate voltage V is raised to 2×V DD =1.2V.

[0046] The double gate voltage bootstrap sampling switch circuit and its control clock in this embodiment are as follows: Figure 3 As shown, where C1=C2, in Φ S =0, the circuit is in the "hold" state, M1, M2, M5, M6, M9 and M10 are turned on, so that the upper and lower plates of C1 and C2 are charged to V DD and GND; in Φ S =1, the circuit is in the "sampling" state, M3 and M4 are turned on, C1 and C2 are connected in series, and the gate voltage of M7 and M8 is boosted to 2×V DD , ensuring that the sampling tube has a sampling amplitude of 2×VDD The input signal is inputted, the gate-source voltage is unchanged, the sampling switch resistance is constant, and sampling distortion is avoided.

[0047] The specific implementation of the passive reference voltage circuit switching the lower plates of the capacitors of the CDAC is shown in Figure 4 The switching circuit of the 4th to 6th bits is shown in the figure, the lower plates of the capacitors of the bits are connected to the upper and lower plates of the reference voltage circuit according to the comparison result of the dynamic comparator, so as to update the residual voltage at the input end of the dynamic comparator, and the capacitors are short-circuited to realize reset in the sampling stage.

[0048] The structure of the dynamic comparator circuit in the embodiment is shown in Figure 5 The dynamic comparator circuit in the embodiment includes a preamplifier in the first stage and a latch in the second stage. C When the comparator clock Φ DD =0, the comparator is in a reset state, the parasitic capacitances of the VXN and VXP nodes are charged to V C =1, the comparator is in a working state, the preamplifier pulls down the charges of the VXN and VXP nodes at different speeds according to the sizes of the input signals VIP and VIN, and the latch establishes a latching state according to the voltage difference between VXN and VXP.

[0049] The dynamic performance of the 10-bit successive approximation type analog-to-digital converter in the embodiment is simulated at the circuit level, wherein Figure 6 The signal spectrum after digital-to-analog conversion of the SAR ADC output signal is shown in the figure, the SNDR is 60.27 dB, and the effective number of bits reaches 9.7 bits; Figure 7 The signal spectrum after digital-to-analog conversion of the SAR ADC output signal is shown in the figure, the SNDR is 60.03 dB, and the effective number of bits remains 9.7 bits; the correctness of the quantization result of the successive approximation type analog-to-digital converter is verified.

[0050] The successive approximation type analog-to-digital converter can correctly quantize the 1.2V input signal under the low power voltage of 0.6V, the digital and analog circuits in the analog-to-digital converter are designed in cooperation, and the analog-to-digital converter is suitable for low-voltage analog-to-digital converter design under an advanced process node; in addition, the full dynamic working mode is realized, the static current is eliminated, and the analog-to-digital converter is also suitable for low-power analog-to-digital converter design.

[0051] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A successive approximation analog-to-digital converter based on a charge pump quantization range doubling, characterized in that: include: Double gate voltage bootstrap sampling switch circuit for accurate sampling of differential input signals; The capacitor array is used to receive the sampled signal and generate a differential residual signal through level switching of the lower plate; A passive reference voltage boost circuit based on a charge pump is used to provide double the power supply voltage as a reference voltage for the lower plate of the capacitor array; Dynamic comparator, used to compare the differential residual signal and generate N The comparison result is used as the final output of SAR ADC. N is the number of bits of SAR ADC; The successive approximation control logic module controls the level switching of the lower plate of the capacitor array according to the comparison results, and provides the corresponding clock signal for the passive reference voltage boost circuit and the dynamic comparator; The passive reference voltage boost circuit includes N A charge pump boost circuit is formed, which is used to provide a reference voltage of double the power supply voltage to the lower plate of the bit capacitor of the corresponding position in the capacitor array. The charge pump boost circuit includes four switches S1~S4 and two capacitors C with equal capacitance. nREF,1 and C nREF,2 , where one end of S1 is connected to the power supply voltage V DD , the other end of S1 is connected to C nREF,1 One end is connected as node A, C nREF,1 The other end of S2 is connected to one end of S4, the other end of S2 is grounded, and the other end of S4 is connected to C nREF,2 One end is connected to the power supply voltage V DD , C nREF,2 The other end of S1 is connected to one end of S3 as node B, the other end of S3 is grounded, nodes A and B are connected to the lower plate of the P-end bit capacitor or the lower plate of the N-end bit capacitor of the corresponding position in the capacitor array, the control electrodes of S1 to S3 are connected to the clock signal Φ1, and the control electrode of S4 is connected to the clock signal Φ2; the clock signals Φ1 and Φ2 are complementary in phase and have a certain dead time, and Φ1 is parallel to the SAR ADC sampling clock Φ S The switching timing is synchronized.

2. The successive approximation analog-to-digital converter based on charge pump quantization range doubling according to claim 1, characterized in that: When the comparison result of the positive-phase output of the dynamic comparator is 0, node A is connected to the lower plate of the P-end bit capacitor of the corresponding bit, and node B is connected to the lower plate of the N-end bit capacitor of the corresponding bit; when the comparison result of the positive-phase output of the dynamic comparator is 1, node A is connected to the lower plate of the N-end bit capacitor of the corresponding bit, and node B is connected to the lower plate of the P-end bit capacitor of the corresponding bit.

3. The successive approximation analog-to-digital converter based on charge pump quantization range doubling according to claim 1, characterized in that: The capacitor array adopts CDAC.

4. The successive approximation analog-to-digital converter based on charge pump quantization range doubling according to claim 1, characterized in that: The double gate voltage bootstrap sampling switch circuit includes two double gate voltage bootstrap sampling switches, which are used to sample the positive and negative input signals respectively. The double gate voltage bootstrap sampling switches include four PMOS transistors M1 to M4, seven NMOS transistors M5 to M11, and two capacitors C1 and C2 with equal capacitance. The source of M1 is connected to the source of M2 and the gate of M5 and is connected to the power supply voltage V DD , the drain of M1 is connected to one end of C1 and the drain of M3, the gate of M1 is connected to the source of M3, the gate of M11, one end of C2 and the drain of M10, the drain of M2 is connected to the other end of C2 and the drain of M4, the gate of M2 is connected to the source of M4, the source of M5, the gate of M7 and the gate of M8, the drain of M5 is connected to the source of M6, the drain of M6 is grounded, the other end of C1 is connected to the drain of M9 and the source of M11, the drain of M11 is connected to the source of M7, the source of M9 is connected to the source of M10 and grounded, the drain of M7 is connected to the source of M8 and serves as the input end of the double gate voltage bootstrap sampling switch, the drain of M8 is connected to the upper plate of the bit capacitor at the P end or N end in the capacitor array as the output end of the double gate voltage bootstrap sampling switch, and the control electrodes of M3, M4, M6, M9 and M10 are connected to the clock signal , is the SAR ADC sampling clock Φ S The inverted clock.

5. The successive approximation analog-to-digital converter based on charge pump quantization range doubling according to claim 1, characterized in that: The dynamic comparator includes six PMOS transistors Q4, Q5, Q10, Q11, Q12, Q13 and seven NMOS transistors Q1, Q2, Q3, Q6, Q7, Q8, Q9, wherein the source of Q4 is connected to the source of Q5, the source of Q12 and the source of Q13 and is connected to the power supply voltage V DD , the gate of Q4 is connected to the gate of Q5 and the gate of Q1 and is connected to the clock signal Φ C , the drain of Q4 is connected to the drain of Q2 and the gate of Q10, the drain of Q5 is connected to the drain of Q3 and the gate of Q11, the gate of Q2 is the non-inverting input of the dynamic comparator, the gate of Q3 is the inverting input of the dynamic comparator, the source of Q2 is connected to the source of Q3 and the drain of Q1, the source of Q1 is grounded, the drain of Q12 is connected to the source of Q10, the drain of Q13 is connected to the source of Q11, the gate of Q12 is connected to the gate of Q7, the drain of Q8, the drain of Q9 and the drain of Q11 and serves as the inverting output of the dynamic comparator, the gate of Q13 is connected to the gate of Q8, the drain of Q7, the drain of Q6 and the drain of Q10 and serves as the non-inverting output of the dynamic comparator, the source of Q6 is connected to the source of Q7, the source of Q8 and the source of Q9 and is grounded, and the gate of Q6 is connected to the gate of Q9 and connected to the clock signal , is Φ C The inverted clock.

6. The successive approximation analog-to-digital converter based on charge pump quantization range doubling according to claim 1, characterized in that: The actual weight of the n-th bit capacitor in the capacitor array is W n The calculation expression is as follows: Where: C n is the capacitance value of the nth bit capacitor in the capacitor array, C nREF The capacitor C in the charge pump boost circuit connected to the nth bit capacitor nREF,1 The capacitance value and C nREF =8C n , C k is the capacitance value of the kth bit capacitor in the capacitor array, C kREF =8C k , n is a natural number and 1≤n≤ N .

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