Quasi-cyclic double-diagonal LDPC (Low Density Parity Check) coding device, system and method for efficiently utilizing resources

Abstract

The invention discloses a quasi-cyclic double diagonal LDPC (Low Density Parity Check) coding device, system and method capable of efficiently utilizing resources, and belongs to the field of LDPC coding, and the device comprises an RAM (Random Access Memory) storage module, a read address calculation module, a check bit operation module and a control module; the RAM storage module is used for storing data to be coded; the read address calculation module is used for circularly reading the data to be coded in the RAM; the check bit operation module is used for executing exclusive-or operation on the read data to be coded to directly generate check data; and the control module is used for dynamically adjusting the working state of the encoder so as to realize compatibility with different spread spectrum rates. The method is suitable for a spread spectrum communication system, and has the advantages of few storage resources, simplicity in operation, controllable coding rate and high universality.

Description

Technical Field

[0001] The present invention relates to the field of LDPC coding, and more specifically, to a quasi-cyclic dual-diagonal LDPC coding device, system and method for efficient resource utilization. Background Art

[0002] LDPC (Low-Density Parity-Check) codes have been widely used in satellite communications due to their high coding gain, low hardware implementation complexity, and fast computational capabilities supporting parallel processing. Commonly used LDPC codes in satellite communications include AR4JA codes (compliant with the CCSDS standard) and quasi-cyclic bidiagonal codes (common in DVB-S2 and 802.11 standards). These coding schemes each have their own unique characteristics and are suitable for different application scenarios.

[0003] While quasi-cyclic bi-diagonal LDPC codes do not offer a significant advantage in bit error rate performance compared to AR4JA codes, their unique structural design enables direct encoding, reducing the complexity of the encoding process. This characteristic has led to their widespread application in spread-spectrum communication systems within satellite communications, particularly in scenarios requiring direct encoding and demanding high resource utilization efficiency, where they offer a significant advantage in balancing coding efficiency and resource consumption.

[0004] Current research literature focuses primarily on the architecture and implementation of high-rate LDPC encoders, particularly solutions designed to achieve high throughput. For example, the paper "FPGA Design of a 10Gbps LDPC Encoder" proposes an FPGA-based LDPC encoder capable of achieving up to 10Gbps of information throughput at a 200MHz clock frequency, while occupying only approximately 50% of the chip's memory resources and no more than 15% of its logic resources, demonstrating a good balance in resource efficiency. Another study, "Design and Implementation of an IEEE 802.11ac Low-Density Parity-Check Code Encoder Based on a Digital Signal Processor," uses a low-complexity, fast-iteration algorithm to achieve an average coding rate of 1Gbps on a DSP platform, highlighting the importance of minimizing resource consumption while maintaining performance. The paper titled "A High-Speed ​​LDPC Encoder and Coding Method Based on FPGA Compatible with DVB-S2" goes a step further and designs an LDPC encoder that is compatible with multiple DVB-S2 code rates. By achieving a throughput of 4Gbps at a main frequency of 200MHz, it demonstrates the technical potential in balancing high performance and resource utilization efficiency.

[0005] However, such encoders often consume excessively high resources in low- and medium-speed communication scenarios. For resource-constrained applications, excessive pursuit of high-speed encoders can lead to resource waste. Furthermore, existing research has largely focused on the design of individual encoders, lacking in-depth exploration of the overall optimization of the encoder and the entire spread-spectrum communication system. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a quasi-cyclic dual-diagonal LDPC coding device, system and method with efficient resource utilization, which is particularly suitable for spread spectrum communication systems and has the advantages of small storage resources, simple calculations, controllable coding rate and strong versatility.

[0007] The object of the present invention is achieved through the following solutions:

[0008] A quasi-cyclic dual-diagonal LDPC encoding device with efficient resource utilization includes a RAM storage module, a read address calculation module, a check bit operation module and a control module;

[0009] The RAM storage module is used to store data to be encoded;

[0010] The read address calculation module is used to cyclically read the data to be encoded in the RAM;

[0011] The check bit operation module is used to perform an exclusive OR operation on the read coded data to directly generate check data;

[0012] The control module is used to dynamically adjust the working state of the encoder to achieve compatibility with different spreading rates.

[0013] Furthermore, in the read address calculation module, the cyclic reading of the data to be encoded in the RAM specifically includes the following sub-steps:

[0014] Step 1: The parity check matrix H of the quasi-cyclic bidiagonal LDPC code m×n is composed of m b ×n b The basis matrix H b The only mark, H b Each element in the matrix corresponds to a z×z submatrix in the H matrix; the first k elements in the H matrix b The column definition is H b1 , corresponding to the system bit part; after m b The column definition is H b2 , the part corresponding to the check bit;

[0015]

[0016] H b2The -1 in the matrix represents a z×z all-zero matrix, and the non-negative integer a represents the permutation matrix after the unit integer is cyclically shifted right by a positions; H b2 The first column of the matrix contains only three elements not equal to -1, located in the first row, the mth b -1 row and x row, and k row b The 1st row and the mth row in the column b The values ​​of the elements in the -1th row are the same, which is defined as l, and the values ​​of the elements in the xth row are defined as l x ;

[0017] Define the encoded vector as H b1 The submatrix in is L i , H b1 The first k rows of the matrix and the c vector b The result of multiplying the sub-vectors is expressed as b i =L i s, Indicates p i The vector obtained by circularly shifting l to the right;

[0018] Step 2: c×H T =0 to get m b equations, where:

[0019]

[0020] b i +p i +p i+1 =0 1≤i≤m b -2,i≠x (3);

[0021]

[0022] Step 3: m b By summing up the equations, we get:

[0023]

[0024] Step 4: Substitute formula (6) into formula (2) and formula (5) to obtain and p1, and finally substitute into formula (4) to obtain the remaining p x ;

[0025] Assume that the length of the vector x to be encoded is 1×(z×k b ), H b1 The matrix is ​​divided into blocks according to super rows, and we get The size of each H sub-matrix block is z×(z×k b );b i =L is matrix sub-block L i There are ti non-zero elements in the pth row, and the column positions of the non-zero elements are defined as Then b i (0)= Rewriting formula (6), we get but

[0026]

[0027] Furthermore, in the control module, the dynamic adjustment of the working state of the encoder to achieve compatibility with different spreading rates specifically includes the following sub-steps:

[0028] During spread spectrum communication, after the system completes the calculation of a check bit, it enters a preset idle waiting state. The length of this waiting time is set according to the current spreading factor and the actual time required for the current check bit calculation, which is used to ensure that the calculation cycle of each check bit is uniform, thereby achieving uniform output of the check bits. At the same time, the output coded data rate is adjusted according to the current spreading factor, so that it can adaptively match the rate requirements of the spread spectrum module and ensure that the information transmission rate is controllable.

[0029] Furthermore, the read address calculation module is implemented based on an FPGA platform.

[0030] A spread spectrum communication system comprises the resource-efficient quasi-cyclic dual-diagonal LDPC coding device as described in any one of the above items.

[0031] A quasi-cyclic dual-diagonal LDPC coding method with efficient resource utilization comprises the following steps:

[0032] S1, for the FPGA platform, optimizes the encoding operation of the quasi-cyclic bi-diagonal LDPC code and cyclically reads the data to be encoded in the RAM;

[0033] S2, performs an XOR operation on the read coded data to directly generate the check data;

[0034] S3 achieves compatibility with different spreading rates by dynamically adjusting the working state of the encoder.

[0035] The beneficial effects of the present invention include:

[0036] (1) Low computational complexity. The encoder design of the present invention relies solely on the XOR operation and the calculation of the read address of the encoded data, avoiding complex mathematical operations and the use of a large number of logic gates, thereby significantly reducing computational complexity. As a basic logical operation, the XOR operation is very simple to implement in hardware and has a fast execution speed.

[0037] (2) Existing encoder technologies often require the storage of a large number of intermediate variables to support complex calculations, which not only increases hardware resource consumption but also limits the scalability and flexibility of the system. The technical solution of the present invention, through clever design, avoids the storage of intermediate variables for check digit calculations, significantly saving storage resources. This approach not only reduces hardware costs but also improves the integration and reliability of the encoder, enabling the system to operate efficiently in resource-constrained environments.

[0038] (3) The technical solution of the present invention dynamically reconfigures the encoder through a control module to achieve a variety of coding throughput rates that match spread spectrum modulation. This enables the encoder to adjust its operating mode to match the processing requirements of different rates and data streams according to the needs of actual application scenarios, thereby improving the compatibility of the encoder with subsequent cascade modules. This ensures that the encoder and subsequent cascade modules (such as modulators and spreaders) maintain a good collaborative working state, thereby improving the stability and performance of the entire system.

[0039] (4) The method proposed in this invention is highly versatile and can be applied to LDPC codes of various code rates and code lengths. This versatility not only expands the application range of LDPC codes but also simplifies the design and implementation of encoders, reducing development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 This is a block diagram of the module structure of the device according to an embodiment of the present invention;

[0042] Figure 2 Schematic diagram of a spread spectrum system. DETAILED DESCRIPTION

[0043] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0044] The specific implementation process of the present invention is as follows:

[0045] As a first aspect of the present invention, a quasi-cyclic dual-diagonal LDPC encoding device with efficient resource utilization is provided, comprising a RAM module for storing data to be encoded, a read address calculation module, a check bit operation module and a control module, such as Figure 1 shown.

[0046] (1) RAM module for storing data to be encoded: In the encoding process of traditional LDPC codes, in order to ensure the correctness and integrity of the encoding, it is often necessary to store a large number of intermediate variables, including but not limited to the check matrix, the intermediate values ​​of the encoding operation, etc. The storage of these intermediate variables not only increases the burden on the hardware, but may also limit the overall performance and resource utilization efficiency of the system. In contrast, the present invention avoids the need to store these intermediate variables by optimizing the algorithm design, and only requires the data to be encoded to be stored in the RAM. The data in the RAM is repeatedly read by the control module and the read address calculation module, and the XOR operation is performed on it to obtain the check data.

[0047] (2) Read address calculation module: The check matrix H of the quasi-cyclic bidiagonal LDPC code m×n can be obtained by m b ×n b The basis matrix H b The only mark, H b Each element in corresponds to a z×z submatrix in the H matrix. b The column definition is H b1 , corresponding to the system bit part; after m b The column definition is H b2 , corresponding to the check bit.

[0048]

[0049] H b2 The -1 in the matrix represents a z×z all-zero matrix, and the non-negative integer a represents the permutation matrix after the unit integer is cyclically shifted right by a positions. b2 The first column of the matrix contains only three elements not equal to -1, located in the first row, the mth b -1 row and x row, and k row b The 1st row and the mth row in the column b The values ​​of the elements in the -1th row are the same, which is defined as l, and the values ​​of the elements in the xth row are defined as l x .

[0050] Define the encoded vector as H b1 The submatrix in is L i , H b1 The first k rows of the matrix and the c vector b The result of multiplying the sub-vectors can be expressed as b i =L i s, Indicates p i The vector obtained by circularly right shifting l.

[0051] By c×HT =0 can get m b equations, where:

[0052]

[0053] b i +p i +p i+1 =0 1≤i≤m b -2,i≠x (3)

[0054]

[0055] M b By summing up the equations, we get:

[0056]

[0057] Substituting formula (6) into formula (2) and formula (5), we can obtain and p1, and finally substitute into formula (4) to obtain the remaining p x .

[0058] The length of the vector x to be encoded is 1×(z×k b ), H b1 The matrix is ​​divided into blocks according to super rows, and we get The size of each H sub-matrix block is z×(z×k b ). b i =L i s matrix sub-block L i There are ti non-zero elements in the pth row, and the column positions of the non-zero elements are defined as but

[0059] Rewriting formula (6), we get but

[0060]

[0061] (3) Check bit operation module: Considering that the basic operation of the encoder is modulo-2 addition, this feature is converted into a simple XOR operation in the hardware design. The execution time of each XOR operation is equal to the FPGA clock cycle. Therefore, the number of clock cycles required to calculate and generate each check bit directly depends on the number of variables involved in the XOR operation, that is, the sum of the row weights of all check matrices Hn involved in the operation. Given the sparse nature of the check matrix of the LDPC code, it means that the row weight of Hn is usually small, mostly single digits, which reduces the number of variables involved in the operation. Correspondingly, the number of clock cycles required to calculate the check bit is also relatively low. The spread spectrum multiplier of the spread spectrum communication system is large, generally much greater than the number of clocks required to calculate a check bit. It is worth noting that the number of variables involved in the generation of different check bits varies, which leads to inconsistency in the operation time.

[0062] (4) Control Module: To ensure uniform output of parity bits and improve compatibility between the entire LDPC coding module and the subsequent spread spectrum modulation module, we introduced an intelligent control mechanism. This mechanism is processed through a specific control module to achieve precise system optimization.

[0063] Specifically, during spread spectrum communication, after the system completes calculation of a parity bit, it enters a preset idle wait state. The length of this wait period is carefully set based on the current spread factor and the actual time required to calculate the parity bit. This ensures that the calculation cycle for each parity bit is uniform, thereby achieving uniform parity bit output. This design greatly improves system stability and reduces the potential risk of data disorder.

[0064] Our design also features adaptability, flexibly adjusting the output coded data rate based on the current spreading factor. This means the system can adaptively match the rate requirements of the spreading module, ensuring a controllable information transmission rate. This capability not only enhances compatibility with the next-level spreading modulation module but also significantly improves the performance and efficiency of the overall communication system.

[0065] In summary, by introducing the intelligent control module and optimizing its workflow, the present invention successfully achieves uniform output of check bits, controls the coding rate, improves the compatibility of the system with subsequent modules, and thus optimizes the overall performance of the spread spectrum communication system.

[0066] In addition, the present invention provides an LDPC coding scheme specially designed for spread spectrum communication systems, which optimizes storage resource management, streamlines calculation processes, strengthens the coding rate control mechanism, and ensures its wide applicability. The scheme consists of RAM storage, read address calculation, check bit operation and control module, which can achieve efficient data coding and processing. Specifically, for the FPGA platform, by optimizing the coding operation of the quasi-cyclic dual-diagonal LDPC code, the scheme can cyclically read the data to be encoded in the RAM and perform XOR operations to directly generate check data, which significantly reduces the computational complexity and storage resource consumption. The check bit operation adopts XOR operations, which not only simplifies the hardware structure, but also reduces resource occupation. The control module achieves compatibility with different spread spectrum rates by dynamically adjusting the working state of the encoder, thereby improving the adaptability between the encoded data and subsequent modules. This LDPC coding scheme supports various code rates and code lengths, and demonstrates significant advantages in computational complexity, storage resource consumption, coding throughput adaptability and method versatility. Therefore, it provides an efficient and flexible coding solution for spread spectrum communication systems. Figure 2 shown.

[0067] In another embodiment, the dual diagonal LDPC code in Table 2 is taken as an example for detailed description.

[0068] Table 2

[0069]

[0070]

[0071] From Table 2, we can see that x =0, l=1, the relationship between p and b can be calculated according to formula (2)-formula (6), where p01 is obtained by shifting p0 right by one bit.

[0072] P0=b0+b1+b2+b3+b4+b5+b6+b7+b8+b9+b10+b11

[0073] P1=b0+p01

[0074] P2=b0+b1+p01

[0075] P3=b3+b4+b5+b6+b7+b8+b9+b10+b11+p01

[0076] P4=b4+b5+b6+b7+b8+b9+b10+b11+p01

[0077] P5=b5+b6+b7+b8+b9+b10+b11+p01

[0078] P6=b6+b7+b8+b9+b10+b11+p01

[0079] P7=b7+b8+b9+b10+b11+p01

[0080] P8=b8+b9+b10+b11+p01

[0081] P9=b9+b10+b11+p01

[0082] P10=b10+b11+p01

[0083] P11=b11+p01

[0084] Since p0 is the sum of b0 to b11, p01 is equivalent to the sum of b0 to b11, shifted right by 1 bit. This is the sum of 12 bits. Therefore, p1 is equivalent to the sum of 13 bits. Similarly, we can derive the number of bits required for the summation of the 12 pn values.

[0085] To calculate the value of bn, we only need to perform an XOR operation on the x values ​​at specific positions. The number of x values ​​required to calculate each bn is related to the row weight of Hn. To calculate p0, we need to accumulate b0 to b11. The number of x values ​​required for the operation is the sum of the row weights of H0 to H12. The row weight values ​​in Table 2 show that calculating p0 requires an XOR operation on 50 x values. By analogy, we can determine the number of x values ​​required for each of the 12 pn operations.

[0086] Since the H matrix has a quasi-cyclic property, we only need to know the position of the non-zero submatrix in the H matrix and its offset value to know the position of x that needs to be involved in the calculation when calculating p.

[0087] Assume that H0 = [-1a-1 -1-1 -1b c-1 -1d-1], the row weight is 4, where a, b, c, d are the offset values ​​of the non-zero submatrix, and the size of the submatrix is ​​z×z. Then the addresses of the x values ​​required to calculate b0(0) are z+a, 6×z+b, 7×z+c, 11×z+d, and the addresses of the x values ​​required to calculate b0(1) are z+a+1, 6×z+b+1, 7×z+c+1, 11×z+d+1. Similarly, the values ​​of all x involved in the operation can be read out, and a simple XOR operation can be performed on them to output the value of the check bit.

[0088] Since only a simple XOR operation is required on x, the number of clocks required to calculate a single pn(i) value is equal to the number of x values ​​involved in the operation. As shown in Table 3, the number of x values ​​required to calculate different pn values ​​varies, so the time required to calculate a single pn(i) value also varies. Taking a 128x spreading factor as an example, calculating the pn(i) value within 128 clocks is sufficient to meet the design requirements. As shown in Table 3, the maximum number of clocks required to calculate a single pn(i) value is 88. After the calculation is completed, the system idles and waits until 128 clocks have passed before calculating the next pn(i). This allows for coordination with the post-encoding spreading module.

[0089] Table 3

[0090] P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 b 12 13 14 21 20 19 18 17 16 15 14 13 x 50 54 58 88 84 79 74 70 66 62 58 53

[0091] As a second aspect of the present invention, based on the above device, a spread spectrum communication system is provided, comprising the resource-efficient quasi-cyclic dual-diagonal LDPC coding device as described in any one of the above items.

[0092] As a third aspect of the present invention, based on the above-mentioned apparatus, a quasi-cyclic dual-diagonal LDPC coding method with efficient resource utilization is provided, which performs the following steps:

[0093] S1, for the FPGA platform, optimizes the encoding operation of the quasi-cyclic bi-diagonal LDPC code and cyclically reads the data to be encoded in the RAM;

[0094] S2, performs an XOR operation on the read coded data to directly generate the check data;

[0095] S3 achieves compatibility with different spreading rates by dynamically adjusting the working state of the encoder.

[0096] The units involved in the embodiments of the present invention may be implemented in software or hardware, and the units described may also be provided in a processor. In some cases, the names of these units do not limit the units themselves.

[0097] According to one aspect of an embodiment of the present invention, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0098] As another aspect, embodiments of the present invention further provide a computer-readable medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not incorporated into the electronic device. The computer-readable medium carries one or more programs, and when executed by the electronic device, the electronic device implements the methods described in the above embodiments.

Claims

1. A quasi-cyclic dual-diagonal LDPC coding device with efficient resource utilization, characterized in that: It includes a RAM storage module, a read address calculation module, a check bit operation module and a control module; The RAM storage module is used to store data to be encoded; The read address calculation module is used to cyclically read the data to be encoded in the RAM; The check bit operation module is used to perform an exclusive OR operation on the read coded data to directly generate check data; The control module is used to dynamically adjust the working state of the encoder to achieve compatibility with different spreading rates.

2. The resource-efficient quasi-cyclic dual-diagonal LDPC encoding device according to claim 1, characterized in that: In the read address calculation module, the cyclic reading of the data to be encoded in the RAM specifically includes the following sub-steps: Step 1: The check matrix H of the quasi-cyclic bidiagonal LDPC code m×n is composed of m b ×n b The basis matrix H b The only mark, H b Each element in the matrix corresponds to a z×z submatrix in the H matrix; the first k elements in the H matrix b The column definition is H b1 , corresponding to the system bit part; after m b The column definition is H b2 , the part corresponding to the check bit; H b2 The -1 in the matrix represents a z×z all-zero matrix, and the non-negative integer a represents the permutation matrix after the unit integer is cyclically shifted right by a positions; H b2 The first column of the matrix contains only three elements not equal to -1, located in the first row, the mth b -1 row and x row, and k row b The 1st row and the mth row in the column b The values ​​of the elements in the -1th row are the same, which is defined as l, and the values ​​of the elements in the xth row are defined as l x ; Define the encoded vector as H b1 The submatrix in is L i , H b1 The first k rows of the matrix and the c vector b The result of multiplying the sub-vectors is expressed as b i =L i s, Indicates p i The vector obtained by circularly shifting l to the right; Step 2: c×H T =0 to get m b equations, where: b i +p i +p i+1 =0 1≤i≤m b -2,i≠x (3); Step 3: m b By summing up the equations, we get: Step 4: Substitute formula (6) into formula (2) and formula (5) to obtain and p1, and finally substitute into formula (4) to obtain the remaining p x ; Assume that the length of the vector x to be encoded is 1×(z×k b ), H b1 The matrix is ​​divided into blocks according to super rows, and we get The size of each H sub-matrix block is z×(z×k b );b i =L i s matrix sub-block L i There are ti non-zero elements in the pth row, and the column positions of the non-zero elements are defined as but Rewriting formula (6), we get but 3. The resource-efficient quasi-cyclic dual-diagonal LDPC encoding device according to claim 1, characterized in that: In the control module, the dynamic adjustment of the encoder's working state to achieve compatibility with different spreading rates specifically includes the following sub-steps: During spread spectrum communication, after the system completes the calculation of a check bit, it enters a preset idle waiting state. The length of this waiting time is set according to the current spreading factor and the actual time required for the current check bit calculation, which is used to ensure that the calculation cycle of each check bit is uniform, thereby achieving uniform output of the check bits. At the same time, the output coded data rate is adjusted according to the current spreading factor, so that it can adaptively match the rate requirements of the spread spectrum module and ensure that the information transmission rate is controllable.

4. The resource-efficient quasi-cyclic dual-diagonal LDPC encoding device according to claim 2, characterized in that: The read address calculation module is implemented based on an FPGA platform.

5. A spread spectrum communication system, characterized in that: The invention comprises the resource-efficient quasi-cyclic dual-diagonal LDPC encoding device according to any one of claims 1 to 4.

6. A quasi-cyclic dual-diagonal LDPC coding method with efficient resource utilization, characterized in that: The following steps are involved: S1, for the FPGA platform, optimizes the encoding operation of the quasi-cyclic bi-diagonal LDPC code and cyclically reads the data to be encoded in the RAM; S2, performs an XOR operation on the read coded data to directly generate the check data; S3 achieves compatibility with different spreading rates by dynamically adjusting the working state of the encoder.

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