Gallium nitride high electron mobility transistor and manufacturing method thereof
By using the heat dissipation structure of materials such as molybdenum substrates and aluminum nitride in gallium nitride high-electron mobility transistors, the problems of poor heat dissipation and high cost are solved, and efficient heat dissipation and cost reduction are achieved, which is suitable for packaging of power semiconductor components.
Patent Information
- Application Number
- CN202410194957.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-22
- Publication Date
- 2025-08-26
AI Technical Summary
Existing GaN high-electron mobility transistors have problems of poor heat dissipation and high manufacturing costs, especially when using single-crystal sapphire substrates, the thermal conductivity is low and the material cost is high, and it is difficult to package and integrate with Si MOSFET power semiconductor components and RF components.
Molybdenum substrate is used as the heat dissipation metal plate, combined with aluminum nitride, boron nitride or silicon carbide as the heat dissipation insulating layer, and the electrode is electrically connected to the heat dissipation metal plate through a conductive structure to achieve rapid heat radiation and lead the electrode to the back of the transistor, reducing the packaging cost.
Improves the heat dissipation of transistors, reduces manufacturing costs, and improves durability and packaging flexibility, and is suitable for traditional packaging methods.
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Figure CN120547896A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a power semiconductor component and a manufacturing method thereof, and in particular to a gallium nitride high electron mobility transistor and a manufacturing method thereof. Background Art
[0002] The GaN High Electron Mobility Transistor (GaN HEMT) represents a wide bandgap (WBG) power semiconductor device and holds great potential for high-frequency power applications. Typical GaN HEMTs are horizontal devices, with the gate, drain, and source electrodes fabricated on a single-crystal GaN semiconductor. The breakdown voltage threshold of a GaN HEMT increases not only with the horizontal distance between the gate and drain electrodes, but also, when single-crystal GaN is heteroepitaxially deposited on a conductive substrate such as single-crystal silicon (Si), the breakdown voltage threshold is affected by the vertical thickness of the GaN epitaxial layer. This means that on a conductive substrate, the breakdown voltage threshold is determined by the horizontal electrode design and the vertical epitaxial thickness, whichever has the weakest influence on the breakdown voltage.
[0003] Because the fabrication of single-crystal GaN substrates is not yet mature, and single-crystal GaN can only be grown epitaxially on materials with a similar single-crystal structure, single-crystal GaN is typically grown on single-crystal silicon carbide (SiC), single-crystal silicon (Si), or single-crystal sapphire substrates using a heterojunction method to form a composite semiconductor substrate containing single-crystal GaN. While epitaxial growth of single-crystal GaN on a single-crystal semi-insulated SiC substrate is only 0.4µm thick, GaN high-electron-mobility transistors (HEMTs) using this substrate can achieve a breakdown voltage of nearly 1700V, the high cost of single-crystal semi-insulated SiC substrates has limited commercial applications to high-performance RF (radio frequency) applications, with no commercial applications reported for power supply applications. On the other hand, using single-crystal GaN epitaxially on a single-crystal silicon substrate as a semiconductor substrate, although single-crystal silicon substrates are cheaper than single-crystal silicon carbide substrates, is limited by the conductivity of single-crystal silicon substrates. Therefore, the thickness of the single-crystal GaN epitaxial layer must be as thick as 5.0 μm to achieve a breakdown voltage of GaN-HEMTs close to 650V. Furthermore, the thermal expansion coefficient difference between GaN and silicon is as high as 50%, and a superlattice structure composed of aluminum nitride / gallium nitride (AlN / GaN) must be added during the GaN epitaxial process. This significantly increases the epitaxial growth time of single-crystal GaN on a single-crystal silicon substrate, resulting in high costs for composite semiconductor substrates of single-crystal GaN and single-crystal silicon, making them increasingly unsuitable for commercial manufacturing of GaN-HEMTs.
[0004] Using single-crystal GaN epitaxially deposited on a single-crystal sapphire substrate as the semiconductor substrate allows GaN-HEMTs to achieve a breakdown voltage close to 650V. Single-crystal GaN epitaxial deposition requires only 2.5µm thickness (thinner than epitaxial deposition on a single-crystal silicon substrate), and single-crystal sapphire substrates are cheaper than single-crystal silicon carbide substrates, thus reducing material costs. Therefore, existing GaN-HEMTs typically utilize a heterostructure composed of single-crystal GaN epitaxial deposition and single-crystal sapphire as the semiconductor substrate. However, the thermal conductivity of the sapphire substrate (0.47W / cmK) is lower than that of both the silicon carbide substrate (4.5W / cmK) and the silicon substrate (1.5W / cmK), resulting in overheating during operation of existing GaN-HEMTs.
[0005] On the other hand, the drain of conventional Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) power semiconductor devices is typically designed on the backside of the die. Common RF devices also have their sources designed on the backside to reduce high-frequency parasitic inductance. Therefore, how to route the drain or source of GaN high-electron-mobility transistors to the backside of the die, and enable back-end integration using the same traditional packaging methods as conventional Si MOSFET power semiconductor devices and common RF devices, is currently a key focus for device manufacturers. Summary of the Invention
[0006] An object of the present invention is to provide a gallium nitride high electron mobility transistor with improved heat dissipation and reduced manufacturing cost.
[0007] The gallium nitride high electron mobility transistor of the present invention includes a transistor structure, a heat dissipation structure and at least one conductive structure.
[0008] The transistor structure includes a composite semiconductor layer and an electrode unit disposed on one side of the composite semiconductor layer. The composite semiconductor layer includes a gallium nitride layer portion. The electrode unit includes a gate electrode, and a drain electrode and a source electrode spaced apart and disposed on opposite sides of the gate electrode.
[0009] The heat dissipation structure is used to radiate heat energy generated by the operation of the transistor structure to the external environment and includes a heat dissipation insulating layer bonded to a side of the composite semiconductor layer remote from the electrode unit, and a heat dissipation metal plate disposed on a side of the heat dissipation insulating layer remote from the composite semiconductor layer. The heat dissipation metal plate has a molybdenum base portion. The heat dissipation structure and the transistor structure jointly define at least one channel formed on a side of the heat dissipation insulating layer adjacent to the heat dissipation metal plate and extending through the electrode unit.
[0010] The conductive structure is disposed in the channel and two opposite ends thereof are electrically connected to the heat dissipation metal plate and the electrode unit respectively.
[0011] In the gallium nitride high electron mobility transistor of the present invention, the heat dissipation insulating layer is made of aluminum nitride, boron nitride, diamond-like or silicon carbide.
[0012] In the GaN-HEMT of the present invention, the thickness of the heat dissipation insulating layer is between 0.5 micrometers and 12 micrometers.
[0013] In the gallium nitride high electron mobility transistor of the present invention, two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the gate electrode of the electrode unit, respectively.
[0014] In the gallium nitride high electron mobility transistor of the present invention, two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the source electrode of the electrode unit respectively.
[0015] In the gallium nitride high electron mobility transistor of the present invention, two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the drain electrode of the electrode unit, respectively.
[0016] In the gallium nitride high electron mobility transistor of the present invention, the heat dissipation metal plate further includes a metal bonding layer portion disposed between the molybdenum base plate portion and the heat dissipation insulating layer.
[0017] Another object of the present invention is to provide a method for manufacturing the aforementioned GaN high electron mobility transistor.
[0018] The present invention discloses a method for fabricating a gallium nitride high electron mobility transistor (GaN-HEMT) using at least a transistor component and a temporary substrate. The transistor component includes a sapphire substrate and a transistor structure. The transistor structure comprises a compound semiconductor layer disposed on one side of the sapphire substrate and an electrode unit disposed on a side of the compound semiconductor layer facing away from the sapphire substrate. The compound semiconductor layer includes a GaN layer portion. The fabrication method includes a substrate removal step, a backside plating step, a backside etching step, a channel plating step, and a substrate bonding step.
[0019] The substrate removal step comprises firstly attaching the temporary substrate to a side of the transistor structure away from the sapphire substrate, and then removing the sapphire substrate.
[0020] The backside plating step is to form a heat dissipation insulation layer by plating on a side of the transistor structure away from the temporary substrate.
[0021] The back etching step is to form at least one channel penetrating to the electrode unit on a side surface of the heat dissipation insulation layer away from the temporary substrate.
[0022] The channel plating step is to form a conductive structure electrically connected to the electrode units by plating in the channel.
[0023] The substrate bonding step begins by attaching a heat dissipation metal plate to the side of the heat dissipation insulating layer facing away from the electrode unit. The heat dissipation metal plate is electrically connected to the conductive structure and has a molybdenum substrate portion. The temporary substrate is then removed, completing the fabrication of the GaN high-electron-mobility transistor.
[0024] In the method for manufacturing a GaN-HEMT of the present invention, the substrate removal step is to remove the sapphire substrate by laser lift-off.
[0025] In the method for manufacturing a gallium nitride high electron mobility transistor according to the present invention, the backside plating step forms the heat dissipation insulating layer by physical vapor deposition on the side of the transistor structure away from the temporary substrate. The heat dissipation insulating layer is made of aluminum nitride, boron nitride, diamond-like material, or silicon carbide.
[0026] In the method for manufacturing a gallium nitride high electron mobility transistor according to the present invention, the substrate bonding step is to form a metal bonding layer portion between the molybdenum substrate portion and the heat dissipation insulating layer by metal pressing, so that the heat dissipation metal plate is attached to the heat dissipation insulating layer.
[0027] The beneficial effect of the present invention is that by placing the transistor structure on the molybdenum substrate portion having a higher thermal conductivity than sapphire, the heat energy generated during operation of the transistor structure can be quickly radiated to the external environment through the molybdenum substrate portion, thereby achieving the effect of improving heat dissipation. In addition, by selecting the material of the heat dissipation insulating layer from aluminum nitride, the thickness of the heat dissipation insulating layer can be within the micron range, which can withstand the high breakdown voltage threshold of the transistor structure, thereby reducing the material usage and thinning the heat dissipation insulating layer, thereby achieving the effect of improving heat dissipation and reducing manufacturing costs. In addition, by placing the transistor structure on the molybdenum substrate portion having a thermal expansion coefficient close to that of the gallium nitride layer portion, the volume difference between the gallium nitride layer portion and the molybdenum substrate portion due to thermal expansion is small, thereby avoiding deformation or fracture caused by stress pulling, thereby improving the durability of the gallium nitride high electron mobility transistor. On the other hand, by electrically connecting the heat dissipation metal plate and the source electrode, or electrically connecting the heat dissipation metal plate and the drain electrode at two opposite ends of the conductive structure, the source electrode or the drain electrode can be guided to a side away from the electrode unit (i.e., the back of the chip), and can be applied to traditional packaging, thereby achieving the effect of cost reduction. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a schematic diagram illustrating an embodiment of a gallium nitride high electron mobility transistor according to the present invention;
[0029] Figure 2 is a schematic top view illustrating a first implementation aspect of the embodiment;
[0030] Figure 3 It is a Figure 2 A schematic cross-sectional view along line III-III;
[0031] Figure 4 is a schematic top view illustrating a second implementation of one of the embodiments;
[0032] Figure 5 It is a Figure 4A schematic cross-sectional view taken along line VV;
[0033] Figure 6 is a schematic top view illustrating a third implementation of one of the embodiments;
[0034] Figure 7 It is a Figure 6 A schematic cross-sectional view along line XII-XII;
[0035] Figure 8 is a flow chart illustrating the manufacturing process of the embodiment;
[0036] Figure 9 is a schematic cross-sectional view illustrating an implementation of two transistor components and a temporary substrate used in the manufacturing process of the embodiment;
[0037] Figure 10 is a schematic cross-sectional view illustrating a substrate removal step in the manufacturing process of the embodiment;
[0038] Figure 11 is a cross-sectional schematic diagram illustrating a backside plating step in the manufacturing process of the embodiment;
[0039] Figure 12 is a cross-sectional schematic diagram illustrating a back etching step in the manufacturing process of the embodiment;
[0040] Figure 13 is a schematic cross-sectional view illustrating a channel plating step in the manufacturing process of the embodiment;
[0041] Figure 14 FIG. 1 is a cross-sectional view illustrating a substrate bonding step in the manufacturing process of the embodiment. DETAILED DESCRIPTION
[0042] The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0043] Before the present invention is described in detail, it should be noted that similar components are denoted by the same reference numerals in the following description.
[0044] See Figure 1 , is an embodiment of the gallium nitride high electron mobility transistor 100 of the present invention. First, define the directional terms used in the description herein. Figure 1 , the portion below the GaN-HEMT 100 is defined as the “lower side,” the portion above the GaN-HEMT 100 is defined as the “upper side,” the portion to the left of the GaN-HEMT 100 is defined as the “back side,” and the portion to the right of the GaN-HEMT 100 is defined as the “front side.”
[0045] Continue reading Figure 1 The gallium nitride high electron mobility transistor 100 includes a transistor structure 1, a heat dissipation structure 2, a channel 3 and at least one conductive structure 4. The transistor structure 1 is a horizontal power component and includes a compound semiconductor layer 11 and an electrode unit 12 disposed on a side surface of the compound semiconductor layer 11 (i.e., the front surface / upper surface of the compound semiconductor layer 11). The compound semiconductor layer 11 has a gallium nitride layer portion 111 and an isolation layer portion 112. The gallium nitride layer portion 111 is made of gallium nitride with a single crystal structure. The gallium nitride layer portion 111 is used to form a carrier channel 3. The isolation layer portion 112 is bonded to a side surface of the gallium nitride layer portion 111 adjacent to the electrode unit 12 (i.e., the front surface / upper surface of the gallium nitride layer portion 111) and is provided for the electrode unit 12 to be disposed. The isolation layer 112 is used to isolate the electrode unit 12 from the gallium nitride layer 111, allowing electrons in the gallium nitride layer 111 to be driven by the electrode unit 12 to move, thereby forming an electric current or electron flow. In this embodiment, the isolation layer 112 is made of aluminum gallium nitride (AlGaN), but the isolation layer 112 may also be made of a semiconductor material having a different bandgap than the gallium nitride layer 111, and is not limited to AlGaN.
[0046] See Figures 1 to 3 , the electrode unit 12 is Figure 1 In the figure, a rectangular block is used as an example. Specifically, the electrode unit 12 has the following Figure 2 and Figure 3The device is shown as comprising a gate electrode 121, a drain electrode 122, and a source electrode 123 spaced apart on opposite sides of the gate electrode 121. When a voltage lower than a threshold voltage is applied to the gate electrode 121, the two-dimensional electron cloud in the gallium nitride layer 111 below the gate electrode 121 is depleted, disconnecting the drain electrode 122 from the source electrode 123. Conversely, when a voltage higher than the threshold voltage is applied to the gate electrode 121, a two-dimensional electron cloud forms in the gallium nitride layer 111 below the gate electrode 121, connecting the drain electrode 122 to the source electrode 123. In this embodiment, the drain electrode 122 and the source electrode 123 may have rectangular and interdigitated portions, with the interdigitated portions of the drain electrode 122 and the source electrode 123 interdigitated and spaced apart. The gate electrode 121 may extend in a meandering pattern between the interdigitated portions of the drain electrode 122 and the source electrode 123, and spaced apart from each other. The thickness of the gate electrode 121 is thinner than the thickness of the rectangular portions of the drain electrode 122 and the source electrode 123. However, the shape, thickness, and arrangement of the gate electrode 121, the drain electrode 122, and the source electrode 123 may depend on actual needs and are not limited to the above description.
[0047] See Figure 1 The heat dissipation structure 2 is used to radiate heat energy generated by the operation of the transistor structure 1 to the external environment. It includes a heat dissipation insulating layer 21 bonded to a side of the composite semiconductor layer 11 away from the electrode unit 12 (i.e., the back / bottom surface of the composite semiconductor layer 11), and a heat dissipation metal plate 22 disposed on a side of the heat dissipation insulating layer 21 away from the composite semiconductor layer 11 (i.e., the back / bottom surface of the heat dissipation insulating layer 21). The heat dissipation insulating layer 21 is used to prevent electrical conduction between the gallium nitride layer 111 and the heat dissipation metal plate 22, and to conduct heat generated by the operation of the transistor structure 1 to the heat dissipation metal plate 22 or radiate it to the external environment. In this embodiment, the heat dissipation insulating layer 21 is made of aluminum nitride (AlN), boron nitride (BN), diamond-like carbon (DLC), or silicon carbide (SiC). Aluminum nitride is low-cost and features a wide bandgap (Eg = 6.2 eV), a breakdown voltage (12.5 MV / cm), and a high thermal conductivity (3.21 W / cmK), effectively insulating and dissipating heat within the heatsink insulation layer 21. Furthermore, the aluminum nitride material allows the thickness of the heatsink insulation layer 21 to range from 0.5 microns to 12 microns, enabling applications with breakdown voltages of 650V to 1200V. This allows the overall thickness of the heatsink insulation layer 21 to be thinner, facilitating heat dissipation.
[0048] Continue reading Figure 1 , the heat dissipation metal plate 22 is used to provide support for the transistor structure 1 to prevent the transistor structure 1 from breaking, and to radiate the heat generated from the heat dissipation insulating layer 21 and by the operation of the transistor structure 1 to the external environment. Specifically, the heat dissipation metal plate 22 has a molybdenum substrate portion 221 and a metal bonding layer portion 222 arranged between the molybdenum substrate portion 221 and the heat dissipation insulating layer 21. The metal bonding layer portion 222 is used to bond the molybdenum substrate portion 221 to the heat dissipation insulating layer 21. In this embodiment, the metal bonding layer portion 222 is a surface structure in which the surfaces of the molybdenum substrate portion 221 and the heat dissipation insulating layer 21 are each plated with a layer of metal, and then processed at high temperature and high pressure to produce atomic diffusion bonding. However, in other embodiments, the metal bonding layer portion 222 can also be formed by curing a bonding agent such as a conductive adhesive.
[0049] Continue reading Figure 1 The material of the molybdenum substrate 221 is molybdenum (Mo) metal, which has the following characteristics: thermal expansion coefficient (5.3x10 -6 ) is close to the thermal expansion coefficient of the gallium nitride layer 111 (5.5x10 -6 ), and its thermal conductivity (1.38 W / cmK) is higher than that of sapphire (0.47 W / cmK). Therefore, the heat dissipation effect of the heat dissipation metal plate 22 is better than that of the sapphire substrate. Furthermore, when the transistor structure 1 generates heat during operation and the heat dissipation metal plate 22 absorbs the heat energy from the operation of the transistor structure 1, the thermal expansion coefficients of the gallium nitride layer 111 and the molybdenum substrate 221 of the transistor structure 1 are close. This minimizes the volumetric difference between the gallium nitride layer 111 and the molybdenum substrate 221 due to thermal expansion, thus preventing deformation or fracture of both due to stress.
[0050] Continue reading Figure 1 The heat dissipation structure 2 and the transistor structure 1 jointly define at least one channel 3 formed on a side of the heat dissipation insulating layer 21 adjacent to the heat dissipation metal plate 22 (i.e., the back / bottom surface of the heat dissipation insulating layer 21) and extending through to a side of the electrode unit 12 adjacent to the composite semiconductor layer 11. In this embodiment, the channel 3 penetrates the heat dissipation insulating layer 21, the gallium nitride layer portion 111, and the isolation layer portion 112 from bottom to top, with the openings at both ends of the channel 3 formed on the bottom surface of the heat dissipation insulating layer 21 and the top surface of the isolation layer portion 112, respectively.
[0051] Continue reading Figure 1, the conductive structure 4 is arranged in the channel 3 and its two opposite ends are electrically connected to the heat dissipation metal plate 22 and the electrode unit 12 respectively. In this embodiment, the conductive structure 4 includes a seed layer portion 41 combined with the inner wall of the channel 3, and a conductive main body portion 42 combined with the seed layer portion 41 and filling the channel 3. The seed layer portion 41 allows the conductive structure 4 to be firmly combined with the inner wall of the channel 3. The conductive main body portion 42 is made of gold or copper, which can make the conductive structure 4 have good conductivity. However, the material of the conductive structure 4 can also be other conductive materials and is not limited to a specific form. In addition, the number of the conductive structure 4 and the channel 3 can be one or more, depending on actual needs.
[0052] See Figure 2 and Figure 3 , is a first implementation of one of the embodiments. In this first implementation, the number of the conductive structures 4' of the GaN high electron mobility transistor 100' is two examples. Figure 2 As shown, the conductive structure 4' is electrically connected to both ends of the gate electrode 121, and as shown Figure 3 As shown, the two opposite ends of each conductive structure 4' are electrically connected to the heat dissipation metal plate 22 and the gate electrode 121 respectively. In this way, the gate electrode 121 and the heat dissipation metal plate 22 can be electrically connected through the conductive structure 4' and used as a ground, thereby reducing the parasitic inductance caused by the grounding of the gate electrode 121.
[0053] See Figure 4 and Figure 5 , which is a second implementation of one of the embodiments. In this second implementation, the number of the conductive structures 4" of the GaN high electron mobility transistor 100" is ten. Figure 4 As shown, the conductive structures 4" are arranged at intervals along the length direction of the rectangular portion of the drain electrode 122, and as shown in FIG. Figure 5 As shown, opposite ends of each conductive structure 4" are electrically connected to the heat dissipation metal plate 22 and the drain electrode 122, respectively. Thus, the conductive structure 4" allows the drain electrode 122 to be electrically connected to the heat dissipation metal plate 22, making the GaN high electron mobility transistor 100" structurally similar to a vertical power device (e.g., Si-MOSFET), thereby improving the parasitic inductance problem caused by bonding wires.
[0054] See Figure 6 and Figure 7 , which is a third implementation of one of the embodiments. In this third implementation, the number of the conductive structures 4'' of the GaN high electron mobility transistor 100'' is ten. Figure 6As shown, the conductive structures 4'' are arranged at intervals along the length direction of the rectangular portion of the source electrode 123, and as shown in FIG. Figure 7 As shown, the two opposite ends of each of the conductive structures 4'' are electrically connected to the heat dissipation metal plate 22 and the source electrode 123, respectively. In this way, the source electrode 123 and the heat dissipation metal plate 22 can be electrically connected through the conductive structure 4'', thereby improving the parasitic inductance problem caused by bonding, thereby increasing the operating speed of the transistor structure 1 and reducing heat generation.
[0055] See Figure 8 , is the manufacturing process of this embodiment. Figures 9 to 14 The manufacturing method of this embodiment is described in detail. Figure 9 The transistor element 200 and a temporary substrate 300 for temporarily supporting the transistor structure 1 are shown. In the manufacturing process of this embodiment, the manufacturing method is arranged in front and back ( Figure 8 The two transistor components 200 (separated by a dotted line in the figure) on the left and right of the temporary substrate 300 are used as an example to illustrate how to process multiple transistor components 200 at a time, but the manufacturing method can also be used to process one or more transistor components 200, and the transistor components 200 can also be arranged on the left and right, depending on actual needs.
[0056] See Figure 8 and Figure 9 , each of the transistor components 200 includes a sapphire substrate 201 and the aforementioned transistor structure 1. Each of the transistor structures 1 includes the compound semiconductor layer 11 disposed on one side of the sapphire substrate 201, and the electrode unit 12 disposed on a side of the compound semiconductor layer 11 away from the sapphire substrate 201. In the manufacturing process of this embodiment, the sapphire substrates 201 of the transistor components 200 are interconnected and formed as a whole. The gallium nitride layer portion 111 of the compound semiconductor layer 11 is also interconnected and formed as a whole, and the isolation layer portion 112 of the compound semiconductor layer 11 is also interconnected and formed as a whole, while the electrode units 12 of the transistor components 200 are patterned and separated from each other. See Figure 1 、 Figure 3 and Figure 9 , the temporary substrate 300 may be as follows Figure 9 The rectangular substrate shown corresponds to Figure 1 The electrode units 12 are shown as rectangular blocks, but in practice, the shape of the side of the temporary substrate 300 facing the transistor structure 1 corresponds to the surface morphology of each electrode unit 12 (see FIG. Figure 3) should be concave-convex (not shown) so that the temporary substrate 300 can fit the electrode unit 12 of the transistor structure 1, or the surface of the temporary substrate 300 can elastically deform corresponding to the surface morphology of the electrode unit 12 of the transistor structure 1, so that the temporary substrate 300 can also fit the electrode unit 12 of the transistor structure 1.
[0057] For reference Figure 8 、 Figure 9 and Figure 10 First, a substrate removal step S01 is performed: a temporary substrate 300 is attached to the side of the transistor structure 1 facing away from the sapphire substrate 201, followed by removal of the integrally formed sapphire substrate 201. Specifically, the temporary substrate 300 is adhered to the transistor structure 1 using adhesive. The integrally formed sapphire substrate 201 is removed using laser lift-off.
[0058] For reference Figure 8 、 Figure 11 Then, a backside plating step S02 is performed: a corresponding heat dissipation insulating layer 21 is formed by plating on the side of each transistor structure 1 away from the temporary substrate 300. Specifically, a thin film structure is deposited on the side of the transistor structure 1 away from the temporary substrate 300 by physical vapor deposition to form interconnected and integral heat dissipation insulating layers 21. Each heat dissipation insulating layer 21 is made of aluminum nitride, boron nitride, diamond-like material, or silicon carbide.
[0059] For reference Figure 8 、 Figure 12 , then a back etching step S03 is performed: at least one channel 3 is etched on a side of each heat dissipation insulating layer 21 away from the temporary substrate 300 to penetrate to a side of the electrode unit 12 adjacent to the composite semiconductor layer 11. Specifically, each channel 3 can be formed by an anisotropic etching method such as plasma etching. In the manufacturing process of this embodiment, the position and number of the channels 3 formed on each heat dissipation insulating layer 21 depend on actual needs. For example, the number of channels 3 formed on each heat dissipation insulating layer 21 is two, and they are respectively aligned with the two ends of the gate electrode 121 of the corresponding transistor structure 1; or the number of channels 3 formed on each heat dissipation insulating layer 21 is ten, and they are all aligned with one of the drain electrode 122 and the source electrode 123 of the corresponding transistor structure 1.
[0060] For reference Figure 8 、 Figure 13, then a channel plating step S04 is performed: plating is performed in each of the channels 3 to form the conductive structure 4 electrically connected to the corresponding electrode unit 12. Specifically, the channel plating step S04 may be to first plate the seed layer portion 41 on the inner wall of the channel 3 and the opening of the temporary substrate 300 exposed in the channel 3. Then, gold is plated on the seed layer portion 41 and the gold is filled in the channel 3 to form the conductive main body portion 42, thereby completing the production of the conductive structure 4. However, the channel plating step S04 may also be to directly plate gold or copper in each of the channels 3 and on the side of the heat dissipation insulation layer 21 away from the electrode unit 12 by electroplating or chemical plating, so that the gold or copper structure located in each of the channels 3 and filling each of the channels 3 forms the conductive structure 4 electrically connected to the corresponding electrode unit 12, and the gold or copper located on the surface of the heat dissipation insulation layer 21 can be used for the subsequent metal pressing process.
[0061] For reference Figure 8 、 Figure 14 , and finally a substrate bonding step S05 is performed: first, the integrally formed heat dissipation metal plate 22 is attached to the side of the integrally formed heat dissipation insulation layer 21 away from the electrode unit 12. Each of the heat dissipation metal plates 22 is electrically connected to the corresponding conductive structure 4 and has a molybdenum substrate portion 221. Specifically, the integrally formed molybdenum substrate portion 221 is first placed on the side of the integrally formed heat dissipation insulation layer 21 away from the electrode unit 12, and then the metal bonding layer portion 222 is formed between each molybdenum substrate portion 221 and the corresponding heat dissipation insulation layer 21 by metal pressing (high temperature, high pressure) or applying conductive glue, so that each heat dissipation metal plate 22 is adhered to the corresponding heat dissipation insulation layer 21. Then, the temporary substrate 300 is removed, so that the transistor structure 1 is supported by the integrally formed heat dissipation metal plate 22. Finally, the integrally formed gallium nitride layer, the integrally formed isolation layer 112 , the integrally formed heat dissipation insulating layer 21 , and the integrally formed heat dissipation metal plate 22 are separated at their connected portions by knife cutting or laser cutting, thereby completing the manufacture of the two gallium nitride high electron mobility transistors 100 .
[0062] It is worth mentioning that the manufacturing method can also be performed using a single transistor component 200 and the temporary substrate 300. In this way, the process of separating the gallium nitride layer, the isolation layer 112, the heat dissipation insulating layer 21, and the heat dissipation metal plate 22 can be omitted in the substrate bonding step S05, thereby completing the manufacturing of a single gallium nitride high electron mobility transistor 100.
[0063] In summary, by placing the transistor structure 1 on the molybdenum substrate 221, which has a higher thermal conductivity than sapphire, heat generated during operation of the transistor structure 1 can be quickly radiated to the external environment through the molybdenum substrate 221, thereby achieving improved heat dissipation. Furthermore, by placing the transistor structure 1 on the molybdenum substrate 221, which has a thermal expansion coefficient close to that of the gallium nitride layer 111, the volumetric expansion difference between the gallium nitride layer 111 and the molybdenum substrate 221 due to heat is minimized, thereby preventing deformation or fracture caused by stress and strain, thereby enhancing the durability of the gallium nitride high-electron-mobility transistor 100. On the other hand, by electrically connecting the heat dissipation metal plate 22 and the source electrode 123, or electrically connecting the heat dissipation metal plate 22 and the drain electrode 122, respectively, the source electrode 123 or the drain electrode 122 can be guided to a side surface (i.e., the back of the chip) away from the electrode unit 12, and can be applied to traditional packaging, thereby achieving the effect of cost reduction, and thus can indeed achieve the purpose of the present invention.
Claims
1. A gallium nitride high electron mobility transistor; characterized in that: The gallium nitride high electron mobility transistor comprises: A transistor structure comprising a composite semiconductor layer and an electrode unit disposed on one side of the composite semiconductor layer, wherein the composite semiconductor layer has a gallium nitride layer portion, and the electrode unit has a gate electrode and a drain electrode and a source electrode spaced apart and disposed on opposite sides of the gate electrode; a heat dissipation structure for radiating heat energy generated by the operation of the transistor structure to the external environment, and comprising a heat dissipation insulating layer bonded to a side of the composite semiconductor layer remote from the electrode unit, and a heat dissipation metal plate disposed on a side of the heat dissipation insulating layer remote from the composite semiconductor layer, the heat dissipation metal plate having a molybdenum base portion, the heat dissipation structure and the transistor structure jointly defining at least one channel formed on a side of the heat dissipation insulating layer adjacent to the heat dissipation metal plate and extending through the electrode unit; and At least one conductive structure is disposed in the channel and has two opposite ends electrically connected to the heat dissipation metal plate and the electrode unit respectively.
2. The gallium nitride high electron mobility transistor according to claim 1, wherein: The heat dissipation insulating layer is made of aluminum nitride, boron nitride, diamond-like or silicon carbide.
3. The gallium nitride high electron mobility transistor according to claim 1, wherein: The thickness of the heat dissipation insulation layer is between 0.5 micrometers and 12 micrometers.
4. The gallium nitride high electron mobility transistor according to claim 1, wherein: Two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the gate electrode of the electrode unit respectively.
5. The gallium nitride high electron mobility transistor according to claim 1, wherein: Two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the source electrode of the electrode unit respectively.
6. The gallium nitride high electron mobility transistor according to claim 1, wherein: Two opposite ends of the conductive structure are electrically connected to the heat dissipation metal plate and the drain electrode of the electrode unit respectively.
7. The gallium nitride high electron mobility transistor according to claim 1, wherein: The heat dissipation metal plate further includes a metal bonding layer portion provided between the molybdenum base plate portion and the heat dissipation insulating layer.
8. A method for manufacturing a gallium nitride high electron mobility transistor, adapted to be performed using at least one transistor element and a temporary substrate, wherein the transistor element comprises a sapphire substrate and a transistor structure, wherein the transistor structure comprises a compound semiconductor layer disposed on one side of the sapphire substrate, and an electrode unit disposed on a side of the compound semiconductor layer remote from the sapphire substrate, wherein the compound semiconductor layer comprises a gallium nitride layer portion; characterized in that: The method for manufacturing a gallium nitride high electron mobility transistor comprises the following steps: a substrate removal step of first attaching the temporary substrate to a side of the transistor structure away from the sapphire substrate and then removing the sapphire substrate; a backside plating step of plating a heat dissipation insulating layer on a side of the transistor structure away from the temporary substrate; A back etching step of etching at least one channel penetrating to the electrode unit on a side of the heat dissipation insulating layer away from the temporary substrate; a channel plating step of plating in the channel to form a conductive structure electrically connected to the electrode unit; and In the substrate bonding step, a heat dissipation metal plate is first attached to a side of the heat dissipation insulating layer away from the electrode unit. The heat dissipation metal plate is electrically connected to the conductive structure and has a molybdenum substrate portion. The temporary substrate is then removed to complete the fabrication of the GaN high electron mobility transistor.
9. The method for manufacturing a gallium nitride high electron mobility transistor according to claim 8, wherein: The substrate removal step is to remove the sapphire substrate by laser lift-off.
10. The method for manufacturing a gallium nitride high electron mobility transistor according to claim 8, wherein: The backside plating step forms the heat dissipation insulating layer by plating on a side of the transistor structure away from the temporary substrate in a physical vapor deposition manner. The heat dissipation insulating layer is made of aluminum nitride, boron nitride, diamond-like or silicon carbide.
11. The method for manufacturing a gallium nitride high electron mobility transistor according to claim 8, wherein: The substrate bonding step forms a metal bonding layer portion between the molybdenum substrate portion and the heat dissipation insulating layer by metal pressing, so that the heat dissipation metal plate is attached to the heat dissipation insulating layer.