A method of fabricating a drive array, a drive array and an electronic device

Abstract

The application provides a preparation method of a driving array, the driving array and an electronic device. The preparation method of the driving array provided by the application comprises the following steps: forming a metal wire structure; forming a first gate line array on a first dielectric material layer in the metal wire structure, and covering the first gate line array with a second dielectric material layer; forming a first hole in an overlapping area of a projection area of each metal wire in the first metal wire array on the second dielectric material layer and a projection area of each gate line in the first gate line array on the second dielectric material layer; etching downwardly in the first hole, and stopping the etching process on an upper surface of the metal wire to form a first through hole perpendicular to the metal wire; depositing a third dielectric material layer in the first through hole, and etching the third dielectric material layer at the bottom of the first through hole vertically downward to form a side wall in the first through hole; and depositing a channel material in the first through hole. The preparation method of the driving array provided by the application can be used to prepare a driving array with a micro-structured structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a preparation method of a driving array, a driving array and an electronic device. BACKGROUND

[0002] With the continuous improvement of the performance of electronic equipment, the miniaturization and diversification of integrated circuits have become the main trend of the development of modern electronic technology. Under this background, as a kind of key electronic components, driving arrays play an important role in displays, sensors and various integrated circuits. Especially in liquid crystal display (LCD), organic light emitting diode (OLED) and other display technologies, driving arrays play a crucial role in image output and signal transmission.

[0003] Limited by the physical size of the traditional planar transistor structure and the demand for area arrangement of the driving circuit configuration, the mainstream driving array structure in the current market still stays at the scale of hundreds of microns, which cannot meet the actual needs of nanoscale structures. SUMMARY

[0004] Therefore, the present application provides a preparation method of a driving array, a driving array and an electronic device, which can realize the miniaturization of the driving array without losing its performance.

[0005] Specifically, the present application is realized by the following technical solutions:

[0006] The first aspect of the present application provides a preparation method of a driving array, which comprises:

[0007] forming a metal line structure; wherein the metal line structure comprises a first metal line array and a first dielectric material layer covering the first metal line array;

[0008] forming a first gate line array on the first dielectric material layer and covering the first gate line array with a second dielectric material layer;

[0009] forming a first hole in a first specified position of the second dielectric material layer by exposure technology; wherein the first specified position is the overlapping area of the projection area of each metal line in the first metal line array on the second dielectric material layer and the projection area of each gate line in the first gate line array on the second dielectric material layer;

[0010] etching the first hole downward by etching technology, and stopping the etching process at the upper surface of the metal line to form a first through hole perpendicular to the metal line; wherein the gate line in the first gate line array surrounds the first through hole;

[0011] depositing a third dielectric material layer in the first via, and vertically etching the third dielectric material layer at the bottom of the first via to form a sidewall in the first via;

[0012] depositing a channel material in the first via, and planarizing the deposited channel material.

[0013] The second aspect of the present application provides a drive array, which is prepared based on the preparation method of any one of the drive arrays provided in the first aspect of the present application;

[0014] In a top-down order, the drive array comprises a metal line structure and a first gate line structure; wherein the metal line structure comprises a first metal line array and a first dielectric material layer covering the first metal line array; the first gate line structure comprises a first gate line array formed on the first dielectric material layer, and a second dielectric material layer covering the first gate line array;

[0015] The first specified region of the first gate line structure has a via-shaped first channel structure; the first specified region is an overlapping region of a projection region of the first metal line array on the gate line structure and the first gate line array; the first channel structure comprises a first via perpendicular to each metal line in the first metal line array, a third dielectric material layer formed on a sidewall of the first via, and a channel material formed in a hole surrounded by the third dielectric material layer.

[0016] The third aspect of the present application provides an electronic device, which comprises any one of the drive arrays provided in the second aspect of the present application, and a controlled device;

[0017] The drive array is used to provide a drive signal for the controlled device.

[0018] The preparation method of the driving array, the driving array and the electronic device provided by the application provide a stable foundation for the driving array through the superposition structure of the metal wire array and the dielectric material layer. Further, the accurate overlap of the gate wire array and the metal wire array enables the gate to more effectively reduce the parasitic capacitance between the lower metal wire, thereby improving the switching performance and reducing the power consumption. In particular, the exposure technology is used to form accurately positioned holes on the second dielectric material layer, and the etching technology is used to accurately control the depth of the holes to the surface of the metal wire, thereby ensuring the consistency and high precision of the device in the miniaturization process. In addition, the vertical via hole and the surrounding gate wire provide an ideal space for the formation of the vertical transistor structure, and the channel size can be accurately controlled, thereby effectively improving the switching characteristics and response speed of the driving array. Through the fine process steps, the ring-gate type vertical transistor structure can be successfully prepared, which not only enhances the current control ability of the transistor, but also realizes the effective reduction of the transistor size. Through the precise structure miniaturization and vertical transistor design, the efficient integration of the driving array can be realized, thereby meeting the demand for high performance, high density and low power consumption of modern electronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The flowchart of the preparation method of the driving array provided by the application is shown in Embodiment 1.

[0020] Figure 2 The implementation principle diagram of the preparation method of the driving array is shown in an exemplary embodiment of the application.

[0021] Figure 3 The partial schematic diagram of the prepared driving array is shown in an exemplary embodiment of the application.

[0022] Figure 4 The flowchart of the preparation method of the driving array provided by the application is shown in Embodiment 2.

[0023] Figure 5 The implementation principle diagram of the preparation method of the driving array is shown in another exemplary embodiment of the application.

[0024] Figure 6 The perspective view of the prepared driving array is shown in an exemplary embodiment of the application.

[0025] Figure 7 The flowchart of the preparation method of the driving array provided by the application is shown in Embodiment 3.

[0026] Figure 8 The implementation principle diagram of the preparation method of the driving array is shown in another exemplary embodiment of the application.

[0027] Figure 9 The perspective view of the prepared driving array is shown in an exemplary embodiment of the application.

[0028] Figure 10 A schematic diagram of a driving array embodiment provided in the present application is shown in FIG. 1.

[0029] Figure 11 A schematic diagram of a driving array embodiment provided in the present application is shown in FIG. 1.

[0030] Figure 12 A schematic diagram of a driving array embodiment provided in the present application is shown in FIG. 1. DETAILED DESCRIPTION

[0031] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers in the attached drawings refer to the same or similar elements. The following detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the exemplary embodiments can be practiced without these specific details.

[0032] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0033] It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the term "and / or" as used herein encompasses all possible combinations of particular items listed apart from disjunctively one from another. It is further understood that the terms "comprise" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0034] The following specific embodiments are given to further illustrate the technical solutions of the present application.

[0035] Figure 1 A flow chart of a preparation method of a driving array provided in the present application is shown in FIG. 1. Please refer to Figure 1 The method provided in the present embodiment can include:

[0036] S101, forming a metal line structure; wherein the metal line structure includes a first metal line array and a first dielectric material layer covering the first metal line array.

[0037] In a specific implementation, Figure 2 An implementation schematic diagram of a preparation method of a driving array according to an exemplary embodiment of the present application is shown in FIG. 1. Please refer to Figure 2In 2A, the metal line structure includes an orange first metal line array and a light blue first dielectric material layer.

[0038] Furthermore, the first metal line array is a group of metal lines arranged at the bottom of the array in a regular distribution. For example, it may include a group of parallel metal lines. In a specific implementation, the first metal line array can serve as the source of a transistor. The first metal line array can be Mo, Ru, or ITO metal lines formed by metal deposition.

[0039] Furthermore, the first dielectric material layer can be an insulating layer covering the first metal wire array. The first dielectric material layer is used for electrical isolation and structural support, and can also provide a flat substrate for subsequent fabrication processes. Optionally, in one possible implementation, the first dielectric material layer can be a SiO2 layer or an Al2O3 layer.

[0040] It should be noted that the specific number of metal wires included in the first metal wire array is set according to actual needs and is not limited in this embodiment. For example, in one embodiment, combined with the above example, Figure 2 As shown, the first metal line array may include only one metal line. For another example, in another embodiment, the first metal line array may include three metal lines parallel to each other.

[0041] In a specific implementation, in a possible implementation manner, a first dielectric material layer may be deposited first, and then a groove may be etched on the first dielectric material layer. Further, a metal line may be formed in the groove by electroplating.

[0042] Furthermore, in another possible implementation, a metal layer may be first deposited, and then a first metal line array may be formed by exposure and etching. Furthermore, a first dielectric material layer may be deposited on the first metal line array. It should be noted that in this second implementation, the metal material forming the metal layer may be directly etchable by ICP etching. For example, the metal material may be Mo, Ru, or ITO.

[0043] S102 , forming a first gate line array on the first dielectric material layer, and covering the first gate line array with a second dielectric material layer.

[0044] Specifically, the first gate line array is a metal wire array deposited and patterned on the first dielectric material layer, and the first gate line array serves as a gate electrode of the transistor.

[0045] For specific implementation, please continue to refer to Figure 2 , Mo, Ru or ITO, etc., a material with good conductivity and patternability can be selected to form the first gate line array.

[0046] It should be noted that the first gate line array includes a plurality of parallel gate lines, the number of gate lines included is set according to actual needs, and the spacing between each gate line is also set according to actual needs.

[0047] In a specific implementation, the gate layer can be formed by deposition, and then the first gate line array can be formed by exposure and etching.

[0048] Further, the second dielectric material layer is an insulating material layer covering the first gate line array, which can play an electrical insulation role.

[0049] In a specific implementation, the PECVD deposition method can be used to deposit SiO2 or high dielectric constant material to form the second dielectric material layer for coating the gate line.

[0050] It should be noted that the first gate line array and the first metal line array are at a specified angle, and the specific value of the specified angle is set according to actual needs, which is not limited in the embodiment. In a specific implementation, the included angle of the first gate line array and the first metal line array can be 0 to 90 degrees.

[0051] Optionally, in a possible implementation, the first gate line array is perpendicular to the first metal line array.

[0052] It can be understood that by arranging the first gate line array and the first metal line array vertically, precise pixel addressing and efficient matrix addressing logic can be achieved, which helps to accurately construct a ring gate type transistor in the intersection area, improves the space utilization and pixel integration, avoids wiring conflicts and signal interference, and provides a clear stacking path for subsequent structures, ensuring the high density, low crosstalk, scalability and other performances of the driving array.

[0053] It should be noted that in a specific implementation, the thickness of the first dielectric material layer and the second dielectric material layer can be greater than the thickness of the first metal line array.

[0054] S103, a first hole is formed in a first specified position of the second dielectric material layer by exposure technology; wherein the first specified position is an overlapping region of a projection region of each metal line in the first metal line array on the second dielectric material layer and a projection region of each gate line in the first gate line array on the second dielectric material layer.

[0055] Specifically, the exposure technology is a technology for transferring a pattern to a photoresist by using a photolithography process, and an opening can be formed in a specific region by the exposure technology. In this example, the first hole is an opening formed in the second dielectric material layer by the exposure technology, and the first hole can be used as a starting structure for constructing a vertical via.

[0056] Please continueFigure 2 The first hole can be formed in an overlapping region of a projection region of each metal line on the second dielectric material layer and a projection region of each gate line on the second dielectric material layer. In a specific implementation, in the spatial structure, the profile of the first metal line array in the lower layer is mapped to the first gate line array in the upper layer, and the overlapping region is determined as the first specified position.

[0057] Further, the specific shape and size of the first hole are set according to actual needs, and in the embodiment, the first hole is not limited. In the embodiment, it is required that the diameter of the first hole is smaller than the width of the gate line.

[0058] S104, etching downwardly to the first hole by an etching technology, and stopping the etching process at the upper surface of the metal line to form a first via hole perpendicular to the metal line; wherein the gate line in the first gate line array surrounds the first via hole.

[0059] Specifically, the first hole can be etched downwardly by using a chemical method or a physical method. For example, in a specific implementation, the first via hole can be formed by using a plasma etching, an inductively coupled plasma etching, or the like, to obtain the structure shown in FIG. 4B. Figure 2

[0060] It should be noted that the diameter of the first via hole is smaller than the width of the gate line, and the first via hole formed by vertical etching can be a via hole with a high aspect ratio, a width of tens of nanometers, and a depth corresponding to the thickness of the multi-layer material.

[0061] Further, the sidewall of the first via hole is surrounded by the gate line, that is, the gate line surrounds the first via hole along the periphery, and a full-wrapping layout of a subsequent channel region is realized in three-dimensional space to form a ring gate structure.

[0062] It should be noted that the gate line surrounding the first via hole constitutes a physical basis of the ring gate transistor, which can greatly improve the electric field control efficiency of the gate on the channel and reduce the short channel effect.

[0063] S105, depositing a third dielectric material layer in the first via hole, and etching vertically downwardly to remove the third dielectric material layer at the bottom of the first via hole to form a sidewall in the first via hole.

[0064] Specifically, the third dielectric material layer is a dielectric material deposited in the first via hole, which is used as a gate oxide layer of the transistor to isolate the channel and the gate.

[0065] In a specific implementation, a layer of third dielectric material is deposited in the first via hole to form Figure 2 ​The third dielectric material layer can be formed by depositing a high dielectric constant material (which can include HfO2, Al2O3, SiO2, or a combination of Al2O3 and SiO2) using an atomic layer deposition technique, for example.

[0066] It should be noted that the thickness of the third dielectric material layer is set according to actual needs, and in this embodiment, the thickness of the third dielectric material layer is not limited. For example, in one possible implementation, the thickness of the third dielectric material layer is about 2-4 nm.

[0067] Further, the third dielectric material layer is etched vertically downward to etch away the third dielectric material layer at the bottom of the first via, and only the third dielectric material layer on the sidewall is reserved, to obtain a structure as shown in Figure 2 D.

[0068] In a specific implementation, the third dielectric material layer at the bottom can be etched vertically downward by using an Inductively Coupled Plasma (ICP) anisotropic etching technique, so that the channel material can be connected to the metal line (source).

[0069] It can be understood that the third dielectric material layer constitutes a gate oxide layer between the channel and the gate, which can isolate the channel semiconductor from the gate metal, and at the same time allow the gate electric field to effectively regulate the channel carrier channel.

[0070] S106, depositing a channel material in the first via, and planarizing the deposited channel material.

[0071] Specifically, the channel material is a semiconductor material filled in the first via, located between the source and the drain, and controlled by the gate.

[0072] In a specific implementation, indium gallium zinc oxide (IGZO) or indium tin oxide (ITO) can be used as the channel material.

[0073] Further, the planarization process is to polish or etch the surface of the deposited channel material, so that the surface is consistent with the surrounding area, smooth and without protrusions, which facilitates subsequent superposition on the surface after planarization.

[0074] In a specific implementation, please continue to refer to Figure 2 After the channel material is deposited in the first via, a chemical mechanical polishing (CMP) process can be used to planarize the channel material, to remove the surface redundancy, so that the top of the channel structure is at the same height as the surrounding structure, to obtain a structure as shown in Figure 2 E.

[0075] Optionally, in one possible implementation, after the deposited channel material is planarized, the method further includes:

[0076] A drain is formed above the first via to produce a 1T type driving array.

[0077] In implementation, the drain material can be deposited directly on the planarized structure to form a good contact with the channel material below, forming a drain and obtaining a 1T type driving array.

[0078] In implementation, the drain shape can be defined by patterning and etching processes to form a 1T type driving array. Further, the drain can serve as a current output path, directly connecting to the upper light emitting device or interconnection structure to complete the signal driving function.

[0079] Specifically, Figure 3 A partial schematic diagram of a driving array produced by an exemplary embodiment of the present application is shown. Please refer to Figure 3 By the above method, a 1T type driving array can be produced, which includes a plurality of driving units, Figure 3 Only one driving unit is shown, and each driving unit only contains one transistor without a storage capacitor structure, which is suitable for partially simplified display driving applications and can achieve basic switching control. In addition, please continue to refer to Figure 2 and Figure 3 It can be understood that, Figure 3 There is also a layer of dielectric material between the green channel material and the orange gate line in Figure 3 which is not shown.

[0080] Please refer to Figure 3 The driving array formed in this embodiment is a ring-gate type vertical transistor with the channel of each transistor surrounded by the gate.

[0081] From the foregoing description, it can be understood that a vertical ring-gate transistor can be produced by the above preparation method to achieve the miniaturization of the driving array, and the preparation method has at least the following beneficial effects:

[0082] (1) Accurate gate control and high-efficiency switching performance:

[0083] The gate of the transistor surrounds the channel, providing more efficient current control than traditional planar transistors, thereby improving current switching speed and reducing leakage current when working at low voltage, and optimizing power consumption.

[0084] (2) Vertical via design improves miniaturization effect:

[0085] The design of vertical through holes provides higher structural density for the driving array while precisely controlling the size of the channel, enhancing the integration and reducing the size of the transistor. This design of vertical structure further supports the miniaturization of the driving array, adapting to the needs of high density, high performance and low power consumption of electronic devices.

[0086] (3) Ring gate structure enhances current control ability:

[0087] The ring gate transistor can better control the current transmission of the channel through the three-dimensional gate structure, compared with the traditional planar transistor, which can reduce the short channel effect, improve the switching characteristics and current control ability of the transistor, and is especially suitable for miniaturization and high-frequency applications.

[0088] (4) Meet the miniaturization needs of modern electronic devices:

[0089] The precise miniaturization process of this scheme not only realizes efficient integration in limited space, but also provides stable performance for the driving array, meeting the requirements of miniaturization, high integration and high performance in modern electronic devices.

[0090] This scheme realizes the preparation of ring gate vertical transistors through precise metal wire, dielectric material layer and gate line array design, combined with precise exposure, etching and deposition process, effectively improves the current control ability, switching performance and power consumption optimization of the transistor, and promotes the miniaturization and high integration of the driving array.

[0091] The preparation method of the driving array provided by the embodiment provides a stable foundation for the driving array through the superposition structure of the metal wire array and the dielectric material layer. Further, the accurate overlap of the gate line array and the metal wire array enables the gate to more effectively reduce the parasitic capacitance between the lower metal wire, thereby improving the switching performance and reducing the power consumption. In particular, the exposure technology is used to form a precisely positioned hole on the second dielectric material layer, and the etching technology is used to accurately control the depth of the hole to the surface of the metal wire, ensuring the consistency and high precision of the device during the miniaturization process. In addition, the vertical through hole and the surrounding gate line provide an ideal space for the formation of the ring gate vertical transistor structure, while accurately controlling the channel size, effectively improving the switching characteristics and response speed of the driving array. Through the fine process steps, the ring gate vertical transistor structure can be successfully prepared, not only enhancing the current control ability of the transistor, but also realizing the effective reduction of the transistor size. Through precise structure miniaturization and vertical transistor design, efficient integration of the driving array can be realized, meeting the needs of modern electronic devices for high performance, high density and low power consumption. The implementation of this scheme not only improves the performance and stability of the device, but also promotes the miniaturization and high efficiency of electronic devices, and has wide application prospects.

[0092] A specific embodiment is given below to introduce the preparation process of 1T1C type drive array in detail:

[0093] Figure 4 This is a flow chart of Example 2 of the manufacturing method of the drive array provided in this application. Figure 4 Based on the above embodiment, after planarizing the deposited channel material, the method further includes:

[0094] S401 . Form a sandwich structure on the second dielectric material layer; wherein the sandwich structure includes a fourth dielectric material layer, a metal layer, and a fifth dielectric material layer; and the metal layer is an etchable material layer.

[0095] Specifically, Figure 5 This is a schematic diagram showing the implementation principle of a method for preparing a drive array according to another exemplary embodiment of the present application. Figure 5 , in getting Figure 5 After the structure shown in A ( Figure 5 A (using the left and right drive units as an example), a fourth dielectric material layer, a metal layer, and a fifth dielectric material layer are sequentially formed on this structure to form a sandwich structure. This sandwich structure is a sandwich structure composed of three layers stacked in sequence, namely the fourth dielectric material layer, the metal layer, and the fifth dielectric material layer, which are used to further build vertical capacitors on the vertical transistors.

[0096] Please refer to Figure 5 The fourth dielectric material layer is the bottom dielectric material layer in the sandwich structure, which is used to separate the fourth dielectric material layer from the underlying structure and form a portion of the insulating material of the capacitor.

[0097] Furthermore, the metal layer is the middle layer of the sandwich structure and serves as the metal electrode in the capacitor structure. The metal layer must have good conductivity and be etchable. In practical implementation, the specific material of the metal layer is selected based on actual needs and is not limited in this embodiment. For example, in one embodiment, the material of the metal layer may be Mo (molybdenum), Ru (ruthenium), ITO (indium tin oxide), etc.

[0098] Optionally, in a possible implementation, the metal layer includes a second metal line array.

[0099] Specifically, in one possible implementation, the metal layer is an array structure composed of a plurality of orderly arranged metal wires. In a specific implementation, a set of parallel metal wires (i.e., a second metal wire array) can be formed in the middle of the sandwich structure to serve as one plate of the capacitor.

[0100] Further, the specific material of the second metal wire array is determined according to actual needs, and in the embodiment, the specific material is not limited. For example, in an embodiment, the second metal wire array can be made of molybdenum, ruthenium, indium tin oxide, or other metals having good conductivity and etchability.

[0101] It can be understood that the metal layer is designed in the form of a wire array, which facilitates the independent formation of a vertical capacitor for each pixel unit and the realization of high-density array control. Meanwhile, compared with a whole metal layer, the metal wire array structure is easier to control the feature size, which is conducive to realizing a high-integration driving unit at a nanoscale.

[0102] It should be noted that the included angle between the second metal wire array and the first gate wire array is set according to actual needs, and in the embodiment, the included angle is not limited.

[0103] Optionally, in a possible implementation, the first gate wire array is perpendicular to the first metal wire array, and the second metal wire array is perpendicular to the first gate wire array.

[0104] Further, the fifth dielectric material layer is an electrically insulating layer at the top of the sandwich structure, and together with the fourth dielectric material layer, the fifth dielectric material layer clamps the metal layer in the middle.

[0105] Specifically, as shown in FIG. 5B, after the deposited channel material is planarized, the fourth dielectric material layer is first deposited for bottom electrical insulation, then the metal layer is deposited as the middle conductive electrode of the capacitor, and finally the fifth dielectric material layer is deposited for top insulation protection, and the three together constitute a sandwich structure. Figure 5

[0106] It should be noted that the thicknesses of the fourth dielectric material layer, the metal layer, and the fifth dielectric material layer are set according to actual needs, and in the embodiment, the thicknesses are not limited. For example, in a possible implementation, the thickness of the fourth dielectric material layer ranges from 30 nm to 50 nm, the thickness of the metal layer ranges from 60 nm to 100 nm, and the thickness of the fifth dielectric material layer ranges from 30 nm to 50 nm.

[0107] S402, a second hole is formed in a second specified position of the fifth dielectric material layer through an exposure technology; wherein the second specified position is a projection area of the first through hole on the fifth dielectric material layer.

[0108] Specifically, the second specified position is a region defining the position of the second hole in the photolithography process, and corresponds to the vertical projection area of the underlying first through hole on the fifth dielectric material layer.

[0109] Specifically, the vertical projection area of the first through hole on the fifth dielectric material layer is developed and etched to form the second hole. ​

[0110] It should be noted that the diameter of the second hole is set according to actual needs and is not limited in this embodiment. In specific implementation, the diameter of the second hole can be equal to the diameter of the first through hole, or can be larger or smaller than the diameter of the first through hole.

[0111] S403 , etching the second hole downwards by an etching technique, and stopping the etching process at the upper surface of the first through hole to form a second through hole communicating with the first through hole on the sandwich structure.

[0112] For details, please refer to Figure 5 ,like Figure 5 As shown in C, a second through hole is formed by etching, and the second through hole is connected to the first through hole in the lower layer.

[0113] In specific implementation, anisotropic dry etching technology can be used to etch downward in a vertical direction starting from the fifth dielectric material layer, penetrating the entire sandwich structure. The entire etching process is precisely terminated at the upper surface of the first through-hole through time control or stop layer identification, avoiding damage to the completed lower-layer channel or metal structure.

[0114] Further, such as Figure 5 As shown in C, after the etching is completed, a second through hole is obtained that runs from top to bottom, and its lower end is connected to the first through hole, providing a channel for the subsequent formation of another electrode of the cylindrical capacitor.

[0115] S404 , depositing a sixth dielectric material layer in the second through hole, and vertically etching the sixth dielectric material layer at the bottom of the second through hole downward to form a sidewall in the second through hole.

[0116] The specific implementation process of this step can refer to the description of step S105, which will not be repeated here. Figure 5 The structure shown in D.

[0117] It should be noted that the thickness of the sixth dielectric material layer is also set according to actual needs and is not limited in this embodiment. For example, in one possible implementation, the thickness of the sixth dielectric material layer is 20 nm.

[0118] S405 , depositing an electrode metal material as an electrode in the second through hole, and planarizing the deposited electrode metal material to prepare a 1T1C type driving array.

[0119] Specifically, the electrode metal material is deposited in the second through hole and serves as the material of another electrode of the cylindrical capacitor. The electrode metal material is a conductive material connected to the upper light-emitting device or circuit.

[0120] It should be noted that the sixth dielectric material layer serves as a dielectric layer between the two electrodes of the cylindrical layer capacitor. When depositing the sixth dielectric material layer, it is necessary to ensure that the through hole enclosed by the sixth dielectric material layer is connected to the channel material of the transistor below. After depositing the electrode metal material, it is necessary to ensure that the channel material is in contact with the electrode metal material to achieve electrical connection.

[0121] Furthermore, after depositing the electrode metal material in the second through hole, it is flattened to obtain Figure 5 The structure shown in E. It should be noted that the electrode metal material can be processed using the same planarization method as in step S105, which will not be described in detail here.

[0122] In specific implementation, after connecting the second through hole with the first through hole, physical vapor deposition or atomic layer deposition can be used to fill the second through hole with electrode metal material to construct the internal electrode of the capacitor; since the deposition process usually accumulates excess material above the through hole, it is flattened through processes such as chemical mechanical polishing to make the surface highly uniform and expose the required electrode contact surface.

[0123] Figure 6 This is a three-dimensional diagram of a driving array prepared according to an exemplary embodiment of the present application. Figure 5 and Figure 6 By using the method of this embodiment, a 1T1C type driving array can be prepared, wherein the 1T1C type driving array is composed of multiple driving units, for example, Figure 5 In the example shown, two drive units are shown, left and right. Figure 6 In the example shown, only one driving unit is shown. Each driving unit consists of a transistor (abbreviated as 1T) and a capacitor (abbreviated as 1C) and has a strong voltage holding capability.

[0124] See also Figure 5 and Figure 6 The driving array prepared in this embodiment includes a lower layer of transistors and an upper layer of capacitors. The lower layer of transistors are vertical ring-gate transistors, and the upper layer of capacitors are cylindrical capacitors, and the drain of the transistor is connected to one electrode of the capacitor.

[0125] In addition, if Figure 6 As shown in the figure, for a cylindrical capacitor, the red metal layer constitutes the outer electrode, the dark blue sixth dielectric material layer constitutes the dielectric layer, and the orange electrode metal material constitutes the inner electrode. The capacitance value of this cylindrical capacitor can be calculated using the following formula:

[0126]

[0127] Wherein, C is a capacitance value, h is the height of the cylindrical capacitor, i.e. the height of the sandwich structure, r1 is the radius of the inner cylinder composed of the metal electrode material, r2 is the outer radius of the second through hole, and ε is a preset parameter. In specific implementation, the height of the sandwich structure, the diameter of the second through hole, and the thickness of the sixth dielectric material layer can be set as needed to adjust the capacitance value of the cylindrical capacitor.

[0128] The preparation method of the driving array provided in the embodiment forms a vertical cylindrical capacitor on the top of the ring-gate vertical transistor by constructing a sandwich structure on the second dielectric material layer, forming a second through hole in the vertical projection area of the first through hole, and further forming a side wall and an electrode metal material in the second through hole. Thus, a 1T1C driving array with compact structure, strong driving capability, and excellent voltage retention is finally realized, which significantly improves the vertical integration of the driving array and provides a driving basis for micro display devices with ultra-small pixel pitch and high resolution.

[0129] According to the foregoing description, it can be understood that the preparation method has at least the following beneficial effects:

[0130] (1) Improving vertical integration

[0131] The present scheme improves the vertical integration of the device by stacking the cylindrical capacitor above the ring-gate vertical transistor, and optimizes the overall structure layout. The present scheme realizes the extreme miniaturization of the pixel unit, effectively improves the integration of the unit, reduces the planar occupation space, and provides technical support for constructing micro driving devices with ultra-high resolution and ultra-small pixel pitch.

[0132] (2) Enhancing driving capability

[0133] The cylindrical capacitor structure can flexibly control the capacitance value through the height and inner diameter. Compared with the traditional planar capacitor, the cylindrical structure has large and controllable capacitance and high integration. The increase in capacitance means that the driving array can store more electric charges in a smaller space, thereby providing strong driving capability for each pixel and improving the display effect.

[0134] (3) Realizing high resolution and ultra-small pixel pitch

[0135] The vertically stacked structure not only greatly improves the space utilization, but also significantly enhances the integration density, so that more driving units can be integrated in a unit area, thereby effectively improving the pixel density and image clarity, meeting the future development needs of 8K and higher resolution ultra-high definition display. In addition, the structure has good scalability and compatibility, which helps to promote the evolution of micro display technology to a higher level.

[0136] (4) Compatible with large-size or large-pixel driving devices

[0137] The driver array provided in this embodiment can be widely used in large-pixel driver device scenarios requiring large size or high power output. By collaboratively driving a single light-emitting or output pixel with multiple driver units, it can effectively provide the high-current drive capability required by high-power devices while maintaining low leakage, fast response, and low power consumption. Compared to traditional driver structures, this architecture can be used for large-size pixels to increase the aperture ratio, and can also significantly enhance drive efficiency and stability by utilizing collaborative driving of multiple driver units.

[0138] In summary, the drive array preparation method provided in this embodiment improves the driving capability and enhances the voltage retention by optimizing the structural design, laying the foundation for the development of ultra-small pixel pitch and high-resolution display technology, and has significant application value and technical advantages.

[0139] The following is a specific example to introduce the preparation process of the 2T1C driver array in detail:

[0140] Figure 7 This is a flow chart of Example 3 of the manufacturing method of the drive array provided in this application. Figure 7 Based on the above embodiment, after planarizing the deposited electrode metal material, the method further includes:

[0141] S701 , forming a second gate line array at positions of the fifth dielectric material layer corresponding to the second through holes, and covering the second gate line array with a seventh dielectric material layer; wherein each gate line in the second gate line array is connected to a column of second through holes.

[0142] Specifically, Figure 8 This is a schematic diagram showing the implementation principle of a method for preparing a drive array according to another exemplary embodiment of the present application. Figure 8 In this step, Figure 8 A second gate line array is formed based on the structure shown in A. It should be noted that when forming the second gate line array, it is necessary to ensure that each gate line is aligned with a column of second through holes, that is, each column of second through holes is covered with a gate line, and the gate line is in contact with the electrode metal material in the second through hole to form an electrical connection.

[0143] It should be noted that the second gate line array is composed of multiple gate lines, and the multiple gate lines are parallel. In addition, the width of each gate line is set according to actual needs and is not limited in this embodiment. For example, in one possible implementation, the width of each gate line can be greater than the diameter of the second through hole.

[0144] Further, after the second gate line array is formed, a seventh dielectric material layer can be further formed on the second gate line array. The seventh dielectric material layer is an insulating material layer covering the second gate line array, and is used for electrical isolation and supporting the upper layer process. In particular implementations, please continue to refer to Figure 8 , after the second gate line array is formed, the seventh dielectric material layer is covered on the second gate line array, and the structure shown in FIG. 8B is obtained. Figure 8

[0145] It should be noted that the thickness of the seventh dielectric material layer is also set according to actual needs, and in the embodiment, it is not limited. For example, in a possible implementation, the thickness of the seventh dielectric material layer is 30 nm. Further, for example, in an embodiment, an atomic layer deposition technique can be used to deposit a high dielectric constant material (the high dielectric constant material can include HfO2, Al2O3, SiO2, or a combination of Al2O3 and SiO2) to form the seventh dielectric material layer.

[0146] S702, forming a third hole on a third specified position of the seventh dielectric material layer by an exposure technique; the third specified position is an area outside the projection area of the first via in the second gate line array in the overlapping area of the projection area of the seventh dielectric material layer and the projection area of the metal layer.

[0147] Specifically, the third specified position is the overlapping area of the second gate line array and the lower metal layer on the seventh dielectric material layer except directly above the first via.

[0148] In particular implementations, please continue to refer to Figure 7 , the projection overlapping area of the second gate line and the metal layer on the seventh dielectric material layer can be determined first, and then the target area of the first via in the projection overlapping area is determined, and further, the area of the projection overlapping area except the target area can be used as the third specified position.

[0149] Further, after the third specified position is determined, the third hole can be defined and formed based on the exposure technique. It should be noted that the diameter of the third hole is set according to actual needs, and in the embodiment, it is not limited.

[0150] Optionally, in a possible implementation, the metal layer includes a second metal line array, the first gate line array is perpendicular to the first metal line array, and the second metal line array is perpendicular to the first gate line array; the second gate line array is perpendicular to the second metal line array.

[0151] ​It can be understood that by sequentially arranging four groups of mutually orthogonal linear arrays in the vertical direction, a strictly regular, addressable and three-dimensional scalable pixel matrix structure is constructed. By being placed perpendicular to each other, the entire linear array design is like a three-dimensional chessboard. By orthogonal combination of the plane and the vertical direction, not only is the clear pixel addressing logic realized, but also the wiring density and layer independence of the circuit are greatly improved, signal interference is effectively avoided, and controllable construction of a super-high resolution, nanoscale pixel array is supported. It is a key structural basis for constructing a high-integration, stackable and active driving array.

[0152] S703, etching the third hole downward by an etching technique, and stopping the etching process at the upper surface of the metal layer to form a third via hole perpendicular to the metal layer; the gate line in the second gate line array is wrapped around the third via hole.

[0153] When specifically implemented, the specific process of forming the third via hole can be referred to the introduction of forming the first via hole in the above-mentioned embodiments, which will not be described here again.

[0154] Please continue to refer to Figure 8 After this step, a structure as shown in Figure 8 C can be formed. The third via hole provides a basis for forming the channel of the second transistor.

[0155] S704, depositing an eighth dielectric material layer in the third via hole, and etching the eighth dielectric material layer at the bottom of the third via hole vertically downward to form a side wall in the third via hole.

[0156] The specific implementation process of this step can be referred to the description in the above-mentioned embodiments, which will not be described here again.

[0157] It should be noted that the third via hole, the first via hole and the second via hole can be arranged to have the same shape and size, the first via hole and the second via hole are completely coincident in the vertical direction, and the third via hole and the second via hole do not intersect in the vertical direction.

[0158] S705, depositing a channel material in the third via hole, and planarizing the deposited channel material.

[0159] The specific implementation process of this step can be referred to the description in the above-mentioned embodiments, which will not be described here again. Figure 8 Figure 8 D in

[0160] It should be noted that the thickness of the eighth dielectric material layer is set according to actual needs, which is not limited in this embodiment. Further, after depositing the channel material in the third via hole, it is necessary to ensure that the channel material is in contact with the metal layer to realize electrical connection.

[0161] ​S706, forming a drain on the third via hole to prepare a 2T1C driving array.

[0162] In the implementation, please continue to refer to Figure 8 The drain material can be deposited on the structure of D to obtain the structure shown in E. Figure 8 Figure 8 E.

[0163] Figure 9 A perspective view of the prepared driving array is shown in an exemplary embodiment of the present application. Please refer to Figure 8 and Figure 9 , a 2T1C driving array can be prepared by the method of the embodiment system, wherein the 2T1C driving array is composed of multiple driving units, for example, only one driving unit is shown in the example shown in Figure 9 , each driving unit is composed of two transistors (abbreviated as 1T) and one capacitor (abbreviated as 1C), and has strong voltage holding ability and uniform light emission.

[0164] Referring to Figure 8 and Figure 9 , the first transistor composed of the lower part is responsible for switching, the sandwich structure in the middle forms a cylindrical capacitor, and the second transistor composed of the upper part is responsible for driving, wherein the drain of the first transistor is connected with the inner electrode of the cylindrical capacitor, the outer electrode of the cylindrical capacitor is connected with the source of the second transistor, and the gate of the second transistor is also connected with the inner electrode of the cylindrical capacitor.

[0165] As can be understood from the foregoing description, a 2T1C driving array can be prepared by the method provided in the embodiment, and each driving unit in the driving array is composed of a transistor below, a capacitor stacked above the transistor, and a transistor stacked above the capacitor, which is a three-layer stacked driving array, and at least has the following effective effects:

[0166] (1) Enhance driving ability:

[0167] The capacitor is located between the two transistors, which provides stronger charge storage ability for the driving array. The function of the capacitor is to store charge when the switching transistor is opened, and the voltage stored by the capacitor can stably control the driving transistor to be in an open state after the switching transistor is closed, until the switching transistor is opened again to discharge the capacitor. The purpose is to ensure that the driving transistor outputs current more stably within a frame. Through this structure, the output current can be stabilized in a smaller space, and the driving density and ability are improved.

[0168] ​In addition, the combination of two transistors separates the data line and the driving line, reducing signal crosstalk between adjacent pixels, while further enhancing the switching speed and response capability of the array, enabling the array to drive more pixels, especially for high-resolution display devices.

[0169] (2) Optimize space utilization and integration:

[0170] The three-layer stacked structure saves a lot of space in the vertical direction. Integrating the capacitor and two transistors into a compact vertical level not only improves integration, but also effectively reduces the area occupied by the driving array. This allows more circuit integration in a limited space, adapting to the decreasing size of electronic devices and higher resolution requirements.

[0171] In addition, as the vertical integration increases, the size of each driving unit decreases, allowing smaller pixel pitches to be achieved.

[0172] (3) Support higher resolution and response speed:

[0173] Through the reasonable stacking of transistors, capacitors, and transistors, not only the driving capability of the elements can be improved, but also the response speed of the pixels can be improved. This makes the driving array suitable for higher refresh rates and higher resolution display requirements, especially in the fields of ultra-high-definition display, OLED, micro display, etc.

[0174] In summary, by stacking a capacitor above a transistor and adding another transistor above the capacitor, this three-layer stacked structure has shown significant advantages in enhancing driving capability, voltage retention, response speed, and space utilization efficiency. Its highly integrated and compact design not only meets the needs of ultra-small pixel pitch and high-resolution display, but also provides a solid foundation for the development of future micro display, ultra-high-definition display, and other technologies.

[0175] Corresponding to the foregoing embodiment of the preparation method of the driving array, the present application also provides an embodiment of the driving array, which is introduced as follows.

[0176] Figure 10 The schematic diagram of the driving array embodiment provided by the present application is shown in FIG. 1. Please refer to FIG. 1 Figure 10 The driving array provided by the present embodiment includes a metal line structure and a first gate line structure in order from bottom to top; wherein the metal line structure includes a first metal line array and a first dielectric material layer covering the first metal line array; the first gate line structure includes a first gate line array formed on the first dielectric material layer, and a second dielectric material layer covering the first gate line array;

[0177] The first specified area of the first gate line structure has a first channel structure in the form of a through hole; the first specified area is an overlapping area of a projection area of the first metal line array on the gate line structure and the first gate line array; the first channel structure includes a first through hole perpendicular to each metal line in the first metal line array, a third dielectric material layer formed on a sidewall of the first through hole, and a channel material formed in a hole surrounded by the third dielectric material layer.

[0178] Specifically, please refer to Figure 3 and Figure 10 , Figure 3 The 1T type driving array shown is sequentially arranged from bottom to top as follows:

[0179] (1) Metal line structure: located at the bottom, composed of a first metal line array and a first dielectric material layer thereon.

[0180] (2) First gate line structure: located above the metal line structure, including a first gate line array (composed of a plurality of gate lines) arranged on the first dielectric material layer and a second dielectric material layer.

[0181] Further, the first channel structure is embedded in the above structure, which is composed of a first through hole, a third dielectric material layer on the sidewall of the first through hole, and a channel material inside the through hole.

[0182] It should be noted that the first through hole is located in the overlapping projection area of the first metal line array and the first gate line array in the vertical direction, that is, each through hole is determined by the intersection of the "lateral gate line" and the "vertical metal line", forming an orderly layout.

[0183] Further, the third dielectric material layer covers the sidewall of the first through hole, forming a gate oxide layer, and the channel material is deposited inside the through hole, forming a controllable conductive path.

[0184] The driving array provided by the embodiment realizes a single-pixel switching unit with ultra-small size and high gate control efficiency.

[0185] Figure 11 The schematic diagram of the driving array embodiment provided by the present application is shown in FIG. 2. Please refer to Figure 11 The driving array provided by the embodiment is based on the above-mentioned embodiment, and further includes a sandwich structure formed above the gate line structure; the sandwich structure includes a fourth dielectric material layer, a metal layer, and a fifth dielectric material layer.

[0186] The second designated area of the sandwich structure has a composite structure in the shape of a through hole; the second designated area is a projection area of the first designated area in the sandwich structure; the composite structure includes a second through hole perpendicular to the metal layer and in communication with the first through hole, a sixth dielectric material layer formed on the sidewall of the second through hole, and an electrode metal material formed in the hole surrounded by the sixth dielectric material layer.

[0187] Specifically, please continue to refer to Figure 6 and Figure 11 which is a 1T1C drive array, on the basis of the 1-type drive array, the upper part of the vertical transistor further includes a sandwich structure, which is composed of three layers:

[0188] (1) a fourth dielectric material layer;

[0189] (2) a metal layer;

[0190] (3) a fifth dielectric material layer;

[0191] Further, a second through hole is opened in the second designated area of the sandwich structure (i.e. the projection area of the lower first through hole in the sandwich structure), the second through hole is perpendicular to the metal layer, penetrates the entire sandwich structure, and is in communication with the lower first through hole.

[0192] Further, the sidewall of the second through hole is deposited with a sixth dielectric material layer as a capacitor insulating layer, and the inside of the second through hole is filled with an electrode metal material as a capacitor electrode, which is finally connected with the upper circuit.

[0193] The drive array provided in the embodiment further constructs a stacked structure on the basis of the original vertical 1T0C structure to form a cylindrical capacitor, and finally forms a 1T1C drive array, which not only realizes the vertical integration of the ring gate type transistor and the embedded capacitor, but also provides an upwardly extending interconnection path, lays a structural foundation for constructing a high-density drive array, and has the significant functional advantages of high integration, strong retention capability and scalable stacking.

[0194] Figure 12 The schematic diagram of the drive array provided in the third embodiment of the application is provided. Please refer to Figure 12 The drive array provided in the embodiment is based on the above-mentioned embodiments, and further includes a second gate line structure;

[0195] The second gate line structure includes a second gate line array formed at the position of the corresponding second through hole of the fifth dielectric material layer, and a seventh dielectric material layer covering the second gate line structure; wherein each gate line in the second gate line array is connected with a column of second through holes;

[0196] The third specified region of the second gate line structure has a second channel structure in the form of a through hole; the third specified region is a region outside the projection region of the second gate line structure in which the second through hole and the metal layer overlap with each other; the second channel structure includes a third through hole perpendicular to the metal layer, an eighth dielectric material layer formed on the sidewall of the third through hole, and a channel material formed in a hole surrounded by the eighth dielectric material layer;

[0197] The driving array further includes a drain formed above the third through hole.

[0198] Specifically, please continue to refer to the driving array shown in Figure 9 and Figure 12 , Figure 12 The driving array is a 2T1C driving array. The second gate line structure is composed of a second gate line array and a seventh dielectric material layer thereon, and the second gate line array is arranged on the fifth dielectric material layer and is aligned with the position of the second through hole below.

[0199] Further, please continue to refer to Figure 12 The second channel structure is located above the second gate line structure and includes a third through hole perpendicular to the second gate line structure and not directly connected to the structure below, an eighth dielectric material layer deposited on the sidewall of the through hole for insulation and electric field regulation, and a channel material deposited in the through hole to form a controllable conductive path.

[0200] It should be noted that the third through hole is formed in the overlapping region of the second gate line array and the metal layer projection, which facilitates the realization of the gate control characteristic.

[0201] Further, after filling the third through hole with the channel material, a metal material is further deposited thereon to form a drain, and the drain is used to output the current of the second transistor to the upper device or the light emitting unit after being turned on.

[0202] The driving array provided by the embodiment is a 2T1C driving array, has the advantages of high gate control efficiency and compact layout, realizes column-level control through the second gate line, and is vertically integrated with the first transistor and the capacitor below, which is a core structure supporting ultra-small pixel size and three-dimensional integrated driving array.

[0203] Corresponding to the foregoing embodiment of the driving array, the present application further provides an embodiment of an electronic device.

[0204] Specifically, the electronic device provided by the present application includes the driving array of any of the foregoing embodiments and a controlled device; wherein the driving array is used to provide a driving signal for the controlled device.

[0205] Optionally, the controlled device is any one of the following: a light-emitting device, a detector device, an electrochromic device.

[0206] Specifically, taking a Micro-LED / OLED pixel light-emitting device as an example, the driving array controls the on-off of current or the holding of voltage, so that the light-emitting device emits light according to the set gray scale brightness.

[0207] In specific implementation, a 1T1C driving array or a 2T1C driving array can be used to realize stable brightness control and high-speed refresh capability.

[0208] Further, taking a photodetector and an infrared sensor as examples, the driving array is responsible for providing a bias voltage and reading a photoelectric response signal, so as to realize pixel-level signal acquisition.

[0209] In specific implementation, a 1T0C driving array can meet the basic readout requirement, and the array structure is conducive to the construction of an imaging array, so that the detector device can be applied to an imaging sensor array, environmental perception, low-light imaging, etc.

[0210] Further, taking a WO3 film as an example, the driving array applies a controllable voltage to realize color change, dimming, or transparency switching of the device.

[0211] In specific implementation, a 1T1C structure can maintain the voltage state to realize long-acting display or dimming, so that the electrochromic device can be applied to an electronic window, low-power electronic paper, a flexible color-changing label, etc.

[0212] Optionally, in a possible implementation, the controlled device is a programmable mask; the driving array is specifically configured to generate a mask driving signal corresponding to the layout according to the layout, so as to control the light transmission state of each pixel region on the programmable mask through the mask driving signal, so as to form a mask layout corresponding to the layout on the programmable mask.

[0213] Specifically, the programmable mask plate comprises: an electrolytic reaction layer, the electrolytic reaction layer comprising an electrolyte layer, a first electrolytic material layer, and a second electrolytic material layer, wherein the electrolyte layer is arranged between the first electrolytic material layer and the second electrolytic material layer, one or two of the electrolyte layer, the first electrolytic material layer, and the second electrolytic material layer comprise a plurality of blocks arranged in an array, and the other two or one of the electrolyte layer, the first electrolytic material layer, and the second electrolytic material layer is in a continuous film shape.

[0214] The first control circuit layer is arranged on a first side of the electrolytic reaction layer, and the first control circuit layer comprises a plurality of first control electrodes.

[0215] The second control circuit layer is arranged on a second side opposite to the first side of the electrolysis reaction layer, and the second control circuit layer comprises a plurality of second control electrodes.

[0216] Each pixel region in the mask plate comprises one or more blocks, at least a part of the first control electrode and at least a part of the second control electrode, and the light transmission state of the pixel region in the mask plate for the exposure light beam is configured to be determined by the control voltage between the at least part of the first control electrode and the at least part of the second control electrode contained in the pixel region.

[0217] For the programmable mask plate, please refer to the description in the related art, and the embodiment will not be introduced.

[0218] Specifically, the driving array provided in the embodiment can provide a mask plate driving signal for the programmable mask plate.

[0219] The electronic device provided in the embodiment is the programmable mask plate, the driving array cooperates with the programmable mask plate, the light transmission state of the pixel region in the electrolysis reaction layer is controlled through the pixel-by-pixel output of the driving signal, and a mask pattern matching the input layout is dynamically formed, so that, based on the high-integration vertical GAA driving array, the super-high resolution, fine pattern switching and high-precision exposure control can be supported, the design flexibility is improved and the manufacturing cost is reduced compared with the traditional fixed mask plate.

[0220] The above only describes the preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a drive array, characterized by, A method for manufacturing the driving array, comprising: forming a metal line structure; wherein the metal line structure comprises a first metal line array and a first dielectric material layer covering the first metal line array; forming a first gate line array on the first dielectric material layer and covering the first gate line array with a second dielectric material layer; wherein the first gate line array and the first metal line array are at a specified angle, the specified angle being greater than 0 degree and less than or equal to 90 degrees; forming a first hole on a first specified position of the second dielectric material layer by exposure technology; wherein the first specified position is an overlapping area of a projection area of each metal line in the first metal line array on the second dielectric material layer and a projection area of each gate line in the first gate line array on the second dielectric material layer; etching down the first hole by etching technology, and stopping the etching process on the upper surface of the metal line to form a first via hole perpendicular to the metal line; wherein a gate line in the first gate line array wraps around the first via hole; depositing a third dielectric material layer in the first via hole, and etching down the third dielectric material layer at the bottom of the first via hole to form a sidewall in the first via hole; depositing a channel material in the first via hole, and planarizing the deposited channel material.

2. The method of claim 1, wherein, After the planarizing of the deposited channel material, the method further comprises: forming a sandwich structure on the second dielectric material layer; wherein the sandwich structure comprises a fourth dielectric material layer, a metal layer and a fifth dielectric material layer; the metal layer is a layer of etchable material; forming a second hole on a second specified position of the fifth dielectric material layer by exposure technology; wherein the second specified position is a projection area of the first via hole on the fifth dielectric material layer; etching down the second hole by etching technology, and stopping the etching process on the upper surface of the first via hole to form a second via hole on the sandwich structure, the second via hole being in communication with the first via hole; depositing a sixth dielectric material layer in the second via hole, and etching down the sixth dielectric material layer at the bottom of the second via hole to form a sidewall in the second via hole; depositing an electrode metal material as an electrode in the second via hole, and planarizing the deposited electrode metal material to manufacture a 1T1C type driving array.

3. The method of claim 2, wherein, After the planarizing of the deposited electrode metal material, the method further comprises: forming a second gate line array on the fifth dielectric material layer at a position corresponding to the second via hole, and covering the second gate line array with a seventh dielectric material layer; wherein each gate line in the second gate line array is connected with a column of second via holes; forming a third hole on a third specified position of the seventh dielectric material layer by exposure technology; the third specified position is an overlapping area of a projection area of each gate line in the second gate line array on the seventh dielectric material layer and a projection area of the metal layer on the seventh dielectric material layer in an area outside the projection area of the first via hole on the seventh dielectric material layer; etching down the third hole, the etching process stops at the upper surface of the metal layer, forming a third via perpendicular to the metal layer; the gate lines in the second gate line array wrap around the third via; depositing an eighth dielectric material layer in the third via, and vertically etching away the eighth dielectric material layer at the bottom of the third via to form a sidewall in the third via; depositing a channel material in the third via, and planarizing the deposited channel material; forming a drain above the third via to prepare a 2T1C type driving array.

4. The method of claim 1, wherein, After the planarizing of the deposited channel material, the method further comprises: forming a drain above the first via to prepare a 1T type driving array.

5. The method of claim 2, wherein, The metal layer comprises a second metal line array.

6. The method of claim 5, the first gate line array is perpendicular to the first metal line array, and the second metal line array is perpendicular to the first gate line array.

7. The method of claim 3, wherein, The metal layer comprises a second metal line array, the first gate line array is perpendicular to the first metal line array, the second metal line array is perpendicular to the first gate line array, and the second gate line array is perpendicular to the second metal line array.

8. A drive array, comprising: The driving array is prepared based on the preparation method of the driving array of any one of claims 1-7; In order from bottom to top, the driving array comprises a metal line structure and a first gate line structure; wherein the metal line structure comprises a first metal line array and a first dielectric material layer covering the first metal line array; the first gate line structure comprises a first gate line array formed on the first dielectric material layer, and a second dielectric material layer covering the first gate line array; the first gate line array and the first metal line array are at a specified angle, the specified angle is greater than 0 degrees and less than or equal to 90 degrees; A first specified region of the first gate line structure has a via-shaped first channel structure; the first specified region is an overlapping region of a projection region of the first metal line array on the first gate line structure and the first gate line array; the first channel structure comprises a first via perpendicular to each metal line in the first metal line array, a third dielectric material layer formed on a sidewall of the first via, and a channel material formed in a hole surrounded by the third dielectric material layer.

9. The drive array of claim 8, wherein, The driving array further comprises a sandwich structure formed above the first gate line structure; the sandwich structure comprises a fourth dielectric material layer, a metal layer, and a fifth dielectric material layer; A second specified region of the sandwich structure has a via-shaped composite structure; the second specified region is a projection region of the first specified region on the sandwich structure; the composite structure comprises a second via perpendicular to the metal layer and in communication with the first via, a sixth dielectric material layer formed on a sidewall of the second via, and an electrode metal material formed in a hole surrounded by the sixth dielectric material layer.

10. The drive array of claim 9, wherein, The driving array further comprises a second gate line structure; The second gate line structure includes a second gate line array formed at a position corresponding to the second via hole of the fifth dielectric material layer, and a seventh dielectric material layer covering the second gate line array; wherein each gate line in the second gate line array is connected with a column of second via holes; A third specified region of the second gate line structure has a second channel structure in the shape of a via hole; the third specified region is a region of the second via hole outside the projection region of the second gate line structure, and an overlapping region of the projection region of the second gate line structure and the second gate line array of the metal layer; the second channel structure includes a third via hole perpendicular to the metal layer, an eighth dielectric material layer formed on the sidewall of the third via hole, and a channel material formed in a hole surrounded by the eighth dielectric material layer; The driving array further includes a drain formed above the third via hole.

11. An electronic device, characterized by The electronic device includes the driving array according to any one of claims 8-10, and a controlled device; The driving array is configured to provide a driving signal for the controlled device.

12. Electronic device according to claim 11, characterized in that The controlled device is any one of the following devices: a light emitting device, a detector, an electrochromic device.

13. The electronic device of claim 11, wherein, The controlled device is a programmable mask; The driving array is particularly configured to generate a mask driving signal corresponding to a layout according to the layout, so as to control the light transmission state of each pixel region on the programmable mask through the mask driving signal, and form a mask pattern corresponding to the layout on the programmable mask.

Images