Memory recovery method and device, electronic equipment, storage medium and program product

Abstract

The invention discloses a memory recovery method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of storage. The method comprises the steps of establishing a first address mapping relation between a first physical address and a first logic address of a first virtual memory segment under the condition that a memory recovery request is detected, deleting a second address mapping relation between the second physical address and a second logic address of the second virtual memory segment and a third address mapping relation between the first physical address and a third logic address of the second virtual memory segment; the real memory segment corresponding to the second virtual memory segment comprises valid data and invalid data; the first physical address is a physical address of valid data, the second physical address is a physical address of invalid data, and the first virtual memory segment is an idle virtual memory segment; and executing memory recovery operation on invalid data in the real memory segment.

Description

Technical Field

[0001] The present application belongs to the field of storage technology, and specifically relates to a memory recovery method, device, electronic device, storage medium and program product. Background Art

[0002] Currently, in order to improve the utilization rate of the storage space of the electronic device, the electronic device can recycle the invalid data in the storage space.

[0003] In the prior art, when an electronic device needs to recover data, the system-on-chip (SOC) in the electronic device selects an old segment from the virtual memory space and sends a read command to the universal flash storage (UFS) in the electronic device. The UFS stores the valid data of the old segment in the low power double data rate (LPDDR) cache. After the SOC selects a new segment from the virtual memory space, it sends a write command to the UFS. The UFS writes the valid data temporarily stored in the LPDDR into the real memory segment corresponding to the new segment and establishes a new data mapping. Finally, the SOC sends a clear command to clear the data mapping corresponding to the old segment, invalidate the valid data corresponding to the old segment, and erase all data in the real memory segment corresponding to the old segment.

[0004] However, the above method involves multiple rounds of data flow, which generates redundant input and output (IO), affecting the memory recycling performance of the electronic device. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a memory recovery method, device, electronic device, storage medium and program product, which can improve the memory recovery performance of electronic devices.

[0006] In a first aspect, an embodiment of the present application provides a memory recovery method, which includes: when a memory recovery request is detected, establishing a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment, and deleting a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment; the real memory segment corresponding to the second virtual memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment; and performing a memory recovery operation on the invalid data in the real memory segment.

[0007] In a second aspect, an embodiment of the present application provides a memory recovery device, which includes: an establishment module, a deletion module and a recovery module. The establishment module is used to establish a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment when a memory recovery request is detected. The deletion module is used to delete the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment and the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment; the real memory segment corresponding to the second virtual memory segment contains valid data and invalid data; the first physical address is the physical address of valid data, the second physical address is the physical address of invalid data, and the first virtual memory segment is an idle virtual memory segment. The recovery module is used to perform memory recovery operations on invalid data in the real memory segment.

[0008] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0010] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method described in the first aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method described in the first aspect.

[0012] In an embodiment of the present application, when a memory reclaim request is detected, a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment can be established, and then, a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment and a third address mapping relationship between a first physical address and a third logical address of a second virtual memory segment can be deleted; the real memory segment corresponding to the first memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment; finally, a reclaim operation is performed on the invalid data in the real memory segment. In this solution, when a memory reclaim request is detected, a first address mapping relationship between the physical address of the valid data in the real memory segment and the logical address of the first virtual memory segment can be established, and a third address mapping relationship between the physical address of the valid data in the real memory segment and the logical address of the second virtual memory segment can be deleted. By only changing the address mapping relationship, the second virtual memory segment can be released, so that the memory reclaim operation does not need to perform multiple rounds of data reading and writing, thereby improving the memory reclaim performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of memory recycling processing in the prior art;

[0014] Figure 2 It is a flowchart of memory recycling in the prior art;

[0015] Figure 3 This is a technical schematic diagram of memory recycling in the prior art;

[0016] Figure 4 This is one of the flow charts of a memory recovery method provided in an embodiment of the present application;

[0017] Figure 5 This is a technical principle diagram of memory recycling provided by an embodiment of the present application;

[0018] Figure 6 This is the second flowchart of a memory recovery method provided in an embodiment of the present application;

[0019] Figure 7A This is one of the technical principle diagrams for establishing an address mapping relationship provided in an embodiment of the present application;

[0020] Figure 7B This is the second technical principle diagram of establishing an address mapping relationship provided by an embodiment of the present application;

[0021] Figure 8 This is the third flowchart of a memory recovery method provided in an embodiment of the present application;

[0022] Figure 9 This is the fourth flowchart of a memory recovery method provided in an embodiment of the present application;

[0023] Figure 10 This is the fifth flowchart of a memory recovery method provided in an embodiment of the present application;

[0024] Figure 11 This is a schematic diagram of the structure of an address mapping deletion command provided in an embodiment of the present application;

[0025] Figure 12 This is the sixth flowchart of a memory recovery method provided in an embodiment of the present application;

[0026] Figure 13 This is the seventh flowchart of a memory recovery method provided in an embodiment of the present application;

[0027] Figure 14 This is one of the structural diagrams of a memory recycling device provided in an embodiment of the present application;

[0028] Figure 15 This is the second structural diagram of a memory recycling device provided in an embodiment of the present application;

[0029] Figure 16 This is one of the hardware structure diagrams of an electronic device provided in an embodiment of the present application;

[0030] Figure 17 This is the second hardware structure diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of this application to clearly describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0032] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0033] The terms "at least one" and "at least one of" in the specification and claims of this application refer to any one, any two, or a combination of more than two of the objects included. For example, at least one of a, b, and c can be represented by: "a", "b", "c", "a and b", "a and c", "b and c", and "a, b, and c", where a, b, and c can be single or multiple. Similarly, "at least two" means two or more, and its meaning is similar to "at least one".

[0034] The following is a detailed explanation of the professional terms provided in the embodiments of this application.

[0035] Valid data: Valid data in this application refers to the data being used by applications in electronic devices.

[0036] Invalid data: Valid data in this application refers to the data that has been least recently used by applications in an electronic device.

[0037] Metadata: Metadata is used to describe data. It is a description of the data itself, data source, data usage, data format and other information. It aims to help users better understand and use data. Metadata is the instruction manual of data.

[0038] Logical address: The logical address can also be called a virtual address. The logical address refers to the address space used by applications in electronic devices. It is generated by the compiler and is a continuous address from the process perspective.

[0039] Physical address: The address in the actual memory hardware, accessed by the central processing unit (CPU) in the electronic device through the bus.

[0040] Virtual Memory Segments: Virtual memory segments are a mechanism used by the operating system to divide a process's virtual address space into multiple logical areas (segments) when managing virtual memory. Each segment typically corresponds to a different function or purpose (such as code, data, heap, stack, etc.) and is distinguished by permissions, attributes, and address range.

[0041] Real memory segments: These are memory pages in physical memory. Physical memory (RAM) is the actual hardware memory of electronic devices and is directly managed by the operating system. Its address space is usually managed in units of page frames.

[0042] The memory recovery method, device, electronic device, storage medium and program product provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0043] Currently, electronic devices can implement file system management based on the Flash-Friendly File System (F2FS), which can include UFS and SOC. The UFS is used for data storage, and the SOC is used to select memory segments in the virtual memory space. F2FS adopts a log-structured design. When data is updated, it will not overwrite the old data in place, but write the new data to the free location, and the original data will become invalid data (Stale Data). With the continuous use of users, data fragmentation will become more and more serious, and invalid data will increase. In order to ensure the performance of electronic devices and free up storage space, garbage collection (GC) is required. GC is widely used in the entire cycle of electronic devices.

[0044] For example, Figure 1 The figure shows the implementation principle of GC in F2FS. For the file system, UFS is divided into many memory segments, each of which may contain three types of data, namely valid data (in green), invalid data (in red), and empty data (in white). The purpose of memory recycling is to rewrite valid data to a new memory segment (hereinafter referred to as the new segment) and invalidate the data in the old memory segment (hereinafter referred to as the old segment). Then, a discard command is sent to erase all the contents in the old memory segment to free up space and improve performance. For example, Figure 1 The old segment 1 includes 4 logical addresses of invalid data and 5 logical addresses of valid data. The old segment 1 corresponds to 4 invalid data and 5 valid data in the real memory segment 2. After the electronic device completes the memory recycling process, the old segment 1 is released and the invalid data in the real memory segment 2 is erased.

[0045] For example, Figure 2 This shows a detailed flowchart of the current memory reclamation process. The main steps include:

[0046] Step 20: The SOC selects an old segment in the virtual memory space and sends a read command to the UFS.

[0047] The read command includes the logical address of the old segment, and the old segment includes the logical address of the valid data and the logical address of the invalid data.

[0048] Step 21: UFS receives the read command sent by the SOC and obtains valid data from the real memory segment corresponding to the old segment.

[0049] Step 22: UFS stores the valid data in LPDDR.

[0050] Step 23: The SOC selects a new segment in the virtual memory space and sends a write command to the UFS.

[0051] The write command includes the logical address of the new segment, and the write command is used to instruct the UFS to store valid data in the new segment.

[0052] Step 24: UFS receives a write command, establishes an address mapping relationship between the logical address of the new segment and the real memory segment corresponding to the new segment, and writes the valid data stored in the LPDDR into the real memory segment corresponding to the new segment.

[0053] Step 25: The UFS sends a first confirmation message to the SOC.

[0054] The confirmation message is used to instruct the UFS to complete the storage of valid data.

[0055] Step 26: The SOC sends a discard command to the UFS.

[0056] The discard command is used to instruct the UFS to delete the address mapping relationship between the old segment and the real memory segment corresponding to the old segment, and to delete all data in the real memory segment corresponding to the old segment.

[0057] Step 27: UFS receives the discard command sent by the SOC, deletes the address mapping relationship between the old segment and the real memory segment corresponding to the old segment, invalidates all data in the real memory segment corresponding to the old segment, and deletes all data in the real memory segment corresponding to the old segment.

[0058] Step 28: The UFS sends a second confirmation message to the SOC.

[0059] The second confirmation message is used to instruct the UFS to complete the above-mentioned deletion operation.

[0060] Step 29: The SOC receives the second confirmation message from the UFS and updates metadata corresponding to the valid data.

[0061] It can be understood that the entire memory recycling process is actually the process of moving data from the old segment to the new segment. Figure 3 As shown in the figure, the entire memory recycling process for electronic devices involves deleting the address mappings corresponding to valid data and invalid data in the old segment, as well as deleting all data in the real memory segment corresponding to the old segment. Furthermore, an address mapping relationship is added between the new segment and the real memory segment corresponding to the new segment, and valid data in the real memory segment corresponding to the old segment is moved to the real memory segment corresponding to the new segment. × represents the portion to be removed, and √ represents the portion to be added.

[0062] According to the above steps, the purpose of F2FS memory recycling is to move data from the old segment to the new segment and release the old segment. Figure 2 As can be seen, the process involves multiple rounds of data flow (read and write), invalidating the original UFS data and rewriting it to a new physical address. This process not only generates a large number of redundant I / O operations, affecting system performance, but also causes additional writes to the UFS, reducing its lifespan. Furthermore, multiple commands are sent throughout the process, and LPDDR is used to store temporary data, introducing additional power consumption.

[0063] In the memory recovery method provided in an embodiment of the present application, when a memory recovery request is detected, a first address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the first virtual memory segment can be established, and a third address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the second virtual memory segment can be deleted; therefore, by only changing the address mapping relationship, the second virtual memory segment can be released, and then memory recovery can be performed, without the need for multiple rounds of data reading and writing, thereby improving the speed of memory recovery and further improving the memory recovery performance of the electronic device; and no data is written in the UFS, which improves the service life of the UFS; and there is no need for temporary storage of data, so there is no need to use LPDDR, thereby reducing the power consumption of the electronic device.

[0064] The memory recovery method provided in the embodiment of the present application may be executed by a memory recovery device, which may be an electronic device or a functional module in the electronic device. The technical solution provided in the embodiment of the present application is described below using an electronic device as an example.

[0065] The present invention provides a memory recovery method. Figure 4 The flowchart of a memory recycling method provided by an embodiment of the present application is shown. The method can be applied to an electronic device, which may include a UFS and a SOC. Figure 4 As shown, the memory recovery method provided in the embodiment of the present application may include the following steps 201 and 202.

[0066] Step 201: When a memory reclaim request is detected, the electronic device establishes a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment, and deletes a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment, and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment.

[0067] It should be noted that the memory involved in the embodiments of the present application refers to the memory in the UFS, rather than the running memory of the electronic device, such as Low Power Double Data Rate SDRAM (LPDDR).

[0068] In an embodiment of the present application, the real memory segment corresponding to the above-mentioned second virtual memory segment contains valid data and invalid data; the above-mentioned first physical address is the physical address of the valid data, the above-mentioned second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment.

[0069] In the embodiment of the present application, the first virtual memory segment and the second first virtual memory segment are memory segments in the virtual memory space of the electronic device.

[0070] Optionally, in an embodiment of the present application, the first logical address may be stored in a first virtual memory segment, and the second logical address and the third logical address may be stored in a second virtual memory segment.

[0071] It can be understood that the second logical address is the logical address corresponding to invalid data in the real memory segment corresponding to the second virtual memory segment; the third logical address is the logical address corresponding to valid data in the real memory segment corresponding to the second virtual memory segment.

[0072] Optionally, in an embodiment of the present application, the electronic device may detect a memory reclaim request through a CPU in the electronic device.

[0073] Exemplarily, the memory reclaiming request may be sent by a first application in the electronic device; or, the memory reclaiming request may be generated by the electronic device itself at preset time intervals.

[0074] For example, the memory reclaim request may be a memory reclaim request sent by the first application and received by the CPU in the electronic device; or, the memory reclaim request may be a memory reclaim request generated by the CPU itself.

[0075] Optionally, in the embodiment of the present application, the first application can be any application in the electronic device. For example, the first application can be any of the following: an instant messaging application, a game application, a video application, etc. The specific application can be determined based on actual usage requirements and is not limited in the embodiment of the present application.

[0076] Optionally, in the embodiment of the present application, the preset duration may be preset by the electronic device; or, the preset duration may be user-defined. Specific settings may be determined based on actual usage requirements and are not limited in the embodiment of the present application.

[0077] Exemplarily, the preset duration may be any one of the following: 10 minutes, 20 minutes, 30 minutes, etc.

[0078] For example, when the electronic device detects a memory reclaim request every 30 minutes, the electronic device establishes a first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment, and deletes the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment and the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment.

[0079] It should be noted that the first virtual memory segment is a memory that does not have an address mapping relationship in the virtual memory space, that is, an idle virtual memory segment.

[0080] Optionally, in the embodiment of the present application, the first physical address may be one or more, and the specific number may be determined according to the amount of valid data contained in the real memory segment corresponding to the second virtual memory segment.

[0081] It should be noted that the above-mentioned first physical address is the physical address of the valid data contained in the real memory segment corresponding to the second virtual memory segment.

[0082] Optionally, in the embodiment of the present application, the first logical address may be one or more, and the specific number may be determined according to the amount of valid data contained in the real memory segment corresponding to the second virtual memory segment.

[0083] Exemplarily, assuming that the number of valid data contained in the real memory segment corresponding to the second virtual memory segment is 6, the number of first logical addresses is 6.

[0084] Optionally, in an embodiment of the present application, when there are multiple first logical addresses, each of the multiple first logical addresses may be adjacent.

[0085] Optionally, in the embodiment of the present application, each logical address in the plurality of first logical addresses may correspond one-to-one to each first physical address in the plurality of first physical addresses, ie, the first address mapping relationship.

[0086] Optionally, in the embodiment of the present application, the second physical address may be one or more, and the specific number may be determined according to the amount of invalid data contained in the real memory segment corresponding to the second virtual memory segment.

[0087] It should be noted that the second physical address is the physical address corresponding to the invalid data contained in the real memory segment corresponding to the second virtual memory segment.

[0088] Optionally, in the embodiment of the present application, the second logical address may be one or more, and each of the plurality of second logical addresses may correspond one-to-one to each of the plurality of second physical addresses, ie, the second address mapping relationship.

[0089] Optionally, in an embodiment of the present application, the third logical address may be one or more. Each of the plurality of third logical addresses may correspond one-to-one to each of the plurality of first physical addresses, i.e., the third address mapping relationship.

[0090] It should be noted that the third logical address is a logical address corresponding to valid data contained in the real memory segment corresponding to the second virtual memory segment.

[0091] Optionally, in an embodiment of the present application, when a memory reclaim request is detected, the electronic device may select a first virtual memory segment and a second virtual memory segment from the virtual memory space through the SOC in the electronic device.

[0092] Exemplarily, the SOC in the electronic device may select the first virtual memory segment and the second virtual memory segment from the virtual memory space according to the data address mapping table stored in the F2FS.

[0093] For example, the SOC can query at least one third virtual memory segment in the virtual memory space for which no address mapping relationship exists from the data address mapping table, thereby using any one of the at least one third virtual memory segment as the first virtual memory segment; then, the SOC can query at least one fourth virtual memory segment in the virtual memory space for which an address mapping relationship exists from the data address mapping table, thereby using any one of the at least one fourth virtual memory segment as the second virtual memory segment.

[0094] Optionally, in an embodiment of the present application, after the SOC in the electronic device selects the first virtual memory segment and the second virtual memory segment from the virtual memory space, it can send a first command to the UFS, where the first command is used to instruct the UFS to establish a first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment, and to delete the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment, and the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment.

[0095] Optionally, in an embodiment of the present application, the first command may include a logical address of the first virtual memory segment and a logical address of the second virtual memory segment.

[0096] It can be understood that the logical address of the first virtual memory segment is used by UFS to search for the first virtual memory segment from the virtual memory space; the logical address of the second virtual memory segment is used by UFS to search for the second virtual memory segment from the virtual memory space.

[0097] It should be noted that the specific process of the UFS in the above-mentioned electronic device establishing a first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment, and deleting the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment, and the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment can be seen in detail in the following embodiments. To avoid repetition, it will not be repeated here.

[0098] For example, Figure 5 As shown, after the SOC in the electronic device selects the new segment in the virtual memory space, that is, the first virtual memory segment, and the SOC selects the old segment in the virtual memory space, that is, the second virtual memory segment, the SOC can send a first command to the UFS in the electronic device, where the first command includes the logical address of the old segment and the logical address of the new segment. Then, when the UFS receives the first command, it can establish an address mapping relationship between the valid data stored in the real memory segments corresponding to the new segment and the old segment. Figure 5 The new address mapping is expressed in , and the address mapping relationship of the valid data stored in the real memory segment corresponding to the old segment is deleted, as well as the address mapping relationship of the invalid data stored in the real memory segment corresponding to the old segment is deleted.

[0099] It should be noted that Figure 5 In the system, the address mapping relationship of valid data stored in the real memory segment corresponding to the old segment and the address mapping relationship of invalid data stored in the real memory segment corresponding to the old segment are called old address mapping.

[0100] Step 202: The electronic device performs a memory recycling operation on the invalid data in the real memory segment.

[0101] Optionally, in an embodiment of the present application, the electronic device may delete invalid data in the real memory segment corresponding to the second virtual memory segment through UFS.

[0102] In the memory recovery method provided in an embodiment of the present application, when a memory recovery request is detected, a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment can be established, and then, a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment are deleted; the real memory segment corresponding to the first memory segment contains valid data and invalid data; the first physical address is the physical address of valid data, the second physical address is the physical address of invalid data, and the first virtual memory segment is an idle virtual memory segment; finally, a recovery operation is performed on the invalid data in the real memory segment. In this solution, when a memory reclamation request is detected, a first address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the first virtual memory segment can be established, and a third address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the second virtual memory segment can be deleted; therefore, by only changing the address mapping relationship, the second virtual memory segment can be released, and then memory reclamation can be performed, without the need for multiple rounds of data reading and writing, thereby improving the speed of memory reclamation and further improving the memory reclamation performance of the electronic device; and no data is written in the UFS, which improves the service life of the UFS; and there is no need for temporary storage of data, so there is no need to use LPDDR, thereby reducing the power consumption of the electronic device.

[0103] Optionally, in the embodiment of the present application, Figure 4 ,like Figure 6 As shown, the "electronic device establishes an address mapping relationship between the first physical address and the first logical address of the first virtual memory segment" in the above step 201 can be specifically implemented through the following step 201a.

[0104] Step 201a: When the first virtual memory segment and the second virtual memory segment meet a first condition, the electronic device establishes a first address mapping relationship.

[0105] In an embodiment of the present application, the above-mentioned first condition includes at least one of the following: the memory space sizes of the first virtual memory segment and the second virtual memory segment are both greater than a first predetermined threshold, the logical address of the first virtual memory segment and the logical address of the second virtual memory segment do not overlap, and the memory size of the first virtual memory segment and the memory size of the second virtual memory segment are the same.

[0106] Optionally, in an embodiment of the present application, the first preset threshold may be a fixed value, such as 100K, or the first preset threshold may be a numerical range, such as 0K-100K.

[0107] Optionally, in the embodiment of the present application, the first predetermined threshold may be preset by the electronic device; or the first predetermined threshold may be user-defined. The specific value may be determined based on actual use requirements and is not limited in the embodiment of the present application.

[0108] Optionally, in an embodiment of the present application, the above-mentioned first address mapping relationship may be one or more.

[0109] It can be understood that there are as many first address mapping relationships as there are valid data in the real memory segment.

[0110] For example, assuming that there are 5 valid data in the real memory segment, there are 5 first address mapping relationships.

[0111] Optionally, in an embodiment of the present application, the CPU in the electronic device can find the address offset corresponding to the valid data by querying the stored address offset table, and then add the logical address in the second virtual memory segment corresponding to the valid data to the address offset to obtain the physical address corresponding to the valid data, and then associate the logical address in the first virtual memory segment with the physical address corresponding to the valid data for storage, thereby establishing a first address mapping relationship.

[0112] Optionally, in an embodiment of the present application, the CPU in the electronic device can establish a first address mapping relationship by querying the physical address corresponding to the valid data stored in the data address mapping table, and then associating and storing the logical address in the first virtual memory segment with the physical address corresponding to the valid data.

[0113] For example, Figure 7A As shown, assuming that there is a mapping between logical address 1 and physical address 1, assuming that logical address 1 is the logical address in the second virtual memory segment corresponding to the valid data, logical address 2 is the logical address of the first virtual memory segment, and physical address 1 is the physical address corresponding to the valid data, when the first virtual memory segment and the second virtual memory segment meet the first condition, as shown in FIG. Figure 7B As shown, the UFS in the electronic device will delete the mapping between logical address 1 and physical address 1, and add a mapping between logical address 2 and physical address 1.

[0114] For example, Figure 8 As shown, the following specifically explains "the first virtual memory segment and the second virtual memory segment satisfying the first condition" in the above step 201a, which can be specifically implemented through the following steps 30 to 32.

[0115] Step 30: The SOC in the electronic device detects that the memory size of the old segment and the memory size of the new segment are less than or equal to 0K and less than or equal to 100K.

[0116] Step 31: The SOC in the electronic device detects that the logical address of the old segment does not overlap with the logical address of the new segment.

[0117] Step 32: The SOC in the electronic device detects that the memory size of the old segment is the same as the memory size of the new segment.

[0118] In this way, the electronic device can verify the first virtual memory segment and the second virtual memory segment by detecting whether the first virtual memory segment and the second virtual memory segment meet the first condition, thereby determining the validity of the first virtual memory segment and the second virtual memory segment.

[0119] Optionally, in the embodiment of the present application, Figure 4 ,like Figure 9 As shown, after the above step 201, the memory recycling method provided in the embodiment of the present application further includes the following step 301.

[0120] Step 301: The electronic device adds a first address mapping relationship to a data address mapping table.

[0121] Optionally, in the embodiment of the present application, the storage structure of the data address mapping table may be a data structure or a collection structure, which may be determined based on actual use requirements and is not limited in the embodiment of the present application.

[0122] It can be understood that in the case where there are multiple first address mapping relationships, each of the multiple first address mapping relationships must be added to the data address mapping table.

[0123] Optionally, in an embodiment of the present application, the electronic device may directly add the first address mapping relationship to the header or footer of the data address mapping table.

[0124] Exemplarily, the UFS in the electronic device may add the first address mapping relationship to the header of the data address mapping table through a write operation.

[0125] Optionally, in an embodiment of the present application, the electronic device may find the third address mapping relationship in the data address mapping table according to the logical address of the second virtual memory segment corresponding to the valid data, and then replace the third address mapping relationship with the first address mapping relationship.

[0126] In an embodiment of the present application, by adding the first address mapping relationship to the data address mapping table, the electronic device can directly find the physical address of the valid data in the real memory segment through the data address mapping table when searching for valid data, without having to search for the valid data in the real memory segment by adding the logical address and the address offset, thereby improving the efficiency of the electronic device in searching for valid data.

[0127] Optionally, in an embodiment of the present application, after the UFS in the electronic device establishes the above-mentioned first mapping relationship, the UFS may send a second message to the SOC, where the second message is used to indicate that the first mapping relationship has been established; then after receiving the second message, the SOC may send a first address mapping deletion command to the UFS to instruct the UFS to delete the third address mapping relationship.

[0128] Optionally, in an embodiment of the present application, the first address mapping deletion command may carry a logical address of the second virtual memory segment corresponding to valid data.

[0129] Optionally, in the embodiment of the present application, Figure 4 ,like Figure 10 As shown, the "deletion of the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment" in the above step 201 can be specifically implemented through the following step 201b.

[0130] Step 201b: The electronic device deletes the third address mapping relationship stored in the data address mapping table based on the first address mapping deletion command.

[0131] In an embodiment of the present application, the above-mentioned first address mapping deletion command includes a first identifier, which is used to indicate the deletion of the third address mapping relationship. The above-mentioned data address mapping table includes the address mapping relationship between the physical address and the logical address of the data of the real memory segment corresponding to the virtual memory segment in the virtual memory space. The virtual memory space includes a first virtual memory segment and a second virtual memory segment.

[0132] Optionally, in an embodiment of the present application, the third address mapping relationship may be one or more.

[0133] It can be understood that there are as many third address mapping relationships as there are valid data in the real memory segment.

[0134] For example, assuming that there are 5 valid data in the real memory segment, there are 5 third address mapping relationships.

[0135] In an embodiment of the present application, the UFS in the electronic device can search the third address mapping relationship from the data address mapping table through the first identifier in the first address mapping deletion command and the logical address of the second virtual memory segment corresponding to the valid data, and then delete the third address mapping relationship stored in the data address mapping table.

[0136] Exemplarily, the first address mapping deletion command may be a discard command.

[0137] It should be noted that the first address mapping deletion command provided in the embodiment of the present application is only used in memory recovery scenarios.

[0138] Optionally, in the embodiment of the present application, the first identifier may be any one of the following: a digital identifier, a text identifier, a special symbol identifier, etc. The specific identifier may be determined according to actual use requirements and is not limited in the embodiment of the present application.

[0139] It should be noted that the first identifier is used to distinguish between the discard command for memory recycling, namely the first address mapping deletion command, and the discard command for data deletion. The discard command for memory recycling only deletes the address mapping relationship in the data address mapping table and does not need to invalidate the valid data because the data is pointed to the logical address in the new segment and the valid data remains valid. The discard command for data deletion, on the other hand, not only deletes the mapping relationship but also invalidates the valid data to wait for UFS automatic erasure. This applies to all scenarios except memory recycling.

[0140] For example, Figure 11 As shown, the first address mapping deletion command may include: 8 bits, the size of the first address mapping deletion command may be 10 bits, the 8th bit of the 8 bits may be the most significant bit (MSB). The first bit of the 8 bits may be the least significant bit (LSB), and the second bit of the 8 bits may be the above-mentioned first identifier. Figure 10 Indicated by GCFLAG; the operation code of the first address mapping delete command is: OPERATION COD (42h), the function of the first address mapping delete command is expressed as: ANCHOR = 0b, the group number of the first address mapping delete command is: GROUP NUMBER = 0000b, and the control bit of the first address mapping delete command is: CONTROL = 00h.

[0141] In an embodiment of the present application, the electronic device can delete the original third address mapping relationship to avoid data conflicts caused by the physical address of the valid data corresponding to multiple address mapping relationships when searching for valid data, thereby improving the accuracy of the electronic device in searching for valid data.

[0142] Optionally, in an embodiment of the present application, after the UFS in the electronic device establishes the above-mentioned first mapping relationship, the UFS may send a second message to the SOC, where the second message is used to indicate that the first mapping relationship has been established; then, after receiving the second message, the SOC may send a second address mapping deletion command to the UFS to instruct the UFS to delete the second address mapping relationship.

[0143] Optionally, in an embodiment of the present application, the second address mapping deletion command may carry a logical address stored in the first memory segment corresponding to the invalid data.

[0144] It can be understood that the second address mapping deletion command does not include the first identifier.

[0145] Optionally, in the embodiment of the present application, Figure 4 ,like Figure 12 As shown, the "deletion of the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment" in the above step 201 can be specifically implemented through the following step 201c.

[0146] Step 201c: The electronic device deletes the second address mapping relationship stored in the data address mapping table based on the second address mapping deletion command.

[0147] Optionally, in an embodiment of the present application, the above-mentioned second address mapping relationship may be one or more.

[0148] It can be understood that there are as many second address mapping relationships as there are invalid data in the real memory segment.

[0149] Exemplarily, assuming that there are 4 invalid data in the real memory segment, there are 4 second address mapping relationships.

[0150] In the embodiment of the present application, the UFS in the electronic device can delete the second address mapping relationship stored in the data address mapping table through a second address mapping deletion command.

[0151] For example, the UFS in the electronic device can find the second address mapping relationship stored in the address mapping table in the data address mapping table according to the second address mapping deletion command and the logical address of the second virtual memory segment corresponding to the invalid data, and then delete the second address mapping relationship.

[0152] Optionally, in an embodiment of the present application, after deleting the second address mapping relationship, the UFS in the electronic device may send a third message to the SOC, where the third message is used to instruct the UFS to delete the second address mapping relationship; at this time, the SOC may update the metadata corresponding to the first virtual memory segment and the second virtual memory segment stored in the F2FS.

[0153] Optionally, in the embodiment of the present application, the metadata may include at least one of the following: descriptive metadata, structural metadata, and management metadata, which may be determined based on actual usage requirements and are not limited in the embodiment of the present application.

[0154] Exemplarily, the above-mentioned descriptive metadata is used to describe basic characteristics of the memory segment, and the basic characteristics may include: the name and purpose of the memory segment.

[0155] Exemplarily, the structural metadata is used to describe the structure and layout of the memory segment, such as size and address range.

[0156] Exemplarily, the management metadata is used to manage and control the use of memory segments, such as access rights and life cycle.

[0157] For example, the technical metadata is used to describe technical details of the memory segment, such as data type and data format.

[0158] In an embodiment of the present application, the electronic device can release the second virtual memory segment by deleting the second address mapping relationship stored in the data address mapping table through the second address mapping deletion command, without the need for multiple rounds of data reading and writing, thereby improving the speed of memory recovery.

[0159] For example, Figure 13 As shown, the memory recycling method provided in the embodiment of the present application is specifically described below with an example, which can be implemented through the following steps 40 to 52.

[0160] Step 40: The SOC selects an old segment for recycling from the virtual memory space and obtains the logical address of the old segment corresponding to the valid data.

[0161] Step 41: The SOC selects a new segment from the virtual memory space for data migration, and obtains the address quantity of a logical address that is the same as the address quantity of the logical address of the old segment corresponding to the valid data.

[0162] Step 42: The SOC summarizes the logical address of the old segment, the logical address of the new segment, and the data volume, and verifies the old segment and the new segment.

[0163] In the embodiment of the present application, the above-mentioned data volume includes the logical addresses corresponding to the valid data and the logical addresses corresponding to the new segment and the old segment, as well as the logical addresses of the invalid data.

[0164] Step 43: After the SOC verification is completed, a first message is sent to the UFS.

[0165] In an embodiment of the present application, the above-mentioned first message includes the logical address of the old segment, the logical address of the new segment and the data volume.

[0166] Step 44: The UFS receives the first message sent by the SOC.

[0167] Step 45: The UFS searches the data address mapping table for a third address mapping relationship based on the logical address corresponding to the valid data, and searches the data address mapping table for a second address mapping relationship based on the logical address corresponding to the invalid data.

[0168] Step 46: The UFS establishes a first address mapping relationship between the logical address in the new segment and the physical address of the valid data, and adds the first address mapping relationship to the data address mapping table.

[0169] Step 47: The UFS sends a second message to the SOC.

[0170] Step 48: The SOC receives the second message sent by the UFS, and sends a first address mapping deletion command and a second address mapping deletion command to the UFS in sequence.

[0171] Step 49: The UFS receives the first address mapping deletion command sent by the SOC and deletes the third address mapping relationship.

[0172] Step 50: The UFS receives the second address mapping deletion command sent by the SOC, deletes the second address mapping relationship, and deletes invalid data in the real memory segment corresponding to the first memory segment.

[0173] Step 51: The UFS sends a third message to the SOC.

[0174] Step 52: The SOC receives the third message sent by the UFS, and updates the metadata of the new segment and the old segment stored in the F2FS.

[0175] In an embodiment of the present application, when a memory recovery request is detected, a first address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the first virtual memory segment can be established, and a third address mapping relationship between the physical address of valid data in the real memory segment and the logical address of the second virtual memory segment can be deleted; therefore, by only changing the address mapping relationship, the second virtual memory segment can be released, and then memory recovery can be performed, without the need for multiple rounds of data reading and writing, thereby improving the speed of memory recovery and further improving the memory recovery performance of the electronic device; and no data is written in the UFS, which improves the service life of the UFS; and there is no need for temporary storage of data, so there is no need to use LPDDR, thereby reducing the power consumption of the electronic device.

[0176] The above-mentioned method embodiments, or various possible implementation methods in each method embodiment, can be executed separately, or, under the premise that there is no contradiction, can also be executed in combination with each other. The specific implementation can be determined according to actual usage requirements, and the embodiments of the present application do not limit this.

[0177] It should be noted that the memory recovery method provided in the embodiment of the present application can be executed by a memory recovery device. In the embodiment of the present application, the memory recovery device executing the memory recovery method is taken as an example to illustrate the memory recovery device provided in the embodiment of the present application.

[0178] Figure 14 FIG. 1 shows a possible structural diagram of a memory recycling device involved in an embodiment of the present application. Figure 14 As shown, the memory recycling device 70 may include: a creation module 71 , a deletion module 72 and a recycling module 73 .

[0179] Among them, the establishment module 71 is used to establish a first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment when a memory recovery request is detected. The deletion module 72 is used to delete the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment and the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment; the real memory segment corresponding to the second virtual memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment. The recovery module 73 is used to perform memory recovery operations on invalid data in the real memory segment.

[0180] In a possible implementation, the establishing module 71 is specifically configured to establish a first address mapping relationship when the first virtual memory segment and the second virtual memory segment meet a first condition;

[0181] Among them, the first condition includes at least one of the following: the memory space sizes of the first virtual memory segment and the second virtual memory segment are both greater than a first predetermined threshold, the logical address of the first virtual memory segment and the logical address of the second virtual memory segment do not overlap, and the memory size of the first virtual memory segment and the memory size of the second virtual memory segment are the same.

[0182] In a possible implementation, the deletion module 72 is specifically configured to delete the third address mapping relationship stored in the data address mapping table based on the first address mapping deletion command;

[0183] The data address mapping table includes an address mapping relationship between a physical address and a logical address of data in a real memory segment corresponding to a virtual memory segment in a virtual memory space, and the virtual memory space includes a first virtual memory segment and a second virtual memory segment.

[0184] In one possible implementation, combining Figure 14 ,like Figure 15As shown, the data recovery device 70 provided in the embodiment of the present application further includes an adding module 74. The adding module 74 is configured to add the first address mapping relationship to the data address mapping table after the address mapping relationship between the first physical address and the first logical address of the first virtual memory segment is established by the establishing module 71.

[0185] In a possible implementation, the deletion module 72 is specifically configured to delete the second address mapping relationship stored in the data address mapping table based on the second address mapping deletion command.

[0186] An embodiment of the present application provides a memory recovery device. When a memory recovery request is detected, a first address mapping relationship between the physical address of valid data in a real memory segment and the logical address of a first virtual memory segment can be established, and a third address mapping relationship between the physical address of valid data in the real memory segment and the logical address of a second virtual memory segment can be deleted. Therefore, by only changing the address mapping relationship, the second virtual memory segment can be released, and then memory recovery can be performed, without the need for multiple rounds of data reading and writing, thereby improving the speed of memory recovery and further improving the memory recovery performance of the memory recovery device. Moreover, no data is written in the UFS, which improves the service life of the UFS. There is no need to temporarily store data, so there is no need to use LPDDR, thereby reducing the power consumption of the memory recovery device.

[0187] The memory recovery device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a laptop computer, a palmtop computer, an in-vehicle electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

[0188] The memory recovery device in the embodiment of the present application can be a device having an operating system. The operating system can be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0189] The memory recovery device provided in the embodiment of the present application can implement each process implemented in the above embodiment. To avoid repetition, it will not be described here.

[0190] Alternatively, as Figure 16 As shown, an embodiment of the present application also provides an electronic device 90, including a processor 91 and a memory 92, wherein the memory 92 stores a program or instruction that can be run on the processor 91. When the program or instruction is executed by the processor 91, the various steps of the above-mentioned memory recovery method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0191] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0192] Figure 17 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0193] The electronic device 100 includes but is not limited to components such as a radio frequency unit 101 , a network module 102 , an audio output unit 103 , an input unit 104 , a sensor 105 , a display unit 106 , a user input unit 107 , an interface unit 108 , a memory 109 , and a processor 110 .

[0194] Those skilled in the art will understand that the electronic device 100 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 110 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 17 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0195] Among them, the processor 110 is used to establish a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment, and delete a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment, and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment, when a memory reclamation request is detected; the real memory segment corresponding to the first memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment; and perform a memory reclamation operation on the invalid data in the real memory segment.

[0196] Optionally, in an embodiment of the present application, the above-mentioned processor 110 is specifically used to establish a first address mapping relationship when the first virtual memory segment and the second virtual memory segment meet a first condition; wherein the first condition includes at least one of the following: the memory space sizes of the first virtual memory segment and the second virtual memory segment are both greater than a first predetermined threshold, the logical address of the first virtual memory segment and the logical address of the second virtual memory segment have no overlap, and the memory size of the first virtual memory segment is the same as the memory size of the second virtual memory segment.

[0197] Optionally, in an embodiment of the present application, the above-mentioned processor 110 is specifically used to delete the third address mapping relationship stored in the data address mapping table based on the first address mapping deletion command; wherein, the data address mapping table includes the address mapping relationship between the physical address and the logical address of the data of the real memory segment corresponding to the virtual memory segment in the virtual memory space, and the virtual memory space includes a first virtual memory segment and a second virtual memory segment.

[0198] Optionally, in an embodiment of the present application, the processor 110 is further configured to establish a first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment, and then add the first address mapping relationship to the data address mapping table.

[0199] Optionally, in an embodiment of the present application, the processor 110 is specifically configured to delete the second address mapping relationship stored in the data address mapping table based on a second address mapping deletion command.

[0200] An embodiment of the present application provides an electronic device. When a memory reclamation request is detected, a first address mapping relationship between the physical address of valid data in a real memory segment and the logical address of a first virtual memory segment can be established, and a third address mapping relationship between the physical address of valid data in the real memory segment and the logical address of a second virtual memory segment can be deleted. Therefore, by only changing the address mapping relationship, the second virtual memory segment can be released and then memory reclamation can be performed without the need for multiple rounds of data reading and writing, thereby improving the speed of memory reclamation and further improving the memory reclamation performance of the electronic device. Moreover, no data is written in the UFS, thereby improving the service life of the UFS. Moreover, there is no need to temporarily store data, so there is no need to use LPDDR, thereby reducing the power consumption of the electronic device.

[0201] The electronic device provided in the embodiment of the present application can implement each process implemented in the above method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0202] The beneficial effects of various implementations in this embodiment can be specifically referred to the beneficial effects of the corresponding implementations in the above method embodiment. To avoid repetition, they will not be described here.

[0203] It should be understood that in an embodiment of the present application, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042, and the graphics processor 1041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 107 includes a touch panel 1071 and at least one of other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts: a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here.

[0204] The memory 109 can be used to store software programs and various data. The memory 109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, applications or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 109 may include a volatile memory or a non-volatile memory, or the memory 109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0205] Processor 110 may include one or more processing units. Optionally, processor 110 integrates an application processor and a modem processor. The application processor primarily handles operations related to the operating system, user interface, and application programs, while the modem processor primarily processes wireless communication signals, such as a baseband processor. It is understood that the modem processor may not be integrated into processor 110.

[0206] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0207] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0208] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0209] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0210] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned memory recovery method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0211] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0212] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0213] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A memory recovery method, characterized in that: The method comprises: In the case where a memory reclaim request is detected, a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment is established, and a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment are deleted; the real memory segment corresponding to the second virtual memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment; A memory reclamation operation is performed on the invalid data in the real memory segment.

2. The method according to claim 1, characterized in that The establishing of a first address mapping relationship between the first physical address and the first virtual memory segment includes: When the first virtual memory segment and the second virtual memory segment meet a first condition, establishing the first address mapping relationship; The first condition includes at least one of the following: the memory space sizes of the first virtual memory segment and the second virtual memory segment are both greater than a first predetermined threshold, the logical address of the first virtual memory segment and the logical address of the second virtual memory segment do not overlap, and the memory size of the first virtual memory segment and the memory size of the second virtual memory segment are the same.

3. The method according to claim 1 , wherein deleting the third address mapping relationship between the first physical address and the third logical address of the second virtual memory segment comprises: Deleting the third address mapping relationship stored in the data address mapping table based on the first address mapping deletion command; The data address mapping table includes an address mapping relationship between a physical address and a logical address of data in a real memory segment corresponding to a virtual memory segment in a virtual memory space, and the virtual memory space includes the first virtual memory segment and the second virtual memory segment.

4. The method according to claim 3, characterized in that After establishing the first address mapping relationship between the first physical address and the first logical address of the first virtual memory segment, the method further includes: Add the first address mapping relationship to the data address mapping table.

5. The method according to claim 1 or 3, characterized in that The deleting the second address mapping relationship between the second physical address and the second logical address of the second virtual memory segment includes: Based on the second address mapping deletion command, the second address mapping relationship stored in the data address mapping table is deleted.

6. A memory recovery device, characterized in that: The memory recovery device includes: a creation module, a deletion module and a recovery module; The establishing module is configured to establish a first address mapping relationship between a first physical address and a first logical address of a first virtual memory segment when a memory reclaim request is detected; The deletion module is configured to delete a second address mapping relationship between a second physical address and a second logical address of a second virtual memory segment, and a third address mapping relationship between the first physical address and a third logical address of the second virtual memory segment; the real memory segment corresponding to the second virtual memory segment contains valid data and invalid data; the first physical address is the physical address of the valid data, the second physical address is the physical address of the invalid data, and the first virtual memory segment is an idle virtual memory segment; The recycling module is used to perform a memory recycling operation on the invalid data in the real memory segment.

7. The device according to claim 6, characterized in that The establishing module is specifically configured to establish the first address mapping relationship when the first virtual memory segment and the second virtual memory segment meet a first condition; The first condition includes at least one of the following: the memory space sizes of the first virtual memory segment and the second virtual memory segment are both greater than a first predetermined threshold, the logical address of the first virtual memory segment and the logical address of the second virtual memory segment do not overlap, and the memory size of the first virtual memory segment and the memory size of the second virtual memory segment are the same.

8. The apparatus according to claim 6, wherein the deletion module is specifically configured to delete the third address mapping relationship stored in the data address mapping table based on the first address mapping deletion command; in, The data address mapping table includes an address mapping relationship between a physical address of data in a real memory segment corresponding to a virtual memory segment in a virtual memory space and a corresponding logical address, and the virtual memory space includes the first virtual memory segment and the second virtual memory segment.

9. The device according to claim 8, characterized in that The memory recycling device further includes an adding module; The adding module is configured to add the address mapping relationship between the first physical address and the first logical address of the first virtual memory segment to the data address mapping table after the establishing module establishes the address mapping relationship between the first physical address and the first logical address of the first virtual memory segment.

10. The device according to claim 6 or 8, characterized in that The deletion module is specifically configured to delete the second address mapping relationship stored in the data address mapping table based on a second address mapping deletion command.

11. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the memory recycling method as claimed in any one of claims 1 to 5.

12. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the memory recycling method according to any one of claims 1 to 5 are implemented.

13. A computer program product, characterized in that The computer program product is stored in a storage medium, and is executed by at least one processor to implement the memory recycling method according to any one of claims 1 to 5.

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