Hardware partition of cloud server

Abstract

To provide a system and a method for a hardware partition of a cloud server.SOLUTION: The system includes one or more processor cores including a managed processor core that executes instructions to divide at least a portion of the one or more processor cores into one or more partitions, and at least one distributed virtual memory (DVM) hub that obtains DVM messages from the processor cores, determines one or more recipient processor cores of the DVM messages, and provides the DVM messages to the determined recipient processor cores. The system also includes one or more interrupt interposers that are each associated with a processor core and that prevent interrupts originating from the associated processor core from being provided to processor cores that are outside of the partition of the associated processor core.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification relates generally to computing devices, and more particularly to hardware partitions of cloud servers. [Background technology]

[0002] Cloud computing involves network-based computing in which a collection of computing devices (e.g., servers, processing units, data storage devices) and software (e.g., computer programs, database tools) provide computational resources and data storage to remote end users. A cloud server typically includes hardware (e.g., processor devices, memory devices, IO devices, etc.) used to execute software running on the cloud server. Summary of the Invention

[0003] Disclosed herein are systems and methods for hardware partitioning of a cloud server. One aspect of the present disclosure includes a system. The system includes one or more processor cores. A first processor core of the one or more processor cores executes instructions to divide at least a portion of the one or more processor cores into one or more partitions. The system includes at least one distributed virtual memory (DVM) hub. The DVM hub receives a first DVM message from a second processor core of the one or more processor cores, the first DVM message including a processor core identifier of the second processor core. The DVM hub determines one or more recipient processor cores of the first DVM message based on the processor core identifier. The DVM hub provides the first DVM message to the identified one or more recipient processor cores. The system includes one or more interrupt interposers. Each interrupt interposer is associated with one processor core of the one or more processor cores, and the associated processor core belongs to one of the one or more partitions. Each interrupt interposer prevents a first interrupt originating from an associated processor core from being provided to a processor core outside the partition of the associated processor core.

[0004] Another aspect of the present disclosure includes a method. The method includes dividing one or more processor cores into one or more partitions. The method includes configuring at least one DVM hub to (1) obtain a first DVM message from a first processor core of the one or more processor cores, the first DVM message including a processor core identifier of the first processor core, and further configuring the at least one DVM hub to (2) determine one or more recipient processor cores of the first DVM message based on the processor core identifier of the first DVM message, and (3) provide the first DVM message to the identified one or more processor cores. The method includes configuring an interrupt interposer to be associated with a first processor core of the one or more processor cores. The first processor core belongs to a first partition. The method includes configuring the interrupt interposer to prevent a first interrupt originating from the first processor core from being provided to a processor core outside the first partition.

[0005] Another aspect of the present disclosure includes a non-transitory computer-readable storage medium containing instructions. When executed by a processing device, the instructions cause the processing device to perform operations. The operations include configuring at least one DVM hub to (1) obtain a first DVM message from a first processor core of the one or more processor cores, the first DVM message including a processor core identifier of the first processor core, and further configuring the at least one DVM hub to (2) determine one or more recipient processor cores of the first DVM message based on the processor core identifier of the first DVM message, and (3) provide the first DVM message to the identified one or more processor cores. The operations include configuring an interrupt interposer to be associated with the first processor core of the one or more processor cores. The first processor core belongs to a first partition. The operations include preventing, at the interrupt interposer, a first interrupt originating from the first processor core from being provided to a processor core outside the first partition.

[0006] Aspects and embodiments of the present disclosure will be more fully understood from the following detailed description of various aspects and embodiments of the disclosure and from the accompanying drawings, which should not be construed to limit the disclosure to any particular aspect or embodiment, but are for purposes of illustration and understanding only. [Brief explanation of the drawings]

[0007] [Figure 1] 1 illustrates, in accordance with one or more embodiments, an exemplary computing device for a hardware partition of a cloud server in which some aspects of the present disclosure may be implemented. [Figure 2] 1 illustrates, in accordance with one or more embodiments, an exemplary computing device for a hardware partition of a cloud server in which certain components are divided into multiple partitions and in which some aspects of the present disclosure may be implemented. [Figure 3] 1 illustrates, in accordance with one or more embodiments, a portion of an exemplary computing device for a hardware partition of a cloud server in which some aspects of the present disclosure may be implemented. [Figure 4] 1 shows a flowchart illustrating an exemplary method for practicing some aspects of the present disclosure, according to one or more embodiments. [Figure 5] 1 shows a flowchart illustrating an exemplary method for practicing some aspects of the present disclosure, according to one or more embodiments. [Figure 6] 1 shows a flowchart illustrating an exemplary method for practicing some aspects of the present disclosure, according to one or more embodiments. [Figure 7] 1 illustrates a block diagram of an exemplary computing device capable of creating hardware partitions for cloud servers, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Cloud providers can offer cloud computing environments to customer end users. Cloud providers typically offer two types of cloud computing environments: bare metal cloud computing environments and virtual machine (VM) cloud computing environments. In a bare metal cloud environment, the cloud provider dedicates an entire cloud server to a customer end user. The customer end user can then use all of the cloud server's computing resources (e.g., processor devices, memory devices, input / output (IO) devices, etc.). A customer end user using a bare metal cloud environment does not share any of the computing resources with other customers of the cloud provider; however, the customer end user must typically pay for the entire cloud server even if the customer end user does not use all of the cloud server's computing resources.

[0009] In a VM cloud environment, a customer end user may select a desired computing resource configuration for a VM (e.g., number and type of processor devices, amount of memory, amount of storage capacity, type of IO devices, etc.), and the cloud provider may use a hypervisor to create and run the VM with the selected configuration. The hypervisor may run the VM on multiple cloud servers depending on the availability of computing resources. If the customer end user uses only a portion of the cloud server's hardware required by the VM, the VM may share the cloud server's computing resources with other customers' VMs, which may use the computing resources and be used as a vector for attacks against the customer end user's VM. Furthermore, VMs are managed by a hypervisor, which may use the computing resources of the cloud server(s) and be used as a vector for attacks against the customer end user's VM.

[0010] Aspects and embodiments of the present disclosure address the above deficiencies by, among other things, providing a cloud computing system that statically partitions the computing resources of a cloud server, such that a customer end user uses only the computing resources it requests (unlike a bare-metal cloud environment), and different cloud provider customers do not use the same computing resources or hypervisors (unlike a VM cloud environment). The system may include multiple processor cores. For example, one of the processor cores, such as a management core, may execute instructions (e.g., firmware) that may partition at least some of the other processor cores into one or more partitions. The instructions may configure the processor cores such that the processor cores cannot communicate with or cause actions to be performed on processor cores outside of their respective partitions.

[0011] In some embodiments, the system includes at least one distributed virtual memory (DVM) hub. The DVM hub can obtain a DVM message (e.g., a transaction lookaside buffer (TLB) invalidation instruction) from a processor core, and the DVM message may include a processor core identifier that identifies which processor core generated or sent the DVM message. The DVM hub can determine one or more recipient processor cores of the DVM message based on the processor core identifier of the DVM message. The recipient processor core(s) may include processor core(s) that belong to the same partition as the processor core that generated or sent the DVM message. The DVM hub can provide the DVM message to those recipient processor core(s). The DVM hub can perform one or more preventative actions associated with the DVM message.

[0012] In some embodiments, the system includes one or more interrupt interposers. The interrupt interposers can be associated with processor cores. The interposers can prevent interrupts originating from the associated processor cores from being provided to processor cores outside the partition to which the associated processor core belongs. The system can include other components that prevent components of one partition from affecting other partitions. For example, instructions to partition a processor core can configure the processor core's system address map (SAM) so that the processor core can access only blocks of memory assigned to the partition to which the processor core belongs. The system may include instructions (e.g., firmware) that cause the processor core to emulate one or more IO devices such that there is logical separation of partitions with respect to the IO devices.

[0013] Some advantages of the present disclosure may result from or provide technical effects resulting from a technical solution to a technical problem. For example, one technical problem may relate to inefficient use of computing resources resulting from a bare-metal cloud environment in which a customer end user is allocated an entire cloud server but may not use all of the cloud server's computing resources. One technical solution to the technical problem may include using a system disclosed herein in which computing resources are partitioned for efficient use by different customer end users. As a result, wasted computing resources are reduced or eliminated. One technical problem may relate to a hypervisor using computing resources that would otherwise be used by the customer end user's software. One technical solution to the technical problem may include a system disclosed herein that does not use a hypervisor and allows the customer end user to use the computing resources. As a result, computing resources used by the customer end user instead of the cloud provider increase. Another technical problem may relate to security vulnerabilities in the hypervisor or processor cores, which can serve as a vector for attack. One technical solution to the technical problem may include a system as disclosed herein in which a hypervisor is not used and communications, interrupts, etc. from one partition are not prolonged or tolerated by other partitions. Consequently, such security vulnerabilities are reduced or eliminated.

[0014] 1 is a block diagram illustrating an exemplary computing device 100, according to some embodiments. The computing device 100 may include a computing device 100 used in a cloud computing system. For example, the computing device 100 may include a cloud server, a cloud system-on-chip (SoC), or any other computing device 100 that may be included in a cloud computing system.

[0015] A cloud computing system may include one or more computing devices (or portions of a cloud computing system) provided by a cloud provider to end users. End users may utilize portions of the cloud computing system to host content for use or access by other parties or to perform other computational tasks. In some implementations, the cloud computing system is configured to allow end users to use only portions of the computing device 100 (e.g., specific hardware, software, or other computer system resources). A cloud computing system may include a private cloud, a public cloud, or a hybrid cloud. A cloud computing system may provide Infrastructure as a Service (IaaS), Platform as a Service (PaaS), or Software as a Service (SaaS) computing. A cloud computing system may provide serverless computing.

[0016] In one embodiment, computing device 100 includes one or more processor cores 110A-110F. One or more of processor cores 110A-110F may include a respective system address map (SAM) 112A-112F. Computing device 100 may include one or more distributed virtual memory (DVM) hubs 114. Computing device 100 may include one or more interrupt interposers 116A-116N. Computing system 100 may include one or more memory devices 120A-120B. While the example computing device 100 of FIG. 1 includes six each of processor cores 110A-110F, SAMs 112A-112F, and interrupt interposers 116A-116F, computing device 100 may include other numbers of such components. Computing device 100 may include two or more DVM hubs 114. Computing system 100 may include other numbers of memory devices 120A-120B.

[0017] In some implementations, processor core 110 includes an electronic device that executes instructions. Processor core 110 may include an arithmetic logic unit (ALU) for performing calculations, a control unit for fetching and decoding instructions, or registers for temporary data storage. Processor core 110A can operate independently or in cooperation with other processor cores 110B-110F. Processor core 110 may also be referred to as a "processing element" or "PE."

[0018] In one embodiment, a first processor core 110A of the one or more processor cores 110A-110F includes instructions to divide at least a portion of the computing resources of computing device 100 into one or more partitions. The computing resources that may belong to a partition may include processor core 110, SAM 112, DVM hub 114, interrupt interposer 116, blocks of memory in memory device 120, or other computing resources. The first processor core 110A may include instructions to manage one or more partitions. The instructions may include firmware or other software. The first processor core 110A may be referred to as a “management core.”

[0019] In some implementations, instructions for partitioning one or more computing resources of computing device 100 may execute on an electronic device separate from computing device 100. The separate electronic device may be dedicated to partitioning one or more processor cores 110A-110F and managing one or more partitions. The instructions may execute on a microcontroller located on computing device 100 or in data communication with components of computing device 100.

[0020] In one or more embodiments, as used herein, a "partition" refers to a collection of computing resources configured by instruction of a management core to not affect computing resources of other partitions and / or to not be affected by communications from computing resources of other partitions. In one or more embodiments, a computing resource belongs to only one partition.

[0021] In one embodiment, DVM hub 114 may not belong to a partition. However, dividing at least a portion of computing resources of computing device 100 into one or more partitions may include configuring one or more processor cores 110A-110F to provide DVM messages to DVM hub 114. If computing device 100 includes multiple DVM hubs 114, configuring one or more processor cores 110A-110F to provide DVM messages to DVM hub 114 may include configuring each processor core 110A-110F to provide DVM messages to a particular DVM hub 114 (e.g., configuring processor cores 110B-110D to provide DVM messages generated by processor cores 110B-110D to a first DVM hub 114 and configuring processor cores 110E-110F to provide DVM messages generated by processor cores 110E-110F to a second DVM hub 114).

[0022] In some implementations, management core 110A partitions one or more processor cores 110A-110F in response to receiving commands, instructions, etc. from a management computing device of the cloud computing system. The management computing device may include a cloud management computing device, a hypervisor, or some other management computing device of the cloud computing system. The management computing device may provide the commands, instructions, etc. in response to an end user of the cloud computing system requesting cloud computing resources. The commands, instructions, etc. may include data specifying the configuration of the requested partition (e.g., number of processor cores 110, type of processor cores 110, processing capabilities, etc., amount of memory, amount of storage, etc.).

[0023] In one or more embodiments, the management core 110A is further configured to terminate a partition. The management core 110A can terminate a partition in response to receiving a command, instruction, etc. from the managing computing device. Terminating a partition may include rebooting components of the partition. Rebooting components of a partition may include returning the components to a state as if the computing device 100 had been rebooted. For example, rebooting the processor core 110 may include clearing one or more caches or registers, the SAM 112, or other components of the processor core 110. Rebooting the DVM hub 114 or the interrupt interposer 116 may include clearing data from such components. Rebooting a block of memory allocated to a partition may include clearing the block of memory (e.g., overwriting the block of memory with null or garbage values, etc.). The rebooted components of the partition can then be used as components in one or more other partitions (e.g., newly created partitions).

[0024] In some embodiments, processor core 110A on which instructions that divide one or more components of computing device 100 into one or more partitions execute includes processor core 110 dedicated to executing such instructions. Processor core 110A may not form part of any partition. In one or more embodiments, processor core 110A dedicated to executing instructions does not include an associated DVM hub 114 or interrupt interposer 116A. In some embodiments, a managing computing device of a cloud computing system selects a processor core 110 that is not currently in use or currently part of a partition as the processor core on which to execute the instructions.

[0025] In one embodiment, computing device 100 includes one or more SAMs 112A-112F. For example, as seen in FIG. 1, each processor core 110A-110F may include a respective SAM 112A-112F. SAM 112 may include one or more entries, each of which may include a block of memory and a corresponding channel of a mesh interconnect, which may lead to a memory block. Further details regarding SAMs 112A-112F are described below with respect to FIG. 2.

[0026] Computing device 100 may include one or more DVM hubs 114. DVM may include a memory management technique used in multiprocessor systems (such as computing device 100) to efficiently and transparently manage memory across multiple processor cores 110A-110F. DVM can create an abstraction of a single, unified memory space accessible to multiple processors, even if the physical memory is physically distributed across different locations (e.g., across memory devices 120A-120B). In some implementations, a first processor core 110B sends DVM messages (sometimes referred to as “DVM operations” or “transactions”) that are received by the other processor core 110C to maintain the DVM of computing device 100. DVM hub 114 may include a component located between two of the one or more processor cores 110A-110F. In one embodiment, management core 110A obtains DVM messages from processor cores 110, determines which other processor cores 110 need to receive the DVM messages, and configures DVM hubs 114 to provide the DVM messages to those processor cores 110. Management core 110A may configure one or more DVM hubs 114 to perform proactive actions associated with the DVM messages. More information regarding one or more DVM hubs 114 is provided further below.

[0027] The computing device 100 may include one or more interrupt interposers 116A-116F. The interrupt interposer 116B may include components disposed between an associated processor core 110B and the other processor cores 110A, 110C-110F of one or more processor cores 110A-110F. The management core 110A may configure the interrupt interposer 116B to prevent a first interrupt originating from the associated processor core 110B from being provided to a processor core 110A, 110C-110F that is outside the partition of the associated processor core 110B. The interrupt may include a request to pause code currently being executed by the processor core 110B to process an event. The interrupt may include a hardware interrupt or a software interrupt (e.g., a software-generated interrupt (SGI)). More information regarding the interrupt interposers 116A-116F is described further below.

[0028] In one embodiment, memory device 120 may include a data storage device capable of storing data for use by at least some of one or more processor cores 110A-110F of computing device 100. Memory device 120 may include random access memory (RAM) or some other type of volatile data storage. In some embodiments, computing device 100 may include other types of computing resources (e.g., non-volatile data storage, IO devices, or other types of computing resources) that management core 110A may allocate (or allocate portions of) to partitions.

[0029] FIG. 2 illustrates an exemplary computing device 100 partitioned by firmware of the management core 110A. The firmware for processor core 110A can divide the remaining processor cores 110B-110F into three partitions 202A-202C: (1) a first partition 202A including processor cores 110B-110C, interrupt interposers 116B-116C, and blocks of memory 0x00000000-0x37FFFFFF of memory in memory device 120A; (2) a second partition 202B including processor core 110D, interrupt interposer 116D, and blocks of memory 0x38000000-0x6FFFFFFFF of memory in memory device 120A; and (3) a third partition 202C including processor cores 110E-110F, interrupt interposers 116E-116F, and blocks of memory 0x70000000-0xDFFFFFFF of memory in memory device 120A. Although DVM hub 114 may not belong to a partition 202, management core 110A may configure DVM hub 114 to receive DVM messages from processor cores 110B-110F and provide DVM messages to recipient processor cores 110B-110F, as described below. Although computing device 100 of FIG. 2 includes three partitions 202A-202C having various numbers of processor cores 110B-110F and various sizes of memory blocks, computing device 100 may include other numbers of partitions 202, and partitions may have other numbers of processor cores 110, memory block sizes, or other component configurations.

[0030] As described above, the SAM 112 may include one or more entries, each of which can map a block of memory to a corresponding destination in the mesh interconnect. A destination may lead to a corresponding block of memory. For example, a first processor core 110A may access four blocks in a first memory device 120A. The SAM 112A of the processor core 110A may be as follows: [Table 1]

[0031] In some implementations, computing device 100 includes a mesh interconnect. The mesh interconnect may include one or more channels from one or more processor cores 110A-110F to one or more memory blocks of memory devices 120A-120B. A single processor core 110A may include multiple channels from processor core 110A to different memory blocks of memory devices 120A-120B. In some implementations, channels from different processor cores 110A-110F lead to the same block of memory.

[0032] In some implementations, the SAM 112 is associated with a partition 202 of one or more partitions 202A-220C. For example, as described above, each processor core of one or more processor cores 110A-110F may include a respective SAM 112. In other examples, a subset of one or more processor cores 110A-110F of a partition 202 may include a respective SAM 112. In some implementations, the SAM 112 is stored on a separate electronic device assigned to the associated partition 202.

[0033] The SAM 112 can restrict memory access to one or more blocks of physical address space allocated to the partition 202 associated with the SAM 112. The physical address space can refer to memory, memory-mapped IO devices, or any other component to which a physical address can refer. In one embodiment, the management core 110A, which divides the processor cores 110B-110F into one or more partitions 202A-202C, configures the SAMs 112B-112F to include only entries to the blocks of memory allocated to the partition 202 associated with the SAMs 112B-112F. For example, as described above, the first partition 202A may include the processor cores 110B-110C, the interrupt interposers 116B-116C, and blocks 0x00000000-0x37FFFFFF of memory in the memory device 120A. The management core 110A can delete from the SAMs 112B-112C any entry that includes a memory address outside the memory block 0x00000000-0x37FFFFFF.

[0034] In some embodiments, by removing entries from SAM 112 that reference portions of memory not allocated to a partition 202, processor cores 112A-112F assigned to that partition 202 cannot access portions of memory allocated to other partitions 202 and therefore cannot interfere with memory allocated to other partitions 202.

[0035] In one embodiment, the management core 110A's division of computing resources into one or more partitions 202A-202C includes the management core 110A configuring the processor cores 110B-110F and one or more DVM hubs 114. In a conventional computing device using DVM, when a processor core 110 sends a DVM message, the DVM message is received by all other processor cores 110 of the conventional computing device. However, in the case of a computing device 100 using one or more partitions 202, when a first processor core 110B sends a DVM message, the DVM message should not be received by processor cores 110 outside the partition 202 of the first processor core 110B. Therefore, the management core 110A can configure the processor cores 110B-110F and one or more DVM hubs 114, as described below, so that DVM messages are sent and received only within the same partition 202.

[0036] Management core 110A may assign each processor core 110B-110F to provide DVM messages generated by the respective processor cores 110B-110F to a particular DVM hub 114. In one example, if computing device 100 includes a single DVM hub 114, management core 110A may assign each processor core 110B-110F to provide its respective DVM messages to the single DVM hub 114. In another example, if computing device 100 includes two DVM hubs 114, management core 110A may assign processor cores 110B, 110D, and 110E to provide their respective DVM messages to a first DVM hub 114 and may assign processor cores 110C and 110F to provide their respective DVM messages to a second DVM hub 114. In some implementations, DVM hub 114 may be in data communication with each processor core 110A-F. In other implementations, DVM hub 114 may not be in data communication with one or more processor cores 110. Thus, to obtain a DVM message from or provide a DVM message to a particular processor core 110, DVM hub 114 may obtain a DVM message from or send a DVM message to another DVM hub 114 in data communication with processor core 110.

[0037] In some implementations, the DVM hub 114 obtains a DVM message from a processor core 110. The DVM message may include a processor core identifier of the processor core 110 that generated or sent the DVM message. The DVM hub 114 may determine one or more recipient processor cores 110 of the DVM message. The DVM hub 114 may determine the one or more recipient processor cores 110 based on the processor core identifier.

[0038] In one embodiment, DVM hub 114 includes a processor core partition map. The processor core partition map may include one or more entries, and each entry may include a processor core identifier and a corresponding partition. The corresponding partition may include the partition to which the processor core 110 identified by the corresponding processor core identifier belongs. As an example, the processor core partition map for computing device 100 of FIG. 2 may be as follows: [Table 2] Here, processor core identifier "0" identifies processor core 110A, processor core "1" identifies processor core 110B, processor core "2" identifies processor core 110C, processor core "3" identifies processor core 110D, processor core "4" identifies processor core 110E, processor core "5" identifies processor core 110F, partition "0" indicates that the corresponding processor core (in the example of Figure 2, processor core 110A) does not belong to a partition, partition "1" identifies partition 202A, partition "2" identifies partition 202B, and partition "3" identifies partition 202C.

[0039] In some embodiments, management core 110A, which executes instructions to divide one or more processor cores 110B-110F into one or more partitions 202A-202C, includes configuring a processor core partition map for DVM hub 114 that includes one or more entries. For example, management core 110A may generate a processor core partition map that includes entries indicating which processor cores 110B-110F belong to which partitions 202A-202C, and may provide the processor core partition map to DVM hub 114.

[0040] In one or more embodiments, the DVM hub 114 determining one or more recipient processor cores 110 of the DVM message based on the processor core identifier of the DVM message may include the DVM hub 114 identifying, from a processor core partition map and based on the processor core identifier, a partition to which the processor core identified by the processor core identifier belongs. For example, using the example processor core partition map above, the DVM hub 114 may receive a DVM message including a processor core identifier of “4” (indicating that the DVM message was sent by processor core 110E). The DVM hub 114 may find the processor core identifier “4” in the processor core identifier entry of the processor core partition map and identify the corresponding partition as “3” (i.e., partition 202C).

[0041] In one embodiment, the DVM hub 114 may then determine one or more recipient processor cores 110 of the DVM message. The DVM hub 114 may include a partition processor core map. The partition processor core map may include one or more entries, and each entry may include a partition 202 and one or more corresponding processor core identifiers. The corresponding processor core identifiers may include one or more identifiers of processor cores 110 that belong to the partition 202 identified by the corresponding partition. As an example, the partition map processor core for the computing device 100 of FIG. 2 may be as follows: [Table 3] Here, partition "1" identifies partition 202A, partition "2" identifies partition 202B, partition "3" identifies partition 202C, processor core "1" identifies processor core 110B, processor core "2" identifies processor core 110C, processor core "3" identifies processor core 110D, processor core "4" identifies processor core 110E, and processor core "5" identifies processor core 110F.

[0042] In some embodiments, the management core 110A's execution of the instructions to divide one or more processor cores 110B-110F into one or more partitions 202A-202C includes configuring a partition map processor core of the DVM hub 114 that includes one or more entries. For example, the management core 110A may generate a partition processor core map that includes entries indicating which processor cores 110B-110F belong to which partitions 202A-202C, and may provide the partition processor core map to the DVM hub 114.

[0043] In one or more embodiments, the DVM hub 114 determining one or more recipient processor cores 110 of the DVM message based on the processor core identifier of the DVM message may include the DVM hub 114 identifying, from a partition processor core map, one or more processor cores 110 that belong to a partition based on the partition identifier. Continuing the example, the DVM hub 114 may find an entry in the partition processor core map that identifies the partition as "3," and consequently, the DVM hub 114 identifies processor core identifiers "4" (processor core 110E) and "5" (processor core 110F). In one embodiment, the DVM hub 114 may determine one or more recipient processor cores 110 of the DVM message using functionality other than using the processor core partition and / or partition processor core map(s).

[0044] In some implementations, the DVM hub 114 does not determine the processor core 110 that sent the DVM message as one of the recipient processor cores 110. The DVM hub 114 may provide the DVM message to one or more identified recipient processor cores 110. For example, the DVM hub 114 may send the DVM message to each processor core 110 that is determined to be a recipient processor core 110.

[0045] In some embodiments, management core 110A may further configure DVM hub 114 to perform preventative actions associated with the DVM message. The preventative actions may include actions that help prevent the DVM message from being provided to processor core 110 outside the partition of the processor core 110 that generated the DVM message. The preventative actions may include sending a response to the processor core 110 that generated the DVM message.

[0046] In one or more embodiments, the DVM message includes a translation lookaside buffer (TLB) invalidation instruction. The processor core 110 may include a memory cache that stores recent translations of the DVM to physical memory, which may be referred to as a TLB. From time to time, a first processor core 110B interacting with the DVM may cause its own TLB or the TLBs of the other processor cores 110C-110F to expire. Thus, the first processor core 110B may send TLB invalidation instructions to the other processor cores 110C-110F to prevent the other processor cores 110C-110F from using expired data in their respective TLBs.

[0047] In one embodiment, the DVM hub 114 receives the TLB invalidation instruction. The DVM hub can determine the recipient processor core(s) 110, send the TLB invalidation instruction to the recipient processor core(s) 110, and perform preventative action. The preventative action can include the DVM hub 114 sending a completion response to the processor core 110 that sent the TLB invalidation instruction. The preventative action can include the DVM hub 114 not providing the TLB invalidation instruction to processor cores 110 outside the partition 202 of the processor core 110 that generated the TLB invalidation instruction.

[0048] In some implementations, the DVM message includes a cache invalidation instruction. The processor core 110 may include a memory cache that stores the contents of an external memory (e.g., a portion of the contents stored in the first memory device 120A). From time to time, the first processor core 110B interacting with the external memory may cause its own memory cache or the memory caches of the other processor cores 110C-110F to become outdated. Thus, the first processor core 110B may send cache invalidation instructions to the other processor cores 110C-110F to prevent the other processor cores 110C-110F from using outdated data in their respective caches.

[0049] In one embodiment, the DVM hub 114 receives the cache invalidation instruction. The DVM hub 114 can determine the recipient processor core(s) 110, send the cache invalidation instruction to the recipient processor core(s) 110, and take preventative action. The preventative action can include the DVM hub 114 sending a completion response to the processor core 110 that sent the cache invalidation instruction. The preventative action can include the DVM hub 114 not providing the cache invalidation instruction to processor cores 110 outside the partition 202 of the processor core 110 that generated the cache invalidation instruction.

[0050] In one or more embodiments, the DVM message includes a branch predictor disable instruction. The processor core 110 may include a branch predictor, which may include a component that attempts to predict the outcome of a branch instruction before executing the branch instruction. At times, the first processor core 110B may send a branch predictor disable instruction to the other processor cores 110C-110F so that the other processor cores 110C-110F do not use predictions generated by their respective branch predictors or so that other data associated with the branch predictors is invalidated.

[0051] In one embodiment, the DVM hub 114 receives the branch predictor disable instruction. The DVM hub 114 can determine the recipient processor core(s) 110, send the branch predictor disable instruction to the recipient processor core(s) 110, and perform preventative action. The preventative action can include the DVM hub 114 not providing the branch predictor disable instruction to processor cores 110 outside of the partition 202 of the processor core 110 that generated the branch predictor disable instruction.

[0052] In one or more embodiments, the DVM message includes a DVM synchronization instruction. The first processor core 110B may send the DVM synchronization instruction to the other processor core(s) 110C to determine whether a previously issued DVM operation has completed. In some embodiments, the DVM hub 114 receives the DVM synchronization instruction. The DVM hub 114 may determine the recipient processor core(s) 110, send the DVM synchronization instruction to the recipient processor core(s) 110, and perform proactive action. The proactive action may include the DVM hub 114 sending a completion response to the processor core 110 that sent the DVM synchronization instruction. The proactive action may include the DVM hub 114 not providing the DVM synchronization instruction to processor cores 110 outside the partition 202 of the processor core 110 that generated the branch predictor disable instruction.

[0053] In one embodiment, management core 110A configuring interrupt interposer 116 includes configuring interrupt interposer 116 to store a processor core identifier for each processor core 110 in the partition 202 to which the interrupt interposer 116 belongs. The processor core identifier may include data that uniquely identifies the associated processor core 110 among the other processor cores 110 of computing device 100. For example, interrupt interposer 116B of FIG. 2 may store a processor core identifier for processor core 110B and a processor core identifier for processor core 110C. In some embodiments, interrupt interposer 116B does not store the processor core identifier for processor core 110B associated with interrupt interposer 116B. The management core 110A can configure the interrupt interposer 116B to prevent interrupts generated by the processor core 110B or 110C from being provided to the processor cores 110A, 110D-110F that are outside the partition 202A to which the processor core 110B or 110C belongs.

[0054] FIG. 3 illustrates a portion of a computing device 100 including processor cores 110B-110F and interrupt interposers 116B-116F. The computing device 100 may further include one or more interrupt distribution units 302. The interrupt distribution unit 302 may include components that provide routing or priority configuration for interrupts. The computing device 100 may also include one or more interrupt redistribution units 304B-304F. The processor core 110B may be associated with the interrupt redistribution unit 304. The interrupt redistribution unit 304 may include components that manage the prioritization or delivery of interrupts to the processor core 110B, store configuration data related to the interrupts, or assist the associated processor core 110B with other interrupt-related functions. The interrupt interposer 116B may be disposed between the interrupt redistribution unit 304B and the associated processor core 110B. In one embodiment, the processor core 110B provides a first interrupt request to the interrupt interposer 116B. The interrupt interposer 116B can generate one or more second interrupt requests based on the first interrupt request to prevent the interrupt from being provided to a processor core 110C-110F outside the partition 202 to which the processor core 110B that provided the first interrupt request belongs. The interrupt interposer 116B can send the one or more second interrupt requests to the interrupt redistribution device 304B associated with the processor core 110B. For each second interrupt request, the interrupt redistribution device 304B can generate an interrupt based on the respective interrupt request, which can provide one or more interrupts to the interrupt redistribution device 302, which can route the one or more interrupts to one or more destination processor cores 110C-110F.

[0055] In one embodiment, the first interrupt comprises a broadcast interrupt. The broadcast interrupt may comprise an interrupt configured to be sent to all processor cores 110A-110F of the computing device 100, all processor cores 110A-110F in an affinity cluster of the computing device 100, or some other group of processor cores 110A-110F. Preventing the interrupt interposer 116B from providing the first interrupt originating from the associated processor core 110B to processor cores 110A-110F outside the partition 202A of the associated processor core 110B may include the interrupt interposer 116B generating an interrupt request directed to each processor core 110C in the partition 202A of the associated processor core 110B (the interrupt interposer 116B may not generate an interrupt request directed to the associated processor core 110B). Thus, the interrupt interposer 116B can replace the broadcast interrupt request with multiple interrupt requests, each of which can be configured to send a corresponding second interrupt to each processor core 110C in the partition 202A.

[0056] In some implementations, the first interrupt includes a non-broadcast interrupt. The non-broadcast interrupt may include an interrupt configured to be sent to a list of specific processor cores 110A-110F, and the interrupt may include the list of processor cores 110A-110F. Preventing the interrupt interposer 116B from providing the first interrupt originating from the associated processor core 110B to processor cores 110A-110F that are outside the partition 202A of the associated processor core 110B may include the interrupt interposer 116B removing, from the list of processor cores 110A-110F of the first interrupt request, a processor identifier that identifies a processor core 110A, 110D-110F that is not in the same partition 202A as the associated processor core 110B. Removing a processor core identifier from the list may include hiding the list against processor core identifiers of processor cores 110B-110C within partition 202A, filling the processor core identifiers of processor cores 110A, 110D-110F outside partition 202A in the list with zeros, or some other action.

[0057] In response to the interrupt interposer 116B generating one or more second interrupt requests, as described above, the interrupt interposer 116B can provide the second interrupt requests to an associated interrupt redistribution device 304B. The interrupt redistribution device 304B can generate one or more second interrupts such that the one or more second interrupts are provided to a destination one or more processor cores 110C-110F that belong to the same partition 202 as the associated processor core 110B. The interrupt redistribution device 304B can provide the one or more second interrupts to the interrupt distribution device 302, which can route the one or more second interrupts to their respective target processor cores 110C-110F.

[0058] In some embodiments, one or more processor cores 110A-110F include an IO processor core 110. IO processor core 110 can execute instructions to emulate one or more IO devices of computing device 100. In one embodiment, IO processor core 110 or management core 110A's execution of its respective instructions includes allocating one or more emulated IO devices to a partition 202 of one or more partitions 202A-202C. In this manner, each partition 202 may include a set of emulated IO devices that interact only with components of the partition 202 to which the emulated IO devices are allocated. IO processor cores 110 that emulate one or more emulated IO devices can be associated with different partitions 202A-202C to prevent data provided to or received from the emulated IO devices from being combined. The IO devices emulated by IO processor core 110 may include peripheral component interconnect (PCI) devices, memory management units (MMUs), interrupt distributors and redistributors, serial ports, clocks, power management interfaces, or any other IO devices. In some embodiments, management core 110A blocks some accesses to memory devices 120A-120B where the memory accesses are related to IO device functionality.

[0059] 4 is a flowchart illustrating one embodiment of a method 400 for hardware partitioning of a cloud server according to some implementations of the present disclosure. A processing device having one or more central processing units (CPU(s)), one or more graphics processing units (GPU(s)), and / or a memory device communicatively coupled to the one or more CPU(s) and / or GPU(s) may perform method 400 and / or one or more of the individual functions, routines, subroutines, or operations of method 400. In certain implementations, a single processing thread performs method 400. Alternatively, two or more processing threads may perform method 400, each thread performing one or more individual functions, routines, subroutines, or operations of the method. In illustrative examples, the processing threads performing method 400 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads performing method 400 may execute asynchronously with respect to one another. Various operations of method 400 may be performed in a different (e.g., reversed) order compared to the order shown in FIG. 4. Some operations of method 400 may be performed concurrently with other operations. Some operations may be optional. In some implementations, management core 110A performs one or more operations of method 400 by executing firmware or other instructions as described herein. In other implementations, a separate electronic device in data communication with computing device 100 performs one or more operations of method 400 as described herein.

[0060] At block 410, processing logic divides one or more processor cores 110B-110F into one or more partitions 202A-202C. Dividing the processor cores 110B-110F into one or more partitions 202A-202C may include instructions (e.g., firmware executing on the management core 110) configuring one or more processors 110B-110F for use in one or more partitions 202A-202C. For example, as described above, the instructions may cause one or more processor cores 110B-110F included in one or more partitions 202A-202C to reboot. As described above, the first processor core 110B may include a SAM 112B that includes one or more entries, and each entry may include a block of memory and a corresponding channel leading to the block of memory. Dividing one or more processor cores 110B-110F into one or more partitions 202A-202C may include configuring SAM 112B by removing one entry from the one or more entries if the removed entry includes a channel to a block of memory not allocated to the first partition 202A.

[0061] At block 420, processing logic configures the at least one DVM hub 114 to obtain a first DVM message from a first processor core 110B of the one or more processor cores 110B-110F. The first DVM message may include a processor core identifier of the first processor core 110B. The processing logic further configures the at least one DVM hub 114 to determine one or more recipient processor cores 110 of the first DVM message based on the processor core identifier of the first DVM message. The processing logic further configures the at least one DVM hub 114 to provide the first DVM message to the identified one or more recipient processor cores 110. For example, as described above, instructions (e.g., firmware executing on management core 110A) may include instructions to provide a processor core partition map to the DVM hub 114. The instructions may configure the DVM hub 114 to perform one or more preventative actions associated with the first DVM message.

[0062] At block 430, processing logic configures the interrupt interposer 116B to be associated with a first processor core 110B (e.g., a processor core 110 associated with the interrupt interposer 116B). Configuring the interrupt interposer 116B may include configuring the interrupt interposer 116B such that instructions (e.g., firmware executing on the management core 110A) prevent a first interrupt originating from the associated processor core 110B from being provided to processor cores 110D-110F that are outside the partition 202A of the associated processor core 110B. Configuring the interrupt interposer 116B may include the interrupt interposer 116B storing a processor core identifier for each processor core 110B-110C that is within the partition 202A to which the interrupt interposer 116B belongs.

[0063] At block 440, the processing logic configures the interrupt interposer 116B to prevent a first interrupt originating from the first processor core 110B from being provided to processor cores 110C-110F outside the first partition 202A. As described above, in the case of a broadcast interrupt, the interrupt interposer 116B can cause one or more second interrupts based on the first interrupt to be provided to each processor core 110B-110C in the first partition 202A. The interrupt interposer 116B can generate interrupt requests directed to each processor core 110C-110F in the partition 202A and provide the interrupt requests to the interrupt redistribution unit 304B to generate one or more corresponding second interrupts, and the interrupt redistribution unit 304B and the interrupt distribution unit 302 can route the second interrupts to the respective processor core 110C in the partition 202A as described above. In the case of a non-broadcast interrupt, the interrupt interposer 116B may remove from the list of processor cores 110B-110F of the interrupt request any processor core identifier that identifies a processor core 110A, 110D-110F that is not in the same partition 202A as the associated processor core 110B.

[0064] FIG. 5 is a flowchart illustrating one embodiment of a method 500 for operating DVM hub 114 in accordance with some implementations of the present disclosure. DVM hub 114 may perform method 500 and / or one or more of the individual functions, routines, subroutines, or operations of method 500. In certain implementations, a single processing thread executes method 500. Alternatively, two or more processing threads may execute method 500, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In illustrative examples, the processing threads executing method 500 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads executing method 500 may execute asynchronously with respect to one another. Various operations of method 500 may be executed in a different (e.g., reversed) order compared to the order shown in FIG. 5. Some operations of method 500 may be executed concurrently with other operations. Some operations may be optional.

[0065] At block 510, the DVM hub 114 obtains a DVM message processing configuration. The DVM message processing configuration may include instructions, configuration, or other data that can configure the DVM hub 114 to determine one or more recipient processor cores of the DVM message and send the DVM message to the recipient processor core(s) 110 or perform a preventative action associated with the DVM message. For example, obtaining the DVM message processing configuration may include obtaining a processor core partition map, as described above. In one embodiment, the DVM hub 114 obtains the DVM message processing configuration from the management core 110A.

[0066] At block 520, the DVM hub 114 obtains a first DVM message from the first processor core 110B. The first DVM message may include a processor core identifier of the first processor core 110B. At block 530, the DVM hub 114 determines one or more recipient processor cores 110 of the first DVM message based on the processor core identifier of the first DVM message. For example, as described above, the DVM hub 114 may use a processor core partition map to determine one or more processor cores 110 that belong to the same partition 202A as the first processor core 110B. The one or more recipient processor cores 110 may include one or more processor cores 110 that belong to the same partition 202A as the first processor core 110B. At block 540, the DVM hub provides the first DVM message to the one or more recipient processor cores 110.

[0067] In some implementations of method 500, DVM hub 114 performs preventative action. The preventative action may prevent the DVM message from affecting one or more computing resources of first partition 202A outside the partition 202 to which first processor core 110B belongs. For example, as described above, the DVM message may include a TLB invalidation instruction, and the preventative action may include DVM hub 114 sending a completion response to first processor core 110B that sent the TLB invalidation instruction. The preventative action may further include DVM hub 114 not providing the TLB invalidation instruction to processor cores 110 that do not belong to first partition 202A (i.e., the partition 202 to which processor core 110B belongs).

[0068] FIG. 6 is a flowchart illustrating one embodiment of a method 600 for operating an interrupt interposer 116 in accordance with some implementations of the present disclosure. The interrupt interposer 116 may perform the method 600 and / or one or more of the individual functions, routines, subroutines, or operations of the method 600. In certain implementations, a single processing thread performs the method 600. Alternatively, two or more processing threads may perform the method 600, each thread performing one or more individual functions, routines, subroutines, or operations of the method. In illustrative examples, the processing threads performing the method 600 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads performing the method 600 may execute asynchronously with respect to one another. The various operations of the method 600 may be performed in a different (e.g., reversed) order compared to the order shown in FIG. 6. Some operations of the method 600 may be performed concurrently with other operations. Some operations may be optional.

[0069] At block 610, the interrupt interposer 116B is associated with the processor core 110B. The processor core 110B may belong to the first partition 202A. If the first partition 202A includes multiple processor cores 110B-110C, block 610 may include associating the interrupt interposer 116B with each processor core 110B-110C that belongs to the first partition 202A. The associating with the processor core 110B may include the interrupt interposer 116B storing a processor core identifier of the associated processor core 110B.

[0070] At block 620, the interrupt interposer 116B obtains a first interrupt. The first interrupt may originate from a processor core 110B associated with the interrupt interposer 116B. At block 630, the interrupt interposer 116B determines that the first interrupt is directed to one or more processor cores 110 outside of the first partition 202A. Determining that the first interrupt is directed to one or more processor cores 110 outside of the first partition 202A may include examining a type of the first interrupt (e.g., broadcast, non-broadcast, etc.), a destination list of the first interrupt (e.g., a list of processor core identifiers corresponding to the processor cores 110 to which the interrupt is sent), or other data included in or associated with the first interrupt.

[0071] At block 640, the interrupt interposer 116B prevents the first interrupt from being provided to processor cores 110D-110F outside the first partition 202A. As described above, in the case of a broadcast interrupt, the interrupt interposer 116B may cause one or more second interrupts based on the first interrupt to be provided to each processor core 110B-110C in the first partition 202A. In the case of a non-broadcast interrupt, the interrupt interposer 116B may remove processor core identifiers identifying processor cores 110A, 110D-110F that are not in the same partition 202A as processor core 110B from the list of processor cores 110B-110F of the first interrupt.

[0072] In one embodiment, one or more processor cores 110A-110F are located on the same computing device 100. Computing device 100 may include a system on a chip (SoC), an application specific integrated circuit (ASIC), or other integrated circuit (IC). One or more DVM hubs 114, one or more interrupt interposers 116A-116F, or other components described herein may be located on the same computing device 100.

[0073] In some implementations, one or more processor cores 110 of a partition 202 execute firmware or a boot loader provided by an end user of the cloud computing system. For example, a management core 110A can create a partition 202 that includes one or more components (e.g., processor cores 110, memory blocks, etc.), and the management core 110A can receive the firmware or boot loader and store the firmware or boot loader in the memory blocks of the partition 202. The management core 110A can provide the memory location of the firmware or boot loader to the processor cores 110 of the partition so that the processor cores 110A can execute the firmware or boot loader.

[0074] In some implementations, partition 202 is configured to execute a confidential computing environment. Confidential computing includes providing a hardware-based trusted execution environment (TEE) that executes on one or more hardware components of a computing device. The TEE may include a secure enclave that is isolated from data and hardware outside the TEE, preventing data and processes within the TEE from being directly accessible by other hardware components of the computing device, including the TEE, the operating system, or other software. The TEE can be protected using embedded encryption keys, and embedded authentication operations can prevent access to those keys except by authorized application code. Attempts by unauthorized code can result in the key to the code being denied. Confidential computing can include the TEE receiving encrypted data, the TEE decrypting the encrypted data using the encryption key, the TEE processing the unencrypted data using the authorized code, the TEE encrypting data resulting from the processing, and the TEE outputting the encrypted data from the TEE. In this way, in some examples, encrypted data can be processed only in the TEE, where it is isolated and secure from the rest of the computing device.

[0075] In one implementation, partition 202 may include a TEE. The TEE may include one or more processor cores 110, one or more DVM hubs 114, one or more interrupt interposers, one or more memory blocks of one or more memory devices 120, or other components of partition 202. The TEE may authenticate the initial state of partition 202 and encrypt data in blocks of memory belonging to partition 202. The TEE may use the partition 202 isolation mechanisms and processes described herein to prevent access by unauthorized code associated with other partitions 202 or other computing devices. In some embodiments, the TEE includes a secure enclave within processor core 110 that is isolated from data and hardware outside of processor core 110, preventing other hardware or software on computing device 100 from directly accessing data and processes within the TEE.

[0076] 7 is a block diagram illustrating an exemplary computer system 700 according to an embodiment of the present disclosure. The computer system may be a computing device (e.g., computing device 100 of FIG. 1) or other devices described herein. The computer system 700 may operate in the capacity of a server or endpoint machine in an endpoint-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be any other type of machine capable of executing a set (serial or otherwise) of instructions that specify actions to be performed by the machine. Furthermore, while only a single machine is illustrated, the term "machine" is intended to include any collection of machines that individually or collectively execute a set (or sets) of instructions to perform any one or more of the methodologies discussed herein.

[0077] The exemplary computer system 700 may include a processing device 702, a volatile memory 704, a non-volatile memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and / or a data storage device 716, which communicate with each other via a bus 730.

[0078] The processing device 702 may represent one or more general-purpose processing devices, such as a microprocessor, a CPU, a GPU, a processor core (e.g., processor core 110 of FIG. 1 ), etc. More specifically, the processing device 702 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an ASIC, a field programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device 702 is configured to execute instructions 726 to perform one or more operations described herein.

[0079] The volatile memory 704 may include read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous dynamic random access memory (SDRAM), double data rate (DDR SDRAM), or dynamic random access memory (DRAM), or some other type of volatile memory. The volatile memory 704 may include memory devices 120A-120B of Figure 1. The volatile memory 704 may store at least a portion of the instructions 726.

[0080] The computer system 700 may further include a network interface device 708. The network interface device 708 may facilitate data communication between computing devices. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), input devices 712 (e.g., a keyboard, an alphanumeric keyboard, a motion-sensing input device, a touch screen), a cursor control device 714 (e.g., a mouse), and a signal generation device 718 (e.g., a speaker).

[0081] Data storage device 716 may include a non-transitory machine-readable storage medium 724 (also a computer-readable storage medium) on which one or more sets of instructions 726 are stored. The instructions may embody any one or more of the methods or functions described herein. The instructions 726 may also reside, completely or at least partially, within volatile memory 704 and / or within processing device 702 during execution of the instructions 726 by computer system 700, volatile memory 704, and processing device 702, which also constitute machine-readable storage media. The instructions 726 may further be transmitted or received over network 720 via network interface device 708.

[0082] In one embodiment, instructions 726 include instructions for hardware partitioning of a cloud server. Instructions 726 may include firmware (e.g., firmware of management core 110A). Instructions 726 may include instructions for dividing one or more components of computing device 100 into one or more partitions 202. Instructions 726 may include instructions provided to components of computing device 100, such as DVM hub 114 or interrupt interposer 116, to perform operations as described herein.

[0083] Although the computer-readable storage medium 724 (machine-readable storage medium) is shown as a single medium in the exemplary embodiment, the terms "computer-readable storage medium" and "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The terms "computer-readable storage medium" and "machine-readable storage medium" should also be interpreted to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods of this disclosure. Accordingly, the terms "computer-readable storage medium" and "machine-readable storage medium" should be interpreted to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0084] In the above description, numerous details are set forth. However, it will be apparent to one skilled in the art having the benefit of this disclosure that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present disclosure.

[0085] Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It proves convenient at times, for reasons of common usage, to refer to these symbols as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0086] It should be recognized, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specified as will be apparent from the description that follows, throughout this specification, descriptions using terms such as "receive," "display," "transfer," "adjust," "replace," "determine," "reproduce," and the like will be understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulates and converts data represented as physical (e.g., electronic) quantities in the computer system's registers and memory into other data that is also represented as physical quantities in the computer system's memory or registers, or other such information storage, transmission, or display device.

[0087] For ease of explanation, methods (e.g., methods 400, 500, or 600) are shown and described herein as a series of acts. However, acts in accordance with the present disclosure can be performed in various orders and / or simultaneously, as well as with other acts not shown and described herein. Moreover, not all illustrated acts are required to perform a method in accordance with the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that a method could alternatively be represented as a series of interrelated states via a state diagram or events. Furthermore, it will be appreciated that the methods disclosed herein can be stored on an article of manufacture to facilitate moving and transferring such methodologies to a computing device. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0088] Certain embodiments of the present disclosure also relate to apparatus for performing the operations herein. This apparatus can be constructed for the intended purposes, or the apparatus can include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored on a non-transitory computer-readable storage medium, including, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic disks, read-only memory (ROM), random-access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions.

[0089] References throughout this specification to "one implementation," "an implementation," "some implementations," "one embodiment," "an embodiment," or "some embodiments" mean that a particular feature, structure, or characteristic described in connection with an implementation or embodiment is included in at least one implementation or embodiment. Thus, the appearances of the phrase "in one implementation" or "in an implementation" or other similar terms in various places throughout this specification do not necessarily all refer to the same implementation. In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." Furthermore, the word "example" or similar terms are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or similar terms is intended to present concepts in a concrete manner.

[0090] Throughout this disclosure, references to "first," "second," "third," etc. are used for purposes of clarity and distinction only and do not imply a particular order of assembly or operation. Furthermore, in some embodiments, references to a "first" component and a "second" component may refer to the same component unless expressly stated otherwise.

[0091] To the extent that the terms "includes," "including," "has," "contains," variations thereof, and other similar words are used in either the detailed description or the claims, these terms are intended to be inclusive in the same manner as the open transition word "comprising," without excluding additional or other elements.

[0092] As used herein, the terms "component," "module," or "system," etc., are intended to generally refer to a computer-related entity, either hardware (e.g., circuitry), software, a combination of hardware and software, or an entity related to an operable machine having one or more specific functions. For example, a component may be, but is not limited to, a process running on a processor (e.g., a digital signal processor), a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of example, both an application running on a controller and the controller may be a component. One or more components may reside within a process and / or thread of execution, and a component may be localized on one computer and / or distributed among two or more computers. Furthermore, a "device" may be in the form of specially designed hardware, general-purpose hardware specialized by software executing on the hardware that enables the hardware to perform specific functions (e.g., generating points of interest and / or descriptions), software on a computer-readable medium, or a combination thereof.

[0093] The aforementioned systems, circuits, modules, etc. are described with respect to interactions between certain components and / or blocks. It is understood that such systems, circuits, components, blocks, etc. may include those components or designated subcomponents, portions of the designated components or subcomponents, and / or additional components, according to the various permutations and combinations described above. Subcomponents may also be implemented as components communicatively coupled to other components rather than being contained within a parent component (hierarchical). In addition, it should be noted that one or more components may be combined into a single component providing integrated functionality or may be divided into several separate subcomponents, and that any one or more intermediate layers, such as a management layer, may be provided to communicatively couple such subcomponents to provide integrated functionality. Any component described herein may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0094] It should be understood that the foregoing description is intended to be illustrative, and not limiting. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. 1. A system comprising: a plurality of processor cores including a first processor core that executes an instruction to divide at least a portion of the plurality of processor cores into a plurality of partitions; at least one distributed virtual memory (DVM) hub, said DVM hub comprising: and receiving a first DVM message from a second processor core of the plurality of processor cores, the first DVM message including a processor core identifier of the second processor core, the DVM hub further comprising: determining one or more recipient processor cores of the plurality of processor cores of the first DVM message based on the processor core identifier; providing the first DVM message to the one or more recipient processor cores, the system further comprising: a plurality of interrupt interposers, each of the plurality of interrupt interposers comprising: each interrupt interposer of the plurality of interrupt interposers is associated with one processor core of the plurality of processor cores, the associated processor core belonging to one partition of the plurality of partitions, and further comprising: The system prevents a first interrupt originating from the associated processor core from being provided to a processor core outside the partition of the associated processor core.

2. 2. The system of claim 1, wherein the at least one DVM hub comprises a processor core partition map including a plurality of entries, each entry including a processor core identifier and a corresponding partition of the plurality of partitions.

3. 3. The system of claim 2, wherein the first processor core executing instructions to divide the at least some of the plurality of processor cores into the plurality of partitions comprises configuring the processor core partition map of the at least one DVM hub to include the plurality of entries.

4. The at least one DVM hub determining the one or more recipient processor cores of the first DVM message based on the processor core identifier may include: Identifying, from the processor core partition map, one partition of the plurality of partitions to which the second processor core belongs based on the processor core identifier; and determining the one or more recipient processor cores based on the identified partitions from the processor core partition map.

5. the at least one DVM hub comprises a first DVM hub and a second DVM hub; 2. The system of claim 1, wherein a first subset of the plurality of processor cores provides DVM messages to the first DVM hub and a second subset of the plurality of processor cores provides DVM messages to the second DVM hub.

6. the system further comprises an input / output (IO) processor core that executes instructions to emulate one or more IO devices; 2. The system of claim 1, wherein the first processor core executing the instructions to divide the at least some of the plurality of processor cores into the plurality of partitions includes allocating an emulated IO device of the one or more emulated IO devices to one of the plurality of partitions.

7. The system of claim 1 , wherein the first processor core of the plurality of processor cores is not included in any of the plurality of partitions.

8. 1. A method comprising: Dividing a plurality of processor cores into one or more partitions; at least one distributed virtual memory (DVM) hub; and configuring the at least one distributed virtual memory (DVM) hub to: determining one or more recipient processor cores of the plurality of processor cores of the first DVM message based on the processor core identifier of the first DVM message; providing the first DVM message to the one or more recipient processor cores; configuring an interrupt interposer to be associated with the first processor core, the first processor core belonging to a first partition of the one or more partitions, the method further comprising: and configuring the interrupt interposer to prevent a first interrupt originating from the first processor core from being provided to a processor core outside of the first partition.

9. 10. The method of claim 8, further comprising configuring the at least one DVM hub to perform a preventative action associated with the first DVM message.

10. the first DVM message includes a translation lookaside buffer (TLB) invalidation instruction; 10. The method of claim 9, wherein the proactive action includes sending a completion response to the first processor core.

11. the first DVM message includes a cache invalidation command; 10. The method of claim 9, wherein the proactive action includes sending a completion response to the first processor core.

12. the first DVM message includes a branch predictor disable instruction; 10. The method of claim 9, wherein the proactive action includes sending a completion response to the first processor core.

13. The method of claim 8 , wherein the multiple processor cores are located on the same system-on-chip (SoC).

14. the first processor core includes a system address map (SAM) including a plurality of entries, each entry including a block of memory and a corresponding channel leading to the block of memory; 9. The method of claim 8, wherein dividing the plurality of processor cores into the one or more partitions includes configuring the SAM by deleting one entry from the plurality of entries, the deleted entry including a channel to a block of memory not allocated to the first partition.

15. the first interrupt includes a broadcast interrupt; 9. The method of claim 8, wherein preventing, at the interrupt interposer, the first interrupt from being provided to a processor core outside the first partition includes causing one or more second interrupts based on the first interrupt to be provided to each processor core in the first partition.

16. 1. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations, the operations including: Dividing a plurality of processor cores into one or more partitions; at least one distributed virtual memory (DVM) hub; and configuring the at least one distributed virtual memory (DVM) hub to: obtain a first DVM message from a first processor core of the plurality of processor cores, the first DVM message including a processor core identifier of the first processor core; determining one or more recipient processor cores of the plurality of processor cores of the first DVM message based on the processor core identifier of the first DVM message; providing the first DVM message to the identified one or more recipient processor cores; and configuring an interrupt interposer to be associated with the first processor core, the first processor core belonging to a first partition of the one or more partitions, the operation further comprising: and configuring the interrupt interposer to prevent a first interrupt originating from the first processor core from being provided to a processor core outside the first partition.

17. 17. The computer-readable storage medium of claim 16, wherein the operations further configure the at least one DVM hub with a processor core partition map including a plurality of entries, each entry including a processor core identifier and a corresponding partition of the one or more partitions.

18. 17. The computer-readable storage medium of claim 16, wherein the operation further configures the DVM hub to perform a preventative action associated with the first DVM message.

19. 17. The computer-readable storage medium of claim 16, wherein the first interrupt comprises a software generated interrupt (SGI).

20. the first interrupt includes a broadcast interrupt; 17. The computer-readable storage medium of claim 16, wherein preventing the first interrupt from being provided to a processor core outside the partition of the associated first processor core comprises causing one or more second interrupts based on the first interrupt to be provided to each processor core within the partition of the associated first processor core.

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