Circuit device for fast initialization of block random access memory and working method

Abstract

The invention discloses a circuit device for quickly initializing a block random access memory (BRAM) and a working method, which can improve the initialization speed of the BRAM, greatly save the initialization time and have high resource utilization rate. The BRAM circuit comprises a BRAM circuit, a data pre-classification module and an initialization controller, the BRAM circuits exist in the FPGA in the form of column circuits, and the column serial numbers of the BRAM column circuits in each row are consistent; a data pre-classification module finds a BRAM initial value in a bit stream file, initial value data of BRAM columns in each row of the FPGA are forwarded to an initialization controller in a data frame mode, and one frame of initialization value is forwarded in each row; and the initialization controller writes a plurality of frames of initialization values into the BRAM column circuit of each row in parallel in a clock period, and initializes the BRAM circuits of all rows of the FPGA.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA chips, and in particular to a circuit device for rapid initialization of a block random access memory, and a working method of the circuit device for rapid initialization of a block random access memory. Background Art

[0002] Block Random Access Memory (BRAM) is a type of on-chip memory commonly used in FPGA (Field Programmable Gate Array) designs. It provides an efficient and fast storage method suitable for implementing functions such as caches, buffers, and lookup tables. BRAM consists of multiple memory blocks, each with a fixed storage capacity. Each memory block is composed of small memory cells, each associated with an address number. Data can be quickly written or read by accessing these address numbers. BRAMs are located in fixed locations within an FPGA. FPGAs are typically organized into rows, where rows are horizontally arranged elements within the FPGA's internal structure. Each row contains multiple columns, which are vertically arranged elements within the FPGA's internal structure. An FPGA chip typically contains several BRAM columns, each consisting of multiple BRAM blocks. To facilitate parallel operation and flexible configuration of multiple BRAMs, the capacity of each BRAM block within the same chip is typically fixed.

[0003] After the FPGA is powered on, the contents of the BRAM memory block are typically undefined, random values. Directly using uninitialized BRAM can cause unpredictable behavior in the design logic. Furthermore, many designs require initial values ​​in the BRAM as a starting point, such as the initial state of a state machine, lookup table data, or default parameters during calculations. If this data is not properly initialized, the system will not function properly, so the BRAM needs to be initialized. The BRAM initialization process is implemented during the FPGA configuration phase, and the initialization values ​​are contained in the bitstream file. During the FPGA configuration phase, the configuration logic writes the specified initial values ​​to the BRAM based on the BRAM initialization information in the bitstream file. During the BRAM initialization process, the initialization values ​​are written to the BRAM in data frames, and multiple configuration data frames are typically required to initialize a single BRAM memory block.

[0004] The FPGA configuration logic initializes BRAM blocks on a BRAM block-by-block basis. It first configures the first BRAM block in the first BRAM column of the first row of the FPGA. The initial values ​​of this BRAM block are written one by one, using configuration data frames. After initialization of the first BRAM block is complete, the second BRAM block in the first BRAM column of the first row is initialized. This continues, and so on. After initialization of the last BRAM block in the first BRAM column of the first row is complete, the BRAM block in the second BRAM column of the first row is initialized. After initialization of all BRAM columns in the first row is complete, the FPGA configuration logic initializes the BRAM columns in the second row, and so on until the last BRAM column in the last row is initialized, completing the FPGA's BRAM initialization process. A disadvantage of this BRAM initialization process is that BRAM blocks are initialized row by row, column by column, and frame by frame, taking a long time. This relatively long initialization time can impact overall system performance, particularly for applications that require fast response times, causing delays during system startup or certain critical operations. Summary of the Invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a circuit device for fast initialization of block random access memory, which can improve the BRAM initialization speed, greatly save initialization time, and have high resource utilization.

[0006] The technical solution of the present invention is: a circuit device for fast initialization of a block random access memory, comprising: a BRAM circuit, a data pre-classification module, and an initialization controller; The BRAM circuit exists in the form of column circuits in the FPGA, and the column numbers of the BRAM column circuits in each row are consistent; The data pre-classification module finds the BRAM initial value in the bitstream file and forwards the initial value data of the BRAM column of each row of the FPGA to the initialization controller in the form of a data frame, forwarding one frame of initialization value for each row; The initialization controller writes the initialization values ​​of several frames to the BRAM column circuit of each row in parallel within one clock cycle, and initializes the BRAM circuits of all rows of the FPGA at the same time.

[0007] The data pre-classification module of the present invention finds the BRAM initial value in the bitstream file, and forwards the initial value data of the BRAM column of each row of the FPGA to the initialization controller in the form of a data frame. Each row forwards one frame of initialization value. The initialization controller writes the initialization values ​​of several frames in parallel to the BRAM column circuit of each row within one clock cycle, which is equivalent to initializing the BRAM circuits of all rows of the FPGA at the same time. This can improve the BRAM initialization speed, greatly save initialization time, and achieve high resource utilization.

[0008] A method for operating a circuit device for fast initialization of a block random access memory is also provided, comprising the following steps: (1) The data pre-classification module finds the initialization values ​​of all BRAMs in the storage medium where the bitstream file is stored; (2) The data pre-classification module finds the first frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of FPGA in the BRAM initialization value; (3) When the initialization controller starts to initialize the BRAM circuit of the FPGA, the data pre-classification module forwards several frame initialization values ​​to the initialization controller. The initialization controller writes the several frame initialization values ​​in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a structural block diagram of a circuit device for fast initialization of a block random access memory according to the present invention.

[0010] Figure 2 It is a BRAM column circuit.

[0011] Figure 3 It is a schematic diagram of the initialization controller according to the present invention writing the first frame of initialization data into the first BRAM storage block.

[0012] Figure 4 It is a schematic diagram of the initialization controller according to the present invention writing the second frame initialization data into the first BRAM storage block.

[0013] Figure 5 It is a schematic diagram of the initialization controller according to the present invention writing the first frame initialization data into the second BRAM storage block.

[0014] Figure 6 The flowchart of the working method of the circuit device for fast initialization of block random access memory according to the present invention is shown. DETAILED DESCRIPTION

[0015] like Figure 1-Figure 5As shown, the circuit device for fast initialization of block random access memory includes: a BRAM circuit, a data pre-classification module, and an initialization controller; The BRAM circuit exists in the form of column circuits in the FPGA, and the column numbers of the BRAM column circuits in each row are consistent; The data pre-classification module finds the BRAM initial value in the bitstream file and forwards the initial value data of the BRAM column of each row of the FPGA to the initialization controller in the form of a data frame, forwarding one frame of initialization value for each row; The initialization controller writes the initialization values ​​of several frames to the BRAM column circuit of each row in parallel within one clock cycle, and initializes the BRAM circuits of all rows of the FPGA at the same time.

[0016] The data pre-classification module of the present invention finds the BRAM initial value in the bitstream file, and forwards the initial value data of the BRAM column of each row of the FPGA to the initialization controller in the form of a data frame. Each row forwards one frame of initialization value. The initialization controller writes the initialization values ​​of several frames in parallel to the BRAM column circuit of each row within one clock cycle, which is equivalent to initializing the BRAM circuits of all rows of the FPGA at the same time. This can improve the BRAM initialization speed, greatly save initialization time, and achieve high resource utilization.

[0017] Preferably, the data pre-classification module finds the initialization values ​​of all BRAMs in the storage medium storing the bitstream file, and then the data pre-classification module finds the first frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of the FPGA in the BRAM initialization value. When the initialization controller starts to initialize the BRAM circuit of the FPGA, the data pre-classification module forwards several frame initialization values ​​to the initialization controller, and the initialization controller writes the several frame initialization values ​​in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle.

[0018] Preferably, the data pre-classification module finds the second frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of the FPGA in the BRAM initialization value, forwards it to the initialization controller, and then the initialization controller writes the second frame initialization values ​​of several BRAM storage blocks in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle; and so on, after the initialization of the first BRAM storage block in the first BRAM column of each row is completed, the second BRAM storage block in the first BRAM column of each row is initialized; when all BRAM storage blocks in the first BRAM column of each row are initialized, the second BRAM column of each row is initialized, and the data pre-classification module forwards the first frame initialization value of the first BRAM storage block of the second BRAM column of each row to the initialization controller, and the initialization controller writes multiple frames of initialization values ​​to the corresponding BRAM storage blocks. When the initialization of the last BRAM storage block in the last BRAM column of each row is completed, the initialization of the BRAM circuit of the entire FPGA is completed.

[0019] like Figure 6 As shown, a working method of a circuit device for fast initialization of a block random access memory is also provided, which includes the following steps: (1) The data pre-classification module finds the initialization values ​​of all BRAMs in the storage medium where the bitstream file is stored; (2) The data pre-classification module finds the first frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of FPGA in the BRAM initialization value; (3) When the initialization controller starts to initialize the BRAM circuit of the FPGA, the data pre-classification module forwards several frame initialization values ​​to the initialization controller. The initialization controller writes the several frame initialization values ​​in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle.

[0020] Preferably, in step (3), in the next clock cycle, the initialization controller writes the initialization value in parallel into the second BRAM storage block of the first BRAM column circuit in each row; repeating the above process, within multiple clock cycles, the initialization value is written in parallel into each BRAM storage block in each column BRAM circuit in each row of the FPGA.

[0021] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A circuit device for fast initialization of a block random access memory, characterized in that: It includes: BRAM circuit, data pre-classification module, initialization controller; The BRAM circuit exists in the form of column circuits in the FPGA, and the column numbers of the BRAM column circuits in each row are consistent; The data pre-classification module finds the BRAM initial value in the bitstream file and forwards the initial value data of the BRAM column of each row of the FPGA to the initialization controller in the form of a data frame, forwarding one frame of initialization value for each row; The initialization controller writes the initialization values ​​of several frames to the BRAM column circuit of each row in parallel within one clock cycle, and initializes the BRAM circuits of all rows of the FPGA at the same time.

2. The circuit device for fast initialization of a block random access memory according to claim 1, wherein: The data pre-classification module finds the initialization values ​​of all BRAMs in the storage medium storing the bitstream file, and then finds the first frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of the FPGA in the BRAM initialization value. When the initialization controller starts to initialize the BRAM circuit of the FPGA, the data pre-classification module forwards several frame initialization values ​​to the initialization controller, and the initialization controller writes the several frame initialization values ​​in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle.

3. The circuit device for fast initialization of a block random access memory according to claim 2, wherein: The data pre-classification module finds the second frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of the FPGA in the BRAM initialization value, and forwards it to the initialization controller. Then, the initialization controller writes the second frame initialization values ​​of multiple BRAM storage blocks in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle; and so on. After the initialization of the first BRAM storage block in the first BRAM column of each row is completed, the second BRAM storage block in the first BRAM column of each row is initialized; when all BRAM storage blocks in the first BRAM column of each row are initialized, the second BRAM column of each row is initialized. The data pre-classification module forwards the first frame initialization value of the first BRAM storage block of the second BRAM column of each row to the initialization controller. The initialization controller writes multiple frames of initialization values ​​to the corresponding BRAM storage blocks. When the initialization of the last BRAM storage block of the last BRAM column of each row is completed, the initialization of the BRAM circuit of the entire FPGA is completed.

4. The operating method of the circuit device for fast initialization of block random access memory according to claim 1, characterized in that: It includes the following steps: (1) The data pre-classification module finds the initialization values ​​of all BRAMs in the storage medium where the bitstream file is stored; (2) The data pre-classification module finds the first frame initialization value of the first BRAM storage block in the first BRAM column circuit of each row of FPGA in the BRAM initialization value; (3) When the initialization controller starts to initialize the BRAM circuit of the FPGA, the data pre-classification module forwards several frame initialization values ​​to the initialization controller, and the initialization controller writes the several frame initialization values ​​in parallel to the first BRAM storage block in the first BRAM column circuit of each row within one clock cycle.

5. The operating method of the circuit device for fast initialization of block random access memory according to claim 4, characterized in that: In step (3), in the next clock cycle, the initialization controller writes the initialization value in parallel into the second BRAM storage block of the first BRAM column circuit in each row; repeating the above process, within multiple clock cycles, the initialization value is written in parallel into each BRAM storage block in each column of the BRAM circuit in each row of the FPGA.

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