Amplitude-adjustable attenuation circuit network for differential signal transmission

Abstract

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interface circuits, and in particular to an amplitude-adjustable attenuation circuit network for differential signal transmission. Background Art

[0002] Interface circuits primarily consist of a transmitter and receiver module. The transmitter transmits the data signal, while the receiver receives and analyzes the transmitted signal. When signals need to be transmitted over long distances, the non-ideal characteristics of the transmission channel can easily cause signal distortion. Maintaining signal integrity is a core challenge in interface circuit design.

[0003] SerDes (Serializer / Deserializer) is a typical interface circuit. Its working mechanism is as follows: at the transmitting end, a serializer is used to combine multiple parallel low-speed signals into a single high-speed serial signal. After transmitting it through the transmission medium to the receiving end, a deserializer restores the high-speed serial signal to the original parallel data, thus completing end-to-end communication. In existing high-speed SerDes systems, the attenuation circuit network at the receiving end plays a crucial role.

[0004] In high-speed interface circuit design, receiver-side signal conditioning is a critical step in achieving reliable data recovery. Due to factors such as high-frequency attenuation, impedance mismatch, and noise interference in the transmission channel, the receiver must dynamically adapt the signal amplitude through an attenuation network to balance signal integrity and system sensitivity. Traditional receiver-side attenuation circuits often use fixed resistor-capacitor networks or mechanically adjustable components to achieve signal attenuation. However, due to high-frequency parasitics and component physical characteristics, they struggle to achieve the desired balance between wide bandwidth, low distortion, and precise adjustment. For example, discrete resistor-capacitor networks are prone to phase distortion due to parasitic capacitance when handling multi-band signals. While mechanical potentiometers can achieve step-by-step adjustment, they suffer from contact wear, significant temperature drift, and slow response speed, making them inadequate for the nanosecond-level dynamic adjustment required by high-speed SerDes systems. Furthermore, the performance trade-off between power consumption and swing in existing circuits further complicates receiver-side signal conditioning. A high-precision, low-power, and dynamically configurable attenuation solution is urgently needed to optimize real-time control of the signal attenuation ratio and system robustness. Summary of the Invention

[0005] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide an amplitude-adjustable attenuation circuit network for differential signal transmission, thereby solving the problems of insufficient adjustment flexibility and limited anti-interference capability of the differential signal attenuation circuit.

[0006] The technical solution of the present invention is: an amplitude-adjustable attenuation circuit network for differential signal transmission, comprising an attenuator I and an attenuator II; attenuator I serves as a resistive attenuation circuit, attenuator II serves as a capacitive attenuation network, and attenuator I and attenuator II are connected via a common-mode feedback circuit; wherein,

[0007] The input end of the attenuator 1 receives a differential signal sent from the outside, and after the differential signal is divided by the attenuator 1, the output differential signal enters the common-mode feedback circuit;

[0008] The common-mode feedback circuit receives the differential signal sent from attenuator I, obtains the common-mode level of the differential signal, and then sends it to attenuator II.

[0009] The attenuator II receives the differential serial signal sent from the common-mode feedback circuit, and the differential serial signal undergoes further differential-mode attenuation through the attenuator II.

[0010] The attenuator I includes: fixed resistors RS1p, RS1n, binary weight adjustable resistors R1p-R3p, R1n-R3n, fixed voltage divider resistors R4p, R4n, and NMOS transistors M1-M8;

[0011] The input differential serial signals VPin and VNin are respectively input to one end of the fixed resistors RS1p and RS1n in the attenuator I;

[0012] The gate of the NMOS transistor M1 is connected to the external enable signal EN1, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R1p;

[0013] The gate of the NMOS transistor M2 is connected to the external enable signal EN2, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R2p;

[0014] The gate of the NMOS transistor M3 is connected to the external enable signal EN3, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R3p;

[0015] The gate of the NMOS transistor M4 is connected to the external enable signal EN1, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R1n;

[0016] The gate of the NMOS transistor M5 is connected to the external enable signal EN2, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R2n;

[0017] The gate of the NMOS transistor M6 is connected to the external enable signal EN3, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R3n;

[0018] The gate of NMOS tube M7 is connected to VDD, the source is connected to GND, and the drain is connected to the fixed voltage divider resistor R4p to ensure that the resistor voltage divider state is long-term effective;

[0019] The gate of the NMOS tube M8 is connected to VDD, the source is connected to GND, and the drain is connected to the fixed voltage divider resistor R4n to ensure that the resistor voltage divider state is long-term effective;

[0020] One end of the binary weight adjustable resistors R1p, R2p, and R3p is connected to the output terminal VPout, and the other end is connected to the fixed resistor RS1p and the fixed voltage divider resistor R4p;

[0021] One end of the binary weight adjustable resistors R1n, R2n, and R3n is connected to the output terminal VNout, and the other end is connected to the fixed resistor RS1n and the fixed voltage divider resistor R4n.

[0022] The resistance ratio of the binary weight adjustable resistors R1p, R2p, and R3p is 4:2:1.

[0023] The resistance ratio of the binary weight adjustable resistors R1n, R2n, and R3n is 4:2:1.

[0024] Also included are diodes D1-D4; wherein,

[0025] The positive ends of diodes D1 and D2 are connected together, and the negative ends of diodes D1 and D2 are connected to the input terminal VPin of attenuator I and one end of fixed resistor RS1p respectively to form back-to-back diodes;

[0026] The negative ends of the diodes D3 and D4 are connected to each other, and the positive ends of the diodes D3 and D4 are connected to the input end VNin of the attenuator I and one end of the fixed resistor RS1n respectively to form back-to-back diodes.

[0027] When the input differential signals VPin and VNin are input to attenuator I, they pass through fixed resistors RS1p and RS1n and then enter binary weighted adjustable resistors R1p-R3p and R1n-R3n controlled by an external enable signal to complete voltage division, attenuating the differential and common-mode values ​​of the input signals to a swing range that can be recognized by subsequent circuits.

[0028] The attenuator II includes: binary weight adjustable capacitors C1p-C6p, C1n-C6n, and PMOS tubes M9-M14;

[0029] The common-mode feedback circuit inputs and ultimately outputs a differential serial signal VP, which is connected to the source of the PMOS transistors M9, M10, and M11, and one end of the binary weight adjustable capacitors C1p-C6p respectively;

[0030] The common-mode feedback circuit inputs and ultimately outputs a differential serial signal VN, which is connected to the source terminals of the PMOS transistors M12, M13, and M14 and one end of the binary weight adjustable capacitors C1n-C6n respectively;

[0031] The gate of the PMOS transistor M9 is connected to the external enable signal EN4, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C1n and C2n;

[0032] The gate of the PMOS transistor M10 is connected to the external enable signal EN5, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C3n and C4n;

[0033] The gate of the PMOS transistor M11 is connected to the external enable signal EN6, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C5n and C6n;

[0034] The gate of the PMOS transistor M12 is connected to the external enable signal EN4, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C1p and C2p;

[0035] The gate of the PMOS transistor M13 is connected to the external enable signal EN5, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C3p and C4p;

[0036] The gate of the PMOS transistor M14 is connected to the external enable signal EN6, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C5p and C6p.

[0037] The capacitance ratio of the binary weight adjustable capacitors C1p-C6p is 4:4:2:2:1:1.

[0038] The capacitance ratio of the binary weight adjustable capacitors C1n-C6n is 4:4:2:2:1:1.

[0039] When the input differential signals VP and VN are input to attenuator II, they pass through the binary weight adjustable capacitors C1p-C6p and C1n-C6n. At this time, the input differential signals VP and VN form an AC ground for the circuit, attenuating the differential mode of the input signal to a swing range that can be recognized by the subsequent circuit.

[0040] The advantages of the present invention compared with the prior art are:

[0041] (1) The present invention uses a two-stage composite attenuation structure to achieve broadband optimization. Through the collaborative work of the resistive attenuator (low-frequency dominant, common-mode and differential-mode synchronous attenuation) and the capacitive attenuation network (high-frequency compensation, single differential-mode attenuation), it simultaneously meets the requirements of low-frequency amplitude attenuation and high-frequency signal integrity compensation, as well as single differential-mode attenuation for common-mode and differential-mode synchronous attenuation and preservation of the common-mode voltage after clamping, thus overcoming the limited attenuation capability of a single attenuation structure.

[0042] (2) The present invention uses an ESD impact resistance module to enhance system reliability. The back-to-back diodes at the input end provide a bidirectional electrostatic discharge path, achieving chip-level ESD protection without additional drive circuits and improving interface robustness.

[0043] (3) The present invention uses binary weighted adjustable elements to improve adjustment accuracy. The attenuation resistors and capacitors involved are designed with binary weight arrays, and through switch combinations, exponential attenuation steps are achieved, expanding the dynamic range and providing multi-range attenuation.

[0044] (4) The present invention uses dynamic path reconstruction technology to adapt to multiple scenarios. The MOS transistor switch matrix supports real-time switching of hardware-level attenuation paths, and can quickly configure the optimal attenuation mode for different transmission rates, channel loss and other conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a network structure diagram of an amplitude-adjustable attenuation circuit for differential signal transmission according to the present invention;

[0046] Figure 2 This is a structural principle diagram of an amplitude-adjustable attenuation circuit network attenuator I for differential signal transmission according to the present invention;

[0047] Figure 3 This is a simulation result diagram of the amplitude-adjustable attenuation circuit network attenuator I for differential signal transmission of the present invention;

[0048] Figure 4 This is a structural principle diagram of the amplitude-adjustable attenuation circuit network attenuator II for differential signal transmission of the present invention;

[0049] Figure 5 This is a simulation result diagram of the amplitude-adjustable attenuation circuit network attenuator II for differential signal transmission of the present invention. DETAILED DESCRIPTION

[0050] The present invention presents an amplitude-adjustable attenuation circuit network for differential signal transmission, consisting of Attenuator I (a resistor attenuation circuit) and Attenuator II (a capacitor attenuation network). The cascaded design of Attenuator I and Attenuator II leverages the fundamental signal amplitude regulation provided by the resistor network and the high-frequency compensation provided by the capacitor network, thereby achieving precise control of amplitude attenuation across a wide bandwidth.

[0051] In the specific architecture, an ESD protection module is integrated into the input of attenuator I. This module utilizes back-to-back diodes connected in parallel to the positive and negative differential inputs. When an external electrostatic discharge (ESD) pulse (ESD) occurs, the diodes' bidirectional conduction properties divert the transient current to the power supply or ground, effectively protecting the internal circuitry from high voltage damage while ensuring low-loss transmission of normal signals. The core voltage divider network of attenuator I consists of fixed resistors (RS1p, RS1n) in parallel with binary-weighted adjustable resistors (RS2p, RS2n), and fixed voltage divider resistors (R4p, R4n). The binary-weighted adjustable resistors have a resistance ratio of 4:2:1 for R1p, R2p, and R3p, and a ratio of 4:2:1 for R1n, R2n, and R3n. The fixed resistors provide a baseline voltage divider ratio, while the adjustable resistor array, controlled by switches, allows for discrete resistance adjustment, dynamically adjusting the signal attenuation level. The binary weight design of the resistor array makes the attenuation step change exponentially, significantly improving the coverage capability of the attenuation range.

[0052] Attenuator II, a high-frequency compensation module, consists of binary-weighted adjustable capacitors (CSp and CSn). The ratios of these binary-weighted adjustable capacitors are 4:4:2:2:1:1 for C1p-C6p and 4:4:2:2:1:1 for C1n-C6n. The adjustable capacitor array uses multi-stage switching to adjust the equivalent capacitance, compensating for signal loss in different frequency bands. The binary weighting of the capacitor array ensures precise high-frequency attenuation adjustment while avoiding phase distortion caused by sudden changes in capacitance. Furthermore, because the attenuator utilizes capacitive attenuation, its capacitively coupled attenuation structure leverages the AC coupling and DC isolation properties of the capacitors. The DC blocking mechanism ensures that the common-mode voltage reference locked by the common-mode feedback system is fully maintained, while the differential-mode signal component is controllably attenuated via a capacitive reactance divider network.

[0053] The interval between the two-stage attenuators uses a common-mode feedback circuit with a closed-loop control mechanism to ensure the stability of the common-mode level of the differential signal. Through the combined adjustment of the resistor and capacitor network, the attenuation circuit can simultaneously optimize the low-frequency amplitude attenuation and high-frequency signal integrity. In addition, the attenuation circuit network as a whole uses a MOS tube switch matrix to control the switching of the attenuation path. The switch matrix consists of multiple groups of MOS tubes in a grid-like topology. The conduction and shutdown of specific MOS tubes are controlled by external logic signals, thereby selecting different resistance / capacitance combination paths to achieve dynamic configuration of the attenuation level. All MOS tubes use an independent bias design to ensure the stability of the switching state. This architecture significantly improves the attenuation accuracy and system reliability while ensuring the quality of signal transmission.

[0054] The present invention is described in detail below with reference to the accompanying drawings.

[0055] like Figure 1 The figure shows the overall structural block diagram of an amplitude-adjustable attenuation circuit network for differential signal transmission according to the present invention. The overall amplitude-adjustable attenuation circuit network is composed of attenuator I (resistance attenuation circuit) and attenuator II (capacitance attenuation network), which are isolated and coordinated by a common-mode feedback circuit. The input differential serial signals VPin and VNin pass through attenuators I and II, respectively, to achieve synchronous attenuation of the common-mode and differential-mode voltages and differential-mode attenuation while retaining the common-mode level. The MOS transistors used in the present invention are all enhancement-mode MOS transistors. The signals VPin and VNin at the input ports are transmitted to the output ports VP and VN via differential paths.

[0056] like Figure 2 FIG. 1 is a schematic structural diagram of an amplitude-adjustable attenuation circuit network attenuator I for differential signal transmission according to the present invention. The attenuator I includes:

[0057] (1) Diodes D1, D2, D3, and D4;

[0058] (2) Fixed resistors RS1p and RS1n;

[0059] (3) binary weighted adjustable resistors RS2p (R1p, R2p, R3p) and RS2n (R1n, R2n, R3n), with the binary weighted adjustable resistor ratios being (the resistance ratio of R1p, R2p, R3p is 4:2:1, and the resistance ratio of R1n, R2n, R3n is 4:2:1);

[0060] (4) Fixed voltage divider resistors R4p and R4n;

[0061] (5) NMOS tubes M1, M2, M3, M4, M5, M6, M7, M8.

[0062] The MOS tubes used in attenuator I are all enhancement mode MOS tubes.

[0063] Attenuator I employs four diodes, D1, D2, D3, and D4, forming two diode pairs in a reverse-series configuration. These pairs are symmetrically coupled between the positive and negative input terminals of the differential signal. When an ESD transient overvoltage event occurs at the input, the diode pairs, based on their nonlinear volt-ampere response characteristics, alternately trigger a breakdown mode under forward and reverse bias conditions, thereby forming multipath low-impedance current discharge channels. This structure rapidly shunts the high transient current generated by the ESD pulse through a pre-set power bus or ground plane, limiting the input potential to a safe operating voltage range and effectively preventing insulation breakdown or thermal damage to the internal amplifier circuitry.

[0064] Due to the binary weighted adjustable resistor quantity and ratio, the attenuator I has 8 operating states:

[0065] (1) When the external enable signals EN1, EN2, and EN3 are all low, only the NMOS transistors M7 and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuated voltage levels VPout and VNout should be obtained at the level between the fixed resistors RS1p and RS1n and the fixed voltage divider resistors R4p and R4n;

[0066] (2) When the external enable signal EN1 is high and EN2 and EN3 are low, the NMOS transistors M1, M4, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the level between the fixed resistors RS1p and RS1n and the fixed voltage divider resistors R4p and R4n and the binary weight array attenuation resistors RS2p (R1p) and RS2n (R1n);

[0067] (3) When the external enable signal EN2 is high and EN1 and EN3 are low, the NMOS transistors M2, M5, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the level between the fixed resistors RS1p and RS1n and the fixed voltage divider resistors R4p and R4n and the binary weight array attenuation resistors RS2p (R2p) and RS2n (R2n);

[0068] (4) When the external enable signal EN3 is high and EN1 and EN2 are low, the NMOS transistors M3, M6, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the level between the fixed resistors RS1p and RS1n and the fixed voltage divider resistors R4p and R4n and the binary weight array attenuation resistors RS2p (R3p) and RS2n (R3n);

[0069] (5) When the external enable signals EN1 and EN2 are high and EN3 is low, the NMOS transistors M1, M2, M4, M5, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the points between the fixed resistors RS1p and RS1n, the fixed voltage divider resistors R4p and R4n, and the binary weight array attenuation resistors RS2p (R1p and R2p in parallel) and RS2n (R1n and R2n in parallel);

[0070] (6) When the external enable signals EN1 and EN3 are high and EN2 is low, the NMOS transistors M1, M3, M4, M6, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the points between the fixed resistors RS1p and RS1n, the fixed voltage divider resistors R4p and R4n, and the binary weight array attenuation resistors RS2p (R1p and R3p in parallel) and RS2n (R1n and R3n in parallel);

[0071] (7) When the external enable signals EN2 and EN3 are high and EN1 is low, the NMOS transistors M2, M3, M5, M6, M7, and M8 are turned on, and the other NMOS transistors are turned off. At this time, the input differential serial signals VPin and VNin are input into the attenuation network, and the attenuation voltage levels VPout and VNout should be obtained as the points between the fixed resistors RS1p and RS1n, the fixed voltage divider resistors R4p and R4n, and the binary weight array attenuation resistors RS2p (R2p and R3p are connected in parallel) and RS2n (R2n and R3n are connected in parallel);

[0072] (8) When the external enable signals EN1, EN2, and EN3 are all high, the NMOS tubes are all turned on. At this time, the input differential serial signals VPin and VNin are input into the attenuation network. The attenuation voltage levels VPout and VNout should be obtained as the points between the fixed resistors RS1p, RS1n and the fixed voltage divider resistors R4p, R4n and the binary weight array attenuation resistors RS2p (R1p, R2p, R3p in parallel) and RS2n (R1n, R2n, R3n in parallel).

[0073] like Figure 3 As shown in the figure, it is a simulation result diagram of an amplitude-adjustable attenuation circuit network attenuator I for differential signal transmission of the present invention. It can be seen from the simulation results that under the above 8 working conditions, the signal attenuation network implemented by the attenuator I has a wide-band amplitude response flatness characteristic, which can achieve stable attenuation control within the preset working frequency band, and its attenuation can be controlled within the applicable range of -1dB to -6dB, corresponding to an attenuation ratio of 0.9 to 0.5 times (based on the input signal amplitude). It effectively achieves stable attenuation within the extended frequency range, overcomes the amplitude fluctuation problem of traditional attenuation circuits when working over a wide frequency, and is particularly suitable for front-end modules of communication systems that require precise control of signal strength. By adopting a multi-stage distributed attenuation architecture, the consistency of the attenuation amount of each frequency point is guaranteed, and at the same time, the attenuation parameter is continuously adjustable within a specified range.

[0074] like Figure 4 FIG. 1 is a schematic structural diagram of an amplitude-adjustable attenuation circuit network attenuator II for differential signal transmission according to the present invention. The attenuator II includes:

[0075] (1) Binary weighted adjustable capacitors CSp (C1p, C2p, C3p, C4p, C5p, C6p) and CSn (C1n, C2n, C3n, C4n, C5n, C6n), with the ratios of the binary weighted adjustable capacitors being 4:4:2:2:1:1 for C1p-C6p and 4:4:2:2:1:1 for C1n-C6n respectively;

[0076] (2) PMOS tubes M9, M10, M11, M12, M13, and M14.

[0077] Attenuator II utilizes a capacitor structure with a DC-to-AC impedance. By adjusting the capacitance of the capacitor components, it precisely controls the differential signal amplitude, ensuring that the common-mode voltage reference does not drift. To prevent signal imbalance and mismatch caused by MOS tube resistance, Attenuator II employs a fully symmetrical structure.

[0078] Due to its binary weighted adjustable capacitor quantity and ratio, Attenuator II has 8 operating states:

[0079] (1) When the external enable signals EN4, EN5, and EN6 are all high, the PMOS tubes are all turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Since all MOS are turned off, the differential mode levels of VP and VN will not be attenuated.

[0080] (2) When the external enable signal EN4 is low and EN5 and EN6 are high, the PMOS tubes M9 and M12 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C1p and C2p in parallel) and (C1n and C2n in parallel);

[0081] (3) When the external enable signal EN5 is low, and EN4 and EN6 are high, the PMOS tubes M10 and M13 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C3p and C4p in parallel) and (C3n and C4n in parallel);

[0082] (4) When the external enable signal EN6 is low and EN4 and EN5 are high, the PMOS tubes M11 and M14 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C5p and C6p in parallel) and (C5n and C6n in parallel);

[0083] (5) When the external enable signals EN4 and EN5 are low and EN6 is high, the PMOS tubes M9, M10, M12, and M13 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C1p, C2p, C3p, and C4p in parallel) and (C1n, C2n, C3n, and C4n in parallel);

[0084] (6) When the external enable signals EN4 and EN6 are low and EN5 is high, the PMOS tubes M9, M11, M12, and M14 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C1p, C2p, C5p, and C6p in parallel) and (C1n, C2n, C5n, and C6n in parallel);

[0085] (7) When the external enable signals EN5 and EN6 are low and EN4 is high, the PMOS tubes M10, M11, M13, and M14 are turned on, and the other PMOS tubes are turned off. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C3p, C4p, C5p, and C6p in parallel) and (C3n, C4n, C5n, and C6n in parallel);

[0086] (8) When the external enable signals EN4, EN5, and EN6 are all low, the PMOS tubes are all turned on. At this time, when the differential mode is input, the differential serial signals VP and VN are input into the attenuation network. Due to the characteristics of the capacitor, an AC ground is formed in the middle of the differential end. At this time, the differential mode level of the differential serial signals VP and VN will be attenuated by the capacitors (C1p, C2p, C3p, C4p, C5p, C6p in parallel) and (C1n, C2n, C3n, C4n, C5n, C6n in parallel);

[0087] like Figure 5 Figure 2 shows the simulation results of Attenuator II, an amplitude-adjustable attenuation circuit network for differential signal transmission according to the present invention. The simulation results show that under the eight operating conditions described above, the signal attenuation network implemented by Attenuator II exhibits a wideband amplitude response flatness, enabling stable attenuation control within a preset operating frequency band. The attenuation can be controlled within an applicable range of -0.3dB to -7dB, corresponding to an attenuation ratio of 0.97 to 0.45 times (based on the input signal amplitude), making it suitable for front-end modules of communication systems requiring precise control of signal strength. By adopting a multi-stage distributed attenuation architecture, the consistency of attenuation at each frequency point is ensured, while enabling continuous adjustment of the attenuation parameters within a specified range.

[0088] Although the present invention is disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An amplitude adjustable attenuation circuit network for differential signal transmission, characterized in that: It includes attenuator I and attenuator II; the attenuator I is used as a resistance attenuation circuit, the attenuator II is used as a capacitance attenuation network, and the attenuator I and attenuator II are connected through a common-mode feedback circuit; wherein, The input end of the attenuator 1 receives a differential signal sent from the outside, and after the differential signal is divided by the attenuator 1, the output differential signal enters the common-mode feedback circuit; The common-mode feedback circuit receives the differential signal sent from attenuator I, obtains the common-mode level of the differential signal, and then sends it to attenuator II. The attenuator II receives the differential serial signal sent from the common-mode feedback circuit, and the differential serial signal undergoes further differential-mode attenuation through the attenuator II.

2. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 1, characterized in that: The attenuator I includes: fixed resistors RS1p, RS1n, binary weight adjustable resistors R1p-R3p, R1n-R3n, fixed voltage divider resistors R4p, R4n, and NMOS transistors M1-M8; The input differential serial signals VPin and VNin are respectively input to one end of the fixed resistors RS1p and RS1n in the attenuator I; The gate of the NMOS transistor M1 is connected to the external enable signal EN1, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R1p; The gate of the NMOS transistor M2 is connected to the external enable signal EN2, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R2p; The gate of the NMOS transistor M3 is connected to the external enable signal EN3, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R3p; The gate of the NMOS transistor M4 is connected to the external enable signal EN1, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R1n; The gate of the NMOS transistor M5 is connected to the external enable signal EN2, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R2n; The gate of the NMOS transistor M6 is connected to the external enable signal EN3, the source is connected to GND, and the drain is connected to the binary weight adjustable resistor R3n; The gate of NMOS tube M7 is connected to VDD, the source is connected to GND, and the drain is connected to the fixed voltage divider resistor R4p to ensure that the resistor voltage divider state is long-term effective; The gate of the NMOS tube M8 is connected to VDD, the source is connected to GND, and the drain is connected to the fixed voltage divider resistor R4n to ensure that the resistor voltage divider state is long-term effective; One end of the binary weight adjustable resistors R1p, R2p, and R3p is connected to the output terminal VPout, and the other end is connected to the fixed resistor RS1p and the fixed voltage divider resistor R4p; One end of the binary weight adjustable resistors R1n, R2n, and R3n is connected to the output terminal VNout, and the other end is connected to the fixed resistor RS1n and the fixed voltage divider resistor R4n.

3. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 2, characterized in that: The resistance ratio of the binary weight adjustable resistors R1p, R2p, and R3p is 4:2:

1.

4. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 2, characterized in that: The resistance ratio of the binary weight adjustable resistors R1n, R2n, and R3n is 4:2:

1.

5. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 2, characterized in that: Also included are diodes D1-D4; wherein, The positive ends of diodes D1 and D2 are connected together, and the negative ends of diodes D1 and D2 are connected to the input terminal VPin of attenuator I and one end of fixed resistor RS1p respectively to form back-to-back diodes; The negative ends of the diodes D3 and D4 are connected to each other, and the positive ends of the diodes D3 and D4 are connected to the input end VNin of the attenuator I and one end of the fixed resistor RS1n respectively to form back-to-back diodes.

6. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 2, characterized in that: When the input differential signals VPin and VNin are input to attenuator I, they pass through fixed resistors RS1p and RS1n and then enter binary weighted adjustable resistors R1p-R3p and R1n-R3n controlled by an external enable signal to complete voltage division, attenuating the differential and common-mode values ​​of the input signals to a swing range that can be recognized by subsequent circuits.

7. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 1, characterized in that: The attenuator II includes: binary weight adjustable capacitors C1p-C6p, C1n-C6n, and PMOS tubes M9-M14; The common-mode feedback circuit inputs and ultimately outputs a differential serial signal VP, which is connected to the source of the PMOS transistors M9, M10, and M11, and one end of the binary weight adjustable capacitors C1p-C6p respectively; The common-mode feedback circuit inputs and ultimately outputs a differential serial signal VN, which is connected to the source terminals of the PMOS transistors M12, M13, and M14 and one end of the binary weight adjustable capacitors C1n-C6n respectively; The gate of the PMOS transistor M9 is connected to the external enable signal EN4, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C1n and C2n; The gate of the PMOS transistor M10 is connected to the external enable signal EN5, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C3n and C4n; The gate of the PMOS transistor M11 is connected to the external enable signal EN6, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C5n and C6n; The gate of the PMOS transistor M12 is connected to the external enable signal EN4, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C1p and C2p; The gate of the PMOS transistor M13 is connected to the external enable signal EN5, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C3p and C4p; The gate of the PMOS transistor M14 is connected to the external enable signal EN6, the source is connected to the input and output signal VP, and the drain is connected to the binary weight adjustable capacitors C5p and C6p.

8. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 7, characterized in that: The capacitance ratio of the binary weight adjustable capacitors C1p-C6p is 4:4:2:2:1:

1.

9. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 7, characterized in that: The capacitance ratio of the binary weight adjustable capacitors C1n-C6n is 4:4:2:2:1:

1.

10. The amplitude adjustable attenuation circuit network for differential signal transmission according to claim 7, characterized in that: When the input differential signals VP and VN are input to attenuator II, they pass through the binary weight adjustable capacitors C1p-C6p and C1n-C6n. At this time, the input differential signals VP and VN form an AC ground for the circuit, attenuating the differential mode of the input signal to a swing range that can be recognized by the subsequent circuit.

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