A soft decoding method, device, medium and product

Abstract

The present application discloses a soft decoding method, device, medium and product, which relate to the field of error correction coding technology, wherein the method is applied to low-density parity-check codes, including: obtaining a target low-density parity-check code containing erasure bits on both the information node and the check node; assigning a preset non-zero log-likelihood ratio value to the erasure bit located on the check node, and performing a first soft decoding. If the first soft decoding fails, it is determined whether to perform a second soft decoding based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information node. If it is determined that a second soft decoding is required, a preset non-zero log-likelihood ratio value is assigned to the erasure bit located on the information node, and a second soft decoding is performed. The present application effectively improves the success rate and efficiency of decoding by conditionally processing the erasure bits on different nodes in stages.

Description

Technical Field

[0001] The present application relates to the field of error correction coding technology, and in particular to a soft decoding method, device, medium and product. Background Art

[0002] In existing soft decoding techniques for low-density parity-check codes, the decoder's error correction capabilities are severely impacted when erasure bits located on both information and check nodes are present in the codeword to be decoded. These erasure bits are typically considered completely unreliable information, and their presence hinders the proper convergence of the decoding algorithm, leading to decoding failure. Existing decoding methods often fail to effectively distinguish and handle erasure bits located on different nodes and lack intelligent secondary decoding triggering mechanisms. Blindly retrying after a decoding failure not only results in a low success rate, but also wastes unnecessary computing resources and causes decoding delays.

[0003] Therefore, there is an urgent need for a new soft decoding method for low-density parity-check codes that can process erasure bits located on different nodes in a phased and conditional manner to solve the problem of low decoding success rate and lack of efficiency in the existing technology when processing codewords containing erasure bits. Summary of the Invention

[0004] The present application provides a soft decoding method, device, medium and product to solve the problem of low decoding success rate and lack of efficiency when processing codewords containing erasure bits in the prior art.

[0005] The present application provides a soft decoding method, which is applied to low-density parity-check codes and includes:

[0006] Obtaining a target low-density parity-check code; information nodes and check nodes of the target low-density parity-check code include erasure bits;

[0007] Assigning a preset non-zero log-likelihood ratio value to the erased bit located at the check node and performing a first soft decoding;

[0008] If the first soft decoding fails, a second soft decoding is determined based on the syndrome weight generated by the first soft decoding and the number of erased bits on the information node. The syndrome weight is the number of check nodes that failed the first soft decoding.

[0009] If a second soft decoding is performed, a preset non-zero log-likelihood ratio value is assigned to the erased bit located on the information node, and the second soft decoding is performed.

[0010] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned soft decoding methods when executing the computer program.

[0011] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned soft decoding methods are implemented.

[0012] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above soft decoding methods when executed by a processor.

[0013] This application first assigns a preset non-zero log-likelihood ratio value to the erasure bits located on the check nodes, and then performs a first soft decoding. Since the integrity of check nodes is crucial for maintaining the check relationship and convergence of the decoding algorithm during the decoding process of low-density parity-check codes, the presence of erasure bits on them is far more disruptive to the decoding process than that on information nodes. This method prioritizes the erasure bits on the check nodes that have the greatest impact on the decoding results, injecting critical probabilistic information into the decoder and effectively restoring the disrupted check relationship. Therefore, this method prioritizes addressing the most disruptive issues in the decoding process, significantly improving the success probability of the first soft decoding, thereby enhancing the overall error correction capability and data recovery success rate. Furthermore, if the first soft decoding fails, the method does not blindly perform a second decoding. Instead, it makes an intelligent decision based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information nodes. The syndrome weight directly reflects the number of unsatisfied check equations in a codeword and is an effective indicator of the degree of codeword error. By comprehensively considering the syndrome weight and the number of erasures on an information node, this method can pre-estimate the probability of successful decoding after processing the erasure bits on the information node. This method can therefore intelligently avoid unnecessary secondary decoding attempts that are doomed to fail due to excessive original errors, significantly saving processing time and power consumption, thereby optimizing overall decoding efficiency and reducing average decoding latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 A schematic diagram of a method flow of a soft decoding method provided in an embodiment of the present application;

[0016] Figure 2 A schematic diagram of the structure of the LDPC system code provided in an embodiment of the present application;

[0017] Figure 3A schematic diagram of a method flow of a soft decoder optimization method provided in an embodiment of the present application;

[0018] Figure 4 This is a schematic structural diagram of a soft decoding device provided in an embodiment of the present application;

[0019] Figure 5 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0022] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the soft decoding method depends, the specific application environment architecture or specific hardware architecture is described here.

[0024] First, the terms involved in this application are introduced.

[0025] SSD: Solid State Disk, a data storage device based on NAND flash memory.

[0026] NAND: A non-volatile flash memory technology, the core storage medium of solid-state drives. The read errors and "erase" phenomenon mentioned in the examples of this application are rooted in the physical properties of NAND flash memory (for example, the threshold voltage of the storage cell shifts and widens with use).

[0027] ECC: Error Correction Code, an error correction code, is a coding technology used to detect and correct errors generated during data storage or transmission. The present application embodiment focuses on a specific type of ECC, namely LDPC code.

[0028] LDPC: Low Density Parity Code. A powerful error-correcting code named for the low density of 1s in its check matrix.

[0029] LLR: Log-Likelihood Ratio. In soft decoding, this value represents the probability of a bit being 0 or 1. Its sign (positive or negative) indicates whether the bit is more likely to be 0 or 1, while its magnitude (absolute value) indicates the reliability of the judgment. An LLR of 0 indicates complete uncertainty, i.e., an "erasure."

[0030] RL: ReadLevel, read level or read reference voltage. A reference voltage applied by the controller when reading data from NAND flash memory.

[0031] SW: SyndromeWeight. The number of unsatisfied parity equations after the first iteration of LDPC decoding. It is a key metric used to measure the number and severity of initial errors in the codeword.

[0032] P / ECycle: Program / Erase Cycle. A basic NAND flash memory operation cycle, consisting of a program (write) and an erase. The number of P / E cycles is a key indicator of flash memory wear and lifespan.

[0033] FBC: Failed Bit Count, or FBC, refers to the number of original error bits in the codeword before decoding. The syndrome weight (SW) is positively correlated with FBC.

[0034] Page: The basic unit for read and write operations in NAND flash memory. The decoding operation in the embodiment of the present application is performed on a data page.

[0035] RAID: Redundant Array of Independent Disks. A high-overhead data recovery solution used after LDPC decoding failure.

[0036] Buffer: A hardware storage unit within the LDPC decoder that temporarily stores the results of multiple reads from the NAND flash memory.

[0037] Hostdata: Host data. This refers to user data sent by upper-layer systems (such as a computer operating system) to the SSD for storage. Its length is one of the factors that determine the LDPC code rate and related parameters.

[0038] amp, unr, and abn: These are the three variables used in the LLR configuration and represent the LLR amplitude. amp represents the LLR amplitude of bits located in the reliable region and is typically the largest. unr represents the LLR amplitude of bits located in the unreliable region (i.e., the threshold voltage overlap region) and is smaller than amp. abn is the LLR amplitude assigned to bits identified as erased.

[0039] (N, K)LDPC: A notation used to describe LDPC code parameters. N represents the total length of the codeword (information bits + check bits), and K represents the length of the information bits. The present embodiment utilizes the characteristics of systematic codes, where the positions of information bits and check bits are fixed, making it easier to distinguish between information nodes and check nodes.

[0040] SyndromeWeightThreshold: Syndrome weight threshold. This is a pre-set value used to determine whether the initial error of the codeword exceeds the upper limit of the LDPC decoder's error correction capability.

[0041] With the continuous advancement of NAND flash memory technology, the density of storage cells has increased, resulting in a dramatic compression of the voltage threshold window between cells. This makes data more susceptible to physical noise, read / write disturb, and charge leakage during storage and retrieval, leading to a significant increase in raw bit error rates. To ensure data reliability, modern solid-state drive (SSD) controllers commonly use low-density parity-check (LDPC) codes, which offer extremely strong error correction capabilities. To fully exploit the error correction potential of LDPC codes, controllers typically employ soft decoding techniques. This involves performing multiple reads of NAND flash memory cells (for example, using a center reference voltage and multiple offset reference voltages) to obtain soft information with probabilistic confidence. This soft information is typically represented as a log-likelihood ratio (LLR), where the sign represents the probability of a bit being 0 or 1, and the magnitude represents the reliability of that determination. However, during the physical read process, illogically incorrect anomalous read result combinations (such as "011" or "100") may occur. Traditionally, these anomalous results are assigned an LLR value of 0, which, in information theory, is equivalent to an "erasure."

[0042] The presence of erasure bits is extremely detrimental to the LDPC decoding process. On the one hand, a large number of erasure bits reduces the initial effective information available to the decoder, hindering the convergence of the belief propagation algorithm. On the other hand, the location of the erasure bits is crucial: if the erasure occurs on an information node, decoding can still be recovered; however, if it occurs on a check node, it directly destroys the integrity of the associated parity check equation, easily causing the decoding algorithm to fail and not converge.

[0043] To address soft decoding failures, existing technologies typically employ two strategies: First, multi-stage soft decoding requires performing more physical read operations, but this introduces significant additional read latency, severely impacting SSD performance. Second, after a decoding failure, subsequent data recovery mechanisms, such as RAID, are initiated, but this consumes significant host computing resources and storage overhead. These existing methods generally lack targeted treatment of the causes of failure within the decoder and an intelligent judgment mechanism to avoid unnecessary and costly secondary decoding attempts when the chances of successful decoding are slim. Therefore, an optimization method is urgently needed that can efficiently handle erasure issues within the decoder and intelligently control the decoding process.

[0044] Therefore, an embodiment of the present application provides a soft decoding method, which is applied to low-density parity-check codes. The process of the method is as follows: Figure 1 As shown, the following steps are included:

[0045] S101, obtaining a target low-density parity-check code;

[0046] Specifically, in step S101, the target low-density parity-check code's information nodes and check nodes contain erasure bits. This step first requires obtaining a specific codeword to be processed. This codeword is not arbitrary; it has a clear characteristic: erasure bits are known to exist in both its information nodes and its check nodes.

[0047] S102: Assign a preset non-zero log-likelihood ratio value to the erased bit located on the check node, and perform a first soft decoding.

[0048] Specifically, in step S102, the non-zero log-likelihood ratio value is a value assigned to the erased bit. Its key attribute is non-zero, which means that it provides certain non-zero probability information for the originally erased bit.

[0049] S103: If the first soft decoding fails, determine whether to perform a second soft decoding based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information node.

[0050] Specifically, the syndrome weight is the number of check nodes that failed verification after the first soft decoding; it directly measures the severity of the failure of the first soft decoding operation or the number of remaining errors.

[0051] This step is triggered only after the first soft decode fails. If the first soft decode succeeds, this step is not performed. The decision is based on two key pieces of information: the syndrome weight generated after the first soft decode fails and the total number of erased bits on the information node. These two pieces of information are combined to determine whether to proceed with the second soft decode.

[0052] S104: If a second soft decoding is performed, a preset non-zero log-likelihood ratio value is assigned to the erased bit located on the information node, and the second soft decoding is performed.

[0053] Specifically, step S104 is executed only if the result of the determination is to perform a second soft decoding. Unlike the second step, this step processes all erasure bits located on the information node. The processing method is similar to the second step, namely, assigning a preset non-zero log-likelihood ratio value to each of these erasure bits located on the information node. After the assignment is complete, the second soft decoding is performed.

[0054] In summary, the soft decoding method of the embodiments of the present application first assigns a preset non-zero log-likelihood ratio value to the erasure bits located on the check nodes and performs a first soft decoding. Since the integrity of check nodes is crucial for maintaining the check relationship and convergence of the decoding algorithm during the decoding process of low-density parity-check codes, the presence of erasure bits on them is far more disruptive to the decoding process than that of information nodes. By prioritizing the erasure bits on the check nodes that have the greatest impact on the decoding results, this method injects critical probabilistic information into the decoder, effectively restoring the disrupted check relationship. Therefore, this method can prioritize addressing the most disruptive issues in the decoding process, significantly improving the success probability of the first soft decoding, thereby enhancing the overall error correction capability and data recovery success rate. Furthermore, if the first soft decoding fails, the method does not blindly perform a second decoding. Instead, it makes an intelligent judgment based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information nodes. The syndrome weight directly reflects the number of unsatisfied check equations in a codeword and is an effective indicator of the degree of codeword error. By comprehensively considering the syndrome weight and the number of erasures on an information node, this method can pre-estimate the probability of successful decoding after processing the erasure bits on the information node. This method can therefore intelligently avoid unnecessary secondary decoding attempts that are doomed to fail due to excessive original errors, significantly saving processing time and power consumption, thereby optimizing overall decoding efficiency and reducing average decoding latency.

[0055] In an optional implementation, the low-density parity-check code is a systematic code; the information nodes and check nodes of the low-density parity-check code correspond to information bit regions and check bit regions preset in the low-density parity-check code, respectively.

[0056] The structural characteristics of the systematic code ensure that information bits and check bits are physically separated and fixed in location. This allows the decoder to distinguish node types through simple address determination, eliminating the need for complex graph structure analysis when performing the first step (check node processing) and subsequent steps (statistical information node erasure) of the present invention. This transformation of a logical node type distinction into a physical address range determination is crucial for hardware decoder designs striving for high throughput and low latency, significantly reducing implementation cost and difficulty.

[0057] In an optional implementation, obtaining a target low-density parity-check code includes:

[0058] A storage medium storing a low-density parity-check code to be soft-decoded is read multiple times to obtain multiple reading results; based on the multiple reading results, a preset reading combination on the low-density parity-check code to be soft-decoded is identified to identify erasure bits on information nodes and check nodes in the low-density parity-check code to be soft-decoded, thereby obtaining a target low-density parity-check code.

[0059] By performing multiple reads on the storage medium and identifying specific preset read combinations (i.e., abnormal read patterns) based on the read results, erased bits can be located. This demonstrates that erased bits are not random errors, but are caused by specific, identifiable, and physically illogical read result sequences.

[0060] A storage medium storing a low-density parity-check code to be soft-decoded is read multiple times, including:

[0061] A storage medium storing a low-density parity check code to be soft-decoded is read multiple times using a central read reference voltage and at least one read reference voltage offset based on the central read reference voltage.

[0062] Multiple reads are embodied as using a central read reference voltage and at least one offset read reference voltage, that is, by sampling at the center and edge of the threshold voltage distribution to obtain soft information (LLR) with probabilistic confidence.

[0063] In an optional embodiment, the sign of the preset non-zero log-likelihood ratio value is determined by a reading result obtained by using a central read reference voltage.

[0064] In an abnormal read combination, the center voltage reading is generally considered to be the most representative reference for the original data's logical value. This feature, based on this understanding, assigns the erased bit a probability direction that is most likely to be correct (i.e., determines whether it is more likely to be 0 or 1). Rather than random guessing, this feature utilizes the most reliable information from the abnormal read result to perform probabilistic injection. This increases the probability of the injected information being correct, thereby further improving the success rate of subsequent decoding without increasing complexity.

[0065] The amplitude of the preset non-zero log-likelihood ratio value is less than or equal to the amplitude of the first log-likelihood ratio value; wherein the first log-likelihood ratio value corresponds to a bit located in an unreliable area; a bit located in an unreliable area is a bit located in an unreliable area when, in multiple reading results of the first bit, the result of the offset reading is different from the reading result of the center read reference voltage, then the first bit is determined to be a bit located in the unreliable area.

[0066] The bits in the unreliable region inherently represent low-confidence information. This feature limits the LLR amplitude of the erased bits after repair to a lower or equal level, ensuring that the decoder treats this repaired information as the least confident of all bits with valid information. This ensures that even if the symbol determined by the center voltage reading is erroneous, its negative impact on the entire decoding iteration is minimized, preventing decoding degradation caused by the injection of highly probable erroneous information, making the entire optimization scheme more secure and reliable.

[0067] In an optional implementation, the amplitude of the preset non-zero log-likelihood ratio value is equal to the amplitude of the first log-likelihood ratio value minus one.

[0068] In an optional implementation, determining whether to perform a second soft decoding based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information node includes:

[0069] When the difference between the syndrome weight and the number of erased bits located on the information node is smaller than a preset syndrome weight threshold, it is determined to perform a second soft decoding.

[0070] When the difference is greater than or equal to the preset syndrome weight threshold, it is determined not to perform the second soft decoding.

[0071] The syndrome weight reflects the overall error level of a codeword, while the erasure bits on an information node are known and likely erroneous. The difference between these two values ​​provides a more accurate estimate of the true number of errors inherent in the codeword, beyond the known uncertainties. Comparing this more precise metric with the decoder's upper limit (threshold) enables more accurate decision-making. This precise judgment more effectively identifies codewords with a high probability of being corrected, maximizing the advantages of the conditional judgment mechanism in avoiding invalid decoding and improving efficiency. Furthermore, the triggering conditions for terminating the decoding process are clearly defined. By decisively abandoning codewords predicted to be undecodeable, unnecessary decoding iterations are avoided, significantly saving controller computation time and power consumption, and directly contributing to improved SSD performance and responsiveness under high loads.

[0072] The preset syndrome weight threshold is determined according to the code length and code rate of the low-density parity-check code.

[0073] LDPC codes of different code lengths and rates have different inherent error correction capabilities. Linking the judgment threshold to these two basic parameters means that the threshold is dynamically adapted to the specific LDPC code currently in use. This ensures that regardless of the LDPC code specification used by the system, its core conditional judgment logic always operates optimally, thus ensuring that this invention consistently delivers its efficiency-enhancing advantages across different SSD products and technology generations.

[0074] In an optional embodiment, the method further includes:

[0075] If it is determined that the second soft decoding is not to be performed or the second soft decoding still fails, a data recovery operation is initiated. The data recovery operation includes: reconstructing the data using redundant parity information; or performing a reread operation on the storage medium storing the low-density parity check code after adjusting the read reference voltage.

[0076] In an optional embodiment, the amplitude of the preset non-zero log-likelihood ratio value assigned to the erasure bit located on the check node or the erasure bit on the information node is dynamically adjusted based on the syndrome weight generated after the first soft decoding failure; specifically, the amplitude is inversely proportional to the syndrome weight.

[0077] In summary, the soft decoding method provided by the embodiments of the present application, through multiple readings using center and offset reference voltages, can accurately identify specific erasure bit combinations caused by physical anomalies. Before the first soft decoding, all erasure bits are not treated equally. Instead, the structural convenience of the system code is utilized to prioritize the location and processing of erasure bits on check nodes that are crucial for decoding convergence. During processing, it uses a set of logically rigorous log-likelihood ratio injection rules, whose sign is determined by the most reliable center voltage reading result, ensuring the high accuracy of the direction of probability injection; its amplitude is set to be smaller than that of unreliable areas, or even a certain lower value. This ensures that even if the probability injection is misjudged, its negative impact on the decoding process is limited to a minimum, thereby greatly ensuring the stability and robustness of the method while improving the first decoding success rate. When the first decoding attempt fails, instead of blindly attempting a second attempt, the syndrome weight returned after the decoding failure is subtracted from the number of erasure bits on the information node, and the difference is compared with an adaptive threshold related to the code length and code rate. This difference can more accurately reflect the number of real errors in the codeword other than the known uncertainty than the simple syndrome weight. This judgment logic can extremely accurately predict the success potential of secondary decoding. If the predicted success is hopeless, the secondary decoding is decisively abandoned and the subsequent data recovery operation is directly started, thereby avoiding a large number of decoding iterations that are doomed to be futile and consume controller computing resources and time. This greatly optimizes the average decoding delay and power consumption. The method of the embodiment of the present application organically combines a series of technical features such as physical reading, node type differentiation, phased LLR repair, risk-controlled LLR assignment rules, and intelligent gating logic based on syndrome weight. Without adding any additional physical read delay, it achieves the dual beneficial effects of improving the decoding success rate and maximizing the decoding efficiency, providing a comprehensive and sophisticated solution to the data reliability problem in high-density flash memory.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0079] Illustratively, a specific example is used below to illustrate the soft decoding method provided by the above embodiment.

[0080] Taking the first-level soft decoding (i.e., three readings) as an example, the above soft decoding method is described in detail.

[0081] NAND flash memory will have a read error in the overlapping area of ​​the left and right threshold distributions. After applying the following read reference voltage RL to each memory cell, if it is conductive (i.e., located on the left side of RL), it returns 1; if it is not conductive (located on the right side of RL), it returns 0. In order to obtain the probability information of 0 and 1, the SSD master controller sends multiple read commands to the NAND flash memory, that is, using the read reference voltage based on RL. Read the left and right offsets in sequence. To identify the three reading results. If the three reading results are consistent (111 or 000), it is considered that the storage unit is in a reliable area and a large LLR value is configured, such as , maximum amplitude Determined by the master. If the result of one of the left and right offset reads is different from the RL read, the storage unit is located in an unreliable area near the RL and is configured with an LLR with a smaller amplitude, for example For read results that are impossible in actual physical situations, such as 011 or 100, the LLR is configured as 0, which is erasure in decoding.

[0082] If the left peak of the threshold voltage distribution is 1 and the right peak is 0, after three reads, four reasonable read results will appear: 111 / 110 / 010 / 000. However, in the actual measured results, in addition to the four results mentioned above, four other abnormal situations will also appear that do not meet expectations. Similarly, if the left peak of the threshold voltage distribution is 0 and the right peak is 1, the normal read results will appear as 000 / 001 / 101 / 111. The other four results are also illogical. Combining the two threshold distributions, in any page, it is unreasonable for either 011 or 100 to appear in three reads. Through testing of multiple NAND chips, it was found that the probability of occurrence is not negligible.

[0083] Unreasonable reading results are usually due to interference factors such as electrical noise. This interference cannot be predicted and can be regarded as erasure for LDPC codes. If erasure is not handled, the soft decoding error correction capability will be reduced. Usually, different levels of soft decoding quantization schemes are set to perform multi-level soft decoding. After the first level soft decoding fails, the second level soft decoding operation is performed. The second level soft decoding is based on the first level soft decoding and divides the reading interval into additional intervals in the threshold distribution. If the first soft decoding fails, by increasing the quantization interval, for example, On the basis of Two read reference voltages are used, and an additional read operation is performed before soft decoding. If only one level of soft decoding is used, subsequent data recovery solutions, such as rereading and RAID, will be used after a soft decoding failure. Multi-level soft decoding requires multiple reads before each soft decoding execution, which multiplies the read latency. RAID and other methods also consume a large amount of host control resources. However, neither the decoder nor the firmware handles erase.

[0084] Erasures in soft decoding are essentially caused by abnormalities in the NAND read results. After configuring the LLRs, additional raw error bits are introduced into the decoder input. The introduction of more erasures may exceed the soft decoding's error correction capability, causing soft decoding failure. Therefore, an embodiment of the present application also provides an LDPC soft decoder optimization method, including the following process.

[0085] When configuring LLR for the data read three times in the decoder, check the three read results of each bit in turn. If an abnormality of 011 or 100 is detected in the three read results, the LLR is no longer configured to 0, but to , where the amplitude setting requirements are:

[0086] ;

[0087] Where unr represents the LLR amplitude of bits located in the unreliable region (i.e., the threshold voltage overlap region), and abn is the LLR amplitude assigned to bits identified as erased.

[0088] That is, the amplitude of the erased LLR is smaller than the amplitude of the unreliable region in the threshold voltage distribution, and the positive or negative of the corresponding LLR is determined by the result of the RL read. In other words, if 011 appears, the LLR configuration bit , if 100 appears, the LLR is configured as In this embodiment, it is possible to set .

[0089] In this embodiment, LDPC is a system code, such as Figure 2 As shown, in (N, K) LDPC, the first K lengths are information bits, corresponding to information nodes in LDPC code decoding, and the last (NK) lengths are generated check bits, corresponding to check nodes during decoding.

[0090] Before the first soft decoding, only the erasure on the check node is preprocessed. The check node position can be easily located in the preprocessing. For the data after three reads, only the check bit after (NK) is checked for abnormality of 011 or 100. If found, the LLR of the position is configured as The configured LLR is used as the soft decoding input and the soft decoding operation is performed. If the decoding is successful, the correct data is returned to the user.

[0091] If the first soft decoding fails, the syndrome weight is used to determine whether a second soft decoding operation is necessary. The syndrome weight for LDPC decoding is the number of check nodes that failed verification after the first decoding iteration. The LDPC decoder sets a syndrome weight threshold as a criterion for determining whether the input data exceeds the error correction capability. If the syndrome weight exceeds the threshold after the first decoding, the decoder stops the iteration and returns a decoding failure, avoiding wasted iteration delay. This feature is used to determine whether erasures in the information bits require secondary decoding.

[0092] Specifically, the erasures in the information bits are checked and counted, and the number of erasures in the information bits is recorded as n. The syndrome weight bit returned after the first decoding failure is If the threshold judgment formula is not met, that is, after removing the influence of erasure on the information bit, it still exceeds the error correction capability of LDPC, then no post-processing operation is required and the decoding failure is directly returned. On the contrary, if it is less than the threshold , then perform post-processing decoding operation, that is, use the above processing scheme to modify the LLR of all information bits to be erased After that, continue the soft decoding iteration operation. The threshold judgment formula is:

[0093] ;

[0094] Where, is the syndrome weight returned when the decoding fails for the first time, n is the number of erasures in the information bit, is the threshold.

[0095] The specific implementation process of this method is as follows Figure 3 As shown, the following steps are included:

[0096] The same page of NAND flash memory is read three times in a row, using the voltage axis , input the three reading results into the LDPC decoder and store them in the decoder buffer;

[0097] When the decoder configures LLR, it checks the three reading results of each bit in turn. For the reliable region, the LLR is configured as , unreliable area configuration .

[0098] All check nodes are checked for erasure. The position of the check node corresponds to the check bit of the LDPC code. After detecting the erasure of 011 or 100 type, the LLR value of the position is configured as and , amplitude The setting should be smaller than the LLR amplitude of the unreliable area, that is ;

[0099] The configured LLR is used as decoder input and soft decoding is performed. If the decoding is successful, the decoding success is reported and the user data is returned.

[0100] If decoding fails, count the number of erasures in the information bits and check whether the difference between the syndrome weight of the first decoding and the number of erasures is less than the syndrome weight threshold. If the above judgment formula is satisfied, then for all erased positions in the information bits, follow the same configuration rules for the check nodes and modify the LLRs for the positions of 011 and 100 to After that, additional iterative operations are performed based on the first decoding. , then the decoding stops directly and reports that the soft decoding failed.

[0101] This embodiment addresses the issue of read anomalies encountered during soft decoding operations in solid-state drives, which can lead to the introduction of erasure information during LLR configuration, thereby reducing the soft decoding's error correction capabilities. A solution for addressing erasures is proposed. For erasure nodes, a small-amplitude LLR probability is configured, and the positive or negative sign of this probability is determined by the RL read result. This is based on the understanding that an anomaly may occur in one of the last two reads out of three. If the RL read result is erroneous, the small-amplitude LLR ensures that the embedded probability information has a minimal impact.

[0102] Taking advantage of the fact that erasure affects the integrity of check nodes in LDPC codes and that solid-state drives primarily use systematic codes, we divide the erasure handling in soft decoding into two steps. The first step is to pre-process only the check nodes before soft decoding.

[0103] If soft decoding fails, the system detects and counts the number of erasure bits in the information bits, obtains the syndrome weight returned in the decoding failure, and determines whether the decoding capability is still exceeded after removing the effects of erasures. If it still exceeds the decoding capability, no further processing is required and the decoding failure is directly reported. Data recovery operations are then performed to avoid unnecessary re-decoding.

[0104] On the contrary, if the requirements are met, that is, the difference between the syndrome weight and the number of information bits erased is less than , the probability information is also placed in the erasure of the information bit, and the second decoding iteration is performed. If successful, the data is returned to the host. If the decoding still fails, the subsequent data processing operation is performed.

[0105] This embodiment is described by taking three reads of the first-level soft decoding as an example. For multi-level soft decoding, such as five reads of the second-level soft decoding, the method of this embodiment is also applicable to erasure caused by read anomalies.

[0106] This embodiment performs pre- and post-processing on the soft decoder to address erasure anomalies. By modifying the LDPC decoder's input LLRs and performing additional decoding iterations, the impact of erasures on decoding performance is reduced. Before decoding, only the parity information is pre-processed, reducing the probability of introducing additional errors by inserting probability information into erasure nodes. After a first decoding failure, the syndrome weight and the number of information bit erasures are compared with the syndrome weight threshold. If the decoding capacity is exceeded, a second decoding attempt is not performed, avoiding unnecessary decoding delays.

[0107] In summary, this embodiment processes erasure nodes in LDPC decoding caused by abnormal conditions during NAND flash memory reads. By taking advantage of the different effects of erasure on check nodes and information nodes, the erasure of data information bits and the erasure of check bits are processed twice, thus avoiding the degradation of soft decoding error correction capabilities caused by the introduction of erasure. To avoid introducing errors in the embedded probability information, a small-amplitude LLR value is selected for setting. Before the first decoding, only the erasure of the check node is processed. If the first soft decoding still fails, the judgment is made based on the returned syndrome weight, the number of information bit erasures, and the threshold provided by the master control, avoiding additional and unnecessary secondary decoding. If the requirements are met, the probability information of the introduced information node erasure is processed again, and the soft decoding iteration operation is performed again. Compared with multi-level decoding, no additional flash memory read operations are introduced, no additional flash memory read time is consumed, and the soft decoding error correction success rate is effectively improved.

[0108] The embodiment of the present application also provides a soft decoding device, the structure of which is as follows: Figure 4 As shown, the device is applied to low-density parity-check codes and includes:

[0109] An acquisition module 401 is configured to acquire a target low-density parity-check code; the information nodes and check nodes of the target low-density parity-check code include erasure bits;

[0110] A first soft decoding module 402 is configured to assign a preset non-zero log-likelihood ratio value to the erased bit located on the check node and perform a first soft decoding;

[0111] A determination module 403 is configured to determine whether to perform a second soft decoding if the first soft decoding fails based on a syndrome weight generated by the first soft decoding and the number of erasure bits located on the information node; the syndrome weight is the number of check nodes that failed verification after the first soft decoding;

[0112] The second soft decoding module 404 is configured to assign a preset non-zero log-likelihood ratio value to the erasure bit located on the information node and perform the second soft decoding if the second soft decoding is performed.

[0113] For the description of the features in the embodiment corresponding to the soft decoding device, reference can be made to the relevant description of the embodiment corresponding to the soft decoding method, which will not be repeated here.

[0114] The embodiment of the present application also provides an electronic device, such as Figure 5 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any one of the above soft decoding method embodiments.

[0115] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned soft decoding method embodiments when running.

[0116] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0117] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned soft decoding method embodiments are implemented.

[0118] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned soft decoding method embodiments are implemented.

[0119] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] The above describes in detail the soft decoding method, apparatus, device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is intended only to help understand the method and core concept of the present application. It should be noted that those skilled in the art may make various improvements and modifications to the present application without departing from the principles of the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A soft decoding method, characterized in that: The method is applied to low-density parity-check codes, and comprises: Obtaining a target low-density parity-check code; wherein the information nodes and check nodes of the target low-density parity-check code include erasure bits; Assigning a preset non-zero log-likelihood ratio value to the erased bit located at the check node and performing a first soft decoding; If the first soft decoding fails, determining whether to perform a second soft decoding is based on the syndrome weight generated by the first soft decoding and the number of erased bits on the information node; the syndrome weight is the number of check nodes that failed the first soft decoding. If a second soft decoding is performed, a preset non-zero log-likelihood ratio value is assigned to the erased bit located on the information node, and the second soft decoding is performed; The step of obtaining a target low-density parity-check code comprises: Performing multiple reads on a storage medium storing a low-density parity-check code to be soft-decoded to obtain multiple read results; Identifying a preset reading combination on the low-density parity-check code to be soft-decoded based on the multiple reading results to identify erasure bits on information nodes and check nodes in the low-density parity-check code to be soft-decoded, and obtaining a target low-density parity-check code; The determining whether to perform a second soft decoding based on the syndrome weight generated by the first soft decoding and the number of erasure bits located on the information node includes: When the difference between the syndrome weight and the number of erased bits located on the information node is less than a preset syndrome weight threshold, determining to perform a second soft decoding; When the difference is greater than or equal to a preset syndrome weight threshold, it is determined not to perform the second soft decoding.

2. The method according to claim 1, characterized in that The method of reading a storage medium storing a low-density parity-check code to be soft-decoded multiple times includes: A storage medium storing a low-density parity check code to be soft-decoded is read multiple times using a central read reference voltage and at least one read reference voltage offset based on the central read reference voltage.

3. The method according to claim 2, characterized in that The sign of the predetermined non-zero log-likelihood ratio value is determined by a reading result obtained by reading using the central read reference voltage.

4. The method according to claim 3, characterized in that The magnitude of the preset non-zero log-likelihood ratio value is less than or equal to the magnitude of the first log-likelihood ratio value; wherein the first log-likelihood ratio value corresponds to a bit located in an unreliable region; The bit located in the unreliable area is determined to be a bit located in the unreliable area when, in multiple reading results of the first bit, a result of offset reading is different from a reading result of the central read reference voltage.

5. The method according to claim 4, characterized in that The magnitude of the preset non-zero log-likelihood ratio value is equal to the magnitude of the first log-likelihood ratio value minus one.

6. The method according to claim 1, characterized in that The preset syndrome weight threshold is determined according to the code length and code rate of the low-density parity-check code.

7. The method according to claim 6, characterized in that The low-density parity-check code is a systematic code; the information nodes and check nodes of the low-density parity-check code correspond to an information bit region and a check bit region preset in the low-density parity-check code, respectively.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: When it is determined not to perform the second soft decoding or the second soft decoding still fails, the data recovery operation is started.

9. The method according to claim 8, characterized in that The data recovery operation includes: Reconstruct data through redundant parity information; or perform a reread operation on the storage medium storing the low-density parity check code after adjusting the read reference voltage.

10. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the soft decoding method according to any one of claims 1 to 9 when executing the computer program.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the soft decoding method according to any one of claims 1 to 9.

12. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the soft decoding method according to any one of claims 1 to 9 are implemented.

Images