Dynamic circuit and selection circuit suitable for switch, switch and system

Abstract

The invention discloses a dynamic circuit and selection circuit suitable for a switch, the switch and a system, the dynamic circuit comprises selection circuits in one-to-one correspondence with transmission ports of the switch, and the selection circuits are used for controlling the transmission ports corresponding to the selection circuits to be electrically connected with one of other transmission ports; the selection circuit comprises a first port and a plurality of second ports, the first port is used for being electrically connected with a transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected with other transmission ports in a one-to-one correspondence manner, one of the first port and the second port is an input end, and the other port is an output port; the first port and the second port are respectively and electrically connected to form a plurality of transmission lines, each transmission line is provided with a plurality of controllable switches, and the controllable switches are used for controlling at most one transmission line to be conducted at the same moment. The data transmission delay of the switch can be reduced, and the working efficiency and the overall performance of the switch can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer network equipment, and in particular to a dynamic circuit, a selection circuit, a switch and a system suitable for a switch. Background Art

[0002] With the development of artificial intelligence (AI) technology, computing demands are increasing, prompting switches to expand the number of GPUs to meet the increased computing power. To this end, the number of ports on switches continues to increase, which in turn increases the number of input lines for high-fan-gate circuits between ports. However, to reduce power consumption and increase transistor switching speed, modern process technologies have continuously reduced transistor threshold voltages, resulting in a weakening of the driving capability of traditional high-fan-gate circuits, which are gradually being replaced by circuits composed of multiple low-fan-gate circuits.

[0003] like Figure 1 As shown, multiple low fan-in circuits are cascaded to create a high fan-in circuit to accommodate the increasing number of port inputs. These low fan-in circuits operate synchronously via clock signals, ensuring correct data transmission between different ports. While low fan-in circuits offer lower power consumption and a simpler circuit design, meeting switch scalability requirements to a certain extent, this cascaded circuit design requires data to wait for the clock signal, resulting in significant latency.

[0004] In summary, while low-fan gates offer advantages like low power consumption and simple design, they require a clock signal before data can be transmitted. This results in significant latency during data transmission between these gates. This latency not only impacts the switch's transmission efficiency but also limits overall system performance.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the Invention

[0006] The purpose of the present invention is to provide a dynamic circuit, a selection circuit, a switch and a system applicable to a switch, which can improve the data transmission delay problem of the switch and enhance the working efficiency and overall performance of the switch.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A dynamic circuit applicable to a switch, the dynamic circuit comprising a plurality of selection circuits, the selection circuits corresponding one to one with transmission ports of the switch, the selection circuits being configured to control the electrical connection between the corresponding transmission port and one of the other transmission ports;

[0009] The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, and the plurality of second ports are electrically connected to the other transmission ports in a one-to-one correspondence. It should be noted that "the plurality of second ports are electrically connected to the other transmission ports in a one-to-one correspondence" in the present invention includes two situations: one is that the plurality of second ports are directly electrically connected to the other transmission ports in a one-to-one correspondence; the other is that the plurality of second ports are directly electrically connected to the first ports corresponding to the other transmission ports in a one-to-one correspondence, and of the first port and the second port, one port is configured as an input port, and the other port is configured as an output port;

[0010] The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are provided on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

[0011] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the selection circuit further includes a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches;

[0012] A combination of control circuits where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme for the corresponding transmission circuit, and control schemes for different transmission circuits are not repeated.

[0013] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of the control lines is not less than Among them, log is the logarithm operator, Indicates rounding up log2(N-1).

[0014] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the number of the control circuits is The number of NMOS switches provided on each transmission line is not less than

[0015] Furthermore, according to any one of the above technical solutions or a combination of multiple technical solutions, the number of NMOS switches provided on each of the control circuits is not greater than

[0016] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of the control lines is not less than Among them, log is the logarithm operator, Indicates rounding up log2(N-1).

[0017] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the number of the control circuits is The number of CMOS switches provided on each transmission line is not less than

[0018] Furthermore, according to any one of the above technical solutions or a combination of multiple technical solutions, the number of CMOS switches provided on each of the control circuits is not greater than

[0019] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the dynamic circuit further includes a clock signal management circuit, the clock signal management circuit including a first switching transistor, a second switching transistor, and a capacitor, wherein the gate of the first switching transistor is configured as an input end of the clock signal, the source of the first switching transistor is configured to be electrically connected to the output end of the first power supply, and the drain of the first switching transistor is electrically connected to the first end of the capacitor;

[0020] The gate of the second switch tube is configured as an input end of the clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor;

[0021] The clock signal management circuit corresponds to the selection circuit in a one-to-one manner, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

[0022] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the method further includes determining the clock signal of each selection circuit when it is working by:

[0023] If the capacitor is in a non-charged state, the clock signal must be 0; otherwise, the clock signal is 1;

[0024] and / or,

[0025] It also includes determining the output signal of the selection circuit when it is working in the following way: when the clock signal is monitored to be 0, the capacitor is in a charging and discharging state; if the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1.

[0026] Furthermore, based on any one of the aforementioned technical solutions or a combination of multiple technical solutions, the first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube.

[0027] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, each of the selection circuits is layered on the same circuit unit, the number of transmission ports of the switch is N, and the circuit unit is correspondingly provided with N layers of selection circuits;

[0028] Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on circuits of different layers.

[0029] Furthermore, according to any one of the aforementioned technical solutions or a combination of multiple technical solutions, one controllable switch is provided on each of the transmission lines, and each of the controllable switches is configured to be independently controlled.

[0030] According to another aspect of the present invention, the present invention provides a network selection circuit, comprising a first port and a plurality of second ports, wherein the first port and the second port are two ports, one of which is configured as an input port and the other is configured as an output port;

[0031] The first port is electrically connected to each of the second ports to form a plurality of transmission lines, and a plurality of controllable switches are provided on each of the transmission lines, wherein the controllable switches are configured to control at most one of the transmission lines to be conductive at a time;

[0032] The selection circuit further includes a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches;

[0033] A combination of control circuits where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme for the corresponding transmission circuit, and control schemes for different transmission circuits are not repeated.

[0034] According to another aspect of the present invention, the present invention provides a switch, which includes the dynamic circuit described in any one of the above technical solutions or a combination of multiple technical solutions.

[0035] According to another aspect of the present invention, a computer system is provided, comprising a switch as described in any one of the above technical solutions or a combination of multiple technical solutions, and a device electrically connected to a transmission port of the switch and requiring data transmission.

[0036] The beneficial effects brought about by the technical solution provided by the present invention are as follows:

[0037] a. This invention simplifies the logic gates of the numerous repetitive cascaded multiplexers and demultiplexers in a switch, constructing multiple linear transmission lines from the second port to the first port. By controlling a matrix of multiple transmission lines equipped with controllable switches, data from different sources can be output to the target end. This dynamic circuit can rapidly receive transmitted data within a single clock cycle, avoiding the delay caused by waiting for clock signals in traditional multi-cascade circuits. Furthermore, data from other transmission ports of the switch can be smoothly transmitted to another transmission port of the switch through the corresponding selection circuits of the other transmission ports, further improving data transmission speed and efficiency while reducing circuit complexity.

[0038] b. The logic function circuits of each selection circuit in the present invention can operate independently, reducing the reliance on multiple cascaded circuits and lowering the expansion cost of the switch. Furthermore, the first port in the selection circuit can be either an output port or an input port, facilitating bidirectional data transmission between the two transmission ports of the switch. Furthermore, two transmission lines are provided between the two transmission ports of the switch, enabling simultaneous bidirectional data transmission between the two transmission ports of the switch.

[0039] c. By designing a network-type selection circuit, the present invention can control data transmission between multiple transmission ports using fewer control lines. The greater the number of transmission ports in a switch, the greater the advantages in reducing data transmission delay, simplifying circuit design, and improving switch data transmission reliability. Furthermore, the use of NMOS switches in the selection circuit, which offer lower power consumption and faster switching speeds, can further reduce switch data transmission delay.

[0040] d. The present invention provides a clock signal management circuit connected to a corresponding selection circuit. By detecting whether the capacitor in the clock signal management circuit is discharged, it can be determined whether the clock signal output is 0 or 1 and whether the output end of the selection circuit is a high-level signal or a low-level signal. The clock signal corresponding to the data transmission of each port in the selection circuit can be recorded and the data transmission content can be confirmed. While reducing the data transmission delay between switch ports, this technical solution can also improve the accuracy and reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A circuit diagram of cascading multiple low fan-in circuits in the prior art;

[0043] Figure 2 A dynamic circuit diagram applicable to a switch provided for an exemplary embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a nine-port selection circuit provided for an exemplary embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a five-port selection circuit provided for an exemplary embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a four-port selection circuit provided for an exemplary embodiment of the present invention;

[0047] Figure 6 A schematic diagram of a clock signal management circuit provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] In one embodiment of the present invention, a dynamic circuit suitable for a switch is provided. Figures 1 to 5 The dynamic circuit includes a plurality of selection circuits, each of the selection circuits corresponds to a transmission port of the switch, and the selection circuit is configured to control the transmission port corresponding thereto to be electrically connected to one of the other transmission ports;

[0051] The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected to the other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port and the other port is configured as an output port;

[0052] The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are provided on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

[0053] The existing multiplexer uses multiple small units to form a large unit, such as Figure 1 As shown in FIG, multiple 2-port to 1-port multiplexers are used to form an 8-port to 1-port multiplexer. The current needs to pass through several small multiplexers, which will cause a long delay. The dynamic circuit for the switch described in this embodiment is applied to a large number of repeated applications in the switch. Figure 1The cascaded multiplexer and demultiplexer shown here simplifies the logic gates by constructing multiple linear transmission lines from the second port to the first port. By controlling the controllable switch matrix distributed along each transmission line, data from different sources can be output to the target end. As a result, the dynamic circuit designed in this application can quickly receive transmitted data within a single clock cycle, avoiding the delay caused by waiting for clock signals in traditional multi-cascade circuits. Furthermore, data from other transmission ports of the switch can be smoothly transmitted to another transmission port of the switch through the corresponding selection circuits of the other transmission ports, further improving the speed and efficiency of data transmission.

[0054] The dynamic circuit not only reduces the delay in the data transmission path within the switch and improves the data transmission efficiency, but also enables each logical function circuit to work independently, reducing the dependence on multiple cascade circuits, thereby reducing the complexity of the circuit. When the switch needs to expand the interface, it is sufficient to configure the corresponding selection circuit for the expanded port and connect the first port and the second port in the selection circuit to the transmission port of the switch, which can reduce the expansion cost of the switch. In addition, in this technical solution, if Figure 2 As shown, the first port in each selection circuit can be either an output port or an input port, which can facilitate bidirectional data transmission between the two transmission ports in the switch. In addition, there are two transmission lines between the two transmission ports in the switch, making it possible to simultaneously transmit data in both directions between the two transmission ports of the switch.

[0055] In one embodiment of the present invention, the selection circuit has a network structure and further includes multiple control circuits, with the multiple controllable switches distributed across the multiple control circuits. Each control circuit receives a clock signal and is configured to input control signals to a portion of the multiple controllable switches. The combination of control circuits containing controllable switches in the path electrically connecting the second port to the first port is defined as the control scheme for the corresponding transmission circuit, and the control schemes for different transmission circuits are not repeated. Taking MOS switches as an example, the clock signal received by each control circuit is simultaneously input into the gate of the MOS switch located on that control circuit, thereby turning all MOS switches on that control circuit on or off simultaneously.

[0056] It should be noted that the switching states of all the controllable switches are controlled by several control lines, and one control line is used to control the switching states of several controllable switches on different transmission lines, that is, one control line does not control the switching states of two controllable switches arranged on the same transmission line.

[0057] In this embodiment, the dynamic circuit further includes a clock signal management circuit, see Figure 6, the clock signal management circuit includes a first switch tube, a second switch tube and a capacitor. The gate of the first switch tube is configured as the input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor. The other end of the capacitor can be grounded or connected to other discharge circuits. The gate of the second switch tube is configured as the input end of the clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor. The clock signal management circuit corresponds to the selection circuit one-to-one, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

[0058] See also Figure 6 Preferably, the first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube. When the clock signal is 1, the first switch tube is turned on and the second switch tube is not turned on, and the capacitor is in a charging state; when the clock signal is 0, the first switch tube is not turned on and the first switch tube is turned on. If the output signal of the selection circuit is 1, the capacitor is in a charging state or neither charged nor discharged. If the output signal of the selection circuit is 0, the capacitor is in a discharged state. Therefore, by monitoring the charging and discharging state of the capacitor when the clock signal is 0, it can be determined whether the signal transmitted from the input end to the output end of the selection circuit is 0 or 1, thereby accurately determining the data transmitted by the selection circuit. Therefore, while reducing the data transmission delay between switch ports, this technical solution can also improve the accuracy and reliability of data transmission.

[0059] In order to minimize the area of ​​the selection circuit, the number of controllable switches and the number of control lines, in one embodiment of the present invention, the controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of control lines is not less than Among them, log is the logarithm operator, Indicates rounding up log2(N-1).

[0060] More preferably, the number of the control circuits is The number of CMOS switches provided on each transmission line is not less than The number of CMOS switches provided on each control circuit is not greater than

[0061] In another embodiment of the present invention, unlike the above embodiment in which the controllable switch adopts a CMOS switch tube, in this embodiment, the controllable switch adopts an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of the control lines is not less than Among them, log is the logarithm operator, Indicates rounding up log2(N-1).

[0062] More preferably, the number of the control circuits is The number of NMOS switches provided on each transmission line is not less than The number of NMOS switches provided on each control circuit is not greater than

[0063] This embodiment replaces complementary metal oxide semiconductor (CMOS) switches with N-type metal oxide semiconductor (NMOS) switches. NMOS switches offer lower power consumption and faster switching speeds under certain conditions, which are crucial for reducing data transmission latency. This replacement ensures data transmission accuracy while further reducing data transmission latency.

[0064] In one embodiment of the present invention, in order to reduce the area of ​​the dynamic circuit and the delay of data transmission, for a switch with N transmission ports, N selection circuits are correspondingly set, and the N selection circuits are hierarchically arranged on the same circuit unit. Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on the circuit of different layers. The hierarchical arrangement scheme of the N selection circuits can be designed with reference to the technical solution disclosed in the Chinese patent application with application number 2024114493648. The dynamic circuit applicable to the switch provided by this application is described below through multiple specific embodiments.

[0065] Taking a nine-port switch as an example, if you want to control one of the devices connected to the eight transmission ports of the switch to transmit data to the device connected to the ninth transmission port of the switch, if you use the existing technology, you need at least Figure 1 The three-stage cascade multiplexer shown uses multiple small multiplexers. The larger the multiplexer, the higher the data transmission delay. In addition, there is also the problem of insufficient voltage caused by gate circuits such as AND gates and OR gates.

[0066] Adopt the technical solution proposed by the present invention to construct Figure 3 The network selection circuit shown, Figure 3 The first ports a to h represent eight different input ports, and the second port O / P represents one output port. Ports a to h are electrically connected to port O / P to form 8 (9-1=8) transmission lines, and a number of NMOS switches are set in series on each transmission line. The control of the 8 transmission lines requires 6 The control scheme of the transmission line is defined as follows: Figure 3 The selection circuit is shown.

[0067] Figure 3 S0, S1, and S2 are three control lines with the same output level. There are three control lines with the same output level, and the s0 control line and If one of the control circuits outputs a high level, the other outputs a low level. The s1 control circuit and If one of the control circuits outputs a high level, the other outputs a low level. The s2 control circuit and If one of the control circuits outputs a high level, the other outputs a low level. The gate of the NMOS switch is electrically connected to the output of its corresponding control circuit. When the control circuit output on the NMOS switch is high, the NMOS will be turned on. For example, when the s0, s1, and s2 control circuits output a high level, only the h input terminal and the O / P output terminal are connected. At this time, the device connected to the h input terminal transmits data to the device connected to the O / P output terminal. If you want to achieve the device connected to the a input terminal to transmit data to the device connected to the O / P output terminal, then the control The three control lines output high level respectively.

[0068] By using the selection circuit provided in this application, only 6 control lines (at least 3) are needed to control the transmission of one of the 8 transmission lines, and data transmission can be completed within one clock cycle, effectively reducing data delay and preventing conflicts when two transmission lines transmit data at the same time.

[0069] Taking a five-port switch as an example, if the controllable switch uses an NMOS switch tube, the selection circuit corresponding to each transmission port in the switch is as follows: Figure 4 shown.

[0070] Taking a four-port switch as an example, the connection between the dynamic circuit and the four transmission ports of the switch is as follows: Figure 2As shown. The four-port switch includes transmission ports one to four, which are correspondingly configured with first to fourth selection circuits, and each selection circuit has a first port and three second ports. Taking the first selection circuit as an example, it includes a first port I1 and three second ports O12, O13 and O14, wherein the first port I1 is electrically connected to the transmission port one of the switch, the second port O12 is electrically connected to the transmission port two of the switch or the first port of the second selection circuit, the second port O13 is electrically connected to the transmission port three of the switch or the first port of the third selection circuit, and the second port O14 is electrically connected to the transmission port four of the switch or the first port of the fourth selection circuit. If the controllable switch in the first selection circuit adopts an NMOS switch tube, the structure of the first selection circuit is as follows: Figure 5 The structures of the second selection circuit to the fourth selection circuit are the same as the circuit principles of the first selection circuit, and will not be described in detail.

[0071] It should be noted that the dynamic circuit for switches and the aforementioned network-based selection circuit provided by the present invention are particularly advantageous in reducing data transmission latency, simplifying circuit design, and improving switch data transmission reliability, particularly for switches with a greater number of transmission ports. For switches with a smaller number of transmission ports, a controllable switch can be directly installed on each transmission line, each independently controlled. This approach can reduce latency while saving costs.

[0072] In one embodiment of the present invention, a network-type selection circuit is provided, comprising a first port and multiple second ports, wherein one of the first and second ports is configured as an input port and the other is configured as an output port. The first port is electrically connected to each of the second ports to form multiple transmission lines, and each of the transmission lines is provided with a plurality of controllable switches, each configured to control at most one of the transmission lines to be conductive at any one time.

[0073] The selection circuit further includes a plurality of control circuits, the plurality of controllable switches being distributed across the plurality of control circuits, each of the control circuits being configured to input control signals to a portion of the plurality of controllable switches. A combination of control circuits containing controllable switches in a path electrically connecting the second port to the first port is defined as a control scheme for the corresponding transmission line, and control schemes for different transmission lines are not repeated.

[0074] It should be noted that the network selection circuit is not only applicable to switches, but also to other applications of one-to-multiple-end or multi-end-to-one-end electrical connection control or data transmission control.

[0075] In one embodiment of the present invention, a switch is provided, wherein the switch includes the dynamic circuit described in any one of the above embodiments or a combination of multiple embodiments.

[0076] In one embodiment of the present invention, a computer system is provided. The computer system includes the switch described in the above embodiment and a plurality of devices that require data transmission, wherein the devices are correspondingly connected to the transmission ports of the switch.

[0077] It should be noted that the network-type selection circuit embodiment, switch embodiment and computer system embodiment provided by the present invention are the same as the inventive concept of the above-mentioned dynamic circuit embodiment applicable to the switch. The entire content of the dynamic circuit embodiment applicable to the switch is incorporated into the network-type selection circuit embodiment, switch embodiment and computer system embodiment by introduction.

[0078] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0079] The above is only a specific implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A dynamic circuit suitable for a switch, characterized in that: The dynamic circuit includes a plurality of selection circuits, each of which corresponds to a transmission port of the switch, and is configured to control the transmission port corresponding to the selection circuit to be electrically connected to one of the other transmission ports; The selection circuit includes a first port and a plurality of second ports, wherein the first port is configured to be electrically connected to the transmission port corresponding to the selection circuit, the plurality of second ports are electrically connected to the other transmission ports in a one-to-one correspondence, and one of the first port and the second port is configured as an input port and the other port is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines. A plurality of controllable switches are provided on each of the transmission lines. The controllable switches are configured to control at most one of the transmission lines to be turned on at the same time.

2. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The selection circuit further includes a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control circuits where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme for the corresponding transmission circuit, and control schemes for different transmission circuits are not repeated.

3. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is an NMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of the control lines is not less than Among them, log is the logarithm operator, Express Round up.

4. The dynamic circuit applicable to a switch according to claim 3, characterized in that: The number of control lines is The number of NMOS switches provided on each transmission line is not less than 5. The dynamic circuit applicable to a switch according to claim 4, characterized in that: The number of NMOS switches provided on each control circuit is not greater than 6. The dynamic circuit applicable to a switch according to claim 2, characterized in that: The controllable switch is a CMOS switch tube, the number of transmission ports of the switch is N, N is a natural number greater than 1, and the number of the control lines is not less than Among them, log is the logarithm operator, Indicates rounding up log2(N-1).

7. The dynamic circuit applicable to a switch according to claim 6, characterized in that: The number of control lines is The number of CMOS switches provided on each transmission line is not less than 8. The dynamic circuit applicable to a switch according to claim 7, characterized in that: The number of CMOS switches provided on each control circuit is not greater than 9. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The dynamic circuit further includes a clock signal management circuit, the clock signal management circuit including a first switch tube, a second switch tube and a capacitor, wherein the gate of the first switch tube is configured as an input end of the clock signal, the source of the first switch tube is configured to be electrically connected to the output end of the first power supply, and the drain of the first switch tube is electrically connected to the first end of the capacitor; The gate of the second switch tube is configured as an input end of the clock signal, the source of the second switch tube is configured to be grounded, and the drain of the second switch tube is electrically connected to the first end of the capacitor; The clock signal management circuit corresponds to the selection circuit in a one-to-one manner, and the output end of the selection circuit is electrically connected to the first end of the capacitor.

10. The dynamic circuit applicable to a switch according to claim 9, characterized in that: The method further includes determining a clock signal when each selection circuit is operating in the following manner: if the capacitor is in a non-charging state, the clock signal is 0; otherwise, the clock signal is 1; and / or, The method further includes determining the output signal of the selection circuit when the selection circuit is working by monitoring that when the clock signal is 0, the capacitor is in a charging or discharging state, and if the capacitor is in a discharging state, the output signal of the selection circuit is 0; otherwise, the output signal of the selection circuit is 1; and / or, The first switch tube is an NMOS switch tube, and the second switch tube is a PMOS switch tube.

11. The dynamic circuit applicable to a switch according to claim 1, characterized in that: The selection circuits are layered on the same circuit unit. The number of transmission ports of the switch is N, and the circuit unit is correspondingly provided with N layers of selection circuits. Data is transmitted between the first port and the second port on the selection circuit of the same layer, and data is not transmitted between the first port and the second port on circuits of different layers.

12. The dynamic circuit applicable to a switch according to claim 1, characterized in that: One controllable switch is provided on each transmission line, and each controllable switch is configured to be independently controlled.

13. A network selection circuit, characterized in that: The device comprises a first port and a plurality of second ports, wherein the first port and the second port are two ports, one of which is configured as an input port and the other is configured as an output port; The first port is electrically connected to each of the second ports to form a plurality of transmission lines, and a plurality of controllable switches are provided on each of the transmission lines, wherein the controllable switches are configured to control at most one of the transmission lines to be conductive at the same time; The selection circuit further includes a plurality of control circuits, the plurality of controllable switches are distributed on the plurality of control circuits, and each of the control circuits is configured to input a control signal to some of the plurality of controllable switches; A combination of control circuits where a controllable switch on a path electrically connecting the second port and the first port is located is defined as a control scheme for the corresponding transmission circuit, and control schemes for different transmission circuits are not repeated.

14. A switch, characterized in that: The switch comprises a dynamic circuit as claimed in any one of claims 1 to 12.

15. A computer system, characterized in that: The computer system includes the switch according to claim 14 and a device requiring data transmission electrically connected to a transmission port of the switch.

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