Semiconductor device and electronic device including the same

Abstract

The invention discloses a semiconductor device and an electronic device comprising the same. The semiconductor device comprises a drain electrode, an active layer, a source electrode, a grid electrode and an internal grid electrode current collector, the active layer comprises a substrate, a drift region, a well region and a doped region which are stacked in the direction away from the drain electrode, and the surface, away from the drain electrode, of the active layer extends towards the drift region to form a first groove and a second groove; the source electrode partially extends into the first groove, and the part, extending into the first groove, of the source electrode is insulated from the active layer; the grid electrode at least partially extends into the second groove, and the grid electrode and the active layer are insulated and spaced; the internal gate current collector is arranged on the side, away from the drain electrode, of the active layer, the source electrode and the gate electrode are coupled through the internal gate current collector, and the internal gate current collector has an internal driving potential; wherein the equivalent resistance temperature change coefficient of the source electrode is smaller than the equivalent resistance temperature change coefficient of the grid electrode.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and an electronic device containing the same. Background Art

[0002] Compared with traditional silicon-based devices, silicon carbide-based devices have advantages such as small chip area and fast switching speed, and are widely used in high-frequency and high-voltage scenarios.

[0003] Silicon carbide-based devices include planar gate MOSFETs and trench gate MOSFETs. Trench gate MOSFETs can improve channel mobility, reduce cell pitch, increase current density, and thus reduce specific on-state equivalent resistance, further reducing chip size.

[0004] However, the reduction in cell area and the increase in current density simultaneously lead to a decrease in the short-circuit withstand capability of trench gate MOSFETs, making them more susceptible to rapid temperature rise and thermal failure under short-circuit conditions. Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device and an electronic device containing the same, which can improve the short-circuit reliability of the device by extending the short-circuit withstand time.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device comprising a drain, an active layer, a source, a gate, and an internal gate current collector, wherein the active layer comprises a substrate, a drift region, a well region, and a doped region stacked in a direction away from the drain, the substrate, the drift region, and the doped region being doped with a first conductive type, the well region being doped with a second conductive type, the surface of the active layer away from the drain extending toward the drift region to form a first trench and a second trench, the first trench and the second trench being staggered along a first direction; the source portion extending into the first trench, the source extending into the second trench; An insulating gap is formed between a portion of the first groove and the active layer; the gate is at least partially extended into the second groove, and an insulating gap is formed between the gate and the active layer; an internal gate current collector is provided on a side of the active layer away from the drain, the source and the gate are coupled through the internal gate current collector, and the internal gate current collector has an internal driving potential; wherein, the equivalent temperature variation coefficient of resistance of the source is smaller than the equivalent temperature variation coefficient of resistance of the gate, and when the temperature of the active layer rises, the equivalent resistance increment of the gate is greater than the equivalent resistance increment of the source, so that the internal driving potential remains unchanged or decreases.

[0007] In some optional embodiments, the semiconductor device further includes an external gate current collector, which is disposed on a side of the active layer facing away from the drain and coupled to the gate, the orthographic projection of the external gate current collector on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate, and the external gate current collector has an external driving potential. When the temperature of the active layer increases, the ratio of the internal driving potential to the external driving potential decreases.

[0008] In some optional embodiments, in a plane perpendicular to the thickness direction of the active layer, the internal gate current collector and the external gate current collector are spaced apart along a first direction, the source is symmetrically arranged about the shortest line between the internal gate current collector and the external gate current collector, and the gate is symmetrically arranged about the shortest line between the internal gate current collector and the external gate current collector.

[0009] In some optional embodiments, the orthographic projection of the internal gate current collector on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate, and the orthographic projection of the internal gate current collector on the substrate at least partially overlaps with the orthographic projection of the source on the substrate.

[0010] In some optional embodiments, the source includes a first interconnection and a first electrode, the gate includes a second interconnection and a second electrode, and an equivalent resistance of the first interconnection is less than or equal to an equivalent resistance of the second interconnection.

[0011] In some optional embodiments, the source includes polysilicon of the first conductivity type, the gate includes polysilicon of the first conductivity type, and the ion doping concentration of the gate is set to be less than the ion doping concentration of the source.

[0012] In some optional embodiments, the equivalent temperature variation coefficient of the source resistance is negative, and the equivalent temperature variation coefficient of the gate resistance is positive. When the temperature of the active layer rises, the equivalent resistance value of the gate increases, the equivalent resistance value of the source decreases, and the internal driving potential decreases.

[0013] In some optional embodiments, the active layer further includes a contact region doped with the second conductivity type, the contact region is formed by extending from a surface of the active layer away from the drain toward the drift region, and the source and the well region are coupled through the contact region.

[0014] In some optional embodiments, the contact region is disposed around a portion of the source electrode, and the ion doping concentration of the contact region is greater than the ion doping concentration of the well region.

[0015] In a second aspect, an embodiment of the present application provides an electronic device, which includes the semiconductor device provided by any embodiment of the first aspect.

[0016] The embodiment of the present application provides a semiconductor device, which accommodates the source and gate respectively by staggering the first and second trenches in the active layer. The source in the first trench can alleviate the concentration of the electric field distribution near the gate to improve the reliability of the semiconductor device. The semiconductor device provided by the embodiment of the present application also couples the source and the gate through an internal gate current collector. When a short circuit occurs in the active layer, the source and the gate can achieve voltage division to avoid excessive internal drive potential and aggravate the short circuit failure of the device. Furthermore, by setting the equivalent temperature variation coefficient of resistance of the source and the gate differently to increase the voltage drop at the gate, the internal drive potential can be maintained unchanged or reduced, preventing the device from turning on to achieve an extension of the short circuit withstand time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a schematic structural diagram of a semiconductor device according to some embodiments of the present application;

[0019] Figure 2 This is a schematic diagram of electrical connections of semiconductor devices according to some embodiments of the present application;

[0020] Figure 3 Schematic diagram of the layout of the semiconductor device according to some embodiments of the present application.

[0021] The drawings are not necessarily drawn to scale.

[0022] The specific marking information in the accompanying drawings is as follows:

[0023] 100, drain;

[0024] 210, substrate; 220, drift region; 230, well region; 240, doped region; 251, first trench; 252, second trench; 260, contact region;

[0025] 300, source; 310, first interconnection; 320, first electrode;

[0026] 400, gate; 410, second interconnection; 420, second electrode;

[0027] 510, internal gate current collector; 511, internal driving potential; 520, external gate current collector; 521, external driving potential;

[0028] 600, insulating dielectric layer;

[0029] The first direction X. DETAILED DESCRIPTION

[0030] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0032] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0035] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0036] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0037] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0038] Compared with traditional silicon-based devices, silicon carbide-based devices have advantages such as small chip area and fast switching speed, and are widely used in high-frequency and high-voltage scenarios.

[0039] Silicon carbide-based devices include planar gate MOSFETs and trench gate MOSFETs. Trench gate MOSFETs can improve channel mobility, reduce cell pitch, increase current density, and thus reduce specific on-state equivalent resistance, further reducing chip size.

[0040] However, the reduction in cell area and the increase in current density simultaneously lead to a decrease in the short-circuit withstand capability of trench gate MOSFETs, making them more susceptible to rapid temperature rise and thermal failure under short-circuit conditions.

[0041] On the one hand, trench gate MOSFET will form a stronger electric field at the bottom of the trench structure gate, especially at the gate corners, where the electric field concentration is higher, making it easier to exceed the local withstand voltage limit under short-circuit conditions, resulting in damage to the gate oxide layer or even avalanche breakdown.

[0042] On the other hand, when a short circuit occurs in the device, the temperature near the gate rises rapidly. This temperature rise will cause a decrease in carrier mobility and an increase in the on-state equivalent resistance and power consumption, which in turn causes the temperature near the gate to further increase, forming a positive feedback effect of the short-circuit current, which will more quickly aggravate the short-circuit failure of the device.

[0043] To address the problems of the prior art, embodiments of the present application provide a semiconductor device and an electronic device containing the same, which can maintain or reduce the internal drive potential of the device under short-circuit conditions, thereby reducing the probability of thermal failure of the device and improving short-circuit tolerance. The semiconductor device provided in the embodiments of the present application is first introduced below.

[0044] See also Figures 1 to 3 , Figure 1 This is a schematic structural diagram of a semiconductor device according to some embodiments of the present application; Figure 2 This is a schematic diagram of electrical connections of semiconductor devices according to some embodiments of the present application; Figure 3 Schematic diagram of the layout of the semiconductor device according to some embodiments of the present application.

[0045] In a first aspect, an embodiment of the present application provides a semiconductor device, including a drain 100, an active layer, a source 300, a gate 400, and an internal gate current collector 510, wherein the active layer includes a substrate 210, a drift region 220, a well region 230, and a doping region 240 stacked in a direction away from the drain 100, the substrate 210, the drift region 220, and the doping region 240 are doped with a first conductive type, the well region 230 is doped with a second conductive type, and the surface of the active layer away from the drain 100 extends toward the drift region 220 to form a first trench 251 and a second trench 252. 52, the first trench 251 and the second trench 252 are arranged alternately along the first direction; the source electrode 300 is partially extended into the first trench 251, and the portion of the source electrode 300 extending into the first trench 251 is insulated from the active layer; the gate electrode 400 is at least partially extended into the second trench 252, and the gate electrode 400 is insulated from the active layer; the internal gate current collector 510 is arranged on the side of the active layer away from the drain electrode 100, the source electrode 300 and the gate electrode 400 are coupled through the internal gate current collector 510, and the internal gate current collector 510 has an internal driving potential 511.

[0046] Optionally, the first conductive type doping is N-type doping, and the second conductive type doping is P-type doping.

[0047] Optionally, the material of the active layer includes at least one of silicon carbide, silicon, germanium, and carbon germanium silicon. Wherein, when the active layer includes two or more materials, these materials can be provided in the form of a mixture or in the form of a multilayer structure.

[0048] It is understandable that the semiconductor device further includes an insulating dielectric layer 600 , and the insulating dielectric layer 600 is at least disposed between the gate 400 and the active layer to achieve an insulating gap between the gate 400 and the active layer.

[0049] Optionally, the insulating dielectric layer 600 is disposed between the portion of the source electrode 300 extending into the first trench 251 and the active layer.

[0050] Therefore, the semiconductor device opens a first groove 251 and a second groove 252 arranged in an staggered manner along the first direction in the active layer and accommodates the source 300 and the gate 400 respectively. The part of the source 300 extending into the active layer can achieve an optimized distribution of the electric field at the gate 400 by increasing the contact area between the source 300 and the gate 400, thereby reducing the probability of avalanche breakdown of the device around the gate 400, thereby improving the reliability of the semiconductor device.

[0051] In addition, in the semiconductor device provided in the embodiment of the present application, the equivalent temperature variation coefficient of resistance of the source 300 is set to be smaller than the equivalent temperature variation coefficient of resistance of the gate 400. When the temperature of the active layer rises, the equivalent resistance increment of the gate 400 is greater than the equivalent resistance increment of the source 300, so that the internal driving potential 511 remains unchanged or decreases.

[0052] Optionally, under normal temperature conditions, the equivalent resistance of the source 300 is less than or equal to the equivalent resistance of the gate 400 .

[0053] Therefore, when a short circuit occurs in the semiconductor device and the internal temperature of the device rises rapidly, the equivalent resistance of the source 300 and the equivalent resistance of the gate 400 will each change as the temperature rises, thereby achieving a voltage divider effect. The equivalent resistance increment of the gate 400 is greater than the equivalent resistance increment of the source 300, thereby increasing the voltage drop at the gate 400, causing the internal driving potential 511 at the internal gate current collector 510 to decrease or remain unchanged. This design can cut off the positive feedback mechanism in which the power consumption of the dual-trench semiconductor device increases with increasing temperature under short-circuit conditions, effectively controlling the internal temperature of the device and reducing the probability of the device turning on quickly under short-circuit conditions, ultimately improving the short-circuit tolerance of the semiconductor device.

[0054] According to some embodiments of the first aspect of the present application, the semiconductor device also includes an external gate current collector 520, which is arranged on the side of the active layer away from the drain 100 and is coupled to the gate 400. The external gate current collector 520 has an external driving potential 521. When the temperature of the active layer increases, the ratio of the internal driving potential 511 to the external driving potential 521 decreases.

[0055] It can be understood that both the source 300 and the drain 100 have fixed potentials, and the semiconductor device only controls the opening or closing of the channel in the well region through the internal driving potential 511 to switch the switch function.

[0056] Optionally, the orthographic projection of the external gate current collector 520 on the substrate 210 at least partially overlaps with the orthographic projection of the gate 400 on the substrate 210 to facilitate interconnection of the external gate current collector 520 and the gate 400 .

[0057] As a result, the potential difference between the external driving potential 521 of the external gate current collector 520 and the fixed potential of the source 300 is a constant value, so that the internal driving potential 511 can be reduced due to the increase in the voltage drop of the gate 400 when the temperature of the active layer increases, thereby constructing a negative feedback mechanism inside the semiconductor device in which the higher the temperature under short-circuit conditions, the lower the internal driving potential 511, further reducing the probability of channel opening and improving device reliability.

[0058] According to some embodiments of the first aspect of the present application, in a plane perpendicular to the thickness direction of the active layer, the internal gate current collector 510 and the external gate current collector 520 are spaced apart along a first direction, and the gate 400 is symmetrically arranged about the shortest connecting line between the internal gate current collector 510 and the external gate current collector 520.

[0059] Optionally, the internal gate current collector 510 and the external gate current collector 520 are disposed at two ends of the semiconductor device.

[0060] Optionally, the source electrode 300 is symmetrically arranged with respect to the shortest connection line between the inner gate current collector 510 and the outer gate current collector 520 .

[0061] As a result, the equivalent resistances of different conductive paths between the external gate current collector 520 and the internal gate current collector 510 tend to be the same, thereby making the voltage drops of different conductive paths between the external gate current collector 520 and the internal gate current collector 510 tend to be consistent, thereby improving the stability of the internal driving potential 511, and reducing the probability of failure of the channel-opening device due to fluctuations in the internal driving potential 511 under short-circuit conditions, thereby further improving the reliability of the device; and, the mirror-designed gate 400 can reduce the local temperature gradient of the semiconductor device under short-circuit conditions, thereby reducing the probability of thermal failure of the device.

[0062] According to some embodiments of the first aspect of the present application, the orthographic projection of the internal gate current collector 510 on the substrate 210 at least partially overlaps with the orthographic projection of the gate 400 on the substrate 210, and the orthographic projection of the internal gate current collector 510 on the substrate 210 at least partially overlaps with the orthographic projection of the source 300 on the substrate 210.

[0063] Optionally, the material of the internal gate current collector 510 includes at least one of conductive metal, polysilicon, and conductive polymer.

[0064] Thus, the internal gate current collector 510 is coupled to the source 300 and the gate 400 at the same time, so that the source 300 and the gate 400 can realize a voltage dividing function, thereby constructing a negative feedback mechanism for the temperature rise of the semiconductor device under a short-circuit condition.

[0065] It is understandable that, in addition to the common field plate structure, the internal gate current collector 510 can also be set to other structures that can achieve electrical interconnection between the source 300 and the gate 400, such as a patterned conductive structure formed by etching and other processes.

[0066] According to some embodiments of the first aspect of the present application, the source 300 includes a first interconnect 310 and a first electrode 320 , the gate 400 includes a second interconnect 410 and a second electrode 420 , and the equivalent resistance of the first interconnect 310 is less than or equal to the equivalent resistance of the second interconnect 410 .

[0067] Specifically, the first electrode 320 is the conductive portion of the source 300 extending into the first trench 251 , and the first interconnect 310 is the conductive portion connected between the first electrode 320 and the internal gate current collector 510 .

[0068] It can be understood that the equivalent resistance of the source 300 refers to the total equivalent resistance when current flows through the first interconnect 310 , and can be adjusted by adjusting the material, length or cross-sectional area of ​​the first interconnect 310 .

[0069] Specifically, the second interconnection 410 is a conductive portion for connecting the second electrode 420 and the inner gate current collector 510 or the outer gate current collector 520 .

[0070] It can be understood that the equivalent resistance of the gate 400 refers to the total equivalent resistance when current flows through the second interconnection 410 , and can be adjusted by adjusting the material, length or cross-sectional area of ​​the second interconnection 410 .

[0071] As a result, the first interconnection 310 and the second interconnection 410 exhibit different equivalent resistance changes under the same temperature rise condition, so that the electrothermal coupling relationship between the gate 400 and the source 300 is redistributed, offsetting the positive shift of the internal driving potential 511 caused by the temperature rise, and improving the short-circuit tolerance capability of the semiconductor device.

[0072] According to some embodiments of the first aspect of the present application, the source 300 includes polysilicon of the first conductivity type, the gate 400 includes polysilicon of the first conductivity type, and the ion doping concentration of the gate 400 is set lower than the ion doping concentration of the source 300.

[0073] Optionally, both the first interconnection 310 and the second interconnection 410 are polysilicon of the first conductivity type, and the ion doping concentration of the second interconnection 410 is lower than the ion doping concentration of the first interconnection 310 .

[0074] As a result, the carrier mobility in the gate 400 with a lower ion doping concentration is more sensitive to temperature, and the equivalent resistance increases more significantly with increasing temperature. The carrier mobility in the source 300 with a lower ion doping concentration is less sensitive to temperature, and the equivalent resistance increases less with increasing temperature, and may even decrease with increasing temperature. By changing the equivalent resistance of the gate 400 and source 300, the voltage divider between the gate 400 and source 300 is changed, thereby reducing the internal drive potential 511.

[0075] According to some embodiments of the first aspect of the present application, the equivalent temperature variation coefficient of resistance of the source 300 is negative, and the equivalent temperature variation coefficient of resistance of the gate 400 is positive. When the temperature of the active layer rises, the equivalent resistance value of the gate 400 increases, the equivalent resistance value of the source 300 decreases, and the internal driving potential 511 decreases.

[0076] It can be understood that the equivalent temperature variation coefficient of resistance of the source 300 is negative, and the equivalent resistance value of the source 300 decreases with increasing temperature; the equivalent temperature variation coefficient of resistance of the gate 400 is gate 400, and the equivalent resistance value of the gate 400 increases with increasing temperature.

[0077] Optionally, the material of the source electrode 300 includes at least one of a conductive polymer, a carbon-based material, a conductive oxide, a metal silicon nitride, and a metal nitride.

[0078] Optionally, the material of the gate 400 includes at least one of a conductive polymer, a carbon-based material, a conductive oxide, a metal silicon, and a metal nitride.

[0079] Optionally, the source electrode 300 and the gate electrode 400 are made of the same material so that the first electrode 320 and the second electrode 420 can be prepared synchronously; or, according to different usage requirements, the materials of the source electrode 300 and the gate electrode 400 are set differently.

[0080] Therefore, when the semiconductor device is short-circuited and heated, the difference in the equivalent resistance value between the gate 400 and the source 300 is further widened, thereby widening the voltage drop at the gate 400 to further reduce the internal driving potential 511, thereby reducing the probability of the channel quickly opening under short-circuit conditions and causing thermal failure of the device.

[0081] According to some embodiments of the first aspect of the present application, the active layer further includes a contact region 260 doped with the second conductive type. The contact region 260 is formed by extending from the surface of the active layer away from the drain 100 toward the drift region 220 , and the source 300 is coupled to the well region 230 through the contact region 260 .

[0082] Specifically, the contact region 260 is disposed between the insulating dielectric layer 600 and the active layer.

[0083] Optionally, the contact region 260 is disposed around a portion of the source 300 .

[0084] Optionally, the ion doping concentration of the contact region 260 is greater than the ion doping concentration of the well region 230 .

[0085] Therefore, providing the contact region 260 around the source 300 can further optimize the gate-source electric field distribution inside the active layer, reduce the probability of avalanche breakdown of the device, and improve the reliability and safety of the device.

[0086] In a second aspect, an embodiment of the present application provides an electronic device, which includes the semiconductor device provided by any embodiment of the first aspect.

[0087] The electronic device of this embodiment can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, digital photo frame, camera, camcorder, voice recorder, MP3, MP4, PSP, or any other intermediate product including a circuit. The electronic device of this embodiment of the present invention, due to its use of the semiconductor device of the first aspect, has all the advantages thereof and thus has better performance.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: drain; An active layer includes a substrate, a drift region, a well region, and a doped region stacked in a direction away from the drain, wherein the substrate, the drift region, and the doped region are doped with a first conductivity type, and the well region is doped with a second conductivity type. A surface of the active layer facing away from the drain extends toward the drift region to form a first trench and a second trench, wherein the first trench and the second trench are staggered along a first direction. a source electrode, partially extending into the first trench, with an insulating gap between the portion of the source electrode extending into the first trench and the active layer; a gate electrode, at least partially extending into the second trench, with an insulating space between the gate electrode and the active layer; An internal gate current collector is provided on a side of the active layer away from the drain electrode, the source electrode and the gate electrode are coupled via the internal gate current collector, and the internal gate current collector has an internal driving potential; Among them, the equivalent temperature variation coefficient of resistance of the source is smaller than the equivalent temperature variation coefficient of resistance of the gate. When the temperature of the active layer rises, the equivalent resistance increment of the gate is greater than the equivalent resistance increment of the source, so that the internal driving potential remains unchanged or decreases.

2. The semiconductor device according to claim 1, wherein The semiconductor device also includes an external gate current collector, which is arranged on a side of the active layer away from the drain and coupled to the gate. The orthographic projection of the external gate current collector on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate. The external gate current collector has an external driving potential. When the temperature of the active layer increases, the ratio of the internal driving potential to the external driving potential decreases.

3. The semiconductor device according to claim 2, wherein In a plane perpendicular to the thickness direction of the active layer, the internal gate current collector and the external gate current collector are spaced apart along a first direction, the source is symmetrically arranged about the shortest line between the internal gate current collector and the external gate current collector, and the gate is symmetrically arranged about the shortest line between the internal gate current collector and the external gate current collector.

4. The semiconductor device according to claim 3, wherein The orthographic projection of the internal gate current collector on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate, and the orthographic projection of the internal gate current collector on the substrate at least partially overlaps with the orthographic projection of the source on the substrate.

5. The semiconductor device according to claim 3, wherein The source includes a first interconnection and a first electrode, the gate includes a second interconnection and a second electrode, and an equivalent resistance of the first interconnection is less than or equal to an equivalent resistance of the second interconnection. The semiconductor device according to claim 1 , wherein: The source includes polysilicon of a first conductivity type, the gate includes polysilicon of a first conductivity type, and the ion doping concentration of the gate is lower than the ion doping concentration of the source.

7. The semiconductor device according to claim 1, wherein The temperature variation coefficient of the equivalent resistance of the source is negative, and the temperature variation coefficient of the equivalent resistance of the gate is positive. When the temperature of the active layer increases, the equivalent resistance value of the gate increases, the equivalent resistance value of the source decreases, and the internal driving potential decreases.

8. The semiconductor device according to claim 1, wherein The active layer further includes a contact region doped with the second conductive type. The contact region is formed by extending from a surface of the active layer away from the drain toward the drift region. The source and the well region are coupled via the contact region.

9. The semiconductor device according to claim 8, wherein The contact region is arranged around a portion of the source electrode, and the ion doping concentration of the contact region is greater than the ion doping concentration of the well region.

10. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 9.

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